From d216f570750b8ccde3754c4aef53fc20a90cb32d Mon Sep 17 00:00:00 2001 From: Freddie Liardet Date: Tue, 3 Aug 2021 15:57:32 +0100 Subject: Update cpu depthwise kernels Resolves: COMPMID-4688 Signed-off-by: Freddie Liardet Change-Id: I9e22f967f5b7ccaebff2fc49f0253f621d62d820 Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6030 Tested-by: Arm Jenkins Reviewed-by: Pablo Marquez Tello Reviewed-by: Georgios Pinitas Comments-Addressed: Arm Jenkins --- .../generic_indirect.cpp | 410 ++++++++++----------- 1 file changed, 196 insertions(+), 214 deletions(-) (limited to 'src/core/NEON/kernels/arm_conv/depthwise/kernels/sve_fp16_nhwc_3x3_s1_output3x3_mla_depthfirst/generic_indirect.cpp') diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/sve_fp16_nhwc_3x3_s1_output3x3_mla_depthfirst/generic_indirect.cpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/sve_fp16_nhwc_3x3_s1_output3x3_mla_depthfirst/generic_indirect.cpp index 770576c5da..f79a36b2a3 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/kernels/sve_fp16_nhwc_3x3_s1_output3x3_mla_depthfirst/generic_indirect.cpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/sve_fp16_nhwc_3x3_s1_output3x3_mla_depthfirst/generic_indirect.cpp @@ -25,7 +25,7 @@ #include #include -#if defined(ARM_COMPUTE_ENABLE_SVE) && defined(__ARM_FP16_ARGS) +#if __aarch64__ && defined(ARM_COMPUTE_ENABLE_SVE) && defined(__ARM_FP16_ARGS) namespace arm_conv { namespace depthwise { @@ -87,130 +87,121 @@ void sve_fp16_nhwc_3x3_s1_output3x3_mla_depthfirst_indirect_impl( activation_min, activation_max); __asm__ __volatile__( - "ldr x6, [%x[params_struct], %[offsetof_args_outptrs]]\n" + "ldr x16, [%x[params_struct], %[offsetof_args_outptrs]]\n" "ptrue p3.b\n" - "ldr x7, [%x[params_struct], %[offsetof_args_params]]\n" - "add x8, %x[params_struct], %[offsetof_Args_inptrs]\n" + "ldr x15, [%x[params_struct], %[offsetof_args_params]]\n" + "add x14, %x[params_struct], %[offsetof_Args_inptrs]\n" "ld1rh { z18.h }, p3/Z, [%x[params_struct], %[offsetof_args_min]]\n" - "mov x17, #0x0\n" + "mov x13, #0x0\n" "ld1rh { z17.h }, p3/Z, [%x[params_struct], %[offsetof_args_max]]\n" - "cnth x16\n" - "ld1h { z16.h }, p3/Z, [x7]\n" // Load from weights and bias - "mov z31.d, z16.d\n" - "ld1h { z0.h }, p3/Z, [x7, #1, MUL VL]\n" // Load from weights and bias - "sub x15, XZR, x16\n" - "mov z30.d, z16.d\n" - "ld1h { z1.h }, p3/Z, [x7, #2, MUL VL]\n" // Load from weights and bias + "cnth x12\n" + "ld1h { z16.h }, p3/Z, [x15]\n" + "sub x11, XZR, x12\n" + "ld1h { z0.h }, p3/Z, [x15, #1, MUL VL]\n" "whilelt p2.h, XZR, %x[n_channels]\n" - "mov z29.d, z16.d\n" - "ld1h { z2.h }, p3/Z, [x7, #3, MUL VL]\n" // Load from weights and bias - "cmp x16, %x[n_channels]\n" - "mov z28.d, z16.d\n" - "ld1h { z3.h }, p3/Z, [x7, #4, MUL VL]\n" // Load from weights and bias - "mov z27.d, z16.d\n" - "ld1h { z4.h }, p3/Z, [x7, #5, MUL VL]\n" // Load from weights and bias - "mov z26.d, z16.d\n" - "ld1h { z5.h }, p3/Z, [x7, #6, MUL VL]\n" // Load from weights and bias - "mov z25.d, z16.d\n" - "ld1h { z6.h }, p3/Z, [x7, #7, MUL VL]\n" // Load from weights and bias - "addvl x7, x7, #16\n" - "mov z24.d, z16.d\n" - "ld1h { z7.h }, p3/Z, [x7, #-8, MUL VL]\n" // Load from weights and bias - "mov z23.d, z16.d\n" - "ld1h { z8.h }, p3/Z, [x7, #-7, MUL VL]\n" // Load from weights and bias - "addvl x7, x7, #-6\n" - "ldp x14, x13, [x8, #0x0]\n" - "ldp x12, x11, [x8, #0x10]\n" - "ldr x10, [x8, #0x20]\n" - "ld1h { z9.h }, p2/Z, [x14, x17, LSL #1]\n" - "ld1h { z10.h }, p2/Z, [x13, x17, LSL #1]\n" - "ld1h { z11.h }, p2/Z, [x12, x17, LSL #1]\n" - "ld1h { z12.h }, p2/Z, [x11, x17, LSL #1]\n" - "ld1h { z13.h }, p2/Z, [x10, x17, LSL #1]\n" + "ld1h { z1.h }, p3/Z, [x15, #2, MUL VL]\n" + "cmp x12, %x[n_channels]\n" + "ld1h { z2.h }, p3/Z, [x15, #3, MUL VL]\n" + "ld1h { z3.h }, p3/Z, [x15, #4, MUL VL]\n" + "ld1h { z4.h }, p3/Z, [x15, #5, MUL VL]\n" + "ld1h { z5.h }, p3/Z, [x15, #6, MUL VL]\n" + "ld1h { z6.h }, p3/Z, [x15, #7, MUL VL]\n" + "addvl x15, x15, #16\n" + "ldp x10, x9, [x14, #0x0]\n" + "ld1h { z7.h }, p3/Z, [x15, #-8, MUL VL]\n" + "ld1h { z8.h }, p3/Z, [x15, #-7, MUL VL]\n" + "addvl x15, x15, #-6\n" + "ld1h { z9.h }, p2/Z, [x10, x13, LSL #1]\n" + "ld1h { z10.h }, p2/Z, [x9, x13, LSL #1]\n" + "ldp x28, x27, [x14, #0x10]\n" + "ldr x26, [x14, #0x20]\n" + "ld1h { z11.h }, p2/Z, [x28, x13, LSL #1]\n" + "ld1h { z12.h }, p2/Z, [x27, x13, LSL #1]\n" + "ld1h { z13.h }, p2/Z, [x26, x13, LSL #1]\n" "bge 2f\n" "1:" // Channel loop - "fmla z31.h, p3/M, z8.h, z9.h\n" - "ldr x9, [x8, #0x28]\n" - "whilelt p1.h, x16, %x[n_channels]\n" - "fmla z30.h, p3/M, z7.h, z9.h\n" - "ldr x28, [x8, #0x30]\n" - "inch x15\n" - "fmla z29.h, p3/M, z6.h, z9.h\n" - "ldr x27, [x8, #0x38]\n" + "movprfx z31, z16\n fmla z31.h, p3/M, z8.h, z9.h\n" + "ldr x25, [x14, #0x28]\n" + "whilelt p1.h, x12, %x[n_channels]\n" + "movprfx z30, z16\n fmla z30.h, p3/M, z7.h, z9.h\n" + "ldr x24, [x14, #0x30]\n" + "inch x11\n" + "movprfx z29, z16\n fmla z29.h, p3/M, z6.h, z9.h\n" + "ldr x23, [x14, #0x38]\n" "mov p0.b, p2.b\n" - "fmla z28.h, p3/M, z5.h, z9.h\n" - "ldr x26, [x8, #0x40]\n" - "fmla z27.h, p3/M, z4.h, z9.h\n" - "ldr x22, [x8, #0x48]\n" - "fmla z26.h, p3/M, z3.h, z9.h\n" - "ldr x21, [x8, #0x50]\n" - "fmla z25.h, p3/M, z2.h, z9.h\n" - "ldr x20, [x8, #0x58]\n" - "fmla z24.h, p3/M, z1.h, z9.h\n" - "ldr x19, [x8, #0x60]\n" - "fmla z23.h, p3/M, z0.h, z9.h\n" - "ldr x25, [x8, #0x68]\n" + "movprfx z28, z16\n fmla z28.h, p3/M, z5.h, z9.h\n" + "ldr x10, [x14, #0x40]\n" + "movprfx z27, z16\n fmla z27.h, p3/M, z4.h, z9.h\n" + "ldr x9, [x14, #0x48]\n" + "movprfx z26, z16\n fmla z26.h, p3/M, z3.h, z9.h\n" + "ldr x28, [x14, #0x50]\n" + "movprfx z25, z16\n fmla z25.h, p3/M, z2.h, z9.h\n" + "ldr x27, [x14, #0x58]\n" + "movprfx z24, z16\n fmla z24.h, p3/M, z1.h, z9.h\n" + "ldr x26, [x14, #0x60]\n" + "movprfx z23, z16\n fmla z23.h, p3/M, z0.h, z9.h\n" + "ldr x22, [x16, #0x0]\n" "fmla z31.h, p3/M, z0.h, z10.h\n" - "ld1h { z10.h }, p2/Z, [x22, x17, LSL #1]\n" + "ld1h { z10.h }, p2/Z, [x9, x13, LSL #1]\n" "fmla z29.h, p3/M, z2.h, z11.h\n" - "ld1h { z11.h }, p2/Z, [x28, x17, LSL #1]\n" + "ld1h { z11.h }, p2/Z, [x24, x13, LSL #1]\n" "fmla z25.h, p3/M, z6.h, z12.h\n" - "ld1h { z12.h }, p2/Z, [x9, x17, LSL #1]\n" + "ld1h { z12.h }, p2/Z, [x25, x13, LSL #1]\n" "fmla z30.h, p3/M, z4.h, z13.h\n" - "ldr x24, [x8, #0x70]\n" + "ldr x25, [x14, #0x68]\n" "fmla z31.h, p3/M, z5.h, z13.h\n" - "ldr x23, [x8, #0x78]\n" + "ldr x24, [x14, #0x70]\n" "fmla z29.h, p3/M, z3.h, z13.h\n" - "ldr x14, [x8, #0x80]\n" + "ldr x9, [x14, #0x88]\n" "fmla z28.h, p3/M, z2.h, z13.h\n" - "ldr x13, [x8, #0x88]\n" + "ldr x21, [x16, #0x8]\n" "fmla z27.h, p3/M, z1.h, z13.h\n" - "ldr x12, [x8, #0x90]\n" + "ldr x20, [x16, #0x10]\n" "fmla z26.h, p3/M, z0.h, z13.h\n" - "ld1h { z13.h }, p2/Z, [x27, x17, LSL #1]\n" + "ld1h { z13.h }, p2/Z, [x23, x13, LSL #1]\n" "fmla z23.h, p3/M, z8.h, z12.h\n" - "ld1h { z12.h }, p2/Z, [x26, x17, LSL #1]\n" + "ld1h { z12.h }, p2/Z, [x10, x13, LSL #1]\n" "fmla z31.h, p3/M, z7.h, z11.h\n" - "ldr x11, [x8, #0x98]\n" + "ldr x23, [x14, #0x78]\n" "fmla z30.h, p3/M, z6.h, z11.h\n" - "ldr x10, [x8, #0xa0]\n" + "ldr x10, [x14, #0x80]\n" "fmla z28.h, p3/M, z4.h, z11.h\n" - "ldr x9, [x8, #0xa8]\n" + "ldr x19, [x16, #0x18]\n" "fmla z27.h, p3/M, z3.h, z11.h\n" - "ldr x28, [x8, #0xb0]\n" + "ld1h { z16.h }, p3/Z, [x15]\n" "fmla z25.h, p3/M, z1.h, z11.h\n" - "ldr x27, [x8, #0xb8]\n" "fmla z24.h, p3/M, z0.h, z11.h\n" - "ld1h { z11.h }, p2/Z, [x21, x17, LSL #1]\n" + "ld1h { z11.h }, p2/Z, [x28, x13, LSL #1]\n" "fmla z31.h, p3/M, z1.h, z13.h\n" - "ldr x26, [x8, #0xc0]\n" + "ldr x28, [x14, #0x90]\n" "fmla z30.h, p3/M, z0.h, z13.h\n" - "ld1h { z13.h }, p2/Z, [x20, x17, LSL #1]\n" + "ld1h { z13.h }, p2/Z, [x27, x13, LSL #1]\n" "fmla z29.h, p3/M, z1.h, z12.h\n" - "ldr x22, [x6, #0x0]\n" + "ldr x27, [x14, #0x98]\n" "fmla z27.h, p3/M, z5.h, z10.h\n" - "ldr x21, [x6, #0x8]\n" "fmla z26.h, p3/M, z4.h, z10.h\n" - "ldr x20, [x6, #0x10]\n" "fmla z30.h, p3/M, z2.h, z12.h\n" - "ld1h { z12.h }, p2/Z, [x19, x17, LSL #1]\n" + "ld1h { z12.h }, p2/Z, [x26, x13, LSL #1]\n" "fmla z29.h, p3/M, z7.h, z10.h\n" - "ldr x19, [x6, #0x18]\n" + "ldr x26, [x14, #0xa0]\n" "fmla z24.h, p3/M, z2.h, z10.h\n" - "ld1h { z16.h }, p3/Z, [x7]\n" // Load from weights and bias "fmla z23.h, p3/M, z1.h, z10.h\n" "fmla z30.h, p3/M, z8.h, z10.h\n" - "ld1h { z10.h }, p2/Z, [x25, x17, LSL #1]\n" + "ld1h { z10.h }, p2/Z, [x25, x13, LSL #1]\n" "fmla z31.h, p3/M, z3.h, z11.h\n" + "ldr x25, [x14, #0xa8]\n" "fmla z28.h, p3/M, z0.h, z11.h\n" - "ld1h { z11.h }, p2/Z, [x24, x17, LSL #1]\n" + "ld1h { z11.h }, p2/Z, [x24, x13, LSL #1]\n" "fmla z29.h, p3/M, z5.h, z13.h\n" + "ldr x24, [x14, #0xb0]\n" "fmla z26.h, p3/M, z2.h, z13.h\n" - "ld1h { z13.h }, p2/Z, [x23, x17, LSL #1]\n" + "ld1h { z13.h }, p2/Z, [x23, x13, LSL #1]\n" "fmla z25.h, p3/M, z3.h, z12.h\n" + "ldr x23, [x14, #0xb8]\n" "fmla z28.h, p3/M, z6.h, z12.h\n" - "ld1h { z12.h }, p2/Z, [x14, x17, LSL #1]\n" + "ld1h { z12.h }, p2/Z, [x10, x13, LSL #1]\n" "fmla z27.h, p3/M, z7.h, z10.h\n" + "ldr x10, [x14, #0xc0]\n" "fmla z26.h, p3/M, z6.h, z10.h\n" "fmla z25.h, p3/M, z5.h, z10.h\n" "fmla z28.h, p3/M, z8.h, z10.h\n" @@ -219,191 +210,182 @@ void sve_fp16_nhwc_3x3_s1_output3x3_mla_depthfirst_indirect_impl( "fmla z26.h, p3/M, z8.h, z11.h\n" "fmla z25.h, p3/M, z7.h, z13.h\n" "fmla z24.h, p3/M, z6.h, z13.h\n" - "ld1h { z13.h }, p2/Z, [x12, x17, LSL #1]\n" + "ld1h { z13.h }, p2/Z, [x28, x13, LSL #1]\n" "fmla z23.h, p3/M, z5.h, z11.h\n" - "ld1h { z11.h }, p2/Z, [x13, x17, LSL #1]\n" + "ld1h { z11.h }, p2/Z, [x9, x13, LSL #1]\n" "fmla z31.h, p3/M, z4.h, z12.h\n" - "ldp x14, x13, [x8, #0x0]\n" "fmla z30.h, p3/M, z3.h, z12.h\n" - "ld1h { z9.h }, p1/Z, [x14, x16, LSL #1]\n" "fmla z28.h, p3/M, z1.h, z12.h\n" "fmla z27.h, p3/M, z0.h, z12.h\n" - "ld1h { z12.h }, p2/Z, [x11, x17, LSL #1]\n" - "fmla z30.h, p3/M, z5.h, z11.h\n" - "ld1h { z10.h }, p1/Z, [x13, x16, LSL #1]\n" + "ld1h { z12.h }, p2/Z, [x27, x13, LSL #1]\n" "fmla z29.h, p3/M, z4.h, z11.h\n" - "ldp x12, x11, [x8, #0x10]\n" + "fmla z30.h, p3/M, z5.h, z11.h\n" "fmla z26.h, p3/M, z1.h, z11.h\n" "fmla z27.h, p3/M, z2.h, z11.h\n" - "ld1h { z11.h }, p2/Z, [x10, x17, LSL #1]\n" + "ld1h { z11.h }, p2/Z, [x26, x13, LSL #1]\n" "fmla z24.h, p3/M, z8.h, z13.h\n" - "ldr x10, [x8, #0x20]\n" + "ldr x26, [x14, #0x20]\n" "fmla z23.h, p3/M, z7.h, z13.h\n" - "ld1h { z13.h }, p2/Z, [x9, x17, LSL #1]\n" + "ld1h { z13.h }, p2/Z, [x25, x13, LSL #1]\n" "fmla z28.h, p3/M, z7.h, z12.h\n" "fmla z27.h, p3/M, z6.h, z12.h\n" "fmla z25.h, p3/M, z4.h, z12.h\n" "fmla z24.h, p3/M, z3.h, z12.h\n" - "ld1h { z12.h }, p2/Z, [x28, x17, LSL #1]\n" + "ld1h { z12.h }, p2/Z, [x24, x13, LSL #1]\n" "fmla z31.h, p3/M, z2.h, z11.h\n" "fmla z30.h, p3/M, z1.h, z11.h\n" - "ld1h { z1.h }, p3/Z, [x7, #2, MUL VL]\n" // Load from weights and bias + "ld1h { z1.h }, p3/Z, [x15, #2, MUL VL]\n" "fmla z29.h, p3/M, z0.h, z11.h\n" - "ld1h { z11.h }, p2/Z, [x27, x17, LSL #1]\n" + "ld1h { z11.h }, p2/Z, [x23, x13, LSL #1]\n" "fmla z27.h, p3/M, z8.h, z13.h\n" "fmla z26.h, p3/M, z7.h, z13.h\n" "fmla z24.h, p3/M, z5.h, z13.h\n" "fmla z23.h, p3/M, z4.h, z13.h\n" - "ld1h { z13.h }, p2/Z, [x26, x17, LSL #1]\n" - "inch x17\n" + "ld1h { z13.h }, p2/Z, [x10, x13, LSL #1]\n" + "inch x13\n" "fmla z31.h, p3/M, z6.h, z12.h\n" - "ld1h { z4.h }, p3/Z, [x7, #5, MUL VL]\n" // Load from weights and bias - "whilelt p2.h, x17, %x[n_channels]\n" + "ldp x10, x9, [x14, #0x0]\n" + "whilelt p2.h, x13, %x[n_channels]\n" "fmla z28.h, p3/M, z3.h, z12.h\n" - "ld1h { z3.h }, p3/Z, [x7, #4, MUL VL]\n" // Load from weights and bias + "ldp x28, x27, [x14, #0x10]\n" "fmla z25.h, p3/M, z0.h, z12.h\n" - "ld1h { z12.h }, p1/Z, [x11, x16, LSL #1]\n" + "ld1h { z0.h }, p3/Z, [x15, #1, MUL VL]\n" "fmla z29.h, p3/M, z8.h, z11.h\n" - "ld1h { z0.h }, p3/Z, [x7, #1, MUL VL]\n" // Load from weights and bias + "ld1h { z9.h }, p1/Z, [x10, x12, LSL #1]\n" "fmla z26.h, p3/M, z5.h, z11.h\n" - "ld1h { z5.h }, p3/Z, [x7, #6, MUL VL]\n" // Load from weights and bias + "ld1h { z10.h }, p1/Z, [x9, x12, LSL #1]\n" "fmla z23.h, p3/M, z2.h, z11.h\n" - "ld1h { z11.h }, p1/Z, [x12, x16, LSL #1]\n" + "ld1h { z11.h }, p1/Z, [x28, x12, LSL #1]\n" "fmla z25.h, p3/M, z8.h, z13.h\n" - "ld1h { z2.h }, p3/Z, [x7, #3, MUL VL]\n" // Load from weights and bias + "ld1h { z12.h }, p1/Z, [x27, x12, LSL #1]\n" "fmla z24.h, p3/M, z7.h, z13.h\n" + "ld1h { z2.h }, p3/Z, [x15, #3, MUL VL]\n" "fmax z31.h, p3/M, z31.h, z18.h\n" + "ld1h { z3.h }, p3/Z, [x15, #4, MUL VL]\n" "fmla z23.h, p3/M, z6.h, z13.h\n" - "ld1h { z13.h }, p1/Z, [x10, x16, LSL #1]\n" - "inch x16\n" + "ld1h { z13.h }, p1/Z, [x26, x12, LSL #1]\n" + "inch x12\n" "fmax z30.h, p3/M, z30.h, z18.h\n" - "ld1h { z6.h }, p3/Z, [x7, #7, MUL VL]\n" // Load from weights and bias - "addvl x7, x7, #16\n" + "ld1h { z4.h }, p3/Z, [x15, #5, MUL VL]\n" + "cmp x12, %x[n_channels]\n" "fmin z31.h, p3/M, z31.h, z17.h\n" - "ld1h { z7.h }, p3/Z, [x7, #-8, MUL VL]\n" // Load from weights and bias - "cmp x16, %x[n_channels]\n" + "ld1h { z5.h }, p3/Z, [x15, #6, MUL VL]\n" "fmax z29.h, p3/M, z29.h, z18.h\n" - "ld1h { z8.h }, p3/Z, [x7, #-7, MUL VL]\n" // Load from weights and bias - "addvl x7, x7, #-6\n" + "ld1h { z6.h }, p3/Z, [x15, #7, MUL VL]\n" + "addvl x15, x15, #16\n" "fmax z28.h, p3/M, z28.h, z18.h\n" - "st1h { z31.h }, p0, [x22, x15, LSL #1]\n" - "mov z31.d, z16.d\n" + "ld1h { z7.h }, p3/Z, [x15, #-8, MUL VL]\n" + "fmax z27.h, p3/M, z27.h, z18.h\n" + "ld1h { z8.h }, p3/Z, [x15, #-7, MUL VL]\n" + "addvl x15, x15, #-6\n" "fmin z30.h, p3/M, z30.h, z17.h\n" - "ldr x22, [x6, #0x20]\n" + "st1h { z31.h }, p0, [x22, x11, LSL #1]\n" "fmin z29.h, p3/M, z29.h, z17.h\n" - "st1h { z30.h }, p0, [x21, x15, LSL #1]\n" - "mov z30.d, z16.d\n" - "fmin z28.h, p3/M, z28.h, z17.h\n" - "st1h { z29.h }, p0, [x20, x15, LSL #1]\n" - "mov z29.d, z16.d\n" - "ldr x21, [x6, #0x28]\n" - "fmax z27.h, p3/M, z27.h, z18.h\n" - "ldr x20, [x6, #0x30]\n" + "ldr x22, [x16, #0x20]\n" "fmax z26.h, p3/M, z26.h, z18.h\n" - "st1h { z28.h }, p0, [x19, x15, LSL #1]\n" - "mov z28.d, z16.d\n" - "ldr x19, [x6, #0x38]\n" - "fmax z25.h, p3/M, z25.h, z18.h\n" + "st1h { z30.h }, p0, [x21, x11, LSL #1]\n" + "fmin z28.h, p3/M, z28.h, z17.h\n" "fmin z27.h, p3/M, z27.h, z17.h\n" - "st1h { z27.h }, p0, [x22, x15, LSL #1]\n" - "mov z27.d, z16.d\n" + "st1h { z29.h }, p0, [x20, x11, LSL #1]\n" "fmin z26.h, p3/M, z26.h, z17.h\n" - "ldr x22, [x6, #0x40]\n" - "fmin z25.h, p3/M, z25.h, z17.h\n" - "st1h { z26.h }, p0, [x21, x15, LSL #1]\n" - "mov z26.d, z16.d\n" + "ldr x21, [x16, #0x28]\n" + "fmax z25.h, p3/M, z25.h, z18.h\n" + "ldr x20, [x16, #0x30]\n" "fmax z24.h, p3/M, z24.h, z18.h\n" - "st1h { z25.h }, p0, [x20, x15, LSL #1]\n" - "mov z25.d, z16.d\n" + "st1h { z28.h }, p0, [x19, x11, LSL #1]\n" "fmax z23.h, p3/M, z23.h, z18.h\n" + "st1h { z27.h }, p0, [x22, x11, LSL #1]\n" + "st1h { z26.h }, p0, [x21, x11, LSL #1]\n" + "fmin z25.h, p3/M, z25.h, z17.h\n" + "ldr x19, [x16, #0x38]\n" "fmin z24.h, p3/M, z24.h, z17.h\n" - "st1h { z24.h }, p0, [x19, x15, LSL #1]\n" - "mov z24.d, z16.d\n" + "ldr x22, [x16, #0x40]\n" "fmin z23.h, p3/M, z23.h, z17.h\n" - "st1h { z23.h }, p0, [x22, x15, LSL #1]\n" - "mov z23.d, z16.d\n" + "st1h { z25.h }, p0, [x20, x11, LSL #1]\n" + "st1h { z24.h }, p0, [x19, x11, LSL #1]\n" + "st1h { z23.h }, p0, [x22, x11, LSL #1]\n" "blt 1b\n" "2:" // Channel tail - "fmla z31.h, p3/M, z8.h, z9.h\n" - "ldr x9, [x8, #0x28]\n" - "inch x15\n" - "fmla z30.h, p3/M, z7.h, z9.h\n" - "ldr x28, [x8, #0x30]\n" + "movprfx z31, z16\n fmla z31.h, p3/M, z8.h, z9.h\n" + "ldr x25, [x14, #0x28]\n" + "inch x11\n" + "movprfx z30, z16\n fmla z30.h, p3/M, z7.h, z9.h\n" + "ldr x24, [x14, #0x30]\n" "mov p0.b, p2.b\n" - "fmla z29.h, p3/M, z6.h, z9.h\n" - "ldr x27, [x8, #0x38]\n" - "fmla z28.h, p3/M, z5.h, z9.h\n" - "ldr x26, [x8, #0x40]\n" - "fmla z27.h, p3/M, z4.h, z9.h\n" - "ldr x22, [x8, #0x48]\n" - "fmla z26.h, p3/M, z3.h, z9.h\n" - "ldr x21, [x8, #0x50]\n" - "fmla z25.h, p3/M, z2.h, z9.h\n" - "ldr x20, [x8, #0x58]\n" - "fmla z24.h, p3/M, z1.h, z9.h\n" - "ldr x19, [x8, #0x60]\n" - "fmla z23.h, p3/M, z0.h, z9.h\n" - "ldr x25, [x8, #0x68]\n" + "movprfx z29, z16\n fmla z29.h, p3/M, z6.h, z9.h\n" + "ldr x23, [x14, #0x38]\n" + "movprfx z28, z16\n fmla z28.h, p3/M, z5.h, z9.h\n" + "ldr x10, [x14, #0x40]\n" + "movprfx z27, z16\n fmla z27.h, p3/M, z4.h, z9.h\n" + "ldr x9, [x14, #0x48]\n" + "movprfx z26, z16\n fmla z26.h, p3/M, z3.h, z9.h\n" + "ldr x28, [x14, #0x50]\n" + "movprfx z25, z16\n fmla z25.h, p3/M, z2.h, z9.h\n" + "ldr x27, [x14, #0x58]\n" + "movprfx z24, z16\n fmla z24.h, p3/M, z1.h, z9.h\n" + "ldr x26, [x14, #0x60]\n" + "movprfx z23, z16\n fmla z23.h, p3/M, z0.h, z9.h\n" + "ldr x22, [x16, #0x0]\n" "fmla z31.h, p3/M, z0.h, z10.h\n" - "ld1h { z10.h }, p2/Z, [x22, x17, LSL #1]\n" + "ld1h { z10.h }, p2/Z, [x9, x13, LSL #1]\n" "fmla z29.h, p3/M, z2.h, z11.h\n" - "ld1h { z11.h }, p2/Z, [x28, x17, LSL #1]\n" + "ld1h { z11.h }, p2/Z, [x24, x13, LSL #1]\n" "fmla z25.h, p3/M, z6.h, z12.h\n" - "ld1h { z12.h }, p2/Z, [x9, x17, LSL #1]\n" + "ld1h { z12.h }, p2/Z, [x25, x13, LSL #1]\n" "fmla z30.h, p3/M, z4.h, z13.h\n" - "ldr x24, [x8, #0x70]\n" + "ldr x25, [x14, #0x68]\n" "fmla z31.h, p3/M, z5.h, z13.h\n" - "ldr x23, [x8, #0x78]\n" + "ldr x24, [x14, #0x70]\n" "fmla z29.h, p3/M, z3.h, z13.h\n" - "ldr x14, [x8, #0x80]\n" + "ldr x9, [x14, #0x88]\n" "fmla z28.h, p3/M, z2.h, z13.h\n" - "ldr x13, [x8, #0x88]\n" + "ldr x21, [x16, #0x8]\n" "fmla z27.h, p3/M, z1.h, z13.h\n" - "ldr x12, [x8, #0x90]\n" + "ldr x20, [x16, #0x10]\n" "fmla z26.h, p3/M, z0.h, z13.h\n" - "ld1h { z13.h }, p2/Z, [x27, x17, LSL #1]\n" + "ld1h { z13.h }, p2/Z, [x23, x13, LSL #1]\n" "fmla z23.h, p3/M, z8.h, z12.h\n" - "ld1h { z12.h }, p2/Z, [x26, x17, LSL #1]\n" + "ld1h { z12.h }, p2/Z, [x10, x13, LSL #1]\n" "fmla z31.h, p3/M, z7.h, z11.h\n" - "ldr x11, [x8, #0x98]\n" + "ldr x23, [x14, #0x78]\n" "fmla z30.h, p3/M, z6.h, z11.h\n" - "ldr x10, [x8, #0xa0]\n" + "ldr x10, [x14, #0x80]\n" "fmla z28.h, p3/M, z4.h, z11.h\n" - "ldr x9, [x8, #0xa8]\n" + "ldr x19, [x16, #0x18]\n" "fmla z27.h, p3/M, z3.h, z11.h\n" - "ldr x28, [x8, #0xb0]\n" "fmla z25.h, p3/M, z1.h, z11.h\n" - "ldr x27, [x8, #0xb8]\n" "fmla z24.h, p3/M, z0.h, z11.h\n" - "ld1h { z11.h }, p2/Z, [x21, x17, LSL #1]\n" + "ld1h { z11.h }, p2/Z, [x28, x13, LSL #1]\n" "fmla z31.h, p3/M, z1.h, z13.h\n" - "ldr x26, [x8, #0xc0]\n" + "ldr x28, [x14, #0x90]\n" "fmla z30.h, p3/M, z0.h, z13.h\n" - "ld1h { z13.h }, p2/Z, [x20, x17, LSL #1]\n" + "ld1h { z13.h }, p2/Z, [x27, x13, LSL #1]\n" "fmla z29.h, p3/M, z1.h, z12.h\n" - "ldr x22, [x6, #0x0]\n" + "ldr x27, [x14, #0x98]\n" "fmla z27.h, p3/M, z5.h, z10.h\n" - "ldr x21, [x6, #0x8]\n" "fmla z26.h, p3/M, z4.h, z10.h\n" - "ldr x20, [x6, #0x10]\n" "fmla z30.h, p3/M, z2.h, z12.h\n" - "ld1h { z12.h }, p2/Z, [x19, x17, LSL #1]\n" + "ld1h { z12.h }, p2/Z, [x26, x13, LSL #1]\n" "fmla z29.h, p3/M, z7.h, z10.h\n" - "ldr x19, [x6, #0x18]\n" + "ldr x26, [x14, #0xa0]\n" "fmla z24.h, p3/M, z2.h, z10.h\n" "fmla z23.h, p3/M, z1.h, z10.h\n" "fmla z30.h, p3/M, z8.h, z10.h\n" - "ld1h { z10.h }, p2/Z, [x25, x17, LSL #1]\n" + "ld1h { z10.h }, p2/Z, [x25, x13, LSL #1]\n" "fmla z31.h, p3/M, z3.h, z11.h\n" + "ldr x25, [x14, #0xa8]\n" "fmla z28.h, p3/M, z0.h, z11.h\n" - "ld1h { z11.h }, p2/Z, [x24, x17, LSL #1]\n" + "ld1h { z11.h }, p2/Z, [x24, x13, LSL #1]\n" "fmla z29.h, p3/M, z5.h, z13.h\n" + "ldr x24, [x14, #0xb0]\n" "fmla z26.h, p3/M, z2.h, z13.h\n" - "ld1h { z13.h }, p2/Z, [x23, x17, LSL #1]\n" + "ld1h { z13.h }, p2/Z, [x23, x13, LSL #1]\n" "fmla z25.h, p3/M, z3.h, z12.h\n" + "ldr x23, [x14, #0xb8]\n" "fmla z28.h, p3/M, z6.h, z12.h\n" - "ld1h { z12.h }, p2/Z, [x14, x17, LSL #1]\n" + "ld1h { z12.h }, p2/Z, [x10, x13, LSL #1]\n" "fmla z27.h, p3/M, z7.h, z10.h\n" + "ldr x10, [x14, #0xc0]\n" "fmla z26.h, p3/M, z6.h, z10.h\n" "fmla z25.h, p3/M, z5.h, z10.h\n" "fmla z28.h, p3/M, z8.h, z10.h\n" @@ -412,36 +394,36 @@ void sve_fp16_nhwc_3x3_s1_output3x3_mla_depthfirst_indirect_impl( "fmla z26.h, p3/M, z8.h, z11.h\n" "fmla z25.h, p3/M, z7.h, z13.h\n" "fmla z24.h, p3/M, z6.h, z13.h\n" - "ld1h { z13.h }, p2/Z, [x12, x17, LSL #1]\n" + "ld1h { z13.h }, p2/Z, [x28, x13, LSL #1]\n" "fmla z23.h, p3/M, z5.h, z11.h\n" - "ld1h { z11.h }, p2/Z, [x13, x17, LSL #1]\n" + "ld1h { z11.h }, p2/Z, [x9, x13, LSL #1]\n" "fmla z31.h, p3/M, z4.h, z12.h\n" "fmla z30.h, p3/M, z3.h, z12.h\n" "fmla z28.h, p3/M, z1.h, z12.h\n" "fmla z27.h, p3/M, z0.h, z12.h\n" - "ld1h { z12.h }, p2/Z, [x11, x17, LSL #1]\n" + "ld1h { z12.h }, p2/Z, [x27, x13, LSL #1]\n" "fmla z29.h, p3/M, z4.h, z11.h\n" "fmla z30.h, p3/M, z5.h, z11.h\n" "fmla z26.h, p3/M, z1.h, z11.h\n" "fmla z27.h, p3/M, z2.h, z11.h\n" - "ld1h { z11.h }, p2/Z, [x10, x17, LSL #1]\n" + "ld1h { z11.h }, p2/Z, [x26, x13, LSL #1]\n" "fmla z24.h, p3/M, z8.h, z13.h\n" "fmla z23.h, p3/M, z7.h, z13.h\n" - "ld1h { z13.h }, p2/Z, [x9, x17, LSL #1]\n" + "ld1h { z13.h }, p2/Z, [x25, x13, LSL #1]\n" "fmla z28.h, p3/M, z7.h, z12.h\n" "fmla z27.h, p3/M, z6.h, z12.h\n" "fmla z25.h, p3/M, z4.h, z12.h\n" "fmla z24.h, p3/M, z3.h, z12.h\n" - "ld1h { z12.h }, p2/Z, [x28, x17, LSL #1]\n" + "ld1h { z12.h }, p2/Z, [x24, x13, LSL #1]\n" "fmla z31.h, p3/M, z2.h, z11.h\n" "fmla z30.h, p3/M, z1.h, z11.h\n" "fmla z29.h, p3/M, z0.h, z11.h\n" - "ld1h { z11.h }, p2/Z, [x27, x17, LSL #1]\n" + "ld1h { z11.h }, p2/Z, [x23, x13, LSL #1]\n" "fmla z27.h, p3/M, z8.h, z13.h\n" "fmla z26.h, p3/M, z7.h, z13.h\n" "fmla z24.h, p3/M, z5.h, z13.h\n" "fmla z23.h, p3/M, z4.h, z13.h\n" - "ld1h { z13.h }, p2/Z, [x26, x17, LSL #1]\n" + "ld1h { z13.h }, p2/Z, [x10, x13, LSL #1]\n" "fmla z31.h, p3/M, z6.h, z12.h\n" "fmla z28.h, p3/M, z3.h, z12.h\n" "fmla z25.h, p3/M, z0.h, z12.h\n" @@ -455,41 +437,41 @@ void sve_fp16_nhwc_3x3_s1_output3x3_mla_depthfirst_indirect_impl( "fmax z30.h, p3/M, z30.h, z18.h\n" "fmax z29.h, p3/M, z29.h, z18.h\n" "fmin z31.h, p3/M, z31.h, z17.h\n" - "st1h { z31.h }, p0, [x22, x15, LSL #1]\n" + "st1h { z31.h }, p0, [x22, x11, LSL #1]\n" "fmin z30.h, p3/M, z30.h, z17.h\n" "fmin z29.h, p3/M, z29.h, z17.h\n" - "ldr x22, [x6, #0x20]\n" + "ldr x22, [x16, #0x20]\n" "fmax z28.h, p3/M, z28.h, z18.h\n" - "st1h { z30.h }, p0, [x21, x15, LSL #1]\n" + "st1h { z30.h }, p0, [x21, x11, LSL #1]\n" "fmax z27.h, p3/M, z27.h, z18.h\n" "fmax z26.h, p3/M, z26.h, z18.h\n" - "st1h { z29.h }, p0, [x20, x15, LSL #1]\n" + "st1h { z29.h }, p0, [x20, x11, LSL #1]\n" "fmin z28.h, p3/M, z28.h, z17.h\n" - "ldr x21, [x6, #0x28]\n" + "ldr x21, [x16, #0x28]\n" "fmax z25.h, p3/M, z25.h, z18.h\n" - "ldr x20, [x6, #0x30]\n" + "ldr x20, [x16, #0x30]\n" "fmax z24.h, p3/M, z24.h, z18.h\n" - "st1h { z28.h }, p0, [x19, x15, LSL #1]\n" + "st1h { z28.h }, p0, [x19, x11, LSL #1]\n" "fmin z27.h, p3/M, z27.h, z17.h\n" "fmin z26.h, p3/M, z26.h, z17.h\n" - "ldr x19, [x6, #0x38]\n" + "ldr x19, [x16, #0x38]\n" "fmin z25.h, p3/M, z25.h, z17.h\n" - "st1h { z27.h }, p0, [x22, x15, LSL #1]\n" + "st1h { z27.h }, p0, [x22, x11, LSL #1]\n" "fmin z24.h, p3/M, z24.h, z17.h\n" "fmax z23.h, p3/M, z23.h, z18.h\n" - "st1h { z26.h }, p0, [x21, x15, LSL #1]\n" - "st1h { z25.h }, p0, [x20, x15, LSL #1]\n" + "st1h { z26.h }, p0, [x21, x11, LSL #1]\n" + "st1h { z25.h }, p0, [x20, x11, LSL #1]\n" "fmin z23.h, p3/M, z23.h, z17.h\n" - "st1h { z24.h }, p0, [x19, x15, LSL #1]\n" - "ldr x22, [x6, #0x40]\n" - "st1h { z23.h }, p0, [x22, x15, LSL #1]\n" + "st1h { z24.h }, p0, [x19, x11, LSL #1]\n" + "ldr x22, [x16, #0x40]\n" + "st1h { z23.h }, p0, [x22, x11, LSL #1]\n" : : [n_channels] "r" ((unsigned long) n_channels), [offsetof_Args_inptrs] "I" (offsetof(Args, inptrs)), [offsetof_args_max] "I" (offsetof(Args, max)), [offsetof_args_min] "I" (offsetof(Args, min)), [offsetof_args_outptrs] "I" (offsetof(Args, outptrs)), [offsetof_args_params] "I" (offsetof(Args, params)), [params_struct] "r" (¶ms_struct) - : "cc", "memory", "p0", "p1", "p2", "p3", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z16", "z17", "z18", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + : "cc", "memory", "p0", "p1", "p2", "p3", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z16", "z17", "z18", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" ); } } // namespace depthwise } // namespace arm_conv -#endif // defined(ARM_COMPUTE_ENABLE_SVE) && defined(__ARM_FP16_ARGS) +#endif // __aarch64__ && defined(ARM_COMPUTE_ENABLE_SVE) && defined(__ARM_FP16_ARGS) -- cgit v1.2.1