From ba209750abc1ac7e42bab9fef5db284384d70fb3 Mon Sep 17 00:00:00 2001 From: Michael Tyler Date: Thu, 15 Dec 2022 12:39:29 +0000 Subject: Update CPU kernels to remove x19 Resolves: COMPMID-5805 Signed-off-by: Michael Tyler Change-Id: I250f64531e209625e4ff176dd5a552c1c34bc484 Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/8909 Tested-by: Arm Jenkins Comments-Addressed: Arm Jenkins Reviewed-by: Gunes Bayir Reviewed-by: Viet-Hoa Do Benchmark: Arm Jenkins --- .../generic.cpp | 247 ++++++++++----------- 1 file changed, 123 insertions(+), 124 deletions(-) (limited to 'src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_packed_to_nhwc_5x5_s1_with_multiplier_output2x4_mla_depthfirst/generic.cpp') diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_packed_to_nhwc_5x5_s1_with_multiplier_output2x4_mla_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_packed_to_nhwc_5x5_s1_with_multiplier_output2x4_mla_depthfirst/generic.cpp index 67fc09b2ee..50848cc2e8 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_packed_to_nhwc_5x5_s1_with_multiplier_output2x4_mla_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_packed_to_nhwc_5x5_s1_with_multiplier_output2x4_mla_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021, 2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -42,56 +42,56 @@ void a64_fp32_packed_to_nhwc_5x5_s1_with_multiplier_output2x4_mla_depthfirst_imp const float minmax_vals[2] = { activation_min, activation_max }; __asm__ __volatile__( - "ldp x13, x12, [%x[outptrs], #0x0]\n" - "add x11, %x[clamps], #0x4\n" - "ldp x10, x9, [%x[outptrs], #0x10]\n" - "mov x28, #0x0\n" - "ldp x27, x26, [%x[outptrs], #0x20]\n" - "mov x25, #0x0\n" - "ldp x24, x23, [%x[outptrs], #0x30]\n" - "lsr x22, %x[channel_multiplier], #0x2\n" + "ld1r { v21.4s }, [%x[clamps]]\n" "ldr x21, [%x[inptrs], #0x0]\n" - "ldr x20, [%x[inptrs], #0x8]\n" - "ldr x19, [%x[inptrs], #0x10]\n" + "lsr x22, %x[channel_multiplier], #0x2\n" + "add x20, %x[clamps], #0x4\n" "ldr q0, [x21, #0x0]\n" "ldr q1, [x21, #0x10]\n" + "mov x21, #0x0\n" + "mov x13, #0x0\n" + "ld1r { v20.4s }, [x20]\n" + "ldr x20, [%x[inptrs], #0x8]\n" "ldr q2, [x20, #0x0]\n" "ldr q3, [x20, #0x10]\n" - "ldr q4, [x19, #0x0]\n" - "ldr q5, [x19, #0x10]\n" - "ldr x21, [%x[inptrs], #0x18]\n" + "ldr x20, [%x[inptrs], #0x10]\n" + "ldr q4, [x20, #0x0]\n" + "ldr q5, [x20, #0x10]\n" + "ldr x20, [%x[inptrs], #0x18]\n" + "ldr q6, [x20, #0x0]\n" + "ldr q7, [x20, #0x10]\n" "ldr x20, [%x[inptrs], #0x20]\n" - "ldr x19, [%x[inptrs], #0x28]\n" - "ldr q6, [x21, #0x0]\n" - "ldr q7, [x21, #0x10]\n" "ldr q8, [x20, #0x0]\n" "ldr q9, [x20, #0x10]\n" - "ldr q10, [x19, #0x0]\n" - "ldr q11, [x19, #0x10]\n" - "ld1r { v21.4s }, [%x[clamps]]\n" - "ld1r { v20.4s }, [x11]\n" + "ldr x20, [%x[inptrs], #0x28]\n" + "ldr q10, [x20, #0x0]\n" + "ldr q11, [x20, #0x10]\n" + "ldp x12, x11, [%x[outptrs], #0x0]\n" + "ldp x10, x9, [%x[outptrs], #0x10]\n" + "ldp x28, x27, [%x[outptrs], #0x20]\n" + "ldp x26, x25, [%x[outptrs], #0x30]\n" "cbz x22, 3f\n" "ldr q12, [%x[params], #0x0]\n" - "mov v13.16b, v12.16b\n" "ldr q31, [%x[params], #0x10]\n" "subs x22, x22, #0x1\n" - "mov v14.16b, v12.16b\n" + "mov v13.16b, v12.16b\n" "ldr q30, [%x[params], #0x20]\n" - "mov v15.16b, v12.16b\n" "ldr q29, [%x[params], #0x30]\n" - "mov v16.16b, v12.16b\n" + "mov v14.16b, v12.16b\n" + "mov v15.16b, v12.16b\n" "ldr q28, [%x[params], #0x40]\n" - "mov v17.16b, v12.16b\n" "ldr q27, [%x[params], #0x50]\n" - "add %x[params], %x[params], #0x60\n" + "mov v16.16b, v12.16b\n" + "mov v17.16b, v12.16b\n" "mov v18.16b, v12.16b\n" "mov v19.16b, v12.16b\n" + "add %x[params], %x[params], #0x60\n" "beq 2f\n" "1:" // Output channel complete vector loop "fmla v12.4s, v31.4s, v0.s[0]\n" - "add x28, x28, #0x4\n" "fmla v13.4s, v31.4s, v0.s[1]\n" "subs x22, x22, #0x1\n" + "add x21, x21, #0x4\n" "fmla v14.4s, v31.4s, v0.s[2]\n" "fmla v15.4s, v31.4s, v0.s[3]\n" "fmla v16.4s, v31.4s, v2.s[0]\n" @@ -308,46 +308,46 @@ void a64_fp32_packed_to_nhwc_5x5_s1_with_multiplier_output2x4_mla_depthfirst_imp "ldr q28, [%x[params], #0x180]\n" "fmla v12.4s, v27.4s, v9.s[0]\n" "fmla v13.4s, v27.4s, v9.s[1]\n" + "fmin v12.4s, v12.4s, v20.4s\n" "fmla v14.4s, v27.4s, v9.s[2]\n" "fmla v15.4s, v27.4s, v9.s[3]\n" + "fmax v12.4s, v12.4s, v21.4s\n" + "str q12, [x12, x13]\n" + "ldr q12, [%x[params], #0x140]\n" "fmla v16.4s, v27.4s, v11.s[0]\n" "fmla v17.4s, v27.4s, v11.s[1]\n" + "fmin v13.4s, v13.4s, v20.4s\n" "fmla v18.4s, v27.4s, v11.s[2]\n" "fmla v19.4s, v27.4s, v11.s[3]\n" "ldr q27, [%x[params], #0x190]\n" - "fmin v12.4s, v12.4s, v20.4s\n" - "fmin v13.4s, v13.4s, v20.4s\n" "fmin v14.4s, v14.4s, v20.4s\n" - "fmax v12.4s, v12.4s, v21.4s\n" - "str q12, [x13, x25]\n" - "fmax v13.4s, v13.4s, v21.4s\n" - "fmax v14.4s, v14.4s, v21.4s\n" - "ldr q12, [%x[params], #0x140]\n" - "add %x[params], %x[params], #0x1a0\n" "fmin v15.4s, v15.4s, v20.4s\n" - "str q13, [x12, x25]\n" "fmin v16.4s, v16.4s, v20.4s\n" + "add %x[params], %x[params], #0x1a0\n" "fmin v17.4s, v17.4s, v20.4s\n" - "str q14, [x10, x25]\n" "fmin v18.4s, v18.4s, v20.4s\n" + "fmin v19.4s, v19.4s, v20.4s\n" + "fmax v13.4s, v13.4s, v21.4s\n" + "str q13, [x11, x13]\n" + "fmax v14.4s, v14.4s, v21.4s\n" "fmax v15.4s, v15.4s, v21.4s\n" - "str q15, [x9, x25]\n" + "str q14, [x10, x13]\n" "fmax v16.4s, v16.4s, v21.4s\n" "fmax v17.4s, v17.4s, v21.4s\n" - "str q16, [x27, x25]\n" + "str q15, [x9, x13]\n" "fmax v18.4s, v18.4s, v21.4s\n" - "fmin v19.4s, v19.4s, v20.4s\n" - "str q17, [x26, x25]\n" - "mov v13.16b, v12.16b\n" - "str q18, [x24, x25]\n" "fmax v19.4s, v19.4s, v21.4s\n" + "str q16, [x28, x13]\n" + "str q17, [x27, x13]\n" + "mov v13.16b, v12.16b\n" "mov v14.16b, v12.16b\n" - "str q19, [x23, x25]\n" + "str q18, [x26, x13]\n" "mov v15.16b, v12.16b\n" - "add x25, x25, #0x10\n" "mov v16.16b, v12.16b\n" + "str q19, [x25, x13]\n" "mov v17.16b, v12.16b\n" "mov v18.16b, v12.16b\n" + "add x13, x13, #0x10\n" "mov v19.16b, v12.16b\n" "bgt 1b\n" "2:" // Output channel complete vector tail @@ -566,51 +566,51 @@ void a64_fp32_packed_to_nhwc_5x5_s1_with_multiplier_output2x4_mla_depthfirst_imp "fmla v19.4s, v28.4s, v11.s[2]\n" "fmla v12.4s, v27.4s, v9.s[0]\n" "fmla v13.4s, v27.4s, v9.s[1]\n" + "fmin v12.4s, v12.4s, v20.4s\n" "fmla v14.4s, v27.4s, v9.s[2]\n" "fmla v15.4s, v27.4s, v9.s[3]\n" + "fmin v13.4s, v13.4s, v20.4s\n" "fmla v16.4s, v27.4s, v11.s[0]\n" "fmla v17.4s, v27.4s, v11.s[1]\n" + "fmin v14.4s, v14.4s, v20.4s\n" "fmla v18.4s, v27.4s, v11.s[2]\n" "fmla v19.4s, v27.4s, v11.s[3]\n" - "fmin v12.4s, v12.4s, v20.4s\n" - "fmin v13.4s, v13.4s, v20.4s\n" - "fmin v14.4s, v14.4s, v20.4s\n" - "fmax v12.4s, v12.4s, v21.4s\n" - "str q12, [x13, x25]\n" - "fmax v13.4s, v13.4s, v21.4s\n" - "fmax v14.4s, v14.4s, v21.4s\n" - "str q13, [x12, x25]\n" "fmin v15.4s, v15.4s, v20.4s\n" "fmin v16.4s, v16.4s, v20.4s\n" - "str q14, [x10, x25]\n" "fmin v17.4s, v17.4s, v20.4s\n" "fmin v18.4s, v18.4s, v20.4s\n" + "fmin v19.4s, v19.4s, v20.4s\n" + "fmax v12.4s, v12.4s, v21.4s\n" + "fmax v13.4s, v13.4s, v21.4s\n" + "str q12, [x12, x13]\n" + "fmax v14.4s, v14.4s, v21.4s\n" "fmax v15.4s, v15.4s, v21.4s\n" - "str q15, [x9, x25]\n" + "str q13, [x11, x13]\n" "fmax v16.4s, v16.4s, v21.4s\n" "fmax v17.4s, v17.4s, v21.4s\n" - "str q16, [x27, x25]\n" + "str q14, [x10, x13]\n" "fmax v18.4s, v18.4s, v21.4s\n" - "fmin v19.4s, v19.4s, v20.4s\n" - "str q17, [x26, x25]\n" "fmax v19.4s, v19.4s, v21.4s\n" - "str q18, [x24, x25]\n" - "str q19, [x23, x25]\n" - "add x25, x25, #0x10\n" + "str q15, [x9, x13]\n" + "str q16, [x28, x13]\n" + "str q17, [x27, x13]\n" + "str q18, [x26, x13]\n" + "str q19, [x25, x13]\n" + "add x13, x13, #0x10\n" "3:" // Output channel oddments "tst %x[channel_multiplier], #0x3\n" "beq 6f\n" "ldr q12, [%x[params], #0x0]\n" - "mov v13.16b, v12.16b\n" "ldr q31, [%x[params], #0x10]\n" + "mov v13.16b, v12.16b\n" "mov v14.16b, v12.16b\n" "ldr q30, [%x[params], #0x20]\n" - "mov v15.16b, v12.16b\n" "ldr q29, [%x[params], #0x30]\n" + "mov v15.16b, v12.16b\n" "mov v16.16b, v12.16b\n" "ldr q28, [%x[params], #0x40]\n" - "mov v17.16b, v12.16b\n" "ldr q27, [%x[params], #0x50]\n" + "mov v17.16b, v12.16b\n" "mov v18.16b, v12.16b\n" "mov v19.16b, v12.16b\n" "fmla v12.4s, v31.4s, v0.s[0]\n" @@ -828,89 +828,88 @@ void a64_fp32_packed_to_nhwc_5x5_s1_with_multiplier_output2x4_mla_depthfirst_imp "fmla v19.4s, v28.4s, v11.s[2]\n" "fmla v12.4s, v27.4s, v9.s[0]\n" "fmla v13.4s, v27.4s, v9.s[1]\n" + "fmin v12.4s, v12.4s, v20.4s\n" "fmla v14.4s, v27.4s, v9.s[2]\n" "fmla v15.4s, v27.4s, v9.s[3]\n" + "fmin v13.4s, v13.4s, v20.4s\n" "fmla v16.4s, v27.4s, v11.s[0]\n" "fmla v17.4s, v27.4s, v11.s[1]\n" + "fmin v14.4s, v14.4s, v20.4s\n" "fmla v18.4s, v27.4s, v11.s[2]\n" "fmla v19.4s, v27.4s, v11.s[3]\n" - "fmin v12.4s, v12.4s, v20.4s\n" - "fmin v13.4s, v13.4s, v20.4s\n" - "fmin v14.4s, v14.4s, v20.4s\n" - "fmax v12.4s, v12.4s, v21.4s\n" - "fmax v13.4s, v13.4s, v21.4s\n" - "fmax v14.4s, v14.4s, v21.4s\n" "fmin v15.4s, v15.4s, v20.4s\n" "fmin v16.4s, v16.4s, v20.4s\n" "fmin v17.4s, v17.4s, v20.4s\n" + "fmin v18.4s, v18.4s, v20.4s\n" + "fmin v19.4s, v19.4s, v20.4s\n" + "fmax v12.4s, v12.4s, v21.4s\n" + "fmax v13.4s, v13.4s, v21.4s\n" + "fmax v14.4s, v14.4s, v21.4s\n" "fmax v15.4s, v15.4s, v21.4s\n" "fmax v16.4s, v16.4s, v21.4s\n" "fmax v17.4s, v17.4s, v21.4s\n" - "fmin v18.4s, v18.4s, v20.4s\n" - "fmin v19.4s, v19.4s, v20.4s\n" "fmax v18.4s, v18.4s, v21.4s\n" "fmax v19.4s, v19.4s, v21.4s\n" "tbz %x[channel_multiplier], #1, 4f\n" - "add x19, x13, x25\n" - "st1 { v12.d }[0], [x19]\n" - "add x19, x12, x25\n" - "st1 { v13.d }[0], [x19]\n" - "add x19, x10, x25\n" - "st1 { v14.d }[0], [x19]\n" - "add x19, x9, x25\n" - "st1 { v15.d }[0], [x19]\n" - "add x19, x27, x25\n" - "st1 { v16.d }[0], [x19]\n" - "add x19, x26, x25\n" - "st1 { v17.d }[0], [x19]\n" - "add x19, x24, x25\n" - "st1 { v18.d }[0], [x19]\n" - "add x19, x23, x25\n" - "st1 { v19.d }[0], [x19]\n" - "add x25, x25, #0x8\n" + "add x20, x12, x13\n" + "add x21, x11, x13\n" + "st1 { v12.d }[0], [x20]\n" + "add x20, x10, x13\n" + "add x24, x9, x13\n" + "st1 { v13.d }[0], [x21]\n" + "add x23, x28, x13\n" + "add x22, x27, x13\n" + "st1 { v14.d }[0], [x20]\n" + "add x21, x26, x13\n" + "add x20, x25, x13\n" + "st1 { v15.d }[0], [x24]\n" + "st1 { v16.d }[0], [x23]\n" + "add x13, x13, #0x8\n" + "st1 { v17.d }[0], [x22]\n" + "st1 { v18.d }[0], [x21]\n" + "st1 { v19.d }[0], [x20]\n" "tbz %x[channel_multiplier], #0, 5f\n" - "add x19, x13, x25\n" - "st1 { v12.s }[2], [x19]\n" - "add x19, x12, x25\n" - "st1 { v13.s }[2], [x19]\n" - "add x19, x10, x25\n" - "st1 { v14.s }[2], [x19]\n" - "add x19, x9, x25\n" - "st1 { v15.s }[2], [x19]\n" - "add x19, x27, x25\n" - "st1 { v16.s }[2], [x19]\n" - "add x19, x26, x25\n" - "st1 { v17.s }[2], [x19]\n" - "add x19, x24, x25\n" - "st1 { v18.s }[2], [x19]\n" - "add x19, x23, x25\n" - "st1 { v19.s }[2], [x19]\n" + "add x20, x12, x13\n" + "add x21, x11, x13\n" + "st1 { v12.s }[2], [x20]\n" + "add x20, x10, x13\n" + "add x24, x9, x13\n" + "st1 { v13.s }[2], [x21]\n" + "add x23, x28, x13\n" + "add x22, x27, x13\n" + "st1 { v14.s }[2], [x20]\n" + "add x21, x26, x13\n" + "add x20, x25, x13\n" + "st1 { v15.s }[2], [x24]\n" + "st1 { v16.s }[2], [x23]\n" + "st1 { v17.s }[2], [x22]\n" + "st1 { v18.s }[2], [x21]\n" + "st1 { v19.s }[2], [x20]\n" "b 5f\n" "4:" // Output channel oddments: Store: Bit 1: Unset - "tbz %x[channel_multiplier], #0, 5f\n" - "add x19, x13, x25\n" - "st1 { v12.s }[0], [x19]\n" - "add x19, x12, x25\n" - "st1 { v13.s }[0], [x19]\n" - "add x19, x10, x25\n" - "st1 { v14.s }[0], [x19]\n" - "add x19, x9, x25\n" - "st1 { v15.s }[0], [x19]\n" - "add x19, x27, x25\n" - "st1 { v16.s }[0], [x19]\n" - "add x19, x26, x25\n" - "st1 { v17.s }[0], [x19]\n" - "add x19, x24, x25\n" - "st1 { v18.s }[0], [x19]\n" - "add x19, x23, x25\n" - "st1 { v19.s }[0], [x19]\n" + "add x20, x12, x13\n" + "add x21, x11, x13\n" + "st1 { v12.s }[0], [x20]\n" + "add x20, x10, x13\n" + "add x24, x9, x13\n" + "st1 { v13.s }[0], [x21]\n" + "add x23, x28, x13\n" + "add x22, x27, x13\n" + "st1 { v14.s }[0], [x20]\n" + "add x21, x26, x13\n" + "add x20, x25, x13\n" + "st1 { v15.s }[0], [x24]\n" + "st1 { v16.s }[0], [x23]\n" + "st1 { v17.s }[0], [x22]\n" + "st1 { v18.s }[0], [x21]\n" + "st1 { v19.s }[0], [x20]\n" "5:" // Output channel oddments: Store: Bit 1: End "6:" // End : [params] "+&r" (params) : [channel_multiplier] "r" (n_output_channels), [clamps] "r" (minmax_vals), [inptrs] "r" (inptrs), [outptrs] "r" (outptrs) - : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v27", "v28", "v29", "v30", "v31", "x9", "x10", "x11", "x12", "x13", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" + : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v27", "v28", "v29", "v30", "v31", "x9", "x10", "x11", "x12", "x13", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" ); } -- cgit v1.2.1