From d02d5edfa15ba6c04a9986a8a362a945cb38ac31 Mon Sep 17 00:00:00 2001 From: Michele Di Giorgio Date: Fri, 22 Jan 2021 09:47:04 +0000 Subject: Integrate improved CPU depthwise convolution kernels * Replace assembly kernels for depthwise convolution with more optimized ones. * Add int8 assembly kernels. * Fix implicit padding on optimized kernels Resolves: COMPMID-3867, COMPMID-4361 Change-Id: I0b0867e05f61be4f368f62190d55e14d0ab3ebf2 Signed-off-by: Michele Di Giorgio Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/5622 Tested-by: Arm Jenkins Reviewed-by: Georgios Pinitas --- .../generic.cpp | 379 +++++++++++++++++++++ 1 file changed, 379 insertions(+) create mode 100644 src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_generic_output9_mla_depthfirst/generic.cpp (limited to 'src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_generic_output9_mla_depthfirst/generic.cpp') diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_generic_output9_mla_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_generic_output9_mla_depthfirst/generic.cpp new file mode 100644 index 0000000000..e8e817e9cc --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_generic_output9_mla_depthfirst/generic.cpp @@ -0,0 +1,379 @@ +/* + * Copyright (c) 2021 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include +#include + +namespace arm_conv { +namespace depthwise { + +void a64_fp32_nhwc_generic_output9_mla_depthfirst_impl( + const float *const *const inptrs, + float *const *const outptrs, + const void *params, + const void *bias, + const unsigned int n_points, + const unsigned int n_channels, + const float activation_min, + const float activation_max +) +{ + const float minmax_vals[2] = { activation_min, activation_max }; + + __asm__ __volatile__( + "ld1r { v4.4s }, [%x[minmax_vals]]\n" + "add x19, %x[minmax_vals], #0x4\n" + "mov x11, #0x0\n" + "ld1r { v3.4s }, [x19]\n" + "lsr x10, %x[n_channels], #0x2\n" + "cbz x10, 5f\n" + "1:" // Channel loop + "movi v25.16b, #0x0\n" + "cbz %x[bias], 2f\n" + "ldr q25, [%x[bias], x11]\n" + "2:" // Channel loop: Load bias: Done + "mov v24.16b, v25.16b\n" + "ldr q23, [%x[params], #0x0]\n" + "mov x20, %x[inptrs]\n" + "mov v22.16b, v25.16b\n" + "ldp x9, x28, [x20], #0x10\n" + "subs x19, %x[n_points], #0x1\n" + "mov v21.16b, v25.16b\n" + "ldr q2, [x9, x11]\n" + "mov v20.16b, v25.16b\n" + "add %x[params], %x[params], #0x10\n" + "mov v19.16b, v25.16b\n" + "ldr q1, [x28, x11]\n" + "mov v18.16b, v25.16b\n" + "ldp x27, x26, [x20], #0x10\n" + "mov v17.16b, v25.16b\n" + "ldr q0, [x27, x11]\n" + "mov v16.16b, v25.16b\n" + "ldr q31, [x26, x11]\n" + "ldp x25, x24, [x20], #0x10\n" + "ldr q30, [x25, x11]\n" + "ldr q29, [x24, x11]\n" + "ldp x23, x22, [x20], #0x10\n" + "ldr q28, [x23, x11]\n" + "ldr q27, [x22, x11]\n" + "ldr x21, [x20], #0x8\n" + "ldr q26, [x21, x11]\n" + "ble 4f\n" + "3:" // Channel loop: Planar loop + "fmla v25.4s, v2.4s, v23.4s\n" + "ldp x9, x28, [x20], #0x10\n" + "subs x19, x19, #0x1\n" + "fmla v24.4s, v1.4s, v23.4s\n" + "ldr q2, [x9, x11]\n" + "fmla v22.4s, v0.4s, v23.4s\n" + "fmla v21.4s, v31.4s, v23.4s\n" + "ldr q1, [x28, x11]\n" + "fmla v20.4s, v30.4s, v23.4s\n" + "ldp x27, x26, [x20], #0x10\n" + "fmla v19.4s, v29.4s, v23.4s\n" + "fmla v18.4s, v28.4s, v23.4s\n" + "ldr q0, [x27, x11]\n" + "fmla v17.4s, v27.4s, v23.4s\n" + "fmla v16.4s, v26.4s, v23.4s\n" + "ldr q23, [%x[params], #0x0]\n" + "add %x[params], %x[params], #0x10\n" + "ldr q31, [x26, x11]\n" + "ldp x25, x24, [x20], #0x10\n" + "ldr q30, [x25, x11]\n" + "ldr q29, [x24, x11]\n" + "ldp x23, x22, [x20], #0x10\n" + "ldr q28, [x23, x11]\n" + "ldr q27, [x22, x11]\n" + "ldr x21, [x20], #0x8\n" + "ldr q26, [x21, x11]\n" + "bgt 3b\n" + "4:" // Channel loop: Planar tail + "fmla v25.4s, v2.4s, v23.4s\n" + "ldp x27, x26, [%x[outptrs], #0x0]\n" + "fmla v24.4s, v1.4s, v23.4s\n" + "ldp x25, x24, [%x[outptrs], #0x10]\n" + "fmla v22.4s, v0.4s, v23.4s\n" + "ldp x23, x22, [%x[outptrs], #0x20]\n" + "fmla v21.4s, v31.4s, v23.4s\n" + "ldp x21, x20, [%x[outptrs], #0x30]\n" + "fmla v20.4s, v30.4s, v23.4s\n" + "ldr x19, [%x[outptrs], #0x40]\n" + "fmla v19.4s, v29.4s, v23.4s\n" + "fmla v18.4s, v28.4s, v23.4s\n" + "fmla v17.4s, v27.4s, v23.4s\n" + "fmla v16.4s, v26.4s, v23.4s\n" + "fmax v25.4s, v25.4s, v4.4s\n" + "fmax v24.4s, v24.4s, v4.4s\n" + "fmax v22.4s, v22.4s, v4.4s\n" + "fmin v25.4s, v25.4s, v3.4s\n" + "str q25, [x27, x11]\n" + "fmin v24.4s, v24.4s, v3.4s\n" + "fmin v22.4s, v22.4s, v3.4s\n" + "str q24, [x26, x11]\n" + "fmax v21.4s, v21.4s, v4.4s\n" + "fmax v20.4s, v20.4s, v4.4s\n" + "str q22, [x25, x11]\n" + "fmax v19.4s, v19.4s, v4.4s\n" + "fmax v18.4s, v18.4s, v4.4s\n" + "fmin v21.4s, v21.4s, v3.4s\n" + "str q21, [x24, x11]\n" + "fmin v20.4s, v20.4s, v3.4s\n" + "fmin v19.4s, v19.4s, v3.4s\n" + "str q20, [x23, x11]\n" + "fmin v18.4s, v18.4s, v3.4s\n" + "fmax v17.4s, v17.4s, v4.4s\n" + "str q19, [x22, x11]\n" + "fmax v16.4s, v16.4s, v4.4s\n" + "str q18, [x21, x11]\n" + "fmin v17.4s, v17.4s, v3.4s\n" + "fmin v16.4s, v16.4s, v3.4s\n" + "str q17, [x20, x11]\n" + "str q16, [x19, x11]\n" + "add x11, x11, #0x10\n" + "cmp x11, x10, LSL #4\n" + "blt 1b\n" + "5:" // Oddments + "tst %x[n_channels], #0x3\n" + "beq 17f\n" + "movi v25.16b, #0x0\n" + "cbz %x[bias], 8f\n" + "add x19, %x[bias], x11\n" + "tbz %x[n_channels], #1, 6f\n" + "ld1 { v25.d }[0], [x19], #0x8\n" + "tbz %x[n_channels], #0, 7f\n" + "ld1 { v25.s }[2], [x19], #0x4\n" + "b 7f\n" + "6:" // Oddments: Load bias: Bit 1: Unset + "tbz %x[n_channels], #0, 7f\n" + "ld1 { v25.s }[0], [x19], #0x4\n" + "7:" // Oddments: Load bias: Bit 1: End + + "8:" // Oddments: Load bias: Done + "mov v24.16b, v25.16b\n" + "ldr q23, [%x[params], #0x0]\n" + "mov x20, %x[inptrs]\n" + "mov v22.16b, v25.16b\n" + "ldp x9, x28, [x20], #0x10\n" + "add %x[params], %x[params], #0x10\n" + "mov v21.16b, v25.16b\n" + "ldp x27, x26, [x20], #0x10\n" + "mov v20.16b, v25.16b\n" + "add x9, x9, x11\n" + "mov v19.16b, v25.16b\n" + "ldp x25, x24, [x20], #0x10\n" + "mov v18.16b, v25.16b\n" + "add x28, x28, x11\n" + "mov v17.16b, v25.16b\n" + "ldp x23, x22, [x20], #0x10\n" + "mov v16.16b, v25.16b\n" + "add x27, x27, x11\n" + "ldr x21, [x20], #0x8\n" + "add x26, x26, x11\n" + "add x25, x25, x11\n" + "add x24, x24, x11\n" + "add x23, x23, x11\n" + "add x22, x22, x11\n" + "add x21, x21, x11\n" + "tbz %x[n_channels], #1, 9f\n" + "ldr d2, [x9], #0x8\n" + "ldr d1, [x28], #0x8\n" + "ldr d0, [x27], #0x8\n" + "ldr d31, [x26], #0x8\n" + "ldr d30, [x25], #0x8\n" + "ldr d29, [x24], #0x8\n" + "ldr d28, [x23], #0x8\n" + "ldr d27, [x22], #0x8\n" + "ldr d26, [x21], #0x8\n" + "tbz %x[n_channels], #0, 10f\n" + "ld1 { v2.s }[2], [x9], #0x4\n" + "ld1 { v1.s }[2], [x28], #0x4\n" + "ld1 { v0.s }[2], [x27], #0x4\n" + "ld1 { v31.s }[2], [x26], #0x4\n" + "ld1 { v30.s }[2], [x25], #0x4\n" + "ld1 { v29.s }[2], [x24], #0x4\n" + "ld1 { v28.s }[2], [x23], #0x4\n" + "ld1 { v27.s }[2], [x22], #0x4\n" + "ld1 { v26.s }[2], [x21], #0x4\n" + "b 10f\n" + "9:" // Oddments: Load: Bit 1: Unset + "tbz %x[n_channels], #0, 10f\n" + "ldr s2, [x9], #0x4\n" + "ldr s1, [x28], #0x4\n" + "ldr s0, [x27], #0x4\n" + "ldr s31, [x26], #0x4\n" + "ldr s30, [x25], #0x4\n" + "ldr s29, [x24], #0x4\n" + "ldr s28, [x23], #0x4\n" + "ldr s27, [x22], #0x4\n" + "ldr s26, [x21], #0x4\n" + "10:" // Oddments: Load: Bit 1: End + "subs x19, %x[n_points], #0x1\n" + "ble 14f\n" + "11:" // Oddments: Planar loop + "fmla v25.4s, v2.4s, v23.4s\n" + "ldp x9, x28, [x20], #0x10\n" + "add x9, x9, x11\n" + "fmla v24.4s, v1.4s, v23.4s\n" + "ldp x27, x26, [x20], #0x10\n" + "fmla v22.4s, v0.4s, v23.4s\n" + "ldp x25, x24, [x20], #0x10\n" + "fmla v21.4s, v31.4s, v23.4s\n" + "add x28, x28, x11\n" + "fmla v20.4s, v30.4s, v23.4s\n" + "ldp x23, x22, [x20], #0x10\n" + "fmla v19.4s, v29.4s, v23.4s\n" + "add x27, x27, x11\n" + "fmla v18.4s, v28.4s, v23.4s\n" + "ldr x21, [x20], #0x8\n" + "fmla v17.4s, v27.4s, v23.4s\n" + "add x26, x26, x11\n" + "fmla v16.4s, v26.4s, v23.4s\n" + "ldr q23, [%x[params], #0x0]\n" + "add x25, x25, x11\n" + "add x24, x24, x11\n" + "add x23, x23, x11\n" + "add x22, x22, x11\n" + "add x21, x21, x11\n" + "add %x[params], %x[params], #0x10\n" + "tbz %x[n_channels], #1, 12f\n" + "ldr d2, [x9], #0x8\n" + "ldr d1, [x28], #0x8\n" + "ldr d0, [x27], #0x8\n" + "ldr d31, [x26], #0x8\n" + "ldr d30, [x25], #0x8\n" + "ldr d29, [x24], #0x8\n" + "ldr d28, [x23], #0x8\n" + "ldr d27, [x22], #0x8\n" + "ldr d26, [x21], #0x8\n" + "tbz %x[n_channels], #0, 13f\n" + "ld1 { v2.s }[2], [x9], #0x4\n" + "ld1 { v1.s }[2], [x28], #0x4\n" + "ld1 { v0.s }[2], [x27], #0x4\n" + "ld1 { v31.s }[2], [x26], #0x4\n" + "ld1 { v30.s }[2], [x25], #0x4\n" + "ld1 { v29.s }[2], [x24], #0x4\n" + "ld1 { v28.s }[2], [x23], #0x4\n" + "ld1 { v27.s }[2], [x22], #0x4\n" + "ld1 { v26.s }[2], [x21], #0x4\n" + "b 13f\n" + "12:" // Oddments: Planar loop: Load: Bit 1: Unset + "tbz %x[n_channels], #0, 13f\n" + "ldr s2, [x9], #0x4\n" + "ldr s1, [x28], #0x4\n" + "ldr s0, [x27], #0x4\n" + "ldr s31, [x26], #0x4\n" + "ldr s30, [x25], #0x4\n" + "ldr s29, [x24], #0x4\n" + "ldr s28, [x23], #0x4\n" + "ldr s27, [x22], #0x4\n" + "ldr s26, [x21], #0x4\n" + "13:" // Oddments: Planar loop: Load: Bit 1: End + "subs x19, x19, #0x1\n" + "bgt 11b\n" + "14:" // Oddments: Planar tail + "fmla v25.4s, v2.4s, v23.4s\n" + "ldp x27, x26, [%x[outptrs], #0x0]\n" + "add x27, x27, x11\n" + "fmla v24.4s, v1.4s, v23.4s\n" + "ldp x25, x24, [%x[outptrs], #0x10]\n" + "fmla v22.4s, v0.4s, v23.4s\n" + "ldp x23, x22, [%x[outptrs], #0x20]\n" + "add x26, x26, x11\n" + "fmla v21.4s, v31.4s, v23.4s\n" + "ldp x21, x20, [%x[outptrs], #0x30]\n" + "fmla v20.4s, v30.4s, v23.4s\n" + "ldr x19, [%x[outptrs], #0x40]\n" + "add x25, x25, x11\n" + "fmla v19.4s, v29.4s, v23.4s\n" + "add x24, x24, x11\n" + "fmla v18.4s, v28.4s, v23.4s\n" + "add x23, x23, x11\n" + "fmla v17.4s, v27.4s, v23.4s\n" + "add x22, x22, x11\n" + "fmla v16.4s, v26.4s, v23.4s\n" + "add x21, x21, x11\n" + "fmax v25.4s, v25.4s, v4.4s\n" + "add x20, x20, x11\n" + "fmax v24.4s, v24.4s, v4.4s\n" + "add x19, x19, x11\n" + "fmax v22.4s, v22.4s, v4.4s\n" + "fmin v25.4s, v25.4s, v3.4s\n" + "fmin v24.4s, v24.4s, v3.4s\n" + "fmin v22.4s, v22.4s, v3.4s\n" + "fmax v21.4s, v21.4s, v4.4s\n" + "fmax v20.4s, v20.4s, v4.4s\n" + "fmax v19.4s, v19.4s, v4.4s\n" + "fmin v21.4s, v21.4s, v3.4s\n" + "fmin v20.4s, v20.4s, v3.4s\n" + "fmin v19.4s, v19.4s, v3.4s\n" + "fmax v18.4s, v18.4s, v4.4s\n" + "fmax v17.4s, v17.4s, v4.4s\n" + "fmax v16.4s, v16.4s, v4.4s\n" + "fmin v18.4s, v18.4s, v3.4s\n" + "fmin v17.4s, v17.4s, v3.4s\n" + "fmin v16.4s, v16.4s, v3.4s\n" + "tbz %x[n_channels], #1, 15f\n" + "st1 { v25.d }[0], [x27], #0x8\n" + "st1 { v24.d }[0], [x26], #0x8\n" + "st1 { v22.d }[0], [x25], #0x8\n" + "st1 { v21.d }[0], [x24], #0x8\n" + "st1 { v20.d }[0], [x23], #0x8\n" + "st1 { v19.d }[0], [x22], #0x8\n" + "st1 { v18.d }[0], [x21], #0x8\n" + "st1 { v17.d }[0], [x20], #0x8\n" + "st1 { v16.d }[0], [x19], #0x8\n" + "tbz %x[n_channels], #0, 16f\n" + "st1 { v25.s }[2], [x27], #0x4\n" + "st1 { v24.s }[2], [x26], #0x4\n" + "st1 { v22.s }[2], [x25], #0x4\n" + "st1 { v21.s }[2], [x24], #0x4\n" + "st1 { v20.s }[2], [x23], #0x4\n" + "st1 { v19.s }[2], [x22], #0x4\n" + "st1 { v18.s }[2], [x21], #0x4\n" + "st1 { v17.s }[2], [x20], #0x4\n" + "st1 { v16.s }[2], [x19], #0x4\n" + "b 16f\n" + "15:" // Oddments: Store: Bit 1: Unset + "tbz %x[n_channels], #0, 16f\n" + "st1 { v25.s }[0], [x27], #0x4\n" + "st1 { v24.s }[0], [x26], #0x4\n" + "st1 { v22.s }[0], [x25], #0x4\n" + "st1 { v21.s }[0], [x24], #0x4\n" + "st1 { v20.s }[0], [x23], #0x4\n" + "st1 { v19.s }[0], [x22], #0x4\n" + "st1 { v18.s }[0], [x21], #0x4\n" + "st1 { v17.s }[0], [x20], #0x4\n" + "st1 { v16.s }[0], [x19], #0x4\n" + "16:" // Oddments: Store: Bit 1: End + + "17:" // End + + : [params] "+&r" (params) + : [bias] "r" (bias), [inptrs] "r" (inptrs), [minmax_vals] "r" (minmax_vals), [n_channels] "r" ((uint64_t) n_channels), [n_points] "r" ((uint64_t) n_points), [outptrs] "r" (outptrs) + : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x9", "x10", "x11", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" + ); +} + +} // namespace depthwise +} // namespace arm_conv -- cgit v1.2.1