From ba209750abc1ac7e42bab9fef5db284384d70fb3 Mon Sep 17 00:00:00 2001 From: Michael Tyler Date: Thu, 15 Dec 2022 12:39:29 +0000 Subject: Update CPU kernels to remove x19 Resolves: COMPMID-5805 Signed-off-by: Michael Tyler Change-Id: I250f64531e209625e4ff176dd5a552c1c34bc484 Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/8909 Tested-by: Arm Jenkins Comments-Addressed: Arm Jenkins Reviewed-by: Gunes Bayir Reviewed-by: Viet-Hoa Do Benchmark: Arm Jenkins --- .../generic.cpp | 517 ++++++++++----------- 1 file changed, 255 insertions(+), 262 deletions(-) (limited to 'src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_generic_output9_mla_depthfirst/generic.cpp') diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_generic_output9_mla_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_generic_output9_mla_depthfirst/generic.cpp index c0b87ada75..0ea3a8fbed 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_generic_output9_mla_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_generic_output9_mla_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021, 2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -43,336 +43,329 @@ void a64_fp32_nhwc_generic_output9_mla_depthfirst_impl( const float minmax_vals[2] = { activation_min, activation_max }; __asm__ __volatile__( - "ld1r { v4.4s }, [%x[minmax_vals]]\n" - "add x19, %x[minmax_vals], #0x4\n" + "ld1r { v2.4s }, [%x[minmax_vals]]\n" + "lsr x12, %x[n_channels], #0x2\n" + "add x20, %x[minmax_vals], #0x4\n" + "ld1r { v1.4s }, [x20]\n" "mov x11, #0x0\n" - "ld1r { v3.4s }, [x19]\n" - "lsr x10, %x[n_channels], #0x2\n" - "cbz x10, 5f\n" + "cbz x12, 5f\n" "1:" // Channel loop - "movi v25.16b, #0x0\n" + "movi v23.16b, #0x0\n" "cbz %x[bias], 2f\n" - "ldr q25, [%x[bias], x11]\n" + "ldr q23, [%x[bias], x11]\n" "2:" // Channel loop: Load bias: Done - "mov v24.16b, v25.16b\n" - "ldr q23, [%x[params], #0x0]\n" - "mov x20, %x[inptrs]\n" - "mov v22.16b, v25.16b\n" - "ldp x9, x28, [x20], #0x10\n" - "subs x19, %x[n_points], #0x1\n" - "mov v21.16b, v25.16b\n" - "ldr q2, [x9, x11]\n" - "mov v20.16b, v25.16b\n" + "ldr q0, [%x[params], #0x0]\n" + "mov x21, %x[inptrs]\n" + "ldp x10, x9, [x21], #0x10\n" + "subs x20, %x[n_points], #0x1\n" + "ldr q14, [x10, x11]\n" + "ldr q15, [x9, x11]\n" + "mov v24.16b, v23.16b\n" + "mov v25.16b, v23.16b\n" + "ldp x28, x27, [x21], #0x10\n" + "ldr q16, [x28, x11]\n" + "mov v26.16b, v23.16b\n" + "mov v27.16b, v23.16b\n" + "ldr q17, [x27, x11]\n" + "ldp x26, x25, [x21], #0x10\n" + "mov v28.16b, v23.16b\n" + "mov v29.16b, v23.16b\n" + "ldr q18, [x26, x11]\n" + "ldr q19, [x25, x11]\n" + "mov v30.16b, v23.16b\n" + "mov v31.16b, v23.16b\n" + "ldp x24, x23, [x21], #0x10\n" + "ldr q20, [x24, x11]\n" "add %x[params], %x[params], #0x10\n" - "mov v19.16b, v25.16b\n" - "ldr q1, [x28, x11]\n" - "mov v18.16b, v25.16b\n" - "ldp x27, x26, [x20], #0x10\n" - "mov v17.16b, v25.16b\n" - "ldr q0, [x27, x11]\n" - "mov v16.16b, v25.16b\n" - "ldr q31, [x26, x11]\n" - "ldp x25, x24, [x20], #0x10\n" - "ldr q30, [x25, x11]\n" - "ldr q29, [x24, x11]\n" - "ldp x23, x22, [x20], #0x10\n" - "ldr q28, [x23, x11]\n" - "ldr q27, [x22, x11]\n" - "ldr x21, [x20], #0x8\n" - "ldr q26, [x21, x11]\n" + "ldr q21, [x23, x11]\n" + "ldr x22, [x21], #0x8\n" + "ldr q22, [x22, x11]\n" "ble 4f\n" "3:" // Channel loop: Planar loop - "fmla v25.4s, v2.4s, v23.4s\n" - "ldp x9, x28, [x20], #0x10\n" - "subs x19, x19, #0x1\n" - "fmla v24.4s, v1.4s, v23.4s\n" - "ldr q2, [x9, x11]\n" - "fmla v22.4s, v0.4s, v23.4s\n" - "fmla v21.4s, v31.4s, v23.4s\n" - "ldr q1, [x28, x11]\n" - "fmla v20.4s, v30.4s, v23.4s\n" - "ldp x27, x26, [x20], #0x10\n" - "fmla v19.4s, v29.4s, v23.4s\n" - "fmla v18.4s, v28.4s, v23.4s\n" - "ldr q0, [x27, x11]\n" - "fmla v17.4s, v27.4s, v23.4s\n" - "fmla v16.4s, v26.4s, v23.4s\n" - "ldr q23, [%x[params], #0x0]\n" + "ldp x10, x9, [x21], #0x10\n" + "ldp x28, x27, [x21], #0x10\n" + "subs x20, x20, #0x1\n" + "fmla v23.4s, v14.4s, v0.4s\n" + "ldr q14, [x10, x11]\n" + "ldp x26, x25, [x21], #0x10\n" + "fmla v24.4s, v15.4s, v0.4s\n" + "fmla v25.4s, v16.4s, v0.4s\n" + "ldr q15, [x9, x11]\n" + "ldr q16, [x28, x11]\n" + "fmla v26.4s, v17.4s, v0.4s\n" + "fmla v27.4s, v18.4s, v0.4s\n" + "ldr q17, [x27, x11]\n" + "ldr q18, [x26, x11]\n" + "fmla v28.4s, v19.4s, v0.4s\n" + "fmla v29.4s, v20.4s, v0.4s\n" + "ldr q19, [x25, x11]\n" + "ldp x24, x23, [x21], #0x10\n" + "fmla v30.4s, v21.4s, v0.4s\n" + "fmla v31.4s, v22.4s, v0.4s\n" + "ldr q0, [%x[params], #0x0]\n" + "ldr q20, [x24, x11]\n" "add %x[params], %x[params], #0x10\n" - "ldr q31, [x26, x11]\n" - "ldp x25, x24, [x20], #0x10\n" - "ldr q30, [x25, x11]\n" - "ldr q29, [x24, x11]\n" - "ldp x23, x22, [x20], #0x10\n" - "ldr q28, [x23, x11]\n" - "ldr q27, [x22, x11]\n" - "ldr x21, [x20], #0x8\n" - "ldr q26, [x21, x11]\n" + "ldr q21, [x23, x11]\n" + "ldr x22, [x21], #0x8\n" + "ldr q22, [x22, x11]\n" "bgt 3b\n" "4:" // Channel loop: Planar tail - "fmla v25.4s, v2.4s, v23.4s\n" - "ldp x27, x26, [%x[outptrs], #0x0]\n" - "fmla v24.4s, v1.4s, v23.4s\n" - "ldp x25, x24, [%x[outptrs], #0x10]\n" - "fmla v22.4s, v0.4s, v23.4s\n" - "ldp x23, x22, [%x[outptrs], #0x20]\n" - "fmla v21.4s, v31.4s, v23.4s\n" - "ldp x21, x20, [%x[outptrs], #0x30]\n" - "fmla v20.4s, v30.4s, v23.4s\n" - "ldr x19, [%x[outptrs], #0x40]\n" - "fmla v19.4s, v29.4s, v23.4s\n" - "fmla v18.4s, v28.4s, v23.4s\n" - "fmla v17.4s, v27.4s, v23.4s\n" - "fmla v16.4s, v26.4s, v23.4s\n" - "fmax v25.4s, v25.4s, v4.4s\n" - "fmax v24.4s, v24.4s, v4.4s\n" - "fmax v22.4s, v22.4s, v4.4s\n" - "fmin v25.4s, v25.4s, v3.4s\n" - "str q25, [x27, x11]\n" - "fmin v24.4s, v24.4s, v3.4s\n" - "fmin v22.4s, v22.4s, v3.4s\n" - "str q24, [x26, x11]\n" - "fmax v21.4s, v21.4s, v4.4s\n" - "fmax v20.4s, v20.4s, v4.4s\n" - "str q22, [x25, x11]\n" - "fmax v19.4s, v19.4s, v4.4s\n" - "fmax v18.4s, v18.4s, v4.4s\n" - "fmin v21.4s, v21.4s, v3.4s\n" - "str q21, [x24, x11]\n" - "fmin v20.4s, v20.4s, v3.4s\n" - "fmin v19.4s, v19.4s, v3.4s\n" - "str q20, [x23, x11]\n" - "fmin v18.4s, v18.4s, v3.4s\n" - "fmax v17.4s, v17.4s, v4.4s\n" - "str q19, [x22, x11]\n" - "fmax v16.4s, v16.4s, v4.4s\n" - "str q18, [x21, x11]\n" - "fmin v17.4s, v17.4s, v3.4s\n" - "fmin v16.4s, v16.4s, v3.4s\n" - "str q17, [x20, x11]\n" - "str q16, [x19, x11]\n" + "fmla v23.4s, v14.4s, v0.4s\n" + "fmla v24.4s, v15.4s, v0.4s\n" + "fmax v23.4s, v23.4s, v2.4s\n" + "ldp x28, x27, [%x[outptrs], #0x0]\n" + "fmla v25.4s, v16.4s, v0.4s\n" + "fmla v26.4s, v17.4s, v0.4s\n" + "fmax v24.4s, v24.4s, v2.4s\n" + "ldp x26, x25, [%x[outptrs], #0x10]\n" + "fmla v27.4s, v18.4s, v0.4s\n" + "fmla v28.4s, v19.4s, v0.4s\n" + "fmax v25.4s, v25.4s, v2.4s\n" + "ldp x24, x23, [%x[outptrs], #0x20]\n" + "fmla v29.4s, v20.4s, v0.4s\n" + "fmla v30.4s, v21.4s, v0.4s\n" + "fmax v26.4s, v26.4s, v2.4s\n" + "ldp x22, x21, [%x[outptrs], #0x30]\n" + "fmla v31.4s, v22.4s, v0.4s\n" + "fmax v27.4s, v27.4s, v2.4s\n" + "ldr x20, [%x[outptrs], #0x40]\n" + "fmax v28.4s, v28.4s, v2.4s\n" + "fmax v29.4s, v29.4s, v2.4s\n" + "fmax v30.4s, v30.4s, v2.4s\n" + "fmax v31.4s, v31.4s, v2.4s\n" + "fmin v23.4s, v23.4s, v1.4s\n" + "fmin v24.4s, v24.4s, v1.4s\n" + "str q23, [x28, x11]\n" + "fmin v25.4s, v25.4s, v1.4s\n" + "fmin v26.4s, v26.4s, v1.4s\n" + "str q24, [x27, x11]\n" + "fmin v27.4s, v27.4s, v1.4s\n" + "fmin v28.4s, v28.4s, v1.4s\n" + "str q25, [x26, x11]\n" + "fmin v29.4s, v29.4s, v1.4s\n" + "fmin v30.4s, v30.4s, v1.4s\n" + "str q26, [x25, x11]\n" + "fmin v31.4s, v31.4s, v1.4s\n" + "str q27, [x24, x11]\n" + "str q28, [x23, x11]\n" + "str q29, [x22, x11]\n" + "str q30, [x21, x11]\n" + "str q31, [x20, x11]\n" "add x11, x11, #0x10\n" - "cmp x11, x10, LSL #4\n" + "cmp x11, x12, LSL #4\n" "blt 1b\n" "5:" // Oddments "tst %x[n_channels], #0x3\n" "beq 17f\n" - "movi v25.16b, #0x0\n" + "movi v23.16b, #0x0\n" "cbz %x[bias], 8f\n" - "add x19, %x[bias], x11\n" + "add x20, %x[bias], x11\n" "tbz %x[n_channels], #1, 6f\n" - "ld1 { v25.d }[0], [x19], #0x8\n" + "ld1 { v23.d }[0], [x20], #0x8\n" "tbz %x[n_channels], #0, 7f\n" - "ld1 { v25.s }[2], [x19], #0x4\n" + "ld1 { v23.s }[2], [x20], #0x4\n" "b 7f\n" "6:" // Oddments: Load bias: Bit 1: Unset - "tbz %x[n_channels], #0, 7f\n" - "ld1 { v25.s }[0], [x19], #0x4\n" + "ld1 { v23.s }[0], [x20], #0x4\n" "7:" // Oddments: Load bias: Bit 1: End - "8:" // Oddments: Load bias: Done - "mov v24.16b, v25.16b\n" - "ldr q23, [%x[params], #0x0]\n" - "mov x20, %x[inptrs]\n" - "mov v22.16b, v25.16b\n" - "ldp x9, x28, [x20], #0x10\n" - "add %x[params], %x[params], #0x10\n" - "mov v21.16b, v25.16b\n" - "ldp x27, x26, [x20], #0x10\n" - "mov v20.16b, v25.16b\n" + "ldr q0, [%x[params], #0x0]\n" + "mov x21, %x[inptrs]\n" + "ldp x10, x9, [x21], #0x10\n" + "mov v24.16b, v23.16b\n" + "ldp x28, x27, [x21], #0x10\n" + "ldp x26, x25, [x21], #0x10\n" + "mov v25.16b, v23.16b\n" + "mov v26.16b, v23.16b\n" + "ldp x24, x23, [x21], #0x10\n" + "ldr x22, [x21], #0x8\n" + "mov v27.16b, v23.16b\n" + "mov v28.16b, v23.16b\n" + "mov v29.16b, v23.16b\n" + "mov v30.16b, v23.16b\n" + "add x10, x10, x11\n" "add x9, x9, x11\n" - "mov v19.16b, v25.16b\n" - "ldp x25, x24, [x20], #0x10\n" - "mov v18.16b, v25.16b\n" + "mov v31.16b, v23.16b\n" "add x28, x28, x11\n" - "mov v17.16b, v25.16b\n" - "ldp x23, x22, [x20], #0x10\n" - "mov v16.16b, v25.16b\n" "add x27, x27, x11\n" - "ldr x21, [x20], #0x8\n" "add x26, x26, x11\n" "add x25, x25, x11\n" "add x24, x24, x11\n" "add x23, x23, x11\n" "add x22, x22, x11\n" - "add x21, x21, x11\n" + "add %x[params], %x[params], #0x10\n" "tbz %x[n_channels], #1, 9f\n" - "ldr d2, [x9], #0x8\n" - "ldr d1, [x28], #0x8\n" - "ldr d0, [x27], #0x8\n" - "ldr d31, [x26], #0x8\n" - "ldr d30, [x25], #0x8\n" - "ldr d29, [x24], #0x8\n" - "ldr d28, [x23], #0x8\n" - "ldr d27, [x22], #0x8\n" - "ldr d26, [x21], #0x8\n" + "ldr d14, [x10], #0x8\n" + "ldr d15, [x9], #0x8\n" + "ldr d16, [x28], #0x8\n" + "ldr d17, [x27], #0x8\n" + "ldr d18, [x26], #0x8\n" + "ldr d19, [x25], #0x8\n" + "ldr d20, [x24], #0x8\n" + "ldr d21, [x23], #0x8\n" + "ldr d22, [x22], #0x8\n" "tbz %x[n_channels], #0, 10f\n" - "ld1 { v2.s }[2], [x9], #0x4\n" - "ld1 { v1.s }[2], [x28], #0x4\n" - "ld1 { v0.s }[2], [x27], #0x4\n" - "ld1 { v31.s }[2], [x26], #0x4\n" - "ld1 { v30.s }[2], [x25], #0x4\n" - "ld1 { v29.s }[2], [x24], #0x4\n" - "ld1 { v28.s }[2], [x23], #0x4\n" - "ld1 { v27.s }[2], [x22], #0x4\n" - "ld1 { v26.s }[2], [x21], #0x4\n" + "ld1 { v14.s }[2], [x10], #0x4\n" + "ld1 { v15.s }[2], [x9], #0x4\n" + "ld1 { v16.s }[2], [x28], #0x4\n" + "ld1 { v17.s }[2], [x27], #0x4\n" + "ld1 { v18.s }[2], [x26], #0x4\n" + "ld1 { v19.s }[2], [x25], #0x4\n" + "ld1 { v20.s }[2], [x24], #0x4\n" + "ld1 { v21.s }[2], [x23], #0x4\n" + "ld1 { v22.s }[2], [x22], #0x4\n" "b 10f\n" "9:" // Oddments: Load: Bit 1: Unset - "tbz %x[n_channels], #0, 10f\n" - "ldr s2, [x9], #0x4\n" - "ldr s1, [x28], #0x4\n" - "ldr s0, [x27], #0x4\n" - "ldr s31, [x26], #0x4\n" - "ldr s30, [x25], #0x4\n" - "ldr s29, [x24], #0x4\n" - "ldr s28, [x23], #0x4\n" - "ldr s27, [x22], #0x4\n" - "ldr s26, [x21], #0x4\n" + "ldr s14, [x10], #0x4\n" + "ldr s15, [x9], #0x4\n" + "ldr s16, [x28], #0x4\n" + "ldr s17, [x27], #0x4\n" + "ldr s18, [x26], #0x4\n" + "ldr s19, [x25], #0x4\n" + "ldr s20, [x24], #0x4\n" + "ldr s21, [x23], #0x4\n" + "ldr s22, [x22], #0x4\n" "10:" // Oddments: Load: Bit 1: End - "subs x19, %x[n_points], #0x1\n" + "subs x20, %x[n_points], #0x1\n" "ble 14f\n" "11:" // Oddments: Planar loop - "fmla v25.4s, v2.4s, v23.4s\n" - "ldp x9, x28, [x20], #0x10\n" + "ldp x10, x9, [x21], #0x10\n" + "ldp x28, x27, [x21], #0x10\n" + "fmla v23.4s, v14.4s, v0.4s\n" + "fmla v24.4s, v15.4s, v0.4s\n" + "ldp x26, x25, [x21], #0x10\n" + "ldp x24, x23, [x21], #0x10\n" + "fmla v25.4s, v16.4s, v0.4s\n" + "fmla v26.4s, v17.4s, v0.4s\n" + "ldr x22, [x21], #0x8\n" + "fmla v27.4s, v18.4s, v0.4s\n" + "fmla v28.4s, v19.4s, v0.4s\n" + "add x10, x10, x11\n" + "fmla v29.4s, v20.4s, v0.4s\n" + "fmla v30.4s, v21.4s, v0.4s\n" "add x9, x9, x11\n" - "fmla v24.4s, v1.4s, v23.4s\n" - "ldp x27, x26, [x20], #0x10\n" - "fmla v22.4s, v0.4s, v23.4s\n" - "ldp x25, x24, [x20], #0x10\n" - "fmla v21.4s, v31.4s, v23.4s\n" "add x28, x28, x11\n" - "fmla v20.4s, v30.4s, v23.4s\n" - "ldp x23, x22, [x20], #0x10\n" - "fmla v19.4s, v29.4s, v23.4s\n" + "fmla v31.4s, v22.4s, v0.4s\n" + "ldr q0, [%x[params], #0x0]\n" "add x27, x27, x11\n" - "fmla v18.4s, v28.4s, v23.4s\n" - "ldr x21, [x20], #0x8\n" - "fmla v17.4s, v27.4s, v23.4s\n" "add x26, x26, x11\n" - "fmla v16.4s, v26.4s, v23.4s\n" - "ldr q23, [%x[params], #0x0]\n" "add x25, x25, x11\n" "add x24, x24, x11\n" "add x23, x23, x11\n" "add x22, x22, x11\n" - "add x21, x21, x11\n" "add %x[params], %x[params], #0x10\n" "tbz %x[n_channels], #1, 12f\n" - "ldr d2, [x9], #0x8\n" - "ldr d1, [x28], #0x8\n" - "ldr d0, [x27], #0x8\n" - "ldr d31, [x26], #0x8\n" - "ldr d30, [x25], #0x8\n" - "ldr d29, [x24], #0x8\n" - "ldr d28, [x23], #0x8\n" - "ldr d27, [x22], #0x8\n" - "ldr d26, [x21], #0x8\n" + "ldr d14, [x10], #0x8\n" + "ldr d15, [x9], #0x8\n" + "ldr d16, [x28], #0x8\n" + "ldr d17, [x27], #0x8\n" + "ldr d18, [x26], #0x8\n" + "ldr d19, [x25], #0x8\n" + "ldr d20, [x24], #0x8\n" + "ldr d21, [x23], #0x8\n" + "ldr d22, [x22], #0x8\n" "tbz %x[n_channels], #0, 13f\n" - "ld1 { v2.s }[2], [x9], #0x4\n" - "ld1 { v1.s }[2], [x28], #0x4\n" - "ld1 { v0.s }[2], [x27], #0x4\n" - "ld1 { v31.s }[2], [x26], #0x4\n" - "ld1 { v30.s }[2], [x25], #0x4\n" - "ld1 { v29.s }[2], [x24], #0x4\n" - "ld1 { v28.s }[2], [x23], #0x4\n" - "ld1 { v27.s }[2], [x22], #0x4\n" - "ld1 { v26.s }[2], [x21], #0x4\n" + "ld1 { v14.s }[2], [x10], #0x4\n" + "ld1 { v15.s }[2], [x9], #0x4\n" + "ld1 { v16.s }[2], [x28], #0x4\n" + "ld1 { v17.s }[2], [x27], #0x4\n" + "ld1 { v18.s }[2], [x26], #0x4\n" + "ld1 { v19.s }[2], [x25], #0x4\n" + "ld1 { v20.s }[2], [x24], #0x4\n" + "ld1 { v21.s }[2], [x23], #0x4\n" + "ld1 { v22.s }[2], [x22], #0x4\n" "b 13f\n" "12:" // Oddments: Planar loop: Load: Bit 1: Unset - "tbz %x[n_channels], #0, 13f\n" - "ldr s2, [x9], #0x4\n" - "ldr s1, [x28], #0x4\n" - "ldr s0, [x27], #0x4\n" - "ldr s31, [x26], #0x4\n" - "ldr s30, [x25], #0x4\n" - "ldr s29, [x24], #0x4\n" - "ldr s28, [x23], #0x4\n" - "ldr s27, [x22], #0x4\n" - "ldr s26, [x21], #0x4\n" + "ldr s14, [x10], #0x4\n" + "ldr s15, [x9], #0x4\n" + "ldr s16, [x28], #0x4\n" + "ldr s17, [x27], #0x4\n" + "ldr s18, [x26], #0x4\n" + "ldr s19, [x25], #0x4\n" + "ldr s20, [x24], #0x4\n" + "ldr s21, [x23], #0x4\n" + "ldr s22, [x22], #0x4\n" "13:" // Oddments: Planar loop: Load: Bit 1: End - "subs x19, x19, #0x1\n" + "subs x20, x20, #0x1\n" "bgt 11b\n" "14:" // Oddments: Planar tail - "fmla v25.4s, v2.4s, v23.4s\n" - "ldp x27, x26, [%x[outptrs], #0x0]\n" + "fmla v23.4s, v14.4s, v0.4s\n" + "fmla v24.4s, v15.4s, v0.4s\n" + "fmax v23.4s, v23.4s, v2.4s\n" + "ldp x28, x27, [%x[outptrs], #0x0]\n" + "fmla v25.4s, v16.4s, v0.4s\n" + "fmla v26.4s, v17.4s, v0.4s\n" + "fmax v24.4s, v24.4s, v2.4s\n" + "ldp x26, x25, [%x[outptrs], #0x10]\n" + "fmla v27.4s, v18.4s, v0.4s\n" + "fmla v28.4s, v19.4s, v0.4s\n" + "fmax v25.4s, v25.4s, v2.4s\n" + "ldp x24, x23, [%x[outptrs], #0x20]\n" + "fmla v29.4s, v20.4s, v0.4s\n" + "fmla v30.4s, v21.4s, v0.4s\n" + "fmax v26.4s, v26.4s, v2.4s\n" + "ldp x22, x21, [%x[outptrs], #0x30]\n" + "fmla v31.4s, v22.4s, v0.4s\n" + "fmax v27.4s, v27.4s, v2.4s\n" + "ldr x20, [%x[outptrs], #0x40]\n" + "add x28, x28, x11\n" + "fmax v28.4s, v28.4s, v2.4s\n" + "fmax v29.4s, v29.4s, v2.4s\n" "add x27, x27, x11\n" - "fmla v24.4s, v1.4s, v23.4s\n" - "ldp x25, x24, [%x[outptrs], #0x10]\n" - "fmla v22.4s, v0.4s, v23.4s\n" - "ldp x23, x22, [%x[outptrs], #0x20]\n" "add x26, x26, x11\n" - "fmla v21.4s, v31.4s, v23.4s\n" - "ldp x21, x20, [%x[outptrs], #0x30]\n" - "fmla v20.4s, v30.4s, v23.4s\n" - "ldr x19, [%x[outptrs], #0x40]\n" + "fmax v30.4s, v30.4s, v2.4s\n" + "fmax v31.4s, v31.4s, v2.4s\n" "add x25, x25, x11\n" - "fmla v19.4s, v29.4s, v23.4s\n" "add x24, x24, x11\n" - "fmla v18.4s, v28.4s, v23.4s\n" + "fmin v23.4s, v23.4s, v1.4s\n" + "fmin v24.4s, v24.4s, v1.4s\n" "add x23, x23, x11\n" - "fmla v17.4s, v27.4s, v23.4s\n" "add x22, x22, x11\n" - "fmla v16.4s, v26.4s, v23.4s\n" + "fmin v25.4s, v25.4s, v1.4s\n" + "fmin v26.4s, v26.4s, v1.4s\n" "add x21, x21, x11\n" - "fmax v25.4s, v25.4s, v4.4s\n" "add x20, x20, x11\n" - "fmax v24.4s, v24.4s, v4.4s\n" - "add x19, x19, x11\n" - "fmax v22.4s, v22.4s, v4.4s\n" - "fmin v25.4s, v25.4s, v3.4s\n" - "fmin v24.4s, v24.4s, v3.4s\n" - "fmin v22.4s, v22.4s, v3.4s\n" - "fmax v21.4s, v21.4s, v4.4s\n" - "fmax v20.4s, v20.4s, v4.4s\n" - "fmax v19.4s, v19.4s, v4.4s\n" - "fmin v21.4s, v21.4s, v3.4s\n" - "fmin v20.4s, v20.4s, v3.4s\n" - "fmin v19.4s, v19.4s, v3.4s\n" - "fmax v18.4s, v18.4s, v4.4s\n" - "fmax v17.4s, v17.4s, v4.4s\n" - "fmax v16.4s, v16.4s, v4.4s\n" - "fmin v18.4s, v18.4s, v3.4s\n" - "fmin v17.4s, v17.4s, v3.4s\n" - "fmin v16.4s, v16.4s, v3.4s\n" + "fmin v27.4s, v27.4s, v1.4s\n" + "fmin v28.4s, v28.4s, v1.4s\n" + "fmin v29.4s, v29.4s, v1.4s\n" + "fmin v30.4s, v30.4s, v1.4s\n" + "fmin v31.4s, v31.4s, v1.4s\n" "tbz %x[n_channels], #1, 15f\n" - "st1 { v25.d }[0], [x27], #0x8\n" - "st1 { v24.d }[0], [x26], #0x8\n" - "st1 { v22.d }[0], [x25], #0x8\n" - "st1 { v21.d }[0], [x24], #0x8\n" - "st1 { v20.d }[0], [x23], #0x8\n" - "st1 { v19.d }[0], [x22], #0x8\n" - "st1 { v18.d }[0], [x21], #0x8\n" - "st1 { v17.d }[0], [x20], #0x8\n" - "st1 { v16.d }[0], [x19], #0x8\n" + "st1 { v23.d }[0], [x28], #0x8\n" + "st1 { v24.d }[0], [x27], #0x8\n" + "st1 { v25.d }[0], [x26], #0x8\n" + "st1 { v26.d }[0], [x25], #0x8\n" + "st1 { v27.d }[0], [x24], #0x8\n" + "st1 { v28.d }[0], [x23], #0x8\n" + "st1 { v29.d }[0], [x22], #0x8\n" + "st1 { v30.d }[0], [x21], #0x8\n" + "st1 { v31.d }[0], [x20], #0x8\n" "tbz %x[n_channels], #0, 16f\n" - "st1 { v25.s }[2], [x27], #0x4\n" - "st1 { v24.s }[2], [x26], #0x4\n" - "st1 { v22.s }[2], [x25], #0x4\n" - "st1 { v21.s }[2], [x24], #0x4\n" - "st1 { v20.s }[2], [x23], #0x4\n" - "st1 { v19.s }[2], [x22], #0x4\n" - "st1 { v18.s }[2], [x21], #0x4\n" - "st1 { v17.s }[2], [x20], #0x4\n" - "st1 { v16.s }[2], [x19], #0x4\n" + "st1 { v23.s }[2], [x28], #0x4\n" + "st1 { v24.s }[2], [x27], #0x4\n" + "st1 { v25.s }[2], [x26], #0x4\n" + "st1 { v26.s }[2], [x25], #0x4\n" + "st1 { v27.s }[2], [x24], #0x4\n" + "st1 { v28.s }[2], [x23], #0x4\n" + "st1 { v29.s }[2], [x22], #0x4\n" + "st1 { v30.s }[2], [x21], #0x4\n" + "st1 { v31.s }[2], [x20], #0x4\n" "b 16f\n" "15:" // Oddments: Store: Bit 1: Unset - "tbz %x[n_channels], #0, 16f\n" - "st1 { v25.s }[0], [x27], #0x4\n" - "st1 { v24.s }[0], [x26], #0x4\n" - "st1 { v22.s }[0], [x25], #0x4\n" - "st1 { v21.s }[0], [x24], #0x4\n" - "st1 { v20.s }[0], [x23], #0x4\n" - "st1 { v19.s }[0], [x22], #0x4\n" - "st1 { v18.s }[0], [x21], #0x4\n" - "st1 { v17.s }[0], [x20], #0x4\n" - "st1 { v16.s }[0], [x19], #0x4\n" + "st1 { v23.s }[0], [x28], #0x4\n" + "st1 { v24.s }[0], [x27], #0x4\n" + "st1 { v25.s }[0], [x26], #0x4\n" + "st1 { v26.s }[0], [x25], #0x4\n" + "st1 { v27.s }[0], [x24], #0x4\n" + "st1 { v28.s }[0], [x23], #0x4\n" + "st1 { v29.s }[0], [x22], #0x4\n" + "st1 { v30.s }[0], [x21], #0x4\n" + "st1 { v31.s }[0], [x20], #0x4\n" "16:" // Oddments: Store: Bit 1: End - "17:" // End - : [params] "+&r" (params) : [bias] "r" (bias), [inptrs] "r" (inptrs), [minmax_vals] "r" (minmax_vals), [n_channels] "r" ((uint64_t) n_channels), [n_points] "r" ((uint64_t) n_points), [outptrs] "r" (outptrs) - : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x9", "x10", "x11", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" + : "cc", "memory", "v0", "v1", "v2", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x9", "x10", "x11", "x12", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" ); } -- cgit v1.2.1