From 74921eee924625426429044decefe3673561b174 Mon Sep 17 00:00:00 2001 From: Michael Tyler Date: Wed, 12 Apr 2023 17:43:17 +0100 Subject: Update CPU kernel implementations and guard directives Resolves COMPMID-6023 Change-Id: I868975d14c4f98af6716726feda22405a6a4c891 Signed-off-by: Michael Tyler Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/9686 Tested-by: Arm Jenkins Reviewed-by: Viet-Hoa Do Comments-Addressed: Arm Jenkins Benchmark: Arm Jenkins --- .../generic.cpp | 216 +++++++++++---------- 1 file changed, 109 insertions(+), 107 deletions(-) (limited to 'src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_generic_output9_mla_depthfirst/generic.cpp') diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_generic_output9_mla_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_generic_output9_mla_depthfirst/generic.cpp index 0ea3a8fbed..a2f577784f 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_generic_output9_mla_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_generic_output9_mla_depthfirst/generic.cpp @@ -22,10 +22,11 @@ * SOFTWARE. */ -#if defined(__aarch64__) #include #include +#if defined(__aarch64__) + namespace arm_conv { namespace depthwise { @@ -44,70 +45,70 @@ void a64_fp32_nhwc_generic_output9_mla_depthfirst_impl( __asm__ __volatile__( "ld1r { v2.4s }, [%x[minmax_vals]]\n" - "lsr x12, %x[n_channels], #0x2\n" + "lsr x9, %x[n_channels], #0x2\n" "add x20, %x[minmax_vals], #0x4\n" "ld1r { v1.4s }, [x20]\n" "mov x11, #0x0\n" - "cbz x12, 5f\n" + "cbz x9, 5f\n" "1:" // Channel loop "movi v23.16b, #0x0\n" "cbz %x[bias], 2f\n" "ldr q23, [%x[bias], x11]\n" "2:" // Channel loop: Load bias: Done "ldr q0, [%x[params], #0x0]\n" - "mov x21, %x[inptrs]\n" - "ldp x10, x9, [x21], #0x10\n" - "subs x20, %x[n_points], #0x1\n" - "ldr q14, [x10, x11]\n" - "ldr q15, [x9, x11]\n" + "mov x26, %x[inptrs]\n" + "ldp x21, x20, [x26], #0x10\n" + "subs x25, %x[n_points], #0x1\n" + "ldr q14, [x21, x11]\n" + "ldr q15, [x20, x11]\n" "mov v24.16b, v23.16b\n" "mov v25.16b, v23.16b\n" - "ldp x28, x27, [x21], #0x10\n" - "ldr q16, [x28, x11]\n" + "ldp x21, x20, [x26], #0x10\n" + "ldr q16, [x21, x11]\n" "mov v26.16b, v23.16b\n" "mov v27.16b, v23.16b\n" - "ldr q17, [x27, x11]\n" - "ldp x26, x25, [x21], #0x10\n" + "ldr q17, [x20, x11]\n" + "ldp x21, x20, [x26], #0x10\n" "mov v28.16b, v23.16b\n" "mov v29.16b, v23.16b\n" - "ldr q18, [x26, x11]\n" - "ldr q19, [x25, x11]\n" + "ldr q18, [x21, x11]\n" + "ldr q19, [x20, x11]\n" "mov v30.16b, v23.16b\n" "mov v31.16b, v23.16b\n" - "ldp x24, x23, [x21], #0x10\n" - "ldr q20, [x24, x11]\n" + "ldp x21, x20, [x26], #0x10\n" + "ldr q20, [x21, x11]\n" "add %x[params], %x[params], #0x10\n" - "ldr q21, [x23, x11]\n" - "ldr x22, [x21], #0x8\n" - "ldr q22, [x22, x11]\n" + "ldr q21, [x20, x11]\n" + "ldr x20, [x26], #0x8\n" + "ldr q22, [x20, x11]\n" "ble 4f\n" "3:" // Channel loop: Planar loop - "ldp x10, x9, [x21], #0x10\n" - "ldp x28, x27, [x21], #0x10\n" - "subs x20, x20, #0x1\n" + "ldp x20, x24, [x26], #0x10\n" + "ldp x23, x22, [x26], #0x10\n" + "subs x25, x25, #0x1\n" "fmla v23.4s, v14.4s, v0.4s\n" - "ldr q14, [x10, x11]\n" - "ldp x26, x25, [x21], #0x10\n" + "ldr q14, [x20, x11]\n" + "ldp x21, x20, [x26], #0x10\n" "fmla v24.4s, v15.4s, v0.4s\n" "fmla v25.4s, v16.4s, v0.4s\n" - "ldr q15, [x9, x11]\n" - "ldr q16, [x28, x11]\n" + "ldr q15, [x24, x11]\n" + "ldr q16, [x23, x11]\n" "fmla v26.4s, v17.4s, v0.4s\n" "fmla v27.4s, v18.4s, v0.4s\n" - "ldr q17, [x27, x11]\n" - "ldr q18, [x26, x11]\n" + "ldr q17, [x22, x11]\n" + "ldr q18, [x21, x11]\n" "fmla v28.4s, v19.4s, v0.4s\n" "fmla v29.4s, v20.4s, v0.4s\n" - "ldr q19, [x25, x11]\n" - "ldp x24, x23, [x21], #0x10\n" + "ldr q19, [x20, x11]\n" + "ldp x21, x20, [x26], #0x10\n" "fmla v30.4s, v21.4s, v0.4s\n" "fmla v31.4s, v22.4s, v0.4s\n" "ldr q0, [%x[params], #0x0]\n" - "ldr q20, [x24, x11]\n" + "ldr q20, [x21, x11]\n" "add %x[params], %x[params], #0x10\n" - "ldr q21, [x23, x11]\n" - "ldr x22, [x21], #0x8\n" - "ldr q22, [x22, x11]\n" + "ldr q21, [x20, x11]\n" + "ldr x20, [x26], #0x8\n" + "ldr q22, [x20, x11]\n" "bgt 3b\n" "4:" // Channel loop: Planar tail "fmla v23.4s, v14.4s, v0.4s\n" @@ -152,7 +153,7 @@ void a64_fp32_nhwc_generic_output9_mla_depthfirst_impl( "str q30, [x21, x11]\n" "str q31, [x20, x11]\n" "add x11, x11, #0x10\n" - "cmp x11, x12, LSL #4\n" + "cmp x11, x9, LSL #4\n" "blt 1b\n" "5:" // Oddments "tst %x[n_channels], #0x3\n" @@ -170,121 +171,121 @@ void a64_fp32_nhwc_generic_output9_mla_depthfirst_impl( "7:" // Oddments: Load bias: Bit 1: End "8:" // Oddments: Load bias: Done "ldr q0, [%x[params], #0x0]\n" - "mov x21, %x[inptrs]\n" - "ldp x10, x9, [x21], #0x10\n" + "mov x10, %x[inptrs]\n" + "ldp x9, x28, [x10], #0x10\n" "mov v24.16b, v23.16b\n" - "ldp x28, x27, [x21], #0x10\n" - "ldp x26, x25, [x21], #0x10\n" + "ldp x27, x26, [x10], #0x10\n" + "ldp x25, x24, [x10], #0x10\n" "mov v25.16b, v23.16b\n" "mov v26.16b, v23.16b\n" - "ldp x24, x23, [x21], #0x10\n" - "ldr x22, [x21], #0x8\n" + "ldp x23, x22, [x10], #0x10\n" + "ldr x21, [x10], #0x8\n" "mov v27.16b, v23.16b\n" "mov v28.16b, v23.16b\n" "mov v29.16b, v23.16b\n" "mov v30.16b, v23.16b\n" - "add x10, x10, x11\n" "add x9, x9, x11\n" - "mov v31.16b, v23.16b\n" "add x28, x28, x11\n" + "mov v31.16b, v23.16b\n" "add x27, x27, x11\n" "add x26, x26, x11\n" "add x25, x25, x11\n" "add x24, x24, x11\n" "add x23, x23, x11\n" "add x22, x22, x11\n" + "add x21, x21, x11\n" "add %x[params], %x[params], #0x10\n" "tbz %x[n_channels], #1, 9f\n" - "ldr d14, [x10], #0x8\n" - "ldr d15, [x9], #0x8\n" - "ldr d16, [x28], #0x8\n" - "ldr d17, [x27], #0x8\n" - "ldr d18, [x26], #0x8\n" - "ldr d19, [x25], #0x8\n" - "ldr d20, [x24], #0x8\n" - "ldr d21, [x23], #0x8\n" - "ldr d22, [x22], #0x8\n" + "ldr d14, [x9], #0x8\n" + "ldr d15, [x28], #0x8\n" + "ldr d16, [x27], #0x8\n" + "ldr d17, [x26], #0x8\n" + "ldr d18, [x25], #0x8\n" + "ldr d19, [x24], #0x8\n" + "ldr d20, [x23], #0x8\n" + "ldr d21, [x22], #0x8\n" + "ldr d22, [x21], #0x8\n" "tbz %x[n_channels], #0, 10f\n" - "ld1 { v14.s }[2], [x10], #0x4\n" - "ld1 { v15.s }[2], [x9], #0x4\n" - "ld1 { v16.s }[2], [x28], #0x4\n" - "ld1 { v17.s }[2], [x27], #0x4\n" - "ld1 { v18.s }[2], [x26], #0x4\n" - "ld1 { v19.s }[2], [x25], #0x4\n" - "ld1 { v20.s }[2], [x24], #0x4\n" - "ld1 { v21.s }[2], [x23], #0x4\n" - "ld1 { v22.s }[2], [x22], #0x4\n" + "ld1 { v14.s }[2], [x9], #0x4\n" + "ld1 { v15.s }[2], [x28], #0x4\n" + "ld1 { v16.s }[2], [x27], #0x4\n" + "ld1 { v17.s }[2], [x26], #0x4\n" + "ld1 { v18.s }[2], [x25], #0x4\n" + "ld1 { v19.s }[2], [x24], #0x4\n" + "ld1 { v20.s }[2], [x23], #0x4\n" + "ld1 { v21.s }[2], [x22], #0x4\n" + "ld1 { v22.s }[2], [x21], #0x4\n" "b 10f\n" "9:" // Oddments: Load: Bit 1: Unset - "ldr s14, [x10], #0x4\n" - "ldr s15, [x9], #0x4\n" - "ldr s16, [x28], #0x4\n" - "ldr s17, [x27], #0x4\n" - "ldr s18, [x26], #0x4\n" - "ldr s19, [x25], #0x4\n" - "ldr s20, [x24], #0x4\n" - "ldr s21, [x23], #0x4\n" - "ldr s22, [x22], #0x4\n" + "ldr s14, [x9], #0x4\n" + "ldr s15, [x28], #0x4\n" + "ldr s16, [x27], #0x4\n" + "ldr s17, [x26], #0x4\n" + "ldr s18, [x25], #0x4\n" + "ldr s19, [x24], #0x4\n" + "ldr s20, [x23], #0x4\n" + "ldr s21, [x22], #0x4\n" + "ldr s22, [x21], #0x4\n" "10:" // Oddments: Load: Bit 1: End "subs x20, %x[n_points], #0x1\n" "ble 14f\n" "11:" // Oddments: Planar loop - "ldp x10, x9, [x21], #0x10\n" - "ldp x28, x27, [x21], #0x10\n" + "ldp x9, x28, [x10], #0x10\n" + "ldp x27, x26, [x10], #0x10\n" "fmla v23.4s, v14.4s, v0.4s\n" "fmla v24.4s, v15.4s, v0.4s\n" - "ldp x26, x25, [x21], #0x10\n" - "ldp x24, x23, [x21], #0x10\n" + "ldp x25, x24, [x10], #0x10\n" + "ldp x23, x22, [x10], #0x10\n" "fmla v25.4s, v16.4s, v0.4s\n" "fmla v26.4s, v17.4s, v0.4s\n" - "ldr x22, [x21], #0x8\n" + "ldr x21, [x10], #0x8\n" "fmla v27.4s, v18.4s, v0.4s\n" "fmla v28.4s, v19.4s, v0.4s\n" - "add x10, x10, x11\n" + "add x9, x9, x11\n" "fmla v29.4s, v20.4s, v0.4s\n" "fmla v30.4s, v21.4s, v0.4s\n" - "add x9, x9, x11\n" "add x28, x28, x11\n" + "add x27, x27, x11\n" "fmla v31.4s, v22.4s, v0.4s\n" "ldr q0, [%x[params], #0x0]\n" - "add x27, x27, x11\n" "add x26, x26, x11\n" "add x25, x25, x11\n" "add x24, x24, x11\n" "add x23, x23, x11\n" "add x22, x22, x11\n" + "add x21, x21, x11\n" "add %x[params], %x[params], #0x10\n" "tbz %x[n_channels], #1, 12f\n" - "ldr d14, [x10], #0x8\n" - "ldr d15, [x9], #0x8\n" - "ldr d16, [x28], #0x8\n" - "ldr d17, [x27], #0x8\n" - "ldr d18, [x26], #0x8\n" - "ldr d19, [x25], #0x8\n" - "ldr d20, [x24], #0x8\n" - "ldr d21, [x23], #0x8\n" - "ldr d22, [x22], #0x8\n" + "ldr d14, [x9], #0x8\n" + "ldr d15, [x28], #0x8\n" + "ldr d16, [x27], #0x8\n" + "ldr d17, [x26], #0x8\n" + "ldr d18, [x25], #0x8\n" + "ldr d19, [x24], #0x8\n" + "ldr d20, [x23], #0x8\n" + "ldr d21, [x22], #0x8\n" + "ldr d22, [x21], #0x8\n" "tbz %x[n_channels], #0, 13f\n" - "ld1 { v14.s }[2], [x10], #0x4\n" - "ld1 { v15.s }[2], [x9], #0x4\n" - "ld1 { v16.s }[2], [x28], #0x4\n" - "ld1 { v17.s }[2], [x27], #0x4\n" - "ld1 { v18.s }[2], [x26], #0x4\n" - "ld1 { v19.s }[2], [x25], #0x4\n" - "ld1 { v20.s }[2], [x24], #0x4\n" - "ld1 { v21.s }[2], [x23], #0x4\n" - "ld1 { v22.s }[2], [x22], #0x4\n" + "ld1 { v14.s }[2], [x9], #0x4\n" + "ld1 { v15.s }[2], [x28], #0x4\n" + "ld1 { v16.s }[2], [x27], #0x4\n" + "ld1 { v17.s }[2], [x26], #0x4\n" + "ld1 { v18.s }[2], [x25], #0x4\n" + "ld1 { v19.s }[2], [x24], #0x4\n" + "ld1 { v20.s }[2], [x23], #0x4\n" + "ld1 { v21.s }[2], [x22], #0x4\n" + "ld1 { v22.s }[2], [x21], #0x4\n" "b 13f\n" "12:" // Oddments: Planar loop: Load: Bit 1: Unset - "ldr s14, [x10], #0x4\n" - "ldr s15, [x9], #0x4\n" - "ldr s16, [x28], #0x4\n" - "ldr s17, [x27], #0x4\n" - "ldr s18, [x26], #0x4\n" - "ldr s19, [x25], #0x4\n" - "ldr s20, [x24], #0x4\n" - "ldr s21, [x23], #0x4\n" - "ldr s22, [x22], #0x4\n" + "ldr s14, [x9], #0x4\n" + "ldr s15, [x28], #0x4\n" + "ldr s16, [x27], #0x4\n" + "ldr s17, [x26], #0x4\n" + "ldr s18, [x25], #0x4\n" + "ldr s19, [x24], #0x4\n" + "ldr s20, [x23], #0x4\n" + "ldr s21, [x22], #0x4\n" + "ldr s22, [x21], #0x4\n" "13:" // Oddments: Planar loop: Load: Bit 1: End "subs x20, x20, #0x1\n" "bgt 11b\n" @@ -365,10 +366,11 @@ void a64_fp32_nhwc_generic_output9_mla_depthfirst_impl( "17:" // End : [params] "+&r" (params) : [bias] "r" (bias), [inptrs] "r" (inptrs), [minmax_vals] "r" (minmax_vals), [n_channels] "r" ((uint64_t) n_channels), [n_points] "r" ((uint64_t) n_points), [outptrs] "r" (outptrs) - : "cc", "memory", "v0", "v1", "v2", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x9", "x10", "x11", "x12", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" + : "cc", "memory", "v0", "v1", "v2", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x9", "x10", "x11", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" ); } } // namespace depthwise } // namespace arm_conv -#endif // defined(__aarch64__) + +#endif // defined(__aarch64__) -- cgit v1.2.1