From 74921eee924625426429044decefe3673561b174 Mon Sep 17 00:00:00 2001 From: Michael Tyler Date: Wed, 12 Apr 2023 17:43:17 +0100 Subject: Update CPU kernel implementations and guard directives Resolves COMPMID-6023 Change-Id: I868975d14c4f98af6716726feda22405a6a4c891 Signed-off-by: Michael Tyler Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/9686 Tested-by: Arm Jenkins Reviewed-by: Viet-Hoa Do Comments-Addressed: Arm Jenkins Benchmark: Arm Jenkins --- .../generic_direct.cpp | 299 ++++++++++----------- 1 file changed, 149 insertions(+), 150 deletions(-) (limited to 'src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_3x3_s2_output2x2_mla_depthfirst/generic_direct.cpp') diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_3x3_s2_output2x2_mla_depthfirst/generic_direct.cpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_3x3_s2_output2x2_mla_depthfirst/generic_direct.cpp index e42ceffb50..5ab61fad4c 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_3x3_s2_output2x2_mla_depthfirst/generic_direct.cpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_3x3_s2_output2x2_mla_depthfirst/generic_direct.cpp @@ -25,7 +25,7 @@ #include #include -#if __aarch64__ +#if defined(__aarch64__) namespace arm_conv { namespace depthwise { @@ -106,7 +106,7 @@ void a64_fp32_nhwc_3x3_s2_output2x2_mla_depthfirst_direct_impl( "ldr x17, [%x[params_struct], %[offsetof_args_outptr]]\n" "mov x23, #0x10\n" // cntb _, ALL, #1 "mul x22, x22, x26\n" // offset *= kernel_stride * output_size - "add x8, x8, x22, LSL #2\n" // inptr[0] += offset * sizeof(float) + "add x8, x8, x22, LSL #2\n" // inptr[0] += offset * sizeof(float) "add x16, x8, x24, LSL #2\n" "ldr x15, [%x[params_struct], %[offsetof_args_params]]\n" "madd x20, x27, x7, x20\n" // offset += tile_j * ld_output_col @@ -118,9 +118,9 @@ void a64_fp32_nhwc_3x3_s2_output2x2_mla_depthfirst_direct_impl( "add x11, x13, x6\n" "add x17, x17, x20, LSL #2\n" // outptrs[0] += offset * sizeof(float) "add x20, %x[params_struct], %[offsetof_args_min]\n" - "ld1r { v19.4s }, [x20]\n" + "ld1r { v26.4s }, [x20]\n" "add x20, %x[params_struct], %[offsetof_args_max]\n" - "ld1r { v18.4s }, [x20]\n" + "ld1r { v27.4s }, [x20]\n" "add x10, x12, x24, LSL #2\n" "add x9, x11, x6\n" "add x28, x17, x21, LSL #2\n" @@ -128,7 +128,7 @@ void a64_fp32_nhwc_3x3_s2_output2x2_mla_depthfirst_direct_impl( "mov x21, #0x0\n" "sub x20, XZR, x23\n" "cbz x22, 4f\n" - "ldr q17, [x15, #0x0]\n" + "ldr q31, [x15, #0x0]\n" "ldr q0, [x15, #0x10]\n" "cmp x23, x22, LSL #4\n" "ldr q1, [x15, #0x20]\n" @@ -150,179 +150,179 @@ void a64_fp32_nhwc_3x3_s2_output2x2_mla_depthfirst_direct_impl( "ldr q16, [x8, x13]\n" "bge 3f\n" "2:" // Tile loop: Channel loop - "mov v28.16b, v17.16b\n fmla v28.4s, v8.4s, v9.4s\n" - "mov v29.16b, v17.16b\n fmla v29.4s, v6.4s, v9.4s\n" + "mov v29.16b, v31.16b\n fmla v29.4s, v8.4s, v9.4s\n" + "mov v28.16b, v31.16b\n fmla v28.4s, v6.4s, v9.4s\n" "add x23, x23, #0x10\n" "add x8, x8, #0x10\n" - "fmla v28.4s, v0.4s, v10.4s\n" + "fmla v29.4s, v0.4s, v10.4s\n" "ld1 { v10.4s }, [x8]\n" - "fmla v29.4s, v1.4s, v12.4s\n" - "ldr q12, [x16, x9]\n" - "fmla v28.4s, v1.4s, v11.4s\n" - "ldr q11, [x16, x11]\n" - "fmla v29.4s, v2.4s, v13.4s\n" - "ldr q13, [x16, x13]\n" - "fmla v28.4s, v3.4s, v14.4s\n" - "ld1 { v14.4s }, [x12]\n" - "fmla v29.4s, v0.4s, v16.4s\n" + "fmla v28.4s, v1.4s, v12.4s\n" + "ldr q21, [x16, x9]\n" + "fmla v29.4s, v1.4s, v11.4s\n" + "ldr q18, [x16, x11]\n" + "fmla v28.4s, v2.4s, v13.4s\n" + "ldr q17, [x16, x13]\n" + "fmla v29.4s, v3.4s, v14.4s\n" + "ld1 { v20.4s }, [x12]\n" + "fmla v28.4s, v0.4s, v16.4s\n" "add x16, x16, #0x10\n" - "fmla v28.4s, v4.4s, v15.4s\n" - "ld1 { v15.4s }, [x14]\n" - "fmla v29.4s, v4.4s, v11.4s\n" - "ldr q11, [x12, x6]\n" - "fmla v28.4s, v2.4s, v16.4s\n" - "ldr q16, [x14, x6]\n" - "fmla v29.4s, v5.4s, v12.4s\n" - "ldr q12, [x14, x11]\n" - "mov v30.16b, v17.16b\n fmla v30.4s, v2.4s, v9.4s\n" - "mov v31.16b, v17.16b\n fmla v31.4s, v0.4s, v9.4s\n" - "ldr q17, [x15, #0x0]\n" + "fmla v29.4s, v4.4s, v15.4s\n" + "ld1 { v25.4s }, [x14]\n" + "fmla v28.4s, v4.4s, v18.4s\n" + "ldr q19, [x12, x6]\n" + "fmla v29.4s, v2.4s, v16.4s\n" + "ldr q18, [x14, x6]\n" + "fmla v28.4s, v5.4s, v21.4s\n" + "ldr q24, [x14, x11]\n" + "mov v23.16b, v31.16b\n fmla v23.4s, v2.4s, v9.4s\n" + "mov v22.16b, v31.16b\n fmla v22.4s, v0.4s, v9.4s\n" + "ldr q31, [x15, #0x0]\n" "cmp x23, x22, LSL #4\n" - "fmla v28.4s, v5.4s, v13.4s\n" - "fmla v29.4s, v3.4s, v13.4s\n" - "ldr q13, [x12, x11]\n" + "fmla v29.4s, v5.4s, v17.4s\n" + "fmla v28.4s, v3.4s, v17.4s\n" + "ldr q17, [x12, x11]\n" "add x20, x20, #0x10\n" - "fmla v30.4s, v3.4s, v14.4s\n" - "ldr q14, [x12, x9]\n" - "fmla v31.4s, v4.4s, v13.4s\n" - "ldr q13, [x10, x6]\n" - "fmla v30.4s, v0.4s, v15.4s\n" + "fmla v23.4s, v3.4s, v20.4s\n" + "ldr q16, [x12, x9]\n" + "fmla v22.4s, v4.4s, v17.4s\n" + "ldr q21, [x10, x6]\n" + "fmla v23.4s, v0.4s, v25.4s\n" "ldr q0, [x15, #0x10]\n" - "fmla v31.4s, v1.4s, v12.4s\n" + "fmla v22.4s, v1.4s, v24.4s\n" "add x21, x21, #0x10\n" - "fmla v30.4s, v4.4s, v11.4s\n" - "ldr q11, [x14, x9]\n" + "fmla v23.4s, v4.4s, v19.4s\n" + "ldr q20, [x14, x9]\n" "ldr q4, [x15, #0x50]\n" - "fmla v31.4s, v5.4s, v14.4s\n" - "ldr q14, [x10, x11]\n" - "fmla v28.4s, v6.4s, v15.4s\n" - "ld1 { v15.4s }, [x10]\n" - "fmla v30.4s, v1.4s, v16.4s\n" + "fmla v22.4s, v5.4s, v16.4s\n" + "ldr q19, [x10, x11]\n" + "fmla v29.4s, v6.4s, v25.4s\n" + "ld1 { v17.4s }, [x10]\n" + "fmla v23.4s, v1.4s, v18.4s\n" "ldr q1, [x15, #0x20]\n" - "fmla v31.4s, v2.4s, v11.4s\n" + "fmla v22.4s, v2.4s, v20.4s\n" "ldr q2, [x15, #0x30]\n" - "fmla v28.4s, v7.4s, v16.4s\n" + "fmla v29.4s, v7.4s, v18.4s\n" "ldr q16, [x12, x13]\n" - "fmla v30.4s, v6.4s, v15.4s\n" - "ldr q15, [x10, x13]\n" - "fmla v31.4s, v3.4s, v16.4s\n" + "fmla v23.4s, v6.4s, v17.4s\n" + "ldr q18, [x10, x13]\n" + "fmla v22.4s, v3.4s, v16.4s\n" "ldr q3, [x15, #0x40]\n" - "fmla v30.4s, v7.4s, v13.4s\n" + "fmla v23.4s, v7.4s, v21.4s\n" "ldr q13, [x8, x9]\n" - "fmla v31.4s, v7.4s, v14.4s\n" + "fmla v22.4s, v7.4s, v19.4s\n" "ld1 { v14.4s }, [x16]\n" - "fmla v29.4s, v7.4s, v12.4s\n" + "fmla v28.4s, v7.4s, v24.4s\n" "ldr q12, [x8, x11]\n" - "fmla v30.4s, v5.4s, v16.4s\n" + "fmla v23.4s, v5.4s, v16.4s\n" "ldr q16, [x8, x13]\n" "ldr q5, [x15, #0x60]\n" - "fmla v31.4s, v6.4s, v15.4s\n" - "fmla v29.4s, v8.4s, v11.4s\n" - "ldr q11, [x10, x9]\n" + "fmla v22.4s, v6.4s, v18.4s\n" + "fmla v28.4s, v8.4s, v20.4s\n" + "ldr q17, [x10, x9]\n" "ldr q6, [x15, #0x70]\n" - "fmla v30.4s, v8.4s, v15.4s\n" - "fmla v31.4s, v8.4s, v11.4s\n" + "fmla v23.4s, v8.4s, v18.4s\n" + "fmla v22.4s, v8.4s, v17.4s\n" "ldr q11, [x8, x6]\n" "ldr q15, [x16, x6]\n" - "fmax v28.4s, v28.4s, v19.4s\n" - "fmax v29.4s, v29.4s, v19.4s\n" + "fmax v29.4s, v29.4s, v26.4s\n" + "fmax v28.4s, v28.4s, v26.4s\n" "ldr q7, [x15, #0x80]\n" "ldr q8, [x15, #0x90]\n" - "fmax v30.4s, v30.4s, v19.4s\n" - "fmax v31.4s, v31.4s, v19.4s\n" + "fmax v23.4s, v23.4s, v26.4s\n" + "fmax v22.4s, v22.4s, v26.4s\n" "add x14, x14, #0x10\n" "ldr q9, [x14, x13]\n" - "fmin v28.4s, v28.4s, v18.4s\n" - "fmin v29.4s, v29.4s, v18.4s\n" - "fmin v30.4s, v30.4s, v18.4s\n" - "fmin v31.4s, v31.4s, v18.4s\n" + "fmin v29.4s, v29.4s, v27.4s\n" + "fmin v28.4s, v28.4s, v27.4s\n" + "fmin v23.4s, v23.4s, v27.4s\n" + "fmin v22.4s, v22.4s, v27.4s\n" "add x12, x12, #0x10\n" "add x10, x10, #0x10\n" - "st1 { v28.4s }, [x17]\n" + "st1 { v29.4s }, [x17]\n" "add x15, x15, #0xa0\n" - "str q29, [x17, x7]\n" + "str q28, [x17, x7]\n" "add x17, x17, #0x10\n" - "st1 { v30.4s }, [x28]\n" - "str q31, [x28, x7]\n" + "st1 { v23.4s }, [x28]\n" + "str q22, [x28, x7]\n" "add x28, x28, #0x10\n" "blt 2b\n" "3:" // Tile loop: Channel tail - "mov v28.16b, v17.16b\n fmla v28.4s, v8.4s, v9.4s\n" - "mov v29.16b, v17.16b\n fmla v29.4s, v6.4s, v9.4s\n" + "mov v29.16b, v31.16b\n fmla v29.4s, v8.4s, v9.4s\n" + "mov v28.16b, v31.16b\n fmla v28.4s, v6.4s, v9.4s\n" "add x8, x8, #0x10\n" - "fmla v28.4s, v0.4s, v10.4s\n" - "fmla v29.4s, v1.4s, v12.4s\n" - "ldr q12, [x16, x9]\n" - "fmla v28.4s, v1.4s, v11.4s\n" - "ldr q11, [x16, x11]\n" - "fmla v29.4s, v2.4s, v13.4s\n" - "ldr q13, [x16, x13]\n" - "fmla v28.4s, v3.4s, v14.4s\n" - "ld1 { v14.4s }, [x12]\n" - "fmla v29.4s, v0.4s, v16.4s\n" + "fmla v29.4s, v0.4s, v10.4s\n" + "fmla v28.4s, v1.4s, v12.4s\n" + "ldr q20, [x16, x9]\n" + "fmla v29.4s, v1.4s, v11.4s\n" + "ldr q18, [x16, x11]\n" + "fmla v28.4s, v2.4s, v13.4s\n" + "ldr q17, [x16, x13]\n" + "fmla v29.4s, v3.4s, v14.4s\n" + "ld1 { v19.4s }, [x12]\n" + "fmla v28.4s, v0.4s, v16.4s\n" "add x16, x16, #0x10\n" - "fmla v28.4s, v4.4s, v15.4s\n" - "ld1 { v15.4s }, [x14]\n" - "fmla v29.4s, v4.4s, v11.4s\n" - "ldr q11, [x12, x6]\n" - "fmla v28.4s, v2.4s, v16.4s\n" - "ldr q16, [x14, x6]\n" - "fmla v29.4s, v5.4s, v12.4s\n" - "ldr q12, [x14, x11]\n" - "mov v30.16b, v17.16b\n fmla v30.4s, v2.4s, v9.4s\n" - "mov v31.16b, v17.16b\n fmla v31.4s, v0.4s, v9.4s\n" - "fmla v28.4s, v5.4s, v13.4s\n" - "fmla v29.4s, v3.4s, v13.4s\n" - "ldr q13, [x12, x11]\n" - "fmla v30.4s, v3.4s, v14.4s\n" - "ldr q14, [x12, x9]\n" - "fmla v31.4s, v4.4s, v13.4s\n" - "ldr q13, [x10, x6]\n" - "fmla v30.4s, v0.4s, v15.4s\n" - "fmla v31.4s, v1.4s, v12.4s\n" - "fmla v30.4s, v4.4s, v11.4s\n" - "ldr q11, [x14, x9]\n" - "fmla v31.4s, v5.4s, v14.4s\n" - "ldr q14, [x10, x11]\n" - "fmla v28.4s, v6.4s, v15.4s\n" - "ld1 { v15.4s }, [x10]\n" - "fmla v30.4s, v1.4s, v16.4s\n" + "fmla v29.4s, v4.4s, v15.4s\n" + "ld1 { v25.4s }, [x14]\n" + "fmla v28.4s, v4.4s, v18.4s\n" + "ldr q18, [x12, x6]\n" + "fmla v29.4s, v2.4s, v16.4s\n" + "ldr q24, [x14, x6]\n" + "fmla v28.4s, v5.4s, v20.4s\n" + "ldr q23, [x14, x11]\n" + "mov v22.16b, v31.16b\n fmla v22.4s, v2.4s, v9.4s\n" + "mov v21.16b, v31.16b\n fmla v21.4s, v0.4s, v9.4s\n" + "fmla v29.4s, v5.4s, v17.4s\n" + "fmla v28.4s, v3.4s, v17.4s\n" + "ldr q17, [x12, x11]\n" + "fmla v22.4s, v3.4s, v19.4s\n" + "ldr q16, [x12, x9]\n" + "fmla v21.4s, v4.4s, v17.4s\n" + "ldr q20, [x10, x6]\n" + "fmla v22.4s, v0.4s, v25.4s\n" + "fmla v21.4s, v1.4s, v23.4s\n" + "fmla v22.4s, v4.4s, v18.4s\n" + "ldr q19, [x14, x9]\n" + "fmla v21.4s, v5.4s, v16.4s\n" + "ldr q18, [x10, x11]\n" + "fmla v29.4s, v6.4s, v25.4s\n" + "ld1 { v17.4s }, [x10]\n" + "fmla v22.4s, v1.4s, v24.4s\n" "add x14, x14, #0x10\n" - "fmla v31.4s, v2.4s, v11.4s\n" - "fmla v28.4s, v7.4s, v16.4s\n" + "fmla v21.4s, v2.4s, v19.4s\n" + "fmla v29.4s, v7.4s, v24.4s\n" "ldr q16, [x12, x13]\n" - "fmax v28.4s, v28.4s, v19.4s\n" - "fmla v30.4s, v6.4s, v15.4s\n" - "ldr q15, [x10, x13]\n" - "fmla v31.4s, v3.4s, v16.4s\n" - "fmin v28.4s, v28.4s, v18.4s\n" - "fmla v30.4s, v7.4s, v13.4s\n" - "fmla v31.4s, v7.4s, v14.4s\n" - "st1 { v28.4s }, [x17]\n" + "fmax v29.4s, v29.4s, v26.4s\n" + "fmla v22.4s, v6.4s, v17.4s\n" + "ldr q17, [x10, x13]\n" + "fmla v21.4s, v3.4s, v16.4s\n" + "fmin v29.4s, v29.4s, v27.4s\n" + "fmla v22.4s, v7.4s, v20.4s\n" + "fmla v21.4s, v7.4s, v18.4s\n" + "st1 { v29.4s }, [x17]\n" "add x12, x12, #0x10\n" - "fmla v29.4s, v7.4s, v12.4s\n" - "fmla v30.4s, v5.4s, v16.4s\n" - "fmla v31.4s, v6.4s, v15.4s\n" - "fmla v29.4s, v8.4s, v11.4s\n" - "ldr q11, [x10, x9]\n" - "fmax v29.4s, v29.4s, v19.4s\n" - "fmla v30.4s, v8.4s, v15.4s\n" - "fmla v31.4s, v8.4s, v11.4s\n" - "fmax v30.4s, v30.4s, v19.4s\n" + "fmla v28.4s, v7.4s, v23.4s\n" + "fmla v22.4s, v5.4s, v16.4s\n" + "fmla v21.4s, v6.4s, v17.4s\n" + "fmla v28.4s, v8.4s, v19.4s\n" + "ldr q16, [x10, x9]\n" + "fmax v28.4s, v28.4s, v26.4s\n" + "fmla v22.4s, v8.4s, v17.4s\n" + "fmla v21.4s, v8.4s, v16.4s\n" + "fmax v22.4s, v22.4s, v26.4s\n" "add x10, x10, #0x10\n" - "fmax v31.4s, v31.4s, v19.4s\n" - "fmin v29.4s, v29.4s, v18.4s\n" - "str q29, [x17, x7]\n" + "fmax v21.4s, v21.4s, v26.4s\n" + "fmin v28.4s, v28.4s, v27.4s\n" + "str q28, [x17, x7]\n" "add x17, x17, #0x10\n" - "fmin v30.4s, v30.4s, v18.4s\n" - "fmin v31.4s, v31.4s, v18.4s\n" - "st1 { v30.4s }, [x28]\n" - "str q31, [x28, x7]\n" + "fmin v22.4s, v22.4s, v27.4s\n" + "fmin v21.4s, v21.4s, v27.4s\n" + "st1 { v22.4s }, [x28]\n" + "str q21, [x28, x7]\n" "add x28, x28, #0x10\n" "4:" // Tile loop: Oddments "tst %x[n_channels], #0x3\n" "beq 43f\n" - "ldr q17, [x15, #0x0]\n" + "ldr q31, [x15, #0x0]\n" "ldr q0, [x15, #0x10]\n" "add x27, x14, x13\n" "add x26, x8, XZR\n" @@ -369,17 +369,17 @@ void a64_fp32_nhwc_3x3_s2_output2x2_mla_depthfirst_direct_impl( "ldr s15, [x21, #0x0]\n" "ldr s16, [x20, #0x0]\n" "6:" // Tile loop: Oddments: Load inputs: (2, 2), (0, 0), (0, 1), (0, 3), (0, 4), (1, 0), (1, 1), (0, 2): Bit 1: End - "mov v28.16b, v17.16b\n fmla v28.4s, v8.4s, v9.4s\n" + "mov v28.16b, v31.16b\n fmla v28.4s, v8.4s, v9.4s\n" "fmla v28.4s, v0.4s, v10.4s\n" "add x20, x16, x11\n" - "mov v29.16b, v17.16b\n fmla v29.4s, v6.4s, v9.4s\n" + "mov v29.16b, v31.16b\n fmla v29.4s, v6.4s, v9.4s\n" "fmla v28.4s, v1.4s, v11.4s\n" "fmla v29.4s, v1.4s, v12.4s\n" "fmla v28.4s, v3.4s, v14.4s\n" "fmla v29.4s, v2.4s, v13.4s\n" "fmla v28.4s, v4.4s, v15.4s\n" - "mov v30.16b, v17.16b\n fmla v30.4s, v2.4s, v9.4s\n" - "mov v31.16b, v17.16b\n fmla v31.4s, v0.4s, v9.4s\n" + "mov v30.16b, v31.16b\n fmla v30.4s, v2.4s, v9.4s\n" + "fmla v31.4s, v0.4s, v9.4s\n" "fmla v28.4s, v2.4s, v16.4s\n" "fmla v29.4s, v0.4s, v16.4s\n" "tbz %x[n_channels], #1, 7f\n" @@ -558,14 +558,14 @@ void a64_fp32_nhwc_3x3_s2_output2x2_mla_depthfirst_direct_impl( "ldr s11, [x20, #0x0]\n" "40:" // Tile loop: Oddments: Load inputs: (4, 4): Bit 1: End "fmla v31.4s, v8.4s, v11.4s\n" - "fmax v28.4s, v28.4s, v19.4s\n" - "fmax v29.4s, v29.4s, v19.4s\n" - "fmax v30.4s, v30.4s, v19.4s\n" - "fmax v31.4s, v31.4s, v19.4s\n" - "fmin v28.4s, v28.4s, v18.4s\n" - "fmin v29.4s, v29.4s, v18.4s\n" - "fmin v30.4s, v30.4s, v18.4s\n" - "fmin v31.4s, v31.4s, v18.4s\n" + "fmax v28.4s, v28.4s, v26.4s\n" + "fmax v29.4s, v29.4s, v26.4s\n" + "fmax v30.4s, v30.4s, v26.4s\n" + "fmax v31.4s, v31.4s, v26.4s\n" + "fmin v28.4s, v28.4s, v27.4s\n" + "fmin v29.4s, v29.4s, v27.4s\n" + "fmin v30.4s, v30.4s, v27.4s\n" + "fmin v31.4s, v31.4s, v27.4s\n" "tbz %x[n_channels], #1, 41f\n" "mov x21, x17\n" "mov x20, x28\n" @@ -591,7 +591,6 @@ void a64_fp32_nhwc_3x3_s2_output2x2_mla_depthfirst_direct_impl( "st1 { v29.s }[0], [x21]\n" "st1 { v31.s }[0], [x20]\n" "42:" // Tile loop: Oddments: Store: Bit 1: End - "43:" // Tile loop: End "ldr x27, [%x[params_struct], %[offsetof_args_tile_j]]\n" "ldr x23, [%x[params_struct], %[offsetof_args_tile_i]]\n" @@ -606,11 +605,11 @@ void a64_fp32_nhwc_3x3_s2_output2x2_mla_depthfirst_direct_impl( "blt 1b\n" : : [n_channels] "r" ((unsigned long) n_channels), [offsetof_args_inptr] "I" (offsetof(Args, inptr)), [offsetof_args_ld_input_col] "I" (offsetof(Args, ld_input_col)), [offsetof_args_ld_input_row] "I" (offsetof(Args, ld_input_row)), [offsetof_args_ld_output_col] "I" (offsetof(Args, ld_output_col)), [offsetof_args_ld_output_row] "I" (offsetof(Args, ld_output_row)), [offsetof_args_max] "I" (offsetof(Args, max)), [offsetof_args_min] "I" (offsetof(Args, min)), [offsetof_args_n_tile_cols] "I" (offsetof(Args, n_tile_cols)), [offsetof_args_n_tile_rows] "I" (offsetof(Args, n_tile_rows)), [offsetof_args_outptr] "I" (offsetof(Args, outptr)), [offsetof_args_params] "I" (offsetof(Args, params)), [offsetof_args_tile_i] "I" (offsetof(Args, tile_i)), [offsetof_args_tile_j] "I" (offsetof(Args, tile_j)), [params_struct] "r" (¶ms_struct) - : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v28", "v29", "v30", "v31", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" + : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" ); } } // namespace depthwise } // namespace arm_conv -#endif // __aarch64__ +#endif // defined(__aarch64__) -- cgit v1.2.1