From be13cead34e566bdd561ad3ffc3f645b460e482e Mon Sep 17 00:00:00 2001 From: Michael Tyler Date: Tue, 17 Jan 2023 11:04:14 +0000 Subject: Revert "Update CPU kernels to remove x19" This reverts commit 3c59f01c209d2732a15d97d65565ead964787a8b. Resolves: COMPMID-5817 Change-Id: Ie2443a21854a95db1e3d0cafa2121c0187a5e237 Signed-off-by: Michael Tyler Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/8974 Comments-Addressed: Arm Jenkins Tested-by: Arm Jenkins Reviewed-by: Gian Marco Iodice Benchmark: Arm Jenkins --- .../generic_indirect.cpp | 2044 ++++++++++---------- 1 file changed, 1023 insertions(+), 1021 deletions(-) (limited to 'src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_3x3_s1_output4x4_mla_depthfirst/generic_indirect.cpp') diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_3x3_s1_output4x4_mla_depthfirst/generic_indirect.cpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_3x3_s1_output4x4_mla_depthfirst/generic_indirect.cpp index 2353045021..aeaf1049f1 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_3x3_s1_output4x4_mla_depthfirst/generic_indirect.cpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_3x3_s1_output4x4_mla_depthfirst/generic_indirect.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, 2023 Arm Limited. + * Copyright (c) 2021 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -98,21 +98,21 @@ void a64_fp32_nhwc_3x3_s1_output4x4_mla_depthfirst_indirect_impl( activation_min, activation_max); __asm__ __volatile__( - "mov x8, #0x10\n" // cntb _, ALL, #1 - "lsr x17, %x[n_channels], #0x2\n" - "ldr x16, [%x[params_struct], %[offsetof_args_outptrs]]\n" + "ldr x17, [%x[params_struct], %[offsetof_args_outptrs]]\n" + "add x16, %x[params_struct], %[offsetof_Args_inptrs]\n" "ldr x15, [%x[params_struct], %[offsetof_args_params]]\n" "add x20, %x[params_struct], %[offsetof_args_min]\n" + "add x19, %x[params_struct], %[offsetof_args_max]\n" "ld1r { v15.4s }, [x20]\n" - "add x20, %x[params_struct], %[offsetof_args_max]\n" - "ld1r { v14.4s }, [x20]\n" - "add x14, %x[params_struct], %[offsetof_Args_inptrs]\n" - "mov x13, #0x0\n" - "sub x12, XZR, x8\n" - "cbz x17, 3f\n" + "ld1r { v14.4s }, [x19]\n" + "mov x14, #0x0\n" + "mov x13, #0x10\n" // cntb _, ALL, #1 + "sub x12, XZR, x13\n" + "lsr x11, %x[n_channels], #0x2\n" + "cbz x11, 3f\n" "ldr q13, [x15, #0x0]\n" "ldr q0, [x15, #0x10]\n" - "cmp x8, x17, LSL #4\n" + "cmp x13, x11, LSL #4\n" "ldr q1, [x15, #0x20]\n" "ldr q2, [x15, #0x30]\n" "ldr q3, [x15, #0x40]\n" @@ -122,589 +122,589 @@ void a64_fp32_nhwc_3x3_s1_output4x4_mla_depthfirst_indirect_impl( "ldr q7, [x15, #0x80]\n" "ldr q8, [x15, #0x90]\n" "add x15, x15, #0xa0\n" - "ldp x11, x10, [x14, #0x0]\n" - "ldr q9, [x11, x13]\n" - "ldr q10, [x10, x13]\n" - "ldp x9, x28, [x14, #0x10]\n" - "ldr q11, [x9, x13]\n" - "ldr q12, [x28, x13]\n" + "ldp x10, x9, [x16, #0x0]\n" + "ldp x28, x27, [x16, #0x10]\n" + "ldr q9, [x10, x14]\n" + "ldr q10, [x9, x14]\n" + "ldr q11, [x28, x14]\n" + "ldr q12, [x27, x14]\n" "bge 2f\n" "1:" // Channel loop - "mov v21.16b, v13.16b\n fmla v21.4s, v4.4s, v9.4s\n" - "mov v16.16b, v13.16b\n fmla v16.4s, v8.4s, v9.4s\n" - "ldr x27, [x14, #0x20]\n" - "ldr x26, [x14, #0x30]\n" - "mov v22.16b, v13.16b\n fmla v22.4s, v3.4s, v9.4s\n" - "mov v25.16b, v13.16b\n fmla v25.4s, v1.4s, v9.4s\n" - "ldr x25, [x14, #0x28]\n" - "ldr x24, [x14, #0x38]\n" - "mov v26.16b, v13.16b\n fmla v26.4s, v0.4s, v9.4s\n" - "mov v17.16b, v13.16b\n fmla v17.4s, v7.4s, v9.4s\n" - "ldr x11, [x14, #0x40]\n" - "ldr x10, [x14, #0x48]\n" - "mov v18.16b, v13.16b\n fmla v18.4s, v6.4s, v9.4s\n" - "fmla v21.4s, v5.4s, v12.4s\n" - "ldr x9, [x14, #0x50]\n" - "ldr x28, [x14, #0x58]\n" - "mov v20.16b, v13.16b\n fmla v20.4s, v5.4s, v9.4s\n" - "mov v24.16b, v13.16b\n fmla v24.4s, v2.4s, v9.4s\n" - "ldr q9, [x26, x13]\n" - "ldr x26, [x14, #0x70]\n" - "fmla v16.4s, v0.4s, v10.4s\n" - "ldr q10, [x27, x13]\n" - "mov v19.16b, v13.16b\n fmla v19.4s, v2.4s, v11.4s\n" - "ldr q11, [x25, x13]\n" - "fmla v22.4s, v4.4s, v12.4s\n" - "fmla v25.4s, v2.4s, v12.4s\n" - "ldr x27, [x14, #0x60]\n" - "ldr x25, [x14, #0x68]\n" - "fmla v26.4s, v1.4s, v12.4s\n" - "fmla v17.4s, v8.4s, v12.4s\n" - "ldr x23, [x16, #0x0]\n" - "ldr x22, [x16, #0x8]\n" - "fmla v18.4s, v7.4s, v12.4s\n" - "mov v28.16b, v13.16b\n fmla v28.4s, v6.4s, v10.4s\n" - "ldr q10, [x10, x13]\n" - "ldr x10, [x14, #0x88]\n" - "fmla v21.4s, v7.4s, v9.4s\n" - "fmla v19.4s, v6.4s, v12.4s\n" - "ldr x21, [x16, #0x10]\n" - "ldr x20, [x16, #0x18]\n" - "mov v23.16b, v13.16b\n fmla v23.4s, v3.4s, v12.4s\n" - "mov v27.16b, v13.16b\n fmla v27.4s, v0.4s, v12.4s\n" - "ldr q12, [x24, x13]\n" - "ldr x24, [x14, #0x78]\n" - "mov v31.16b, v13.16b\n fmla v31.4s, v8.4s, v11.4s\n" - "ldr q11, [x11, x13]\n" - "fmla v22.4s, v6.4s, v9.4s\n" - "ldr x11, [x14, #0x80]\n" - "fmla v25.4s, v4.4s, v9.4s\n" - "fmla v26.4s, v3.4s, v9.4s\n" + "mov v31.16b, v13.16b\n fmla v31.4s, v8.4s, v9.4s\n" + "ldr x26, [x16, #0x20]\n" "add x12, x12, #0x10\n" - "fmla v20.4s, v8.4s, v9.4s\n" - "fmla v24.4s, v5.4s, v9.4s\n" - "fmla v28.4s, v2.4s, v9.4s\n" - "fmla v16.4s, v1.4s, v12.4s\n" - "fmla v17.4s, v0.4s, v12.4s\n" - "ldr q12, [x28, x13]\n" - "fmla v18.4s, v2.4s, v11.4s\n" - "ldr x28, [x14, #0x98]\n" - "fmla v21.4s, v8.4s, v10.4s\n" - "fmla v19.4s, v1.4s, v11.4s\n" - "ldr q11, [x27, x13]\n" - "ldr x27, [x14, #0xa0]\n" - "fmla v22.4s, v7.4s, v10.4s\n" - "fmla v23.4s, v6.4s, v10.4s\n" - "fmla v25.4s, v5.4s, v10.4s\n" - "fmla v26.4s, v4.4s, v10.4s\n" - "fmla v27.4s, v3.4s, v10.4s\n" + "mov v30.16b, v13.16b\n fmla v30.4s, v7.4s, v9.4s\n" + "ldr x25, [x16, #0x28]\n" + "mov v29.16b, v13.16b\n fmla v29.4s, v6.4s, v9.4s\n" + "ldr x24, [x16, #0x30]\n" + "mov v27.16b, v13.16b\n fmla v27.4s, v5.4s, v9.4s\n" + "ldr x23, [x16, #0x38]\n" + "mov v26.16b, v13.16b\n fmla v26.4s, v4.4s, v9.4s\n" + "ldr x10, [x16, #0x40]\n" + "mov v25.16b, v13.16b\n fmla v25.4s, v3.4s, v9.4s\n" + "ldr x9, [x16, #0x48]\n" + "mov v23.16b, v13.16b\n fmla v23.4s, v2.4s, v9.4s\n" + "ldr x28, [x16, #0x50]\n" + "mov v22.16b, v13.16b\n fmla v22.4s, v1.4s, v9.4s\n" + "ldr x27, [x16, #0x58]\n" + "mov v21.16b, v13.16b\n fmla v21.4s, v0.4s, v9.4s\n" + "ldr q9, [x24, x14]\n" "fmla v31.4s, v0.4s, v10.4s\n" - "fmla v24.4s, v6.4s, v11.4s\n" - "fmla v28.4s, v3.4s, v11.4s\n" - "ldr q11, [x26, x13]\n" - "ldr x26, [x14, #0xb0]\n" - "fmla v19.4s, v5.4s, v12.4s\n" - "fmla v23.4s, v2.4s, v12.4s\n" - "ldr q12, [x24, x13]\n" - "ldr x24, [x14, #0xb8]\n" - "fmla v27.4s, v8.4s, v11.4s\n" - "fmla v31.4s, v5.4s, v11.4s\n" - "mov v29.16b, v13.16b\n fmla v29.4s, v1.4s, v9.4s\n" - "mov v30.16b, v13.16b\n fmla v30.4s, v0.4s, v9.4s\n" - "ldr q9, [x9, x13]\n" - "ldr x9, [x14, #0x90]\n" - "fmla v29.4s, v2.4s, v10.4s\n" - "fmla v30.4s, v1.4s, v10.4s\n" - "ldr q10, [x25, x13]\n" - "ldr x25, [x14, #0xa8]\n" - "fmla v16.4s, v3.4s, v9.4s\n" - "fmla v20.4s, v0.4s, v9.4s\n" - "ldr q11, [x11, x13]\n" - "ldr x11, [x14, #0xc0]\n" - "fmla v17.4s, v4.4s, v10.4s\n" - "fmla v18.4s, v3.4s, v10.4s\n" - "fmla v21.4s, v1.4s, v10.4s\n" - "fmla v22.4s, v0.4s, v10.4s\n" - "fmla v16.4s, v5.4s, v10.4s\n" - "fmla v20.4s, v2.4s, v10.4s\n" - "ldr q10, [x10, x13]\n" - "ldr x10, [x14, #0xc8]\n" - "fmla v17.4s, v5.4s, v12.4s\n" - "fmla v18.4s, v4.4s, v12.4s\n" - "fmla v21.4s, v2.4s, v12.4s\n" - "fmla v19.4s, v3.4s, v12.4s\n" - "fmla v22.4s, v1.4s, v12.4s\n" - "fmla v23.4s, v0.4s, v12.4s\n" - "ldr q12, [x28, x13]\n" - "ldr x28, [x14, #0xd8]\n" - "fmla v28.4s, v7.4s, v11.4s\n" - "fmla v29.4s, v6.4s, v11.4s\n" - "ldr q11, [x9, x13]\n" - "ldr x9, [x14, #0xd0]\n" - "fmla v16.4s, v7.4s, v10.4s\n" - "fmla v17.4s, v6.4s, v10.4s\n" - "fmla v20.4s, v4.4s, v10.4s\n" - "fmla v21.4s, v3.4s, v10.4s\n" - "fmla v24.4s, v1.4s, v10.4s\n" - "fmla v25.4s, v0.4s, v10.4s\n" - "ldr q10, [x27, x13]\n" - "ldr x27, [x14, #0xe0]\n" - "fmla v18.4s, v8.4s, v12.4s\n" - "fmla v30.4s, v8.4s, v11.4s\n" - "fmla v31.4s, v7.4s, v11.4s\n" - "ldr q11, [x25, x13]\n" - "fmla v27.4s, v1.4s, v12.4s\n" - "ldr x25, [x14, #0xe8]\n" - "fmla v19.4s, v7.4s, v12.4s\n" - "fmla v22.4s, v5.4s, v12.4s\n" - "fmla v23.4s, v4.4s, v12.4s\n" - "fmla v26.4s, v2.4s, v12.4s\n" - "ldr q12, [x26, x13]\n" - "ldr x26, [x14, #0xf0]\n" - "fmla v16.4s, v2.4s, v10.4s\n" - "fmla v17.4s, v1.4s, v10.4s\n" - "fmla v18.4s, v0.4s, v10.4s\n" - "ldr q10, [x24, x13]\n" - "fmla v20.4s, v7.4s, v11.4s\n" - "ldr x24, [x14, #0xf8]\n" - "fmla v21.4s, v6.4s, v11.4s\n" - "fmla v24.4s, v4.4s, v11.4s\n" - "fmla v25.4s, v3.4s, v11.4s\n" + "ldr q10, [x26, x14]\n" + "mov v28.16b, v13.16b\n fmla v28.4s, v2.4s, v11.4s\n" + "ldr q11, [x25, x14]\n" + "fmla v30.4s, v8.4s, v12.4s\n" + "ldr x26, [x16, #0x60]\n" + "fmla v29.4s, v7.4s, v12.4s\n" + "ldr x25, [x16, #0x68]\n" + "fmla v26.4s, v5.4s, v12.4s\n" + "ldr x24, [x16, #0x70]\n" + "fmla v28.4s, v6.4s, v12.4s\n" + "ldr x22, [x17, #0x0]\n" + "fmla v25.4s, v4.4s, v12.4s\n" + "ldr x21, [x17, #0x8]\n" + "mov v24.16b, v13.16b\n fmla v24.4s, v3.4s, v12.4s\n" + "ldr x20, [x17, #0x10]\n" + "fmla v22.4s, v2.4s, v12.4s\n" + "ldr x19, [x17, #0x18]\n" + "fmla v21.4s, v1.4s, v12.4s\n" + "mov v20.16b, v13.16b\n fmla v20.4s, v0.4s, v12.4s\n" + "ldr q12, [x23, x14]\n" + "mov v19.16b, v13.16b\n fmla v19.4s, v6.4s, v10.4s\n" + "ldr q10, [x9, x14]\n" + "mov v16.16b, v13.16b\n fmla v16.4s, v8.4s, v11.4s\n" + "ldr q11, [x10, x14]\n" + "fmla v27.4s, v8.4s, v9.4s\n" + "ldr x23, [x16, #0x78]\n" + "fmla v26.4s, v7.4s, v9.4s\n" + "ldr x10, [x16, #0x80]\n" + "fmla v25.4s, v6.4s, v9.4s\n" + "ldr x9, [x16, #0x88]\n" + "fmla v23.4s, v5.4s, v9.4s\n" + "fmla v22.4s, v4.4s, v9.4s\n" + "fmla v21.4s, v3.4s, v9.4s\n" + "fmla v19.4s, v2.4s, v9.4s\n" + "mov v18.16b, v13.16b\n fmla v18.4s, v1.4s, v9.4s\n" + "mov v17.16b, v13.16b\n fmla v17.4s, v0.4s, v9.4s\n" + "ldr q9, [x28, x14]\n" + "fmla v31.4s, v1.4s, v12.4s\n" + "ldr x28, [x16, #0x90]\n" + "fmla v30.4s, v0.4s, v12.4s\n" + "ldr q12, [x27, x14]\n" + "fmla v29.4s, v2.4s, v11.4s\n" + "ldr x27, [x16, #0x98]\n" "fmla v28.4s, v1.4s, v11.4s\n" - "fmla v29.4s, v0.4s, v11.4s\n" - "ldr q11, [x11, x13]\n" - "fmla v27.4s, v4.4s, v11.4s\n" - "ldr x11, [x14, #0x100]\n" - "fmla v30.4s, v2.4s, v11.4s\n" - "fmla v17.4s, v2.4s, v12.4s\n" - "fmla v18.4s, v1.4s, v12.4s\n" - "fmla v19.4s, v0.4s, v12.4s\n" - "ldr q12, [x10, x13]\n" - "ldr x10, [x14, #0x108]\n" - "fmla v16.4s, v6.4s, v10.4s\n" + "ldr q11, [x26, x14]\n" + "fmla v26.4s, v8.4s, v10.4s\n" + "ldr x26, [x16, #0xa0]\n" + "fmla v25.4s, v7.4s, v10.4s\n" + "ldr q13, [x15, #0x0]\n" + "fmla v24.4s, v6.4s, v10.4s\n" + "fmla v22.4s, v5.4s, v10.4s\n" + "fmla v21.4s, v4.4s, v10.4s\n" "fmla v20.4s, v3.4s, v10.4s\n" - "fmla v24.4s, v0.4s, v10.4s\n" - "ldr q10, [x9, x13]\n" - "fmla v22.4s, v8.4s, v11.4s\n" - "ldr x9, [x14, #0x110]\n" - "fmla v23.4s, v7.4s, v11.4s\n" - "fmla v26.4s, v5.4s, v11.4s\n" - "fmla v31.4s, v1.4s, v11.4s\n" - "ldr q11, [x28, x13]\n" - "fmla v27.4s, v2.4s, v12.4s\n" - "ldr x28, [x14, #0x118]\n" - "fmla v28.4s, v0.4s, v10.4s\n" - "fmla v29.4s, v4.4s, v11.4s\n" - "fmla v30.4s, v3.4s, v11.4s\n" - "fmla v19.4s, v8.4s, v12.4s\n" - "fmla v23.4s, v5.4s, v12.4s\n" - "ldr q12, [x27, x13]\n" - "fmla v20.4s, v6.4s, v10.4s\n" - "fmla v24.4s, v3.4s, v10.4s\n" - "ldr q10, [x25, x13]\n" - "fmla v25.4s, v7.4s, v11.4s\n" - "fmla v26.4s, v6.4s, v11.4s\n" - "fmla v28.4s, v5.4s, v11.4s\n" - "fmla v27.4s, v5.4s, v12.4s\n" - "fmla v31.4s, v2.4s, v12.4s\n" - "fmla v29.4s, v7.4s, v10.4s\n" + "fmla v18.4s, v2.4s, v10.4s\n" + "fmla v17.4s, v1.4s, v10.4s\n" + "fmla v16.4s, v0.4s, v10.4s\n" + "ldr q10, [x25, x14]\n" + "fmla v31.4s, v3.4s, v9.4s\n" + "ldr x25, [x16, #0xa8]\n" + "fmla v27.4s, v0.4s, v9.4s\n" + "fmla v28.4s, v5.4s, v12.4s\n" + "fmla v24.4s, v2.4s, v12.4s\n" + "ldr q12, [x23, x14]\n" + "fmla v23.4s, v6.4s, v11.4s\n" + "ldr x23, [x16, #0xb8]\n" + "fmla v19.4s, v3.4s, v11.4s\n" + "ldr q11, [x24, x14]\n" + "fmla v31.4s, v5.4s, v10.4s\n" + "ldr x24, [x16, #0xb0]\n" + "fmla v30.4s, v4.4s, v10.4s\n" + "fmla v29.4s, v3.4s, v10.4s\n" + "fmla v27.4s, v2.4s, v10.4s\n" + "fmla v26.4s, v1.4s, v10.4s\n" + "fmla v25.4s, v0.4s, v10.4s\n" + "ldr q10, [x9, x14]\n" + "fmla v20.4s, v8.4s, v11.4s\n" + "ldr x9, [x16, #0xc8]\n" + "fmla v16.4s, v5.4s, v11.4s\n" + "ldr q11, [x10, x14]\n" + "fmla v30.4s, v5.4s, v12.4s\n" + "ldr x10, [x16, #0xc0]\n" + "fmla v29.4s, v4.4s, v12.4s\n" + "fmla v28.4s, v3.4s, v12.4s\n" + "fmla v26.4s, v2.4s, v12.4s\n" + "fmla v25.4s, v1.4s, v12.4s\n" + "fmla v24.4s, v0.4s, v12.4s\n" + "ldr q12, [x27, x14]\n" + "fmla v19.4s, v7.4s, v11.4s\n" + "ldr x27, [x16, #0xd8]\n" + "fmla v18.4s, v6.4s, v11.4s\n" + "ldr q11, [x28, x14]\n" + "fmla v31.4s, v7.4s, v10.4s\n" + "ldr x28, [x16, #0xd0]\n" "fmla v30.4s, v6.4s, v10.4s\n" - "fmla v24.4s, v8.4s, v11.4s\n" - "ldr q11, [x26, x13]\n" - "fmla v28.4s, v8.4s, v10.4s\n" - "ldr q10, [x11, x13]\n" + "fmla v27.4s, v4.4s, v10.4s\n" + "fmla v26.4s, v3.4s, v10.4s\n" + "fmla v23.4s, v1.4s, v10.4s\n" + "fmla v22.4s, v0.4s, v10.4s\n" + "ldr q10, [x26, x14]\n" + "fmla v17.4s, v8.4s, v11.4s\n" + "ldr x26, [x16, #0xe0]\n" + "fmla v16.4s, v7.4s, v11.4s\n" + "ldr q11, [x25, x14]\n" + "fmla v29.4s, v8.4s, v12.4s\n" + "ldr x25, [x16, #0xe8]\n" + "fmla v28.4s, v7.4s, v12.4s\n" + "fmla v25.4s, v5.4s, v12.4s\n" + "fmla v24.4s, v4.4s, v12.4s\n" + "fmla v21.4s, v2.4s, v12.4s\n" + "fmla v20.4s, v1.4s, v12.4s\n" + "ldr q12, [x24, x14]\n" + "fmla v31.4s, v2.4s, v10.4s\n" + "ldr x24, [x16, #0xf0]\n" + "fmla v30.4s, v1.4s, v10.4s\n" + "fmla v29.4s, v0.4s, v10.4s\n" + "ldr q10, [x23, x14]\n" + "fmla v27.4s, v7.4s, v11.4s\n" + "ldr x23, [x16, #0xf8]\n" + "fmla v26.4s, v6.4s, v11.4s\n" + "fmla v23.4s, v4.4s, v11.4s\n" + "fmla v22.4s, v3.4s, v11.4s\n" + "fmla v19.4s, v1.4s, v11.4s\n" + "fmla v18.4s, v0.4s, v11.4s\n" + "ldr q11, [x10, x14]\n" + "fmla v30.4s, v2.4s, v12.4s\n" + "ldr x10, [x16, #0x100]\n" + "fmla v29.4s, v1.4s, v12.4s\n" + "fmla v28.4s, v0.4s, v12.4s\n" + "ldr q12, [x9, x14]\n" + "fmla v31.4s, v6.4s, v10.4s\n" + "ldr x9, [x16, #0x108]\n" + "fmla v27.4s, v3.4s, v10.4s\n" + "fmla v23.4s, v0.4s, v10.4s\n" + "ldr q10, [x28, x14]\n" "fmla v25.4s, v8.4s, v11.4s\n" - "fmla v26.4s, v7.4s, v11.4s\n" - "fmla v27.4s, v6.4s, v11.4s\n" - "fmla v29.4s, v5.4s, v11.4s\n" - "fmla v30.4s, v4.4s, v11.4s\n" - "fmla v31.4s, v3.4s, v11.4s\n" - "ldr q11, [x10, x13]\n" - "ldp x11, x10, [x14, #0x0]\n" - "fmla v23.4s, v8.4s, v12.4s\n" - "ldr q12, [x24, x13]\n" - "fmla v16.4s, v4.4s, v10.4s\n" - "fmax v16.4s, v16.4s, v15.4s\n" - "fmla v17.4s, v3.4s, v10.4s\n" + "ldr x28, [x16, #0x110]\n" + "fmla v24.4s, v7.4s, v11.4s\n" + "fmla v21.4s, v5.4s, v11.4s\n" + "fmla v20.4s, v4.4s, v11.4s\n" + "fmla v17.4s, v2.4s, v11.4s\n" + "fmla v16.4s, v1.4s, v11.4s\n" + "ldr q11, [x27, x14]\n" + "fmla v28.4s, v8.4s, v12.4s\n" + "ldr x27, [x16, #0x118]\n" + "fmla v24.4s, v5.4s, v12.4s\n" + "fmla v20.4s, v2.4s, v12.4s\n" + "ldr q12, [x26, x14]\n" + "fmla v27.4s, v6.4s, v10.4s\n" + "fmla v23.4s, v3.4s, v10.4s\n" + "fmla v19.4s, v0.4s, v10.4s\n" + "ldr q10, [x25, x14]\n" + "fmla v22.4s, v7.4s, v11.4s\n" + "fmla v21.4s, v6.4s, v11.4s\n" + "fmla v23.4s, v8.4s, v11.4s\n" + "fmla v19.4s, v5.4s, v11.4s\n" + "fmla v18.4s, v4.4s, v11.4s\n" + "fmla v17.4s, v3.4s, v11.4s\n" + "ldr q11, [x24, x14]\n" + "fmla v24.4s, v8.4s, v12.4s\n" + "fmla v20.4s, v5.4s, v12.4s\n" + "fmla v16.4s, v2.4s, v12.4s\n" + "ldr q12, [x23, x14]\n" + "fmla v19.4s, v8.4s, v10.4s\n" + "fmla v18.4s, v7.4s, v10.4s\n" + "fmla v17.4s, v6.4s, v10.4s\n" + "ldr q10, [x10, x14]\n" + "fmla v22.4s, v8.4s, v11.4s\n" + "fmla v21.4s, v7.4s, v11.4s\n" + "fmla v20.4s, v6.4s, v11.4s\n" "fmla v18.4s, v5.4s, v11.4s\n" - "fmax v17.4s, v17.4s, v15.4s\n" - "fmla v19.4s, v4.4s, v11.4s\n" - "fmla v29.4s, v8.4s, v12.4s\n" - "fmax v18.4s, v18.4s, v15.4s\n" - "fmla v30.4s, v7.4s, v12.4s\n" - "fmla v31.4s, v6.4s, v12.4s\n" - "ldr q12, [x9, x13]\n" - "fmax v19.4s, v19.4s, v15.4s\n" - "fmla v20.4s, v1.4s, v10.4s\n" - "fmla v21.4s, v0.4s, v10.4s\n" - "ldr q10, [x28, x13]\n" - "ldr q9, [x11, x8]\n" - "fmla v22.4s, v2.4s, v11.4s\n" - "ldr q13, [x15, #0x0]\n" - "fmla v23.4s, v1.4s, v11.4s\n" + "fmla v17.4s, v4.4s, v11.4s\n" + "fmla v16.4s, v3.4s, v11.4s\n" + "ldr q11, [x9, x14]\n" + "fmla v31.4s, v4.4s, v10.4s\n" + "ldp x10, x9, [x16, #0x0]\n" + "fmla v18.4s, v8.4s, v12.4s\n" + "ldr q9, [x10, x13]\n" + "fmla v17.4s, v7.4s, v12.4s\n" + "fmla v16.4s, v6.4s, v12.4s\n" + "ldr q12, [x28, x14]\n" + "fmla v30.4s, v3.4s, v10.4s\n" + "fmla v27.4s, v1.4s, v10.4s\n" + "fmla v26.4s, v0.4s, v10.4s\n" + "ldr q10, [x27, x14]\n" + "add x14, x14, #0x10\n" + "fmla v29.4s, v5.4s, v11.4s\n" + "ldp x28, x27, [x16, #0x10]\n" + "fmla v28.4s, v4.4s, v11.4s\n" "ldr q0, [x15, #0x10]\n" - "ldr q1, [x15, #0x20]\n" - "fmla v24.4s, v7.4s, v12.4s\n" - "fmla v25.4s, v6.4s, v12.4s\n" + "fmla v25.4s, v2.4s, v11.4s\n" "ldr q2, [x15, #0x30]\n" - "fmla v26.4s, v8.4s, v10.4s\n" + "fmla v24.4s, v1.4s, v11.4s\n" + "ldr q11, [x28, x13]\n" + "fmla v23.4s, v7.4s, v12.4s\n" + "ldr q1, [x15, #0x20]\n" + "fmla v22.4s, v6.4s, v12.4s\n" "ldr q6, [x15, #0x70]\n" - "fmla v27.4s, v7.4s, v10.4s\n" - "ldr q7, [x15, #0x80]\n" - "fmin v16.4s, v16.4s, v14.4s\n" - "fmin v17.4s, v17.4s, v14.4s\n" - "str q16, [x23, x12]\n" - "ldr q8, [x15, #0x90]\n" - "fmin v18.4s, v18.4s, v14.4s\n" - "fmin v19.4s, v19.4s, v14.4s\n" - "str q17, [x22, x12]\n" - "ldr x23, [x16, #0x20]\n" - "fmax v20.4s, v20.4s, v15.4s\n" - "fmax v21.4s, v21.4s, v15.4s\n" - "str q18, [x21, x12]\n" - "ldr x22, [x16, #0x28]\n" - "fmax v22.4s, v22.4s, v15.4s\n" - "fmax v23.4s, v23.4s, v15.4s\n" - "str q19, [x20, x12]\n" - "ldr x21, [x16, #0x30]\n" - "ldr x20, [x16, #0x38]\n" - "fmla v28.4s, v4.4s, v12.4s\n" - "fmla v29.4s, v3.4s, v12.4s\n" + "fmla v19.4s, v4.4s, v12.4s\n" + "fmla v18.4s, v3.4s, v12.4s\n" + "ldr q12, [x27, x13]\n" + "fmla v21.4s, v8.4s, v10.4s\n" "ldr q3, [x15, #0x40]\n" - "fmla v30.4s, v5.4s, v10.4s\n" + "fmla v20.4s, v7.4s, v10.4s\n" + "ldr q7, [x15, #0x80]\n" + "fmla v17.4s, v5.4s, v10.4s\n" "ldr q5, [x15, #0x60]\n" - "fmla v31.4s, v4.4s, v10.4s\n" - "ldr q10, [x10, x8]\n" + "fmla v16.4s, v4.4s, v10.4s\n" + "ldr q10, [x9, x13]\n" + "add x13, x13, #0x10\n" + "fmax v31.4s, v31.4s, v15.4s\n" "ldr q4, [x15, #0x50]\n" - "fmin v20.4s, v20.4s, v14.4s\n" - "fmin v21.4s, v21.4s, v14.4s\n" - "str q20, [x23, x12]\n" - "fmin v22.4s, v22.4s, v14.4s\n" - "fmin v23.4s, v23.4s, v14.4s\n" - "str q21, [x22, x12]\n" - "ldr x23, [x16, #0x40]\n" - "fmax v24.4s, v24.4s, v15.4s\n" - "fmax v25.4s, v25.4s, v15.4s\n" - "str q22, [x21, x12]\n" - "ldr x22, [x16, #0x48]\n" - "fmax v26.4s, v26.4s, v15.4s\n" - "fmax v27.4s, v27.4s, v15.4s\n" - "str q23, [x20, x12]\n" - "ldr x21, [x16, #0x50]\n" - "ldr x20, [x16, #0x58]\n" - "ldp x9, x28, [x14, #0x10]\n" - "fmin v24.4s, v24.4s, v14.4s\n" - "fmin v25.4s, v25.4s, v14.4s\n" - "ldr q11, [x9, x8]\n" - "ldr q12, [x28, x8]\n" - "fmin v26.4s, v26.4s, v14.4s\n" - "fmin v27.4s, v27.4s, v14.4s\n" - "fmax v28.4s, v28.4s, v15.4s\n" - "fmax v29.4s, v29.4s, v15.4s\n" - "str q24, [x23, x12]\n" - "ldr x23, [x16, #0x60]\n" + "cmp x13, x11, LSL #4\n" "fmax v30.4s, v30.4s, v15.4s\n" - "fmax v31.4s, v31.4s, v15.4s\n" - "str q25, [x22, x12]\n" - "ldr x22, [x16, #0x68]\n" - "str q26, [x21, x12]\n" - "ldr x21, [x16, #0x70]\n" - "add x8, x8, #0x10\n" - "cmp x8, x17, LSL #4\n" - "str q27, [x20, x12]\n" - "ldr x20, [x16, #0x78]\n" - "fmin v28.4s, v28.4s, v14.4s\n" - "fmin v29.4s, v29.4s, v14.4s\n" - "fmin v30.4s, v30.4s, v14.4s\n" - "fmin v31.4s, v31.4s, v14.4s\n" - "add x13, x13, #0x10\n" - "str q28, [x23, x12]\n" - "str q29, [x22, x12]\n" + "ldr q8, [x15, #0x90]\n" "add x15, x15, #0xa0\n" + "fmax v29.4s, v29.4s, v15.4s\n" + "fmax v28.4s, v28.4s, v15.4s\n" + "fmin v31.4s, v31.4s, v14.4s\n" + "str q31, [x22, x12]\n" + "fmin v30.4s, v30.4s, v14.4s\n" + "fmin v29.4s, v29.4s, v14.4s\n" + "ldr x22, [x17, #0x20]\n" + "fmin v28.4s, v28.4s, v14.4s\n" "str q30, [x21, x12]\n" - "str q31, [x20, x12]\n" + "fmax v27.4s, v27.4s, v15.4s\n" + "fmax v26.4s, v26.4s, v15.4s\n" + "str q29, [x20, x12]\n" + "fmax v25.4s, v25.4s, v15.4s\n" + "str q28, [x19, x12]\n" + "fmax v24.4s, v24.4s, v15.4s\n" + "ldr x21, [x17, #0x28]\n" + "fmin v27.4s, v27.4s, v14.4s\n" + "ldr x20, [x17, #0x30]\n" + "fmin v26.4s, v26.4s, v14.4s\n" + "ldr x19, [x17, #0x38]\n" + "fmin v25.4s, v25.4s, v14.4s\n" + "str q27, [x22, x12]\n" + "fmin v24.4s, v24.4s, v14.4s\n" + "str q26, [x21, x12]\n" + "fmax v23.4s, v23.4s, v15.4s\n" + "str q25, [x20, x12]\n" + "fmax v22.4s, v22.4s, v15.4s\n" + "str q24, [x19, x12]\n" + "fmax v21.4s, v21.4s, v15.4s\n" + "ldr x22, [x17, #0x40]\n" + "fmin v23.4s, v23.4s, v14.4s\n" + "ldr x21, [x17, #0x48]\n" + "fmin v22.4s, v22.4s, v14.4s\n" + "ldr x20, [x17, #0x50]\n" + "fmin v21.4s, v21.4s, v14.4s\n" + "str q23, [x22, x12]\n" + "fmax v20.4s, v20.4s, v15.4s\n" + "str q22, [x21, x12]\n" + "fmax v19.4s, v19.4s, v15.4s\n" + "str q21, [x20, x12]\n" + "fmax v18.4s, v18.4s, v15.4s\n" + "ldr x19, [x17, #0x58]\n" + "fmin v20.4s, v20.4s, v14.4s\n" + "ldr x22, [x17, #0x60]\n" + "fmin v19.4s, v19.4s, v14.4s\n" + "ldr x21, [x17, #0x68]\n" + "fmin v18.4s, v18.4s, v14.4s\n" + "str q20, [x19, x12]\n" + "fmax v17.4s, v17.4s, v15.4s\n" + "str q19, [x22, x12]\n" + "fmax v16.4s, v16.4s, v15.4s\n" + "str q18, [x21, x12]\n" + "ldr x20, [x17, #0x70]\n" + "fmin v17.4s, v17.4s, v14.4s\n" + "ldr x19, [x17, #0x78]\n" + "fmin v16.4s, v16.4s, v14.4s\n" + "str q17, [x20, x12]\n" + "str q16, [x19, x12]\n" "blt 1b\n" "2:" // Channel tail - "mov v21.16b, v13.16b\n fmla v21.4s, v4.4s, v9.4s\n" - "mov v16.16b, v13.16b\n fmla v16.4s, v8.4s, v9.4s\n" - "ldr x27, [x14, #0x20]\n" - "ldr x26, [x14, #0x30]\n" - "mov v22.16b, v13.16b\n fmla v22.4s, v3.4s, v9.4s\n" - "mov v25.16b, v13.16b\n fmla v25.4s, v1.4s, v9.4s\n" - "ldr x25, [x14, #0x28]\n" - "ldr x24, [x14, #0x38]\n" - "mov v26.16b, v13.16b\n fmla v26.4s, v0.4s, v9.4s\n" - "mov v17.16b, v13.16b\n fmla v17.4s, v7.4s, v9.4s\n" - "ldr x11, [x14, #0x40]\n" - "ldr x10, [x14, #0x48]\n" - "mov v18.16b, v13.16b\n fmla v18.4s, v6.4s, v9.4s\n" - "fmla v21.4s, v5.4s, v12.4s\n" - "ldr x9, [x14, #0x50]\n" - "ldr x28, [x14, #0x58]\n" - "mov v20.16b, v13.16b\n fmla v20.4s, v5.4s, v9.4s\n" - "mov v24.16b, v13.16b\n fmla v24.4s, v2.4s, v9.4s\n" - "ldr q9, [x26, x13]\n" - "ldr x26, [x14, #0x70]\n" - "fmla v16.4s, v0.4s, v10.4s\n" - "ldr q10, [x27, x13]\n" - "mov v19.16b, v13.16b\n fmla v19.4s, v2.4s, v11.4s\n" - "ldr q11, [x25, x13]\n" - "fmla v22.4s, v4.4s, v12.4s\n" - "fmla v25.4s, v2.4s, v12.4s\n" - "ldr x27, [x14, #0x60]\n" - "ldr x25, [x14, #0x68]\n" - "fmla v26.4s, v1.4s, v12.4s\n" - "fmla v17.4s, v8.4s, v12.4s\n" - "ldr x23, [x16, #0x0]\n" - "ldr x22, [x16, #0x8]\n" - "fmla v18.4s, v7.4s, v12.4s\n" - "mov v28.16b, v13.16b\n fmla v28.4s, v6.4s, v10.4s\n" - "ldr q10, [x10, x13]\n" - "ldr x10, [x14, #0x88]\n" - "fmla v21.4s, v7.4s, v9.4s\n" - "fmla v19.4s, v6.4s, v12.4s\n" - "ldr x21, [x16, #0x10]\n" - "ldr x20, [x16, #0x18]\n" - "mov v23.16b, v13.16b\n fmla v23.4s, v3.4s, v12.4s\n" - "mov v27.16b, v13.16b\n fmla v27.4s, v0.4s, v12.4s\n" - "ldr q12, [x24, x13]\n" - "ldr x24, [x14, #0x78]\n" - "mov v31.16b, v13.16b\n fmla v31.4s, v8.4s, v11.4s\n" - "ldr q11, [x11, x13]\n" - "fmla v22.4s, v6.4s, v9.4s\n" - "ldr x11, [x14, #0x80]\n" - "fmla v25.4s, v4.4s, v9.4s\n" - "fmla v26.4s, v3.4s, v9.4s\n" + "mov v31.16b, v13.16b\n fmla v31.4s, v8.4s, v9.4s\n" + "ldr x26, [x16, #0x20]\n" "add x12, x12, #0x10\n" - "fmla v20.4s, v8.4s, v9.4s\n" - "fmla v24.4s, v5.4s, v9.4s\n" - "fmla v28.4s, v2.4s, v9.4s\n" - "fmla v16.4s, v1.4s, v12.4s\n" - "fmla v17.4s, v0.4s, v12.4s\n" - "ldr q12, [x28, x13]\n" - "fmla v18.4s, v2.4s, v11.4s\n" - "ldr x28, [x14, #0x98]\n" - "fmla v21.4s, v8.4s, v10.4s\n" - "fmla v19.4s, v1.4s, v11.4s\n" - "ldr q11, [x27, x13]\n" - "ldr x27, [x14, #0xa0]\n" - "fmla v22.4s, v7.4s, v10.4s\n" - "fmla v23.4s, v6.4s, v10.4s\n" - "fmla v25.4s, v5.4s, v10.4s\n" - "fmla v26.4s, v4.4s, v10.4s\n" - "fmla v27.4s, v3.4s, v10.4s\n" + "mov v30.16b, v13.16b\n fmla v30.4s, v7.4s, v9.4s\n" + "ldr x25, [x16, #0x28]\n" + "mov v29.16b, v13.16b\n fmla v29.4s, v6.4s, v9.4s\n" + "ldr x24, [x16, #0x30]\n" + "mov v27.16b, v13.16b\n fmla v27.4s, v5.4s, v9.4s\n" + "ldr x23, [x16, #0x38]\n" + "mov v26.16b, v13.16b\n fmla v26.4s, v4.4s, v9.4s\n" + "ldr x10, [x16, #0x40]\n" + "mov v25.16b, v13.16b\n fmla v25.4s, v3.4s, v9.4s\n" + "ldr x9, [x16, #0x48]\n" + "mov v23.16b, v13.16b\n fmla v23.4s, v2.4s, v9.4s\n" + "ldr x28, [x16, #0x50]\n" + "mov v22.16b, v13.16b\n fmla v22.4s, v1.4s, v9.4s\n" + "ldr x27, [x16, #0x58]\n" + "mov v21.16b, v13.16b\n fmla v21.4s, v0.4s, v9.4s\n" + "ldr q9, [x24, x14]\n" "fmla v31.4s, v0.4s, v10.4s\n" - "fmla v24.4s, v6.4s, v11.4s\n" - "fmla v28.4s, v3.4s, v11.4s\n" - "ldr q11, [x26, x13]\n" - "ldr x26, [x14, #0xb0]\n" - "fmla v19.4s, v5.4s, v12.4s\n" - "fmla v23.4s, v2.4s, v12.4s\n" - "ldr q12, [x24, x13]\n" - "ldr x24, [x14, #0xb8]\n" - "fmla v27.4s, v8.4s, v11.4s\n" - "fmla v31.4s, v5.4s, v11.4s\n" - "mov v29.16b, v13.16b\n fmla v29.4s, v1.4s, v9.4s\n" - "mov v30.16b, v13.16b\n fmla v30.4s, v0.4s, v9.4s\n" - "ldr q9, [x9, x13]\n" - "ldr x9, [x14, #0x90]\n" - "fmla v29.4s, v2.4s, v10.4s\n" - "fmla v30.4s, v1.4s, v10.4s\n" - "ldr q10, [x25, x13]\n" - "ldr x25, [x14, #0xa8]\n" - "fmla v16.4s, v3.4s, v9.4s\n" - "fmla v20.4s, v0.4s, v9.4s\n" - "ldr q11, [x11, x13]\n" - "ldr x11, [x14, #0xc0]\n" - "fmla v17.4s, v4.4s, v10.4s\n" - "fmla v18.4s, v3.4s, v10.4s\n" - "fmla v21.4s, v1.4s, v10.4s\n" - "fmla v22.4s, v0.4s, v10.4s\n" - "fmla v16.4s, v5.4s, v10.4s\n" - "fmla v20.4s, v2.4s, v10.4s\n" - "ldr q10, [x10, x13]\n" - "ldr x10, [x14, #0xc8]\n" - "fmla v17.4s, v5.4s, v12.4s\n" - "fmla v18.4s, v4.4s, v12.4s\n" - "fmla v21.4s, v2.4s, v12.4s\n" - "fmla v19.4s, v3.4s, v12.4s\n" - "fmla v22.4s, v1.4s, v12.4s\n" - "fmla v23.4s, v0.4s, v12.4s\n" - "ldr q12, [x28, x13]\n" - "ldr x28, [x14, #0xd8]\n" - "fmla v28.4s, v7.4s, v11.4s\n" - "fmla v29.4s, v6.4s, v11.4s\n" - "ldr q11, [x9, x13]\n" - "ldr x9, [x14, #0xd0]\n" - "fmla v16.4s, v7.4s, v10.4s\n" - "fmla v17.4s, v6.4s, v10.4s\n" - "fmla v20.4s, v4.4s, v10.4s\n" - "fmla v21.4s, v3.4s, v10.4s\n" - "fmla v24.4s, v1.4s, v10.4s\n" - "fmla v25.4s, v0.4s, v10.4s\n" - "ldr q10, [x27, x13]\n" - "ldr x27, [x14, #0xe0]\n" - "fmla v18.4s, v8.4s, v12.4s\n" - "fmla v30.4s, v8.4s, v11.4s\n" - "fmla v31.4s, v7.4s, v11.4s\n" - "ldr q11, [x25, x13]\n" - "fmla v27.4s, v1.4s, v12.4s\n" - "ldr x25, [x14, #0xe8]\n" - "fmla v19.4s, v7.4s, v12.4s\n" - "fmla v22.4s, v5.4s, v12.4s\n" - "fmla v23.4s, v4.4s, v12.4s\n" - "fmla v26.4s, v2.4s, v12.4s\n" - "ldr q12, [x26, x13]\n" - "ldr x26, [x14, #0xf0]\n" - "fmla v16.4s, v2.4s, v10.4s\n" - "fmla v17.4s, v1.4s, v10.4s\n" - "fmla v18.4s, v0.4s, v10.4s\n" - "ldr q10, [x24, x13]\n" - "fmla v20.4s, v7.4s, v11.4s\n" - "ldr x24, [x14, #0xf8]\n" - "fmla v21.4s, v6.4s, v11.4s\n" - "fmla v24.4s, v4.4s, v11.4s\n" - "fmla v25.4s, v3.4s, v11.4s\n" + "ldr q10, [x26, x14]\n" + "mov v28.16b, v13.16b\n fmla v28.4s, v2.4s, v11.4s\n" + "ldr q11, [x25, x14]\n" + "fmla v30.4s, v8.4s, v12.4s\n" + "ldr x26, [x16, #0x60]\n" + "fmla v29.4s, v7.4s, v12.4s\n" + "ldr x25, [x16, #0x68]\n" + "fmla v26.4s, v5.4s, v12.4s\n" + "ldr x24, [x16, #0x70]\n" + "fmla v28.4s, v6.4s, v12.4s\n" + "ldr x22, [x17, #0x0]\n" + "fmla v25.4s, v4.4s, v12.4s\n" + "ldr x21, [x17, #0x8]\n" + "mov v24.16b, v13.16b\n fmla v24.4s, v3.4s, v12.4s\n" + "ldr x20, [x17, #0x10]\n" + "fmla v22.4s, v2.4s, v12.4s\n" + "ldr x19, [x17, #0x18]\n" + "fmla v21.4s, v1.4s, v12.4s\n" + "mov v20.16b, v13.16b\n fmla v20.4s, v0.4s, v12.4s\n" + "ldr q12, [x23, x14]\n" + "mov v19.16b, v13.16b\n fmla v19.4s, v6.4s, v10.4s\n" + "ldr q10, [x9, x14]\n" + "mov v16.16b, v13.16b\n fmla v16.4s, v8.4s, v11.4s\n" + "ldr q11, [x10, x14]\n" + "fmla v27.4s, v8.4s, v9.4s\n" + "ldr x23, [x16, #0x78]\n" + "fmla v26.4s, v7.4s, v9.4s\n" + "ldr x10, [x16, #0x80]\n" + "fmla v25.4s, v6.4s, v9.4s\n" + "ldr x9, [x16, #0x88]\n" + "fmla v23.4s, v5.4s, v9.4s\n" + "fmla v22.4s, v4.4s, v9.4s\n" + "fmla v21.4s, v3.4s, v9.4s\n" + "fmla v19.4s, v2.4s, v9.4s\n" + "mov v18.16b, v13.16b\n fmla v18.4s, v1.4s, v9.4s\n" + "mov v17.16b, v13.16b\n fmla v17.4s, v0.4s, v9.4s\n" + "ldr q9, [x28, x14]\n" + "fmla v31.4s, v1.4s, v12.4s\n" + "ldr x28, [x16, #0x90]\n" + "fmla v30.4s, v0.4s, v12.4s\n" + "ldr q12, [x27, x14]\n" + "fmla v29.4s, v2.4s, v11.4s\n" + "ldr x27, [x16, #0x98]\n" "fmla v28.4s, v1.4s, v11.4s\n" - "fmla v29.4s, v0.4s, v11.4s\n" - "ldr q11, [x11, x13]\n" - "fmla v27.4s, v4.4s, v11.4s\n" - "ldr x11, [x14, #0x100]\n" - "fmla v30.4s, v2.4s, v11.4s\n" - "fmla v17.4s, v2.4s, v12.4s\n" - "fmla v18.4s, v1.4s, v12.4s\n" - "fmla v19.4s, v0.4s, v12.4s\n" - "ldr q12, [x10, x13]\n" - "ldr x10, [x14, #0x108]\n" - "fmla v16.4s, v6.4s, v10.4s\n" + "ldr q11, [x26, x14]\n" + "fmla v26.4s, v8.4s, v10.4s\n" + "ldr x26, [x16, #0xa0]\n" + "fmla v25.4s, v7.4s, v10.4s\n" + "fmla v24.4s, v6.4s, v10.4s\n" + "fmla v22.4s, v5.4s, v10.4s\n" + "fmla v21.4s, v4.4s, v10.4s\n" "fmla v20.4s, v3.4s, v10.4s\n" - "fmla v24.4s, v0.4s, v10.4s\n" - "ldr q10, [x9, x13]\n" - "fmla v22.4s, v8.4s, v11.4s\n" - "ldr x9, [x14, #0x110]\n" - "fmla v23.4s, v7.4s, v11.4s\n" - "fmla v26.4s, v5.4s, v11.4s\n" - "fmla v31.4s, v1.4s, v11.4s\n" - "ldr q11, [x28, x13]\n" - "fmla v27.4s, v2.4s, v12.4s\n" - "ldr x28, [x14, #0x118]\n" - "fmla v28.4s, v0.4s, v10.4s\n" - "fmla v29.4s, v4.4s, v11.4s\n" - "fmla v30.4s, v3.4s, v11.4s\n" - "fmla v19.4s, v8.4s, v12.4s\n" - "fmla v23.4s, v5.4s, v12.4s\n" - "ldr q12, [x27, x13]\n" - "fmla v20.4s, v6.4s, v10.4s\n" - "fmla v24.4s, v3.4s, v10.4s\n" - "ldr q10, [x25, x13]\n" - "fmla v25.4s, v7.4s, v11.4s\n" - "fmla v26.4s, v6.4s, v11.4s\n" - "fmla v28.4s, v5.4s, v11.4s\n" - "fmla v27.4s, v5.4s, v12.4s\n" - "fmla v31.4s, v2.4s, v12.4s\n" - "fmla v29.4s, v7.4s, v10.4s\n" + "fmla v18.4s, v2.4s, v10.4s\n" + "fmla v17.4s, v1.4s, v10.4s\n" + "fmla v16.4s, v0.4s, v10.4s\n" + "ldr q10, [x25, x14]\n" + "fmla v31.4s, v3.4s, v9.4s\n" + "ldr x25, [x16, #0xa8]\n" + "fmla v27.4s, v0.4s, v9.4s\n" + "fmla v28.4s, v5.4s, v12.4s\n" + "fmla v24.4s, v2.4s, v12.4s\n" + "ldr q12, [x23, x14]\n" + "fmla v23.4s, v6.4s, v11.4s\n" + "ldr x23, [x16, #0xb8]\n" + "fmla v19.4s, v3.4s, v11.4s\n" + "ldr q11, [x24, x14]\n" + "fmla v31.4s, v5.4s, v10.4s\n" + "ldr x24, [x16, #0xb0]\n" + "fmla v30.4s, v4.4s, v10.4s\n" + "fmla v29.4s, v3.4s, v10.4s\n" + "fmla v27.4s, v2.4s, v10.4s\n" + "fmla v26.4s, v1.4s, v10.4s\n" + "fmla v25.4s, v0.4s, v10.4s\n" + "ldr q10, [x9, x14]\n" + "fmla v20.4s, v8.4s, v11.4s\n" + "ldr x9, [x16, #0xc8]\n" + "fmla v16.4s, v5.4s, v11.4s\n" + "ldr q11, [x10, x14]\n" + "fmla v30.4s, v5.4s, v12.4s\n" + "ldr x10, [x16, #0xc0]\n" + "fmla v29.4s, v4.4s, v12.4s\n" + "fmla v28.4s, v3.4s, v12.4s\n" + "fmla v26.4s, v2.4s, v12.4s\n" + "fmla v25.4s, v1.4s, v12.4s\n" + "fmla v24.4s, v0.4s, v12.4s\n" + "ldr q12, [x27, x14]\n" + "fmla v19.4s, v7.4s, v11.4s\n" + "ldr x27, [x16, #0xd8]\n" + "fmla v18.4s, v6.4s, v11.4s\n" + "ldr q11, [x28, x14]\n" + "fmla v31.4s, v7.4s, v10.4s\n" + "ldr x28, [x16, #0xd0]\n" "fmla v30.4s, v6.4s, v10.4s\n" - "fmla v24.4s, v8.4s, v11.4s\n" - "ldr q11, [x26, x13]\n" - "fmla v28.4s, v8.4s, v10.4s\n" - "ldr q10, [x11, x13]\n" + "fmla v27.4s, v4.4s, v10.4s\n" + "fmla v26.4s, v3.4s, v10.4s\n" + "fmla v23.4s, v1.4s, v10.4s\n" + "fmla v22.4s, v0.4s, v10.4s\n" + "ldr q10, [x26, x14]\n" + "fmla v17.4s, v8.4s, v11.4s\n" + "ldr x26, [x16, #0xe0]\n" + "fmla v16.4s, v7.4s, v11.4s\n" + "ldr q11, [x25, x14]\n" + "fmla v29.4s, v8.4s, v12.4s\n" + "ldr x25, [x16, #0xe8]\n" + "fmla v28.4s, v7.4s, v12.4s\n" + "fmla v25.4s, v5.4s, v12.4s\n" + "fmla v24.4s, v4.4s, v12.4s\n" + "fmla v21.4s, v2.4s, v12.4s\n" + "fmla v20.4s, v1.4s, v12.4s\n" + "ldr q12, [x24, x14]\n" + "fmla v31.4s, v2.4s, v10.4s\n" + "ldr x24, [x16, #0xf0]\n" + "fmla v30.4s, v1.4s, v10.4s\n" + "fmla v29.4s, v0.4s, v10.4s\n" + "ldr q10, [x23, x14]\n" + "fmla v27.4s, v7.4s, v11.4s\n" + "ldr x23, [x16, #0xf8]\n" + "fmla v26.4s, v6.4s, v11.4s\n" + "fmla v23.4s, v4.4s, v11.4s\n" + "fmla v22.4s, v3.4s, v11.4s\n" + "fmla v19.4s, v1.4s, v11.4s\n" + "fmla v18.4s, v0.4s, v11.4s\n" + "ldr q11, [x10, x14]\n" + "fmla v30.4s, v2.4s, v12.4s\n" + "ldr x10, [x16, #0x100]\n" + "fmla v29.4s, v1.4s, v12.4s\n" + "fmla v28.4s, v0.4s, v12.4s\n" + "ldr q12, [x9, x14]\n" + "fmla v31.4s, v6.4s, v10.4s\n" + "ldr x9, [x16, #0x108]\n" + "fmla v27.4s, v3.4s, v10.4s\n" + "fmla v23.4s, v0.4s, v10.4s\n" + "ldr q10, [x28, x14]\n" "fmla v25.4s, v8.4s, v11.4s\n" - "fmla v26.4s, v7.4s, v11.4s\n" - "fmla v27.4s, v6.4s, v11.4s\n" - "fmla v29.4s, v5.4s, v11.4s\n" - "fmla v30.4s, v4.4s, v11.4s\n" - "fmla v31.4s, v3.4s, v11.4s\n" - "ldr q11, [x10, x13]\n" - "fmla v23.4s, v8.4s, v12.4s\n" - "ldr q12, [x24, x13]\n" - "fmla v16.4s, v4.4s, v10.4s\n" - "fmax v16.4s, v16.4s, v15.4s\n" - "fmla v17.4s, v3.4s, v10.4s\n" + "ldr x28, [x16, #0x110]\n" + "fmla v24.4s, v7.4s, v11.4s\n" + "fmla v21.4s, v5.4s, v11.4s\n" + "fmla v20.4s, v4.4s, v11.4s\n" + "fmla v17.4s, v2.4s, v11.4s\n" + "fmla v16.4s, v1.4s, v11.4s\n" + "ldr q11, [x27, x14]\n" + "fmla v28.4s, v8.4s, v12.4s\n" + "ldr x27, [x16, #0x118]\n" + "fmla v24.4s, v5.4s, v12.4s\n" + "fmla v20.4s, v2.4s, v12.4s\n" + "ldr q12, [x26, x14]\n" + "fmla v27.4s, v6.4s, v10.4s\n" + "fmla v23.4s, v3.4s, v10.4s\n" + "fmla v19.4s, v0.4s, v10.4s\n" + "ldr q10, [x25, x14]\n" + "fmla v22.4s, v7.4s, v11.4s\n" + "fmla v21.4s, v6.4s, v11.4s\n" + "fmla v23.4s, v8.4s, v11.4s\n" + "fmla v19.4s, v5.4s, v11.4s\n" + "fmla v18.4s, v4.4s, v11.4s\n" + "fmla v17.4s, v3.4s, v11.4s\n" + "ldr q11, [x24, x14]\n" + "fmla v24.4s, v8.4s, v12.4s\n" + "fmla v20.4s, v5.4s, v12.4s\n" + "fmla v16.4s, v2.4s, v12.4s\n" + "ldr q12, [x23, x14]\n" + "fmla v19.4s, v8.4s, v10.4s\n" + "fmla v18.4s, v7.4s, v10.4s\n" + "fmla v17.4s, v6.4s, v10.4s\n" + "ldr q10, [x10, x14]\n" + "fmla v22.4s, v8.4s, v11.4s\n" + "fmla v21.4s, v7.4s, v11.4s\n" + "fmla v20.4s, v6.4s, v11.4s\n" "fmla v18.4s, v5.4s, v11.4s\n" - "fmax v17.4s, v17.4s, v15.4s\n" - "fmla v19.4s, v4.4s, v11.4s\n" - "fmla v29.4s, v8.4s, v12.4s\n" - "fmax v18.4s, v18.4s, v15.4s\n" - "fmla v30.4s, v7.4s, v12.4s\n" - "fmla v31.4s, v6.4s, v12.4s\n" - "ldr q12, [x9, x13]\n" - "fmax v19.4s, v19.4s, v15.4s\n" - "fmla v20.4s, v1.4s, v10.4s\n" - "fmla v21.4s, v0.4s, v10.4s\n" - "ldr q10, [x28, x13]\n" - "fmin v16.4s, v16.4s, v14.4s\n" - "fmla v22.4s, v2.4s, v11.4s\n" - "fmla v23.4s, v1.4s, v11.4s\n" - "fmin v17.4s, v17.4s, v14.4s\n" - "str q16, [x23, x12]\n" - "fmla v24.4s, v7.4s, v12.4s\n" - "fmla v25.4s, v6.4s, v12.4s\n" - "fmin v18.4s, v18.4s, v14.4s\n" - "str q17, [x22, x12]\n" - "fmla v26.4s, v8.4s, v10.4s\n" - "fmla v27.4s, v7.4s, v10.4s\n" - "fmin v19.4s, v19.4s, v14.4s\n" - "str q18, [x21, x12]\n" - "fmax v20.4s, v20.4s, v15.4s\n" - "fmax v21.4s, v21.4s, v15.4s\n" - "str q19, [x20, x12]\n" - "ldr x23, [x16, #0x20]\n" - "fmax v22.4s, v22.4s, v15.4s\n" - "fmax v23.4s, v23.4s, v15.4s\n" - "ldr x22, [x16, #0x28]\n" - "ldr x21, [x16, #0x30]\n" - "ldr x20, [x16, #0x38]\n" - "fmla v28.4s, v4.4s, v12.4s\n" - "fmla v29.4s, v3.4s, v12.4s\n" - "fmin v20.4s, v20.4s, v14.4s\n" - "fmla v30.4s, v5.4s, v10.4s\n" + "fmla v17.4s, v4.4s, v11.4s\n" + "fmla v16.4s, v3.4s, v11.4s\n" + "ldr q11, [x9, x14]\n" "fmla v31.4s, v4.4s, v10.4s\n" - "fmin v21.4s, v21.4s, v14.4s\n" - "str q20, [x23, x12]\n" - "fmin v22.4s, v22.4s, v14.4s\n" - "fmin v23.4s, v23.4s, v14.4s\n" - "str q21, [x22, x12]\n" - "ldr x23, [x16, #0x40]\n" - "fmax v24.4s, v24.4s, v15.4s\n" - "fmax v25.4s, v25.4s, v15.4s\n" - "str q22, [x21, x12]\n" - "ldr x22, [x16, #0x48]\n" - "fmax v26.4s, v26.4s, v15.4s\n" - "fmax v27.4s, v27.4s, v15.4s\n" - "str q23, [x20, x12]\n" - "ldr x21, [x16, #0x50]\n" - "ldr x20, [x16, #0x58]\n" - "fmin v24.4s, v24.4s, v14.4s\n" - "fmin v25.4s, v25.4s, v14.4s\n" - "str q24, [x23, x12]\n" - "fmin v26.4s, v26.4s, v14.4s\n" - "fmin v27.4s, v27.4s, v14.4s\n" - "str q25, [x22, x12]\n" - "ldr x23, [x16, #0x60]\n" - "fmax v28.4s, v28.4s, v15.4s\n" - "fmax v29.4s, v29.4s, v15.4s\n" - "str q26, [x21, x12]\n" - "ldr x22, [x16, #0x68]\n" - "fmax v30.4s, v30.4s, v15.4s\n" + "fmla v18.4s, v8.4s, v12.4s\n" + "fmla v17.4s, v7.4s, v12.4s\n" + "fmla v16.4s, v6.4s, v12.4s\n" + "ldr q12, [x28, x14]\n" + "fmla v30.4s, v3.4s, v10.4s\n" + "fmla v27.4s, v1.4s, v10.4s\n" + "fmla v26.4s, v0.4s, v10.4s\n" + "ldr q10, [x27, x14]\n" + "add x14, x14, #0x10\n" + "fmla v29.4s, v5.4s, v11.4s\n" + "fmla v28.4s, v4.4s, v11.4s\n" + "fmla v25.4s, v2.4s, v11.4s\n" + "fmla v24.4s, v1.4s, v11.4s\n" + "fmla v23.4s, v7.4s, v12.4s\n" + "fmla v22.4s, v6.4s, v12.4s\n" + "fmla v19.4s, v4.4s, v12.4s\n" + "fmla v18.4s, v3.4s, v12.4s\n" + "fmla v21.4s, v8.4s, v10.4s\n" + "fmla v20.4s, v7.4s, v10.4s\n" + "fmla v17.4s, v5.4s, v10.4s\n" + "fmla v16.4s, v4.4s, v10.4s\n" "fmax v31.4s, v31.4s, v15.4s\n" - "str q27, [x20, x12]\n" - "ldr x21, [x16, #0x70]\n" - "ldr x20, [x16, #0x78]\n" - "fmin v28.4s, v28.4s, v14.4s\n" - "fmin v29.4s, v29.4s, v14.4s\n" - "str q28, [x23, x12]\n" - "fmin v30.4s, v30.4s, v14.4s\n" + "fmax v30.4s, v30.4s, v15.4s\n" + "fmax v29.4s, v29.4s, v15.4s\n" "fmin v31.4s, v31.4s, v14.4s\n" - "str q29, [x22, x12]\n" - "add x13, x13, #0x10\n" + "str q31, [x22, x12]\n" + "fmin v30.4s, v30.4s, v14.4s\n" + "fmin v29.4s, v29.4s, v14.4s\n" + "ldr x22, [x17, #0x20]\n" + "fmax v28.4s, v28.4s, v15.4s\n" "str q30, [x21, x12]\n" - "str q31, [x20, x12]\n" + "fmax v27.4s, v27.4s, v15.4s\n" + "fmax v26.4s, v26.4s, v15.4s\n" + "str q29, [x20, x12]\n" + "fmin v28.4s, v28.4s, v14.4s\n" + "ldr x21, [x17, #0x28]\n" + "fmax v25.4s, v25.4s, v15.4s\n" + "ldr x20, [x17, #0x30]\n" + "fmin v27.4s, v27.4s, v14.4s\n" + "str q28, [x19, x12]\n" + "fmin v26.4s, v26.4s, v14.4s\n" + "ldr x19, [x17, #0x38]\n" + "fmin v25.4s, v25.4s, v14.4s\n" + "str q27, [x22, x12]\n" + "fmax v24.4s, v24.4s, v15.4s\n" + "str q26, [x21, x12]\n" + "fmax v23.4s, v23.4s, v15.4s\n" + "str q25, [x20, x12]\n" + "fmax v22.4s, v22.4s, v15.4s\n" + "ldr x22, [x17, #0x40]\n" + "fmin v24.4s, v24.4s, v14.4s\n" + "ldr x21, [x17, #0x48]\n" + "fmin v23.4s, v23.4s, v14.4s\n" + "ldr x20, [x17, #0x50]\n" + "fmin v22.4s, v22.4s, v14.4s\n" + "str q24, [x19, x12]\n" + "fmax v21.4s, v21.4s, v15.4s\n" + "str q23, [x22, x12]\n" + "fmax v20.4s, v20.4s, v15.4s\n" + "str q22, [x21, x12]\n" + "fmax v19.4s, v19.4s, v15.4s\n" + "ldr x19, [x17, #0x58]\n" + "fmin v21.4s, v21.4s, v14.4s\n" + "ldr x22, [x17, #0x60]\n" + "fmin v20.4s, v20.4s, v14.4s\n" + "ldr x21, [x17, #0x68]\n" + "fmin v19.4s, v19.4s, v14.4s\n" + "str q21, [x20, x12]\n" + "fmax v18.4s, v18.4s, v15.4s\n" + "str q20, [x19, x12]\n" + "fmax v17.4s, v17.4s, v15.4s\n" + "str q19, [x22, x12]\n" + "fmax v16.4s, v16.4s, v15.4s\n" + "ldr x20, [x17, #0x70]\n" + "fmin v18.4s, v18.4s, v14.4s\n" + "ldr x19, [x17, #0x78]\n" + "fmin v17.4s, v17.4s, v14.4s\n" + "str q18, [x21, x12]\n" + "fmin v16.4s, v16.4s, v14.4s\n" + "str q17, [x20, x12]\n" + "str q16, [x19, x12]\n" "3:" // Oddments "tst %x[n_channels], #0x3\n" "beq 72f\n" "ldr q13, [x15, #0x0]\n" "ldr q0, [x15, #0x10]\n" - "mov x12, x13\n" + "mov x12, x14\n" "ldr q1, [x15, #0x20]\n" "ldr q2, [x15, #0x30]\n" "ldr q3, [x15, #0x40]\n" @@ -713,681 +713,683 @@ void a64_fp32_nhwc_3x3_s1_output4x4_mla_depthfirst_indirect_impl( "ldr q6, [x15, #0x70]\n" "ldr q7, [x15, #0x80]\n" "ldr q8, [x15, #0x90]\n" - "ldr x23, [x14, #0x0]\n" - "ldr x22, [x14, #0x8]\n" - "add x23, x23, x13\n" - "add x22, x22, x13\n" - "ldr x21, [x14, #0x10]\n" - "ldr x20, [x14, #0x18]\n" - "add x21, x21, x13\n" - "add x20, x20, x13\n" + "ldr x10, [x16, #0x0]\n" + "add x10, x10, x14\n" + "ldr x9, [x16, #0x8]\n" + "ldr x28, [x16, #0x10]\n" + "add x9, x9, x14\n" + "ldr x27, [x16, #0x18]\n" + "add x28, x28, x14\n" + "add x27, x27, x14\n" "tbz %x[n_channels], #1, 4f\n" - "ld1 { v9.d }[0], [x23], #0x8\n" - "ld1 { v10.d }[0], [x22], #0x8\n" - "ld1 { v11.d }[0], [x21], #0x8\n" - "ld1 { v12.d }[0], [x20], #0x8\n" + "ld1 { v9.d }[0], [x10], #0x8\n" + "ld1 { v10.d }[0], [x9], #0x8\n" + "ld1 { v11.d }[0], [x28], #0x8\n" + "ld1 { v12.d }[0], [x27], #0x8\n" "tbz %x[n_channels], #0, 5f\n" - "ld1 { v9.s }[2], [x23], #0x4\n" - "ld1 { v10.s }[2], [x22], #0x4\n" - "ld1 { v11.s }[2], [x21], #0x4\n" - "ld1 { v12.s }[2], [x20], #0x4\n" + "ld1 { v9.s }[2], [x10], #0x4\n" + "ld1 { v10.s }[2], [x9], #0x4\n" + "ld1 { v11.s }[2], [x28], #0x4\n" + "ld1 { v12.s }[2], [x27], #0x4\n" "b 5f\n" "4:" // Oddments: Load inputs (2, 2), (0, 0), (0, 5), (2, 3): Bit 1: Unset - "ld1 { v9.s }[0], [x23], #0x4\n" - "ld1 { v10.s }[0], [x22], #0x4\n" - "ld1 { v11.s }[0], [x21], #0x4\n" - "ld1 { v12.s }[0], [x20], #0x4\n" + "ld1 { v9.s }[0], [x10], #0x4\n" + "ld1 { v10.s }[0], [x9], #0x4\n" + "ld1 { v11.s }[0], [x28], #0x4\n" + "ld1 { v12.s }[0], [x27], #0x4\n" "5:" // Oddments: Load inputs (2, 2), (0, 0), (0, 5), (2, 3): Bit 1: End - "mov v16.16b, v13.16b\n fmla v16.4s, v8.4s, v9.4s\n" - "mov v17.16b, v13.16b\n fmla v17.4s, v7.4s, v9.4s\n" - "ldr x20, [x14, #0x20]\n" - "add x20, x20, x13\n" - "mov v18.16b, v13.16b\n fmla v18.4s, v6.4s, v9.4s\n" - "mov v21.16b, v13.16b\n fmla v21.4s, v4.4s, v9.4s\n" - "mov v22.16b, v13.16b\n fmla v22.4s, v3.4s, v9.4s\n" - "mov v25.16b, v13.16b\n fmla v25.4s, v1.4s, v9.4s\n" - "mov v26.16b, v13.16b\n fmla v26.4s, v0.4s, v9.4s\n" - "mov v19.16b, v13.16b\n fmla v19.4s, v2.4s, v11.4s\n" - "mov v20.16b, v13.16b\n fmla v20.4s, v5.4s, v9.4s\n" - "mov v24.16b, v13.16b\n fmla v24.4s, v2.4s, v9.4s\n" - "fmla v16.4s, v0.4s, v10.4s\n" - "fmla v17.4s, v8.4s, v12.4s\n" - "fmla v18.4s, v7.4s, v12.4s\n" - "fmla v19.4s, v6.4s, v12.4s\n" - "fmla v21.4s, v5.4s, v12.4s\n" - "fmla v22.4s, v4.4s, v12.4s\n" - "mov v23.16b, v13.16b\n fmla v23.4s, v3.4s, v12.4s\n" - "fmla v25.4s, v2.4s, v12.4s\n" - "fmla v26.4s, v1.4s, v12.4s\n" - "mov v27.16b, v13.16b\n fmla v27.4s, v0.4s, v12.4s\n" + "mov v31.16b, v13.16b\n fmla v31.4s, v8.4s, v9.4s\n" + "ldr x26, [x16, #0x20]\n" + "add x26, x26, x14\n" + "mov v30.16b, v13.16b\n fmla v30.4s, v7.4s, v9.4s\n" + "mov v29.16b, v13.16b\n fmla v29.4s, v6.4s, v9.4s\n" + "mov v27.16b, v13.16b\n fmla v27.4s, v5.4s, v9.4s\n" + "mov v26.16b, v13.16b\n fmla v26.4s, v4.4s, v9.4s\n" + "mov v25.16b, v13.16b\n fmla v25.4s, v3.4s, v9.4s\n" + "mov v23.16b, v13.16b\n fmla v23.4s, v2.4s, v9.4s\n" + "mov v22.16b, v13.16b\n fmla v22.4s, v1.4s, v9.4s\n" + "mov v21.16b, v13.16b\n fmla v21.4s, v0.4s, v9.4s\n" + "fmla v31.4s, v0.4s, v10.4s\n" + "mov v28.16b, v13.16b\n fmla v28.4s, v2.4s, v11.4s\n" + "fmla v30.4s, v8.4s, v12.4s\n" + "fmla v29.4s, v7.4s, v12.4s\n" + "fmla v26.4s, v5.4s, v12.4s\n" + "fmla v28.4s, v6.4s, v12.4s\n" + "fmla v25.4s, v4.4s, v12.4s\n" + "mov v24.16b, v13.16b\n fmla v24.4s, v3.4s, v12.4s\n" + "fmla v22.4s, v2.4s, v12.4s\n" + "fmla v21.4s, v1.4s, v12.4s\n" + "mov v20.16b, v13.16b\n fmla v20.4s, v0.4s, v12.4s\n" "tbz %x[n_channels], #1, 6f\n" - "ld1 { v10.d }[0], [x20], #0x8\n" + "ld1 { v10.d }[0], [x26], #0x8\n" "tbz %x[n_channels], #0, 7f\n" - "ld1 { v10.s }[2], [x20], #0x4\n" + "ld1 { v10.s }[2], [x26], #0x4\n" "b 7f\n" "6:" // Oddments: Load input (5, 0): Bit 1: Unset - "ld1 { v10.s }[0], [x20], #0x4\n" + "ld1 { v10.s }[0], [x26], #0x4\n" "7:" // Oddments: Load input (5, 0): Bit 1: End - "ldr x20, [x14, #0x28]\n" - "mov v28.16b, v13.16b\n fmla v28.4s, v6.4s, v10.4s\n" - "add x20, x20, x13\n" + "mov v19.16b, v13.16b\n fmla v19.4s, v6.4s, v10.4s\n" + "ldr x25, [x16, #0x28]\n" + "add x25, x25, x14\n" "tbz %x[n_channels], #1, 8f\n" - "ld1 { v11.d }[0], [x20], #0x8\n" + "ld1 { v11.d }[0], [x25], #0x8\n" "tbz %x[n_channels], #0, 9f\n" - "ld1 { v11.s }[2], [x20], #0x4\n" + "ld1 { v11.s }[2], [x25], #0x4\n" "b 9f\n" "8:" // Oddments: Load input (5, 5): Bit 1: Unset - "ld1 { v11.s }[0], [x20], #0x4\n" + "ld1 { v11.s }[0], [x25], #0x4\n" "9:" // Oddments: Load input (5, 5): Bit 1: End - "ldr x20, [x14, #0x30]\n" - "mov v31.16b, v13.16b\n fmla v31.4s, v8.4s, v11.4s\n" - "add x20, x20, x13\n" + "mov v16.16b, v13.16b\n fmla v16.4s, v8.4s, v11.4s\n" + "ldr x24, [x16, #0x30]\n" + "add x24, x24, x14\n" "tbz %x[n_channels], #1, 10f\n" - "ld1 { v9.d }[0], [x20], #0x8\n" + "ld1 { v9.d }[0], [x24], #0x8\n" "tbz %x[n_channels], #0, 11f\n" - "ld1 { v9.s }[2], [x20], #0x4\n" + "ld1 { v9.s }[2], [x24], #0x4\n" "b 11f\n" "10:" // Oddments: Load input (3, 2): Bit 1: Unset - "ld1 { v9.s }[0], [x20], #0x4\n" + "ld1 { v9.s }[0], [x24], #0x4\n" "11:" // Oddments: Load input (3, 2): Bit 1: End - "ldr x20, [x14, #0x38]\n" - "fmla v20.4s, v8.4s, v9.4s\n" - "fmla v21.4s, v7.4s, v9.4s\n" - "add x20, x20, x13\n" - "fmla v22.4s, v6.4s, v9.4s\n" - "fmla v24.4s, v5.4s, v9.4s\n" - "fmla v25.4s, v4.4s, v9.4s\n" - "fmla v26.4s, v3.4s, v9.4s\n" - "fmla v28.4s, v2.4s, v9.4s\n" - "mov v29.16b, v13.16b\n fmla v29.4s, v1.4s, v9.4s\n" - "mov v30.16b, v13.16b\n fmla v30.4s, v0.4s, v9.4s\n" + "fmla v27.4s, v8.4s, v9.4s\n" + "ldr x23, [x16, #0x38]\n" + "fmla v26.4s, v7.4s, v9.4s\n" + "add x23, x23, x14\n" + "fmla v25.4s, v6.4s, v9.4s\n" + "fmla v23.4s, v5.4s, v9.4s\n" + "fmla v22.4s, v4.4s, v9.4s\n" + "fmla v21.4s, v3.4s, v9.4s\n" + "fmla v19.4s, v2.4s, v9.4s\n" + "mov v18.16b, v13.16b\n fmla v18.4s, v1.4s, v9.4s\n" + "mov v17.16b, v13.16b\n fmla v17.4s, v0.4s, v9.4s\n" "tbz %x[n_channels], #1, 12f\n" - "ld1 { v12.d }[0], [x20], #0x8\n" + "ld1 { v12.d }[0], [x23], #0x8\n" "tbz %x[n_channels], #0, 13f\n" - "ld1 { v12.s }[2], [x20], #0x4\n" + "ld1 { v12.s }[2], [x23], #0x4\n" "b 13f\n" "12:" // Oddments: Load input (0, 1): Bit 1: Unset - "ld1 { v12.s }[0], [x20], #0x4\n" + "ld1 { v12.s }[0], [x23], #0x4\n" "13:" // Oddments: Load input (0, 1): Bit 1: End - "ldr x20, [x14, #0x40]\n" - "fmla v16.4s, v1.4s, v12.4s\n" - "fmla v17.4s, v0.4s, v12.4s\n" - "add x20, x20, x13\n" + "fmla v31.4s, v1.4s, v12.4s\n" + "ldr x10, [x16, #0x40]\n" + "fmla v30.4s, v0.4s, v12.4s\n" + "add x10, x10, x14\n" "tbz %x[n_channels], #1, 14f\n" - "ld1 { v11.d }[0], [x20], #0x8\n" + "ld1 { v11.d }[0], [x10], #0x8\n" "tbz %x[n_channels], #0, 15f\n" - "ld1 { v11.s }[2], [x20], #0x4\n" + "ld1 { v11.s }[2], [x10], #0x4\n" "b 15f\n" "14:" // Oddments: Load input (0, 4): Bit 1: Unset - "ld1 { v11.s }[0], [x20], #0x4\n" + "ld1 { v11.s }[0], [x10], #0x4\n" "15:" // Oddments: Load input (0, 4): Bit 1: End - "ldr x20, [x14, #0x48]\n" - "fmla v18.4s, v2.4s, v11.4s\n" - "fmla v19.4s, v1.4s, v11.4s\n" - "add x20, x20, x13\n" + "fmla v29.4s, v2.4s, v11.4s\n" + "ldr x9, [x16, #0x48]\n" + "fmla v28.4s, v1.4s, v11.4s\n" + "add x9, x9, x14\n" "tbz %x[n_channels], #1, 16f\n" - "ld1 { v10.d }[0], [x20], #0x8\n" + "ld1 { v10.d }[0], [x9], #0x8\n" "tbz %x[n_channels], #0, 17f\n" - "ld1 { v10.s }[2], [x20], #0x4\n" + "ld1 { v10.s }[2], [x9], #0x4\n" "b 17f\n" "16:" // Oddments: Load input (3, 3): Bit 1: Unset - "ld1 { v10.s }[0], [x20], #0x4\n" + "ld1 { v10.s }[0], [x9], #0x4\n" "17:" // Oddments: Load input (3, 3): Bit 1: End - "ldr x20, [x14, #0x50]\n" - "fmla v21.4s, v8.4s, v10.4s\n" - "fmla v22.4s, v7.4s, v10.4s\n" - "add x20, x20, x13\n" - "fmla v23.4s, v6.4s, v10.4s\n" - "fmla v25.4s, v5.4s, v10.4s\n" - "fmla v26.4s, v4.4s, v10.4s\n" - "fmla v27.4s, v3.4s, v10.4s\n" - "fmla v29.4s, v2.4s, v10.4s\n" - "fmla v30.4s, v1.4s, v10.4s\n" - "fmla v31.4s, v0.4s, v10.4s\n" + "fmla v26.4s, v8.4s, v10.4s\n" + "ldr x28, [x16, #0x50]\n" + "fmla v25.4s, v7.4s, v10.4s\n" + "add x28, x28, x14\n" + "fmla v24.4s, v6.4s, v10.4s\n" + "fmla v22.4s, v5.4s, v10.4s\n" + "fmla v21.4s, v4.4s, v10.4s\n" + "fmla v20.4s, v3.4s, v10.4s\n" + "fmla v18.4s, v2.4s, v10.4s\n" + "fmla v17.4s, v1.4s, v10.4s\n" + "fmla v16.4s, v0.4s, v10.4s\n" "tbz %x[n_channels], #1, 18f\n" - "ld1 { v9.d }[0], [x20], #0x8\n" + "ld1 { v9.d }[0], [x28], #0x8\n" "tbz %x[n_channels], #0, 19f\n" - "ld1 { v9.s }[2], [x20], #0x4\n" + "ld1 { v9.s }[2], [x28], #0x4\n" "b 19f\n" "18:" // Oddments: Load input (1, 0): Bit 1: Unset - "ld1 { v9.s }[0], [x20], #0x4\n" + "ld1 { v9.s }[0], [x28], #0x4\n" "19:" // Oddments: Load input (1, 0): Bit 1: End - "ldr x20, [x14, #0x58]\n" - "fmla v16.4s, v3.4s, v9.4s\n" - "fmla v20.4s, v0.4s, v9.4s\n" - "add x20, x20, x13\n" + "fmla v31.4s, v3.4s, v9.4s\n" + "ldr x27, [x16, #0x58]\n" + "fmla v27.4s, v0.4s, v9.4s\n" + "add x27, x27, x14\n" "tbz %x[n_channels], #1, 20f\n" - "ld1 { v12.d }[0], [x20], #0x8\n" + "ld1 { v12.d }[0], [x27], #0x8\n" "tbz %x[n_channels], #0, 21f\n" - "ld1 { v12.s }[2], [x20], #0x4\n" + "ld1 { v12.s }[2], [x27], #0x4\n" "b 21f\n" "20:" // Oddments: Load input (1, 5): Bit 1: Unset - "ld1 { v12.s }[0], [x20], #0x4\n" + "ld1 { v12.s }[0], [x27], #0x4\n" "21:" // Oddments: Load input (1, 5): Bit 1: End - "ldr x20, [x14, #0x60]\n" - "fmla v19.4s, v5.4s, v12.4s\n" - "fmla v23.4s, v2.4s, v12.4s\n" - "add x20, x20, x13\n" + "fmla v28.4s, v5.4s, v12.4s\n" + "ldr x26, [x16, #0x60]\n" + "fmla v24.4s, v2.4s, v12.4s\n" + "add x26, x26, x14\n" "tbz %x[n_channels], #1, 22f\n" - "ld1 { v11.d }[0], [x20], #0x8\n" + "ld1 { v11.d }[0], [x26], #0x8\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v11.s }[2], [x20], #0x4\n" + "ld1 { v11.s }[2], [x26], #0x4\n" "b 23f\n" "22:" // Oddments: Load input (4, 0): Bit 1: Unset - "ld1 { v11.s }[0], [x20], #0x4\n" + "ld1 { v11.s }[0], [x26], #0x4\n" "23:" // Oddments: Load input (4, 0): Bit 1: End - "ldr x20, [x14, #0x68]\n" - "fmla v24.4s, v6.4s, v11.4s\n" - "fmla v28.4s, v3.4s, v11.4s\n" - "add x20, x20, x13\n" + "fmla v23.4s, v6.4s, v11.4s\n" + "ldr x25, [x16, #0x68]\n" + "fmla v19.4s, v3.4s, v11.4s\n" + "add x25, x25, x14\n" "tbz %x[n_channels], #1, 24f\n" - "ld1 { v10.d }[0], [x20], #0x8\n" + "ld1 { v10.d }[0], [x25], #0x8\n" "tbz %x[n_channels], #0, 25f\n" - "ld1 { v10.s }[2], [x20], #0x4\n" + "ld1 { v10.s }[2], [x25], #0x4\n" "b 25f\n" "24:" // Oddments: Load input (1, 2): Bit 1: Unset - "ld1 { v10.s }[0], [x20], #0x4\n" + "ld1 { v10.s }[0], [x25], #0x4\n" "25:" // Oddments: Load input (1, 2): Bit 1: End - "ldr x20, [x14, #0x70]\n" - "fmla v16.4s, v5.4s, v10.4s\n" - "fmla v17.4s, v4.4s, v10.4s\n" - "add x20, x20, x13\n" - "fmla v18.4s, v3.4s, v10.4s\n" - "fmla v20.4s, v2.4s, v10.4s\n" - "fmla v21.4s, v1.4s, v10.4s\n" - "fmla v22.4s, v0.4s, v10.4s\n" + "fmla v31.4s, v5.4s, v10.4s\n" + "ldr x24, [x16, #0x70]\n" + "fmla v30.4s, v4.4s, v10.4s\n" + "add x24, x24, x14\n" + "fmla v29.4s, v3.4s, v10.4s\n" + "fmla v27.4s, v2.4s, v10.4s\n" + "fmla v26.4s, v1.4s, v10.4s\n" + "fmla v25.4s, v0.4s, v10.4s\n" "tbz %x[n_channels], #1, 26f\n" - "ld1 { v11.d }[0], [x20], #0x8\n" + "ld1 { v11.d }[0], [x24], #0x8\n" "tbz %x[n_channels], #0, 27f\n" - "ld1 { v11.s }[2], [x20], #0x4\n" + "ld1 { v11.s }[2], [x24], #0x4\n" "b 27f\n" "26:" // Oddments: Load input (4, 5): Bit 1: Unset - "ld1 { v11.s }[0], [x20], #0x4\n" + "ld1 { v11.s }[0], [x24], #0x4\n" "27:" // Oddments: Load input (4, 5): Bit 1: End - "ldr x20, [x14, #0x78]\n" - "fmla v27.4s, v8.4s, v11.4s\n" - "fmla v31.4s, v5.4s, v11.4s\n" - "add x20, x20, x13\n" + "fmla v20.4s, v8.4s, v11.4s\n" + "ldr x23, [x16, #0x78]\n" + "fmla v16.4s, v5.4s, v11.4s\n" + "add x23, x23, x14\n" "tbz %x[n_channels], #1, 28f\n" - "ld1 { v12.d }[0], [x20], #0x8\n" + "ld1 { v12.d }[0], [x23], #0x8\n" "tbz %x[n_channels], #0, 29f\n" - "ld1 { v12.s }[2], [x20], #0x4\n" + "ld1 { v12.s }[2], [x23], #0x4\n" "b 29f\n" "28:" // Oddments: Load input (1, 3): Bit 1: Unset - "ld1 { v12.s }[0], [x20], #0x4\n" + "ld1 { v12.s }[0], [x23], #0x4\n" "29:" // Oddments: Load input (1, 3): Bit 1: End - "ldr x20, [x14, #0x80]\n" - "fmla v17.4s, v5.4s, v12.4s\n" - "fmla v18.4s, v4.4s, v12.4s\n" - "add x20, x20, x13\n" - "fmla v19.4s, v3.4s, v12.4s\n" - "fmla v21.4s, v2.4s, v12.4s\n" - "fmla v22.4s, v1.4s, v12.4s\n" - "fmla v23.4s, v0.4s, v12.4s\n" + "fmla v30.4s, v5.4s, v12.4s\n" + "ldr x10, [x16, #0x80]\n" + "fmla v29.4s, v4.4s, v12.4s\n" + "add x10, x10, x14\n" + "fmla v28.4s, v3.4s, v12.4s\n" + "fmla v26.4s, v2.4s, v12.4s\n" + "fmla v25.4s, v1.4s, v12.4s\n" + "fmla v24.4s, v0.4s, v12.4s\n" "tbz %x[n_channels], #1, 30f\n" - "ld1 { v11.d }[0], [x20], #0x8\n" + "ld1 { v11.d }[0], [x10], #0x8\n" "tbz %x[n_channels], #0, 31f\n" - "ld1 { v11.s }[2], [x20], #0x4\n" + "ld1 { v11.s }[2], [x10], #0x4\n" "b 31f\n" "30:" // Oddments: Load input (5, 1): Bit 1: Unset - "ld1 { v11.s }[0], [x20], #0x4\n" + "ld1 { v11.s }[0], [x10], #0x4\n" "31:" // Oddments: Load input (5, 1): Bit 1: End - "ldr x20, [x14, #0x88]\n" - "fmla v28.4s, v7.4s, v11.4s\n" - "fmla v29.4s, v6.4s, v11.4s\n" - "add x20, x20, x13\n" + "fmla v19.4s, v7.4s, v11.4s\n" + "ldr x9, [x16, #0x88]\n" + "fmla v18.4s, v6.4s, v11.4s\n" + "add x9, x9, x14\n" "tbz %x[n_channels], #1, 32f\n" - "ld1 { v10.d }[0], [x20], #0x8\n" + "ld1 { v10.d }[0], [x9], #0x8\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v10.s }[2], [x20], #0x4\n" + "ld1 { v10.s }[2], [x9], #0x4\n" "b 33f\n" "32:" // Oddments: Load input (2, 1): Bit 1: Unset - "ld1 { v10.s }[0], [x20], #0x4\n" + "ld1 { v10.s }[0], [x9], #0x4\n" "33:" // Oddments: Load input (2, 1): Bit 1: End - "ldr x20, [x14, #0x90]\n" - "fmla v16.4s, v7.4s, v10.4s\n" - "fmla v17.4s, v6.4s, v10.4s\n" - "add x20, x20, x13\n" - "fmla v20.4s, v4.4s, v10.4s\n" - "fmla v21.4s, v3.4s, v10.4s\n" - "fmla v24.4s, v1.4s, v10.4s\n" - "fmla v25.4s, v0.4s, v10.4s\n" + "fmla v31.4s, v7.4s, v10.4s\n" + "ldr x28, [x16, #0x90]\n" + "fmla v30.4s, v6.4s, v10.4s\n" + "add x28, x28, x14\n" + "fmla v27.4s, v4.4s, v10.4s\n" + "fmla v26.4s, v3.4s, v10.4s\n" + "fmla v23.4s, v1.4s, v10.4s\n" + "fmla v22.4s, v0.4s, v10.4s\n" "tbz %x[n_channels], #1, 34f\n" - "ld1 { v11.d }[0], [x20], #0x8\n" + "ld1 { v11.d }[0], [x28], #0x8\n" "tbz %x[n_channels], #0, 35f\n" - "ld1 { v11.s }[2], [x20], #0x4\n" + "ld1 { v11.s }[2], [x28], #0x4\n" "b 35f\n" "34:" // Oddments: Load input (5, 4): Bit 1: Unset - "ld1 { v11.s }[0], [x20], #0x4\n" + "ld1 { v11.s }[0], [x28], #0x4\n" "35:" // Oddments: Load input (5, 4): Bit 1: End - "ldr x20, [x14, #0x98]\n" - "fmla v30.4s, v8.4s, v11.4s\n" - "fmla v31.4s, v7.4s, v11.4s\n" - "add x20, x20, x13\n" + "fmla v17.4s, v8.4s, v11.4s\n" + "ldr x27, [x16, #0x98]\n" + "fmla v16.4s, v7.4s, v11.4s\n" + "add x27, x27, x14\n" "tbz %x[n_channels], #1, 36f\n" - "ld1 { v12.d }[0], [x20], #0x8\n" + "ld1 { v12.d }[0], [x27], #0x8\n" "tbz %x[n_channels], #0, 37f\n" - "ld1 { v12.s }[2], [x20], #0x4\n" + "ld1 { v12.s }[2], [x27], #0x4\n" "b 37f\n" "36:" // Oddments: Load input (2, 4): Bit 1: Unset - "ld1 { v12.s }[0], [x20], #0x4\n" + "ld1 { v12.s }[0], [x27], #0x4\n" "37:" // Oddments: Load input (2, 4): Bit 1: End - "ldr x20, [x14, #0xa0]\n" - "fmla v18.4s, v8.4s, v12.4s\n" - "fmla v19.4s, v7.4s, v12.4s\n" - "add x20, x20, x13\n" - "fmla v22.4s, v5.4s, v12.4s\n" - "fmla v23.4s, v4.4s, v12.4s\n" - "fmla v26.4s, v2.4s, v12.4s\n" - "fmla v27.4s, v1.4s, v12.4s\n" + "fmla v29.4s, v8.4s, v12.4s\n" + "ldr x26, [x16, #0xa0]\n" + "fmla v28.4s, v7.4s, v12.4s\n" + "add x26, x26, x14\n" + "fmla v25.4s, v5.4s, v12.4s\n" + "fmla v24.4s, v4.4s, v12.4s\n" + "fmla v21.4s, v2.4s, v12.4s\n" + "fmla v20.4s, v1.4s, v12.4s\n" "tbz %x[n_channels], #1, 38f\n" - "ld1 { v10.d }[0], [x20], #0x8\n" + "ld1 { v10.d }[0], [x26], #0x8\n" "tbz %x[n_channels], #0, 39f\n" - "ld1 { v10.s }[2], [x20], #0x4\n" + "ld1 { v10.s }[2], [x26], #0x4\n" "b 39f\n" "38:" // Oddments: Load input (0, 2): Bit 1: Unset - "ld1 { v10.s }[0], [x20], #0x4\n" + "ld1 { v10.s }[0], [x26], #0x4\n" "39:" // Oddments: Load input (0, 2): Bit 1: End - "ldr x20, [x14, #0xa8]\n" - "fmla v16.4s, v2.4s, v10.4s\n" - "fmla v17.4s, v1.4s, v10.4s\n" - "add x20, x20, x13\n" - "fmla v18.4s, v0.4s, v10.4s\n" + "fmla v31.4s, v2.4s, v10.4s\n" + "ldr x25, [x16, #0xa8]\n" + "fmla v30.4s, v1.4s, v10.4s\n" + "add x25, x25, x14\n" + "fmla v29.4s, v0.4s, v10.4s\n" "tbz %x[n_channels], #1, 40f\n" - "ld1 { v11.d }[0], [x20], #0x8\n" + "ld1 { v11.d }[0], [x25], #0x8\n" "tbz %x[n_channels], #0, 41f\n" - "ld1 { v11.s }[2], [x20], #0x4\n" + "ld1 { v11.s }[2], [x25], #0x4\n" "b 41f\n" "40:" // Oddments: Load input (3, 1): Bit 1: Unset - "ld1 { v11.s }[0], [x20], #0x4\n" + "ld1 { v11.s }[0], [x25], #0x4\n" "41:" // Oddments: Load input (3, 1): Bit 1: End - "ldr x20, [x14, #0xb0]\n" - "fmla v20.4s, v7.4s, v11.4s\n" - "fmla v21.4s, v6.4s, v11.4s\n" - "add x20, x20, x13\n" - "fmla v24.4s, v4.4s, v11.4s\n" - "fmla v25.4s, v3.4s, v11.4s\n" - "fmla v28.4s, v1.4s, v11.4s\n" - "fmla v29.4s, v0.4s, v11.4s\n" + "fmla v27.4s, v7.4s, v11.4s\n" + "ldr x24, [x16, #0xb0]\n" + "fmla v26.4s, v6.4s, v11.4s\n" + "add x24, x24, x14\n" + "fmla v23.4s, v4.4s, v11.4s\n" + "fmla v22.4s, v3.4s, v11.4s\n" + "fmla v19.4s, v1.4s, v11.4s\n" + "fmla v18.4s, v0.4s, v11.4s\n" "tbz %x[n_channels], #1, 42f\n" - "ld1 { v12.d }[0], [x20], #0x8\n" + "ld1 { v12.d }[0], [x24], #0x8\n" "tbz %x[n_channels], #0, 43f\n" - "ld1 { v12.s }[2], [x20], #0x4\n" + "ld1 { v12.s }[2], [x24], #0x4\n" "b 43f\n" "42:" // Oddments: Load input (0, 3): Bit 1: Unset - "ld1 { v12.s }[0], [x20], #0x4\n" + "ld1 { v12.s }[0], [x24], #0x4\n" "43:" // Oddments: Load input (0, 3): Bit 1: End - "ldr x20, [x14, #0xb8]\n" - "fmla v17.4s, v2.4s, v12.4s\n" - "fmla v18.4s, v1.4s, v12.4s\n" - "add x20, x20, x13\n" - "fmla v19.4s, v0.4s, v12.4s\n" + "fmla v30.4s, v2.4s, v12.4s\n" + "ldr x23, [x16, #0xb8]\n" + "fmla v29.4s, v1.4s, v12.4s\n" + "add x23, x23, x14\n" + "fmla v28.4s, v0.4s, v12.4s\n" "tbz %x[n_channels], #1, 44f\n" - "ld1 { v10.d }[0], [x20], #0x8\n" + "ld1 { v10.d }[0], [x23], #0x8\n" "tbz %x[n_channels], #0, 45f\n" - "ld1 { v10.s }[2], [x20], #0x4\n" + "ld1 { v10.s }[2], [x23], #0x4\n" "b 45f\n" "44:" // Oddments: Load input (2, 0): Bit 1: Unset - "ld1 { v10.s }[0], [x20], #0x4\n" + "ld1 { v10.s }[0], [x23], #0x4\n" "45:" // Oddments: Load input (2, 0): Bit 1: End - "ldr x20, [x14, #0xc0]\n" - "fmla v16.4s, v6.4s, v10.4s\n" - "fmla v20.4s, v3.4s, v10.4s\n" - "add x20, x20, x13\n" - "fmla v24.4s, v0.4s, v10.4s\n" + "fmla v31.4s, v6.4s, v10.4s\n" + "ldr x10, [x16, #0xc0]\n" + "fmla v27.4s, v3.4s, v10.4s\n" + "add x10, x10, x14\n" + "fmla v23.4s, v0.4s, v10.4s\n" "tbz %x[n_channels], #1, 46f\n" - "ld1 { v11.d }[0], [x20], #0x8\n" + "ld1 { v11.d }[0], [x10], #0x8\n" "tbz %x[n_channels], #0, 47f\n" - "ld1 { v11.s }[2], [x20], #0x4\n" + "ld1 { v11.s }[2], [x10], #0x4\n" "b 47f\n" "46:" // Oddments: Load input (3, 4): Bit 1: Unset - "ld1 { v11.s }[0], [x20], #0x4\n" + "ld1 { v11.s }[0], [x10], #0x4\n" "47:" // Oddments: Load input (3, 4): Bit 1: End - "ldr x20, [x14, #0xc8]\n" - "fmla v22.4s, v8.4s, v11.4s\n" - "fmla v23.4s, v7.4s, v11.4s\n" - "add x20, x20, x13\n" - "fmla v26.4s, v5.4s, v11.4s\n" - "fmla v27.4s, v4.4s, v11.4s\n" - "fmla v30.4s, v2.4s, v11.4s\n" - "fmla v31.4s, v1.4s, v11.4s\n" + "fmla v25.4s, v8.4s, v11.4s\n" + "ldr x9, [x16, #0xc8]\n" + "fmla v24.4s, v7.4s, v11.4s\n" + "add x9, x9, x14\n" + "fmla v21.4s, v5.4s, v11.4s\n" + "fmla v20.4s, v4.4s, v11.4s\n" + "fmla v17.4s, v2.4s, v11.4s\n" + "fmla v16.4s, v1.4s, v11.4s\n" "tbz %x[n_channels], #1, 48f\n" - "ld1 { v12.d }[0], [x20], #0x8\n" + "ld1 { v12.d }[0], [x9], #0x8\n" "tbz %x[n_channels], #0, 49f\n" - "ld1 { v12.s }[2], [x20], #0x4\n" + "ld1 { v12.s }[2], [x9], #0x4\n" "b 49f\n" "48:" // Oddments: Load input (2, 5): Bit 1: Unset - "ld1 { v12.s }[0], [x20], #0x4\n" + "ld1 { v12.s }[0], [x9], #0x4\n" "49:" // Oddments: Load input (2, 5): Bit 1: End - "ldr x20, [x14, #0xd0]\n" - "fmla v19.4s, v8.4s, v12.4s\n" - "fmla v23.4s, v5.4s, v12.4s\n" - "add x20, x20, x13\n" - "fmla v27.4s, v2.4s, v12.4s\n" + "fmla v28.4s, v8.4s, v12.4s\n" + "ldr x28, [x16, #0xd0]\n" + "fmla v24.4s, v5.4s, v12.4s\n" + "add x28, x28, x14\n" + "fmla v20.4s, v2.4s, v12.4s\n" "tbz %x[n_channels], #1, 50f\n" - "ld1 { v10.d }[0], [x20], #0x8\n" + "ld1 { v10.d }[0], [x28], #0x8\n" "tbz %x[n_channels], #0, 51f\n" - "ld1 { v10.s }[2], [x20], #0x4\n" + "ld1 { v10.s }[2], [x28], #0x4\n" "b 51f\n" "50:" // Oddments: Load input (3, 0): Bit 1: Unset - "ld1 { v10.s }[0], [x20], #0x4\n" + "ld1 { v10.s }[0], [x28], #0x4\n" "51:" // Oddments: Load input (3, 0): Bit 1: End - "ldr x20, [x14, #0xd8]\n" - "fmla v20.4s, v6.4s, v10.4s\n" - "fmla v24.4s, v3.4s, v10.4s\n" - "add x20, x20, x13\n" - "fmla v28.4s, v0.4s, v10.4s\n" + "fmla v27.4s, v6.4s, v10.4s\n" + "ldr x27, [x16, #0xd8]\n" + "fmla v23.4s, v3.4s, v10.4s\n" + "add x27, x27, x14\n" + "fmla v19.4s, v0.4s, v10.4s\n" "tbz %x[n_channels], #1, 52f\n" - "ld1 { v11.d }[0], [x20], #0x8\n" + "ld1 { v11.d }[0], [x27], #0x8\n" "tbz %x[n_channels], #0, 53f\n" - "ld1 { v11.s }[2], [x20], #0x4\n" + "ld1 { v11.s }[2], [x27], #0x4\n" "b 53f\n" "52:" // Oddments: Load input (4, 2): Bit 1: Unset - "ld1 { v11.s }[0], [x20], #0x4\n" + "ld1 { v11.s }[0], [x27], #0x4\n" "53:" // Oddments: Load input (4, 2): Bit 1: End - "ldr x20, [x14, #0xe0]\n" - "fmla v24.4s, v8.4s, v11.4s\n" - "fmla v25.4s, v7.4s, v11.4s\n" - "add x20, x20, x13\n" - "fmla v26.4s, v6.4s, v11.4s\n" - "fmla v28.4s, v5.4s, v11.4s\n" - "fmla v29.4s, v4.4s, v11.4s\n" - "fmla v30.4s, v3.4s, v11.4s\n" + "fmla v23.4s, v8.4s, v11.4s\n" + "ldr x26, [x16, #0xe0]\n" + "fmla v22.4s, v7.4s, v11.4s\n" + "add x26, x26, x14\n" + "fmla v21.4s, v6.4s, v11.4s\n" + "fmla v19.4s, v5.4s, v11.4s\n" + "fmla v18.4s, v4.4s, v11.4s\n" + "fmla v17.4s, v3.4s, v11.4s\n" "tbz %x[n_channels], #1, 54f\n" - "ld1 { v12.d }[0], [x20], #0x8\n" + "ld1 { v12.d }[0], [x26], #0x8\n" "tbz %x[n_channels], #0, 55f\n" - "ld1 { v12.s }[2], [x20], #0x4\n" + "ld1 { v12.s }[2], [x26], #0x4\n" "b 55f\n" "54:" // Oddments: Load input (3, 5): Bit 1: Unset - "ld1 { v12.s }[0], [x20], #0x4\n" + "ld1 { v12.s }[0], [x26], #0x4\n" "55:" // Oddments: Load input (3, 5): Bit 1: End - "ldr x20, [x14, #0xe8]\n" - "fmla v23.4s, v8.4s, v12.4s\n" - "fmla v27.4s, v5.4s, v12.4s\n" - "add x20, x20, x13\n" - "fmla v31.4s, v2.4s, v12.4s\n" + "fmla v24.4s, v8.4s, v12.4s\n" + "ldr x25, [x16, #0xe8]\n" + "fmla v20.4s, v5.4s, v12.4s\n" + "add x25, x25, x14\n" + "fmla v16.4s, v2.4s, v12.4s\n" "tbz %x[n_channels], #1, 56f\n" - "ld1 { v10.d }[0], [x20], #0x8\n" + "ld1 { v10.d }[0], [x25], #0x8\n" "tbz %x[n_channels], #0, 57f\n" - "ld1 { v10.s }[2], [x20], #0x4\n" + "ld1 { v10.s }[2], [x25], #0x4\n" "b 57f\n" "56:" // Oddments: Load input (5, 2): Bit 1: Unset - "ld1 { v10.s }[0], [x20], #0x4\n" + "ld1 { v10.s }[0], [x25], #0x4\n" "57:" // Oddments: Load input (5, 2): Bit 1: End - "ldr x20, [x14, #0xf0]\n" - "fmla v28.4s, v8.4s, v10.4s\n" - "fmla v29.4s, v7.4s, v10.4s\n" - "add x20, x20, x13\n" - "fmla v30.4s, v6.4s, v10.4s\n" + "fmla v19.4s, v8.4s, v10.4s\n" + "ldr x24, [x16, #0xf0]\n" + "fmla v18.4s, v7.4s, v10.4s\n" + "add x24, x24, x14\n" + "fmla v17.4s, v6.4s, v10.4s\n" "tbz %x[n_channels], #1, 58f\n" - "ld1 { v11.d }[0], [x20], #0x8\n" + "ld1 { v11.d }[0], [x24], #0x8\n" "tbz %x[n_channels], #0, 59f\n" - "ld1 { v11.s }[2], [x20], #0x4\n" + "ld1 { v11.s }[2], [x24], #0x4\n" "b 59f\n" "58:" // Oddments: Load input (4, 3): Bit 1: Unset - "ld1 { v11.s }[0], [x20], #0x4\n" + "ld1 { v11.s }[0], [x24], #0x4\n" "59:" // Oddments: Load input (4, 3): Bit 1: End - "ldr x20, [x14, #0xf8]\n" - "fmla v25.4s, v8.4s, v11.4s\n" - "fmla v26.4s, v7.4s, v11.4s\n" - "add x20, x20, x13\n" - "fmla v27.4s, v6.4s, v11.4s\n" - "fmla v29.4s, v5.4s, v11.4s\n" - "fmla v30.4s, v4.4s, v11.4s\n" - "fmla v31.4s, v3.4s, v11.4s\n" + "fmla v22.4s, v8.4s, v11.4s\n" + "ldr x23, [x16, #0xf8]\n" + "fmla v21.4s, v7.4s, v11.4s\n" + "add x23, x23, x14\n" + "fmla v20.4s, v6.4s, v11.4s\n" + "fmla v18.4s, v5.4s, v11.4s\n" + "fmla v17.4s, v4.4s, v11.4s\n" + "fmla v16.4s, v3.4s, v11.4s\n" "tbz %x[n_channels], #1, 60f\n" - "ld1 { v12.d }[0], [x20], #0x8\n" + "ld1 { v12.d }[0], [x23], #0x8\n" "tbz %x[n_channels], #0, 61f\n" - "ld1 { v12.s }[2], [x20], #0x4\n" + "ld1 { v12.s }[2], [x23], #0x4\n" "b 61f\n" "60:" // Oddments: Load input (5, 3): Bit 1: Unset - "ld1 { v12.s }[0], [x20], #0x4\n" + "ld1 { v12.s }[0], [x23], #0x4\n" "61:" // Oddments: Load input (5, 3): Bit 1: End - "ldr x20, [x14, #0x100]\n" - "fmla v29.4s, v8.4s, v12.4s\n" - "fmla v30.4s, v7.4s, v12.4s\n" - "add x20, x20, x13\n" - "fmla v31.4s, v6.4s, v12.4s\n" + "fmla v18.4s, v8.4s, v12.4s\n" + "ldr x10, [x16, #0x100]\n" + "fmla v17.4s, v7.4s, v12.4s\n" + "add x10, x10, x14\n" + "fmla v16.4s, v6.4s, v12.4s\n" "tbz %x[n_channels], #1, 62f\n" - "ld1 { v10.d }[0], [x20], #0x8\n" + "ld1 { v10.d }[0], [x10], #0x8\n" "tbz %x[n_channels], #0, 63f\n" - "ld1 { v10.s }[2], [x20], #0x4\n" + "ld1 { v10.s }[2], [x10], #0x4\n" "b 63f\n" "62:" // Oddments: Load input (1, 1): Bit 1: Unset - "ld1 { v10.s }[0], [x20], #0x4\n" + "ld1 { v10.s }[0], [x10], #0x4\n" "63:" // Oddments: Load input (1, 1): Bit 1: End - "ldr x20, [x14, #0x108]\n" - "fmla v16.4s, v4.4s, v10.4s\n" - "fmla v17.4s, v3.4s, v10.4s\n" - "add x20, x20, x13\n" - "fmla v20.4s, v1.4s, v10.4s\n" - "fmla v21.4s, v0.4s, v10.4s\n" + "fmla v31.4s, v4.4s, v10.4s\n" + "ldr x9, [x16, #0x108]\n" + "fmla v30.4s, v3.4s, v10.4s\n" + "add x9, x9, x14\n" + "fmla v27.4s, v1.4s, v10.4s\n" + "fmla v26.4s, v0.4s, v10.4s\n" "tbz %x[n_channels], #1, 64f\n" - "ld1 { v11.d }[0], [x20], #0x8\n" + "ld1 { v11.d }[0], [x9], #0x8\n" "tbz %x[n_channels], #0, 65f\n" - "ld1 { v11.s }[2], [x20], #0x4\n" + "ld1 { v11.s }[2], [x9], #0x4\n" "b 65f\n" "64:" // Oddments: Load input (1, 4): Bit 1: Unset - "ld1 { v11.s }[0], [x20], #0x4\n" + "ld1 { v11.s }[0], [x9], #0x4\n" "65:" // Oddments: Load input (1, 4): Bit 1: End - "ldr x20, [x14, #0x110]\n" - "fmla v18.4s, v5.4s, v11.4s\n" - "fmla v19.4s, v4.4s, v11.4s\n" - "add x20, x20, x13\n" - "fmla v22.4s, v2.4s, v11.4s\n" - "fmla v23.4s, v1.4s, v11.4s\n" + "fmla v29.4s, v5.4s, v11.4s\n" + "ldr x28, [x16, #0x110]\n" + "fmla v28.4s, v4.4s, v11.4s\n" + "add x28, x28, x14\n" + "fmla v25.4s, v2.4s, v11.4s\n" + "fmla v24.4s, v1.4s, v11.4s\n" "tbz %x[n_channels], #1, 66f\n" - "ld1 { v12.d }[0], [x20], #0x8\n" + "ld1 { v12.d }[0], [x28], #0x8\n" "tbz %x[n_channels], #0, 67f\n" - "ld1 { v12.s }[2], [x20], #0x4\n" + "ld1 { v12.s }[2], [x28], #0x4\n" "b 67f\n" "66:" // Oddments: Load input (4, 1): Bit 1: Unset - "ld1 { v12.s }[0], [x20], #0x4\n" + "ld1 { v12.s }[0], [x28], #0x4\n" "67:" // Oddments: Load input (4, 1): Bit 1: End - "ldr x20, [x14, #0x118]\n" - "fmla v24.4s, v7.4s, v12.4s\n" - "fmla v25.4s, v6.4s, v12.4s\n" - "add x20, x20, x13\n" - "fmla v28.4s, v4.4s, v12.4s\n" - "fmla v29.4s, v3.4s, v12.4s\n" + "fmla v23.4s, v7.4s, v12.4s\n" + "ldr x27, [x16, #0x118]\n" + "fmla v22.4s, v6.4s, v12.4s\n" + "add x27, x27, x14\n" + "fmla v19.4s, v4.4s, v12.4s\n" + "fmla v18.4s, v3.4s, v12.4s\n" "tbz %x[n_channels], #1, 68f\n" - "ld1 { v10.d }[0], [x20], #0x8\n" + "ld1 { v10.d }[0], [x27], #0x8\n" "tbz %x[n_channels], #0, 69f\n" - "ld1 { v10.s }[2], [x20], #0x4\n" + "ld1 { v10.s }[2], [x27], #0x4\n" "b 69f\n" "68:" // Oddments: Load input (4, 4): Bit 1: Unset - "ld1 { v10.s }[0], [x20], #0x4\n" + "ld1 { v10.s }[0], [x27], #0x4\n" "69:" // Oddments: Load input (4, 4): Bit 1: End - "fmla v26.4s, v8.4s, v10.4s\n" - "fmla v27.4s, v7.4s, v10.4s\n" - "fmax v16.4s, v16.4s, v15.4s\n" - "fmla v30.4s, v5.4s, v10.4s\n" - "fmla v31.4s, v4.4s, v10.4s\n" - "fmax v17.4s, v17.4s, v15.4s\n" - "fmax v18.4s, v18.4s, v15.4s\n" - "fmax v19.4s, v19.4s, v15.4s\n" - "fmax v20.4s, v20.4s, v15.4s\n" - "fmax v21.4s, v21.4s, v15.4s\n" - "fmax v22.4s, v22.4s, v15.4s\n" - "fmax v23.4s, v23.4s, v15.4s\n" - "fmax v24.4s, v24.4s, v15.4s\n" - "fmax v25.4s, v25.4s, v15.4s\n" - "fmax v26.4s, v26.4s, v15.4s\n" - "fmax v27.4s, v27.4s, v15.4s\n" - "fmax v28.4s, v28.4s, v15.4s\n" - "fmax v29.4s, v29.4s, v15.4s\n" - "fmax v30.4s, v30.4s, v15.4s\n" + "fmla v21.4s, v8.4s, v10.4s\n" + "fmla v20.4s, v7.4s, v10.4s\n" + "fmla v17.4s, v5.4s, v10.4s\n" + "fmla v16.4s, v4.4s, v10.4s\n" "fmax v31.4s, v31.4s, v15.4s\n" - "fmin v16.4s, v16.4s, v14.4s\n" - "fmin v17.4s, v17.4s, v14.4s\n" - "fmin v18.4s, v18.4s, v14.4s\n" - "fmin v19.4s, v19.4s, v14.4s\n" - "fmin v20.4s, v20.4s, v14.4s\n" - "fmin v21.4s, v21.4s, v14.4s\n" - "fmin v22.4s, v22.4s, v14.4s\n" - "fmin v23.4s, v23.4s, v14.4s\n" - "fmin v24.4s, v24.4s, v14.4s\n" - "fmin v25.4s, v25.4s, v14.4s\n" - "fmin v26.4s, v26.4s, v14.4s\n" - "fmin v27.4s, v27.4s, v14.4s\n" - "fmin v28.4s, v28.4s, v14.4s\n" - "fmin v29.4s, v29.4s, v14.4s\n" - "fmin v30.4s, v30.4s, v14.4s\n" + "fmax v30.4s, v30.4s, v15.4s\n" + "fmax v29.4s, v29.4s, v15.4s\n" "fmin v31.4s, v31.4s, v14.4s\n" + "fmin v30.4s, v30.4s, v14.4s\n" + "fmin v29.4s, v29.4s, v14.4s\n" + "fmax v28.4s, v28.4s, v15.4s\n" + "fmax v27.4s, v27.4s, v15.4s\n" + "fmax v26.4s, v26.4s, v15.4s\n" + "fmin v28.4s, v28.4s, v14.4s\n" + "fmin v27.4s, v27.4s, v14.4s\n" + "fmin v26.4s, v26.4s, v14.4s\n" + "fmax v25.4s, v25.4s, v15.4s\n" + "fmax v24.4s, v24.4s, v15.4s\n" + "fmax v23.4s, v23.4s, v15.4s\n" + "fmin v25.4s, v25.4s, v14.4s\n" + "fmin v24.4s, v24.4s, v14.4s\n" + "fmin v23.4s, v23.4s, v14.4s\n" + "fmax v22.4s, v22.4s, v15.4s\n" + "fmax v21.4s, v21.4s, v15.4s\n" + "fmax v20.4s, v20.4s, v15.4s\n" + "fmin v22.4s, v22.4s, v14.4s\n" + "fmin v21.4s, v21.4s, v14.4s\n" + "fmin v20.4s, v20.4s, v14.4s\n" + "fmax v19.4s, v19.4s, v15.4s\n" + "fmax v18.4s, v18.4s, v15.4s\n" + "fmax v17.4s, v17.4s, v15.4s\n" + "fmin v19.4s, v19.4s, v14.4s\n" + "fmin v18.4s, v18.4s, v14.4s\n" + "fmin v17.4s, v17.4s, v14.4s\n" + "fmax v16.4s, v16.4s, v15.4s\n" + "fmin v16.4s, v16.4s, v14.4s\n" "tbz %x[n_channels], #1, 70f\n" - "ldr x23, [x16, #0x0]\n" - "ldr x22, [x16, #0x8]\n" - "add x23, x23, x12\n" + "ldr x22, [x17, #0x0]\n" + "ldr x21, [x17, #0x8]\n" "add x22, x22, x12\n" - "ldr x21, [x16, #0x10]\n" - "ldr x20, [x16, #0x18]\n" + "ldr x20, [x17, #0x10]\n" + "ldr x19, [x17, #0x18]\n" "add x21, x21, x12\n" + "st1 { v31.d }[0], [x22]\n" "add x20, x20, x12\n" - "st1 { v16.d }[0], [x23]\n" - "ldr x23, [x16, #0x20]\n" - "add x23, x23, x12\n" - "st1 { v17.d }[0], [x22]\n" - "ldr x22, [x16, #0x28]\n" + "st1 { v30.d }[0], [x21]\n" + "ldr x22, [x17, #0x20]\n" + "add x19, x19, x12\n" + "st1 { v29.d }[0], [x20]\n" "add x22, x22, x12\n" - "st1 { v18.d }[0], [x21]\n" - "ldr x21, [x16, #0x30]\n" + "st1 { v28.d }[0], [x19]\n" + "ldr x21, [x17, #0x28]\n" "add x21, x21, x12\n" - "st1 { v19.d }[0], [x20]\n" - "ldr x20, [x16, #0x38]\n" + "st1 { v27.d }[0], [x22]\n" + "ldr x20, [x17, #0x30]\n" "add x20, x20, x12\n" - "st1 { v20.d }[0], [x23]\n" - "ldr x23, [x16, #0x40]\n" - "add x23, x23, x12\n" - "st1 { v21.d }[0], [x22]\n" - "ldr x22, [x16, #0x48]\n" + "st1 { v26.d }[0], [x21]\n" + "ldr x19, [x17, #0x38]\n" + "add x19, x19, x12\n" + "st1 { v25.d }[0], [x20]\n" + "ldr x22, [x17, #0x40]\n" "add x22, x22, x12\n" - "st1 { v22.d }[0], [x21]\n" - "ldr x21, [x16, #0x50]\n" + "st1 { v24.d }[0], [x19]\n" + "ldr x21, [x17, #0x48]\n" "add x21, x21, x12\n" - "st1 { v23.d }[0], [x20]\n" - "ldr x20, [x16, #0x58]\n" + "st1 { v23.d }[0], [x22]\n" + "ldr x20, [x17, #0x50]\n" "add x20, x20, x12\n" - "st1 { v24.d }[0], [x23]\n" - "ldr x23, [x16, #0x60]\n" - "add x23, x23, x12\n" - "st1 { v25.d }[0], [x22]\n" - "ldr x22, [x16, #0x68]\n" + "st1 { v22.d }[0], [x21]\n" + "ldr x19, [x17, #0x58]\n" + "add x19, x19, x12\n" + "st1 { v21.d }[0], [x20]\n" + "ldr x22, [x17, #0x60]\n" "add x22, x22, x12\n" - "st1 { v26.d }[0], [x21]\n" - "ldr x21, [x16, #0x70]\n" + "st1 { v20.d }[0], [x19]\n" + "ldr x21, [x17, #0x68]\n" "add x21, x21, x12\n" - "st1 { v27.d }[0], [x20]\n" - "ldr x20, [x16, #0x78]\n" + "st1 { v19.d }[0], [x22]\n" + "ldr x20, [x17, #0x70]\n" "add x20, x20, x12\n" + "st1 { v18.d }[0], [x21]\n" + "ldr x19, [x17, #0x78]\n" + "add x19, x19, x12\n" + "st1 { v17.d }[0], [x20]\n" "add x12, x12, #0x8\n" - "st1 { v28.d }[0], [x23]\n" - "st1 { v29.d }[0], [x22]\n" - "st1 { v30.d }[0], [x21]\n" - "st1 { v31.d }[0], [x20]\n" + "st1 { v16.d }[0], [x19]\n" "tbz %x[n_channels], #0, 71f\n" - "ldr x23, [x16, #0x0]\n" - "ldr x22, [x16, #0x8]\n" - "add x23, x23, x12\n" + "ldr x22, [x17, #0x0]\n" + "ldr x21, [x17, #0x8]\n" "add x22, x22, x12\n" - "ldr x21, [x16, #0x10]\n" - "ldr x20, [x16, #0x18]\n" + "ldr x20, [x17, #0x10]\n" + "ldr x19, [x17, #0x18]\n" "add x21, x21, x12\n" + "st1 { v31.s }[2], [x22]\n" "add x20, x20, x12\n" - "st1 { v16.s }[2], [x23]\n" - "ldr x23, [x16, #0x20]\n" - "add x23, x23, x12\n" - "st1 { v17.s }[2], [x22]\n" - "ldr x22, [x16, #0x28]\n" + "st1 { v30.s }[2], [x21]\n" + "ldr x22, [x17, #0x20]\n" + "add x19, x19, x12\n" + "st1 { v29.s }[2], [x20]\n" "add x22, x22, x12\n" - "st1 { v18.s }[2], [x21]\n" - "ldr x21, [x16, #0x30]\n" + "st1 { v28.s }[2], [x19]\n" + "ldr x21, [x17, #0x28]\n" "add x21, x21, x12\n" - "st1 { v19.s }[2], [x20]\n" - "ldr x20, [x16, #0x38]\n" + "st1 { v27.s }[2], [x22]\n" + "ldr x20, [x17, #0x30]\n" "add x20, x20, x12\n" - "st1 { v20.s }[2], [x23]\n" - "ldr x23, [x16, #0x40]\n" - "add x23, x23, x12\n" - "st1 { v21.s }[2], [x22]\n" - "ldr x22, [x16, #0x48]\n" + "st1 { v26.s }[2], [x21]\n" + "ldr x19, [x17, #0x38]\n" + "add x19, x19, x12\n" + "st1 { v25.s }[2], [x20]\n" + "ldr x22, [x17, #0x40]\n" "add x22, x22, x12\n" - "st1 { v22.s }[2], [x21]\n" - "ldr x21, [x16, #0x50]\n" + "st1 { v24.s }[2], [x19]\n" + "ldr x21, [x17, #0x48]\n" "add x21, x21, x12\n" - "st1 { v23.s }[2], [x20]\n" - "ldr x20, [x16, #0x58]\n" + "st1 { v23.s }[2], [x22]\n" + "ldr x20, [x17, #0x50]\n" "add x20, x20, x12\n" - "st1 { v24.s }[2], [x23]\n" - "ldr x23, [x16, #0x60]\n" - "add x23, x23, x12\n" - "st1 { v25.s }[2], [x22]\n" - "ldr x22, [x16, #0x68]\n" + "st1 { v22.s }[2], [x21]\n" + "ldr x19, [x17, #0x58]\n" + "add x19, x19, x12\n" + "st1 { v21.s }[2], [x20]\n" + "ldr x22, [x17, #0x60]\n" "add x22, x22, x12\n" - "st1 { v26.s }[2], [x21]\n" - "ldr x21, [x16, #0x70]\n" + "st1 { v20.s }[2], [x19]\n" + "ldr x21, [x17, #0x68]\n" "add x21, x21, x12\n" - "st1 { v27.s }[2], [x20]\n" - "ldr x20, [x16, #0x78]\n" + "st1 { v19.s }[2], [x22]\n" + "ldr x20, [x17, #0x70]\n" "add x20, x20, x12\n" - "st1 { v28.s }[2], [x23]\n" - "st1 { v29.s }[2], [x22]\n" - "st1 { v30.s }[2], [x21]\n" - "st1 { v31.s }[2], [x20]\n" + "st1 { v18.s }[2], [x21]\n" + "ldr x19, [x17, #0x78]\n" + "add x19, x19, x12\n" + "st1 { v17.s }[2], [x20]\n" + "st1 { v16.s }[2], [x19]\n" "b 71f\n" "70:" // Oddments: Store: Bit 1: Unset - "ldr x23, [x16, #0x0]\n" - "ldr x22, [x16, #0x8]\n" - "add x23, x23, x12\n" + "ldr x22, [x17, #0x0]\n" "add x22, x22, x12\n" - "ldr x21, [x16, #0x10]\n" - "ldr x20, [x16, #0x18]\n" + "ldr x21, [x17, #0x8]\n" + "ldr x20, [x17, #0x10]\n" "add x21, x21, x12\n" + "st1 { v31.s }[0], [x22]\n" + "ldr x19, [x17, #0x18]\n" "add x20, x20, x12\n" - "st1 { v16.s }[0], [x23]\n" - "ldr x23, [x16, #0x20]\n" - "add x23, x23, x12\n" - "st1 { v17.s }[0], [x22]\n" - "ldr x22, [x16, #0x28]\n" + "st1 { v30.s }[0], [x21]\n" + "add x19, x19, x12\n" + "st1 { v29.s }[0], [x20]\n" + "ldr x22, [x17, #0x20]\n" "add x22, x22, x12\n" - "st1 { v18.s }[0], [x21]\n" - "ldr x21, [x16, #0x30]\n" + "st1 { v28.s }[0], [x19]\n" + "ldr x21, [x17, #0x28]\n" "add x21, x21, x12\n" - "st1 { v19.s }[0], [x20]\n" - "ldr x20, [x16, #0x38]\n" + "st1 { v27.s }[0], [x22]\n" + "ldr x20, [x17, #0x30]\n" "add x20, x20, x12\n" - "st1 { v20.s }[0], [x23]\n" - "ldr x23, [x16, #0x40]\n" - "add x23, x23, x12\n" - "st1 { v21.s }[0], [x22]\n" - "ldr x22, [x16, #0x48]\n" + "st1 { v26.s }[0], [x21]\n" + "ldr x19, [x17, #0x38]\n" + "add x19, x19, x12\n" + "st1 { v25.s }[0], [x20]\n" + "ldr x22, [x17, #0x40]\n" "add x22, x22, x12\n" - "st1 { v22.s }[0], [x21]\n" - "ldr x21, [x16, #0x50]\n" + "st1 { v24.s }[0], [x19]\n" + "ldr x21, [x17, #0x48]\n" "add x21, x21, x12\n" - "st1 { v23.s }[0], [x20]\n" - "ldr x20, [x16, #0x58]\n" + "st1 { v23.s }[0], [x22]\n" + "ldr x20, [x17, #0x50]\n" "add x20, x20, x12\n" - "st1 { v24.s }[0], [x23]\n" - "ldr x23, [x16, #0x60]\n" - "add x23, x23, x12\n" - "st1 { v25.s }[0], [x22]\n" - "ldr x22, [x16, #0x68]\n" + "st1 { v22.s }[0], [x21]\n" + "ldr x19, [x17, #0x58]\n" + "add x19, x19, x12\n" + "st1 { v21.s }[0], [x20]\n" + "ldr x22, [x17, #0x60]\n" "add x22, x22, x12\n" - "st1 { v26.s }[0], [x21]\n" - "ldr x21, [x16, #0x70]\n" + "st1 { v20.s }[0], [x19]\n" + "ldr x21, [x17, #0x68]\n" "add x21, x21, x12\n" - "st1 { v27.s }[0], [x20]\n" - "ldr x20, [x16, #0x78]\n" + "st1 { v19.s }[0], [x22]\n" + "ldr x20, [x17, #0x70]\n" "add x20, x20, x12\n" - "st1 { v28.s }[0], [x23]\n" - "st1 { v29.s }[0], [x22]\n" - "st1 { v30.s }[0], [x21]\n" - "st1 { v31.s }[0], [x20]\n" + "st1 { v18.s }[0], [x21]\n" + "ldr x19, [x17, #0x78]\n" + "add x19, x19, x12\n" + "st1 { v17.s }[0], [x20]\n" + "st1 { v16.s }[0], [x19]\n" "71:" // Oddments: Store: Bit 1: End + "72:" // End + : : [n_channels] "r" ((unsigned long) n_channels), [offsetof_Args_inptrs] "I" (offsetof(Args, inptrs)), [offsetof_args_max] "I" (offsetof(Args, max)), [offsetof_args_min] "I" (offsetof(Args, min)), [offsetof_args_outptrs] "I" (offsetof(Args, outptrs)), [offsetof_args_params] "I" (offsetof(Args, params)), [params_struct] "r" (¶ms_struct) - : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" + : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" ); } -- cgit v1.2.1