From 74921eee924625426429044decefe3673561b174 Mon Sep 17 00:00:00 2001
From: Michael Tyler <michael.tyler@arm.com>
Date: Wed, 12 Apr 2023 17:43:17 +0100
Subject: Update CPU kernel implementations and guard directives

Resolves COMPMID-6023

Change-Id: I868975d14c4f98af6716726feda22405a6a4c891
Signed-off-by: Michael Tyler <michael.tyler@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/9686
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Viet-Hoa Do <viet-hoa.do@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Benchmark: Arm Jenkins <bsgcomp@arm.com>
---
 .../generic_indirect.cpp                           | 354 ++++++++++-----------
 1 file changed, 177 insertions(+), 177 deletions(-)

(limited to 'src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_3x3_s1_output2x2_mla_depthfirst/generic_indirect.cpp')

diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_3x3_s1_output2x2_mla_depthfirst/generic_indirect.cpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_3x3_s1_output2x2_mla_depthfirst/generic_indirect.cpp
index 56e9ed2e1b..7dedfd972a 100644
--- a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_3x3_s1_output2x2_mla_depthfirst/generic_indirect.cpp
+++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_3x3_s1_output2x2_mla_depthfirst/generic_indirect.cpp
@@ -25,7 +25,7 @@
 #include <cstddef>
 #include <cstdint>
 
-#if __aarch64__
+#if defined(__aarch64__)
 
 namespace arm_conv {
 namespace depthwise {
@@ -83,16 +83,16 @@ void a64_fp32_nhwc_3x3_s1_output2x2_mla_depthfirst_indirect_impl(
     "lsr x15, %x[n_channels], #0x2\n"
     "ldr x14, [%x[params_struct], %[offsetof_args_params]]\n"
     "add x20, %x[params_struct], %[offsetof_args_min]\n"
-    "ld1r { v18.4s }, [x20]\n"
+    "ld1r { v27.4s }, [x20]\n"
     "add x20, %x[params_struct], %[offsetof_args_max]\n"
-    "ld1r { v17.4s }, [x20]\n"
+    "ld1r { v26.4s }, [x20]\n"
     "add x13, %x[params_struct], %[offsetof_Args_inptrs]\n"
     "ldp x12, x11, [x21, #0x0]\n"
     "ldp x10, x9, [x21, #0x10]\n"
     "mov x28, #0x0\n"
     "sub x27, XZR, x16\n"
     "cbz x15, 3f\n"
-    "ldr q16, [x14, #0x0]\n"
+    "ldr q25, [x14, #0x0]\n"
     "ldr q0, [x14, #0x10]\n"
     "cmp x16, x15, LSL #4\n"
     "ldr q1, [x14, #0x20]\n"
@@ -104,197 +104,197 @@ void a64_fp32_nhwc_3x3_s1_output2x2_mla_depthfirst_indirect_impl(
     "ldr q7, [x14, #0x80]\n"
     "ldr q8, [x14, #0x90]\n"
     "add x14, x14, #0xa0\n"
-    "ldp x26, x22, [x13, #0x0]\n"
-    "ldr q9, [x26, x28]\n"
-    "ldr q10, [x22, x28]\n"
-    "ldp x25, x24, [x13, #0x10]\n"
-    "ldr q11, [x25, x28]\n"
-    "ldr q12, [x24, x28]\n"
-    "ldr x23, [x13, #0x20]\n"
-    "ldr q13, [x23, x28]\n"
-    "bge 2f\n"
-    "1:"  // Channel loop
-    "mov v28.16b, v16.16b\n fmla v28.4s, v4.4s, v9.4s\n"
-    "mov v29.16b, v16.16b\n fmla v29.4s, v3.4s, v9.4s\n"
-    "ldr x22, [x13, #0x28]\n"
-    "ldr x21, [x13, #0x30]\n"
-    "mov v30.16b, v16.16b\n fmla v30.4s, v1.4s, v9.4s\n"
-    "mov v31.16b, v16.16b\n fmla v31.4s, v0.4s, v9.4s\n"
-    "ldr q9, [x22, x28]\n"
-    "ldr q16, [x14, #0x0]\n"
-    "fmla v28.4s, v0.4s, v10.4s\n"
-    "fmla v29.4s, v2.4s, v11.4s\n"
+    "ldp x21, x20, [x13, #0x0]\n"
+    "ldr q9, [x21, x28]\n"
+    "ldr q10, [x20, x28]\n"
+    "ldp x21, x20, [x13, #0x10]\n"
     "ldr q11, [x21, x28]\n"
-    "ldr x20, [x13, #0x38]\n"
-    "fmla v30.4s, v2.4s, v12.4s\n"
-    "fmla v31.4s, v1.4s, v12.4s\n"
-    "ldr x22, [x13, #0x48]\n"
-    "ldr q10, [x22, x28]\n"
-    "fmla v28.4s, v5.4s, v12.4s\n"
-    "fmla v29.4s, v4.4s, v12.4s\n"
     "ldr q12, [x20, x28]\n"
-    "ldr x26, [x13, #0x40]\n"
-    "fmla v30.4s, v6.4s, v9.4s\n"
-    "ldr q9, [x26, x28]\n"
-    "fmla v31.4s, v3.4s, v13.4s\n"
-    "ldr x25, [x13, #0x50]\n"
-    "fmla v28.4s, v7.4s, v13.4s\n"
-    "fmla v29.4s, v6.4s, v13.4s\n"
-    "ldr x24, [x13, #0x58]\n"
-    "ldr x23, [x13, #0x60]\n"
-    "fmla v30.4s, v4.4s, v13.4s\n"
-    "fmla v31.4s, v8.4s, v11.4s\n"
-    "ldr q11, [x25, x28]\n"
-    "ldr x22, [x13, #0x68]\n"
-    "fmla v28.4s, v1.4s, v12.4s\n"
-    "fmla v29.4s, v0.4s, v12.4s\n"
-    "ldr q12, [x24, x28]\n"
-    "ldr x21, [x13, #0x70]\n"
-    "fmla v30.4s, v5.4s, v10.4s\n"
-    "fmla v31.4s, v4.4s, v10.4s\n"
+    "ldr x20, [x13, #0x20]\n"
+    "ldr q13, [x20, x28]\n"
+    "bge 2f\n"
+    "1:"  // Channel loop
+    "mov v24.16b, v25.16b\n fmla v24.4s, v4.4s, v9.4s\n"
+    "mov v23.16b, v25.16b\n fmla v23.4s, v3.4s, v9.4s\n"
+    "ldr x21, [x13, #0x28]\n"
+    "ldr x20, [x13, #0x30]\n"
+    "mov v22.16b, v25.16b\n fmla v22.4s, v1.4s, v9.4s\n"
+    "mov v21.16b, v25.16b\n fmla v21.4s, v0.4s, v9.4s\n"
+    "ldr q18, [x21, x28]\n"
+    "ldr q25, [x14, #0x0]\n"
+    "fmla v24.4s, v0.4s, v10.4s\n"
+    "fmla v23.4s, v2.4s, v11.4s\n"
+    "ldr q17, [x20, x28]\n"
+    "ldr x21, [x13, #0x38]\n"
+    "fmla v22.4s, v2.4s, v12.4s\n"
+    "fmla v21.4s, v1.4s, v12.4s\n"
+    "ldr x20, [x13, #0x48]\n"
+    "ldr q20, [x20, x28]\n"
+    "fmla v24.4s, v5.4s, v12.4s\n"
+    "fmla v23.4s, v4.4s, v12.4s\n"
+    "ldr q16, [x21, x28]\n"
+    "ldr x20, [x13, #0x40]\n"
+    "fmla v22.4s, v6.4s, v18.4s\n"
+    "ldr q18, [x20, x28]\n"
+    "fmla v21.4s, v3.4s, v13.4s\n"
+    "ldr x20, [x13, #0x50]\n"
+    "fmla v24.4s, v7.4s, v13.4s\n"
+    "fmla v23.4s, v6.4s, v13.4s\n"
+    "ldr x22, [x13, #0x58]\n"
+    "ldr x21, [x13, #0x60]\n"
+    "fmla v22.4s, v4.4s, v13.4s\n"
+    "fmla v21.4s, v8.4s, v17.4s\n"
+    "ldr q17, [x20, x28]\n"
+    "ldr x20, [x13, #0x68]\n"
+    "fmla v24.4s, v1.4s, v16.4s\n"
+    "fmla v23.4s, v0.4s, v16.4s\n"
+    "ldr q16, [x22, x28]\n"
+    "ldr x26, [x13, #0x70]\n"
+    "fmla v22.4s, v5.4s, v20.4s\n"
+    "fmla v21.4s, v4.4s, v20.4s\n"
     "ldr q4, [x14, #0x50]\n"
-    "ldr x20, [x13, #0x78]\n"
-    "fmla v28.4s, v2.4s, v9.4s\n"
-    "fmla v29.4s, v1.4s, v9.4s\n"
-    "ldr q9, [x23, x28]\n"
+    "ldr x25, [x13, #0x78]\n"
+    "fmla v24.4s, v2.4s, v18.4s\n"
+    "fmla v23.4s, v1.4s, v18.4s\n"
+    "ldr q19, [x21, x28]\n"
     "ldr q1, [x14, #0x20]\n"
-    "fmla v30.4s, v0.4s, v11.4s\n"
+    "fmla v22.4s, v0.4s, v17.4s\n"
     "ldr q0, [x14, #0x10]\n"
-    "fmla v31.4s, v2.4s, v12.4s\n"
+    "fmla v21.4s, v2.4s, v16.4s\n"
     "ldr q2, [x14, #0x30]\n"
-    "fmla v28.4s, v8.4s, v10.4s\n"
-    "fmla v29.4s, v7.4s, v10.4s\n"
-    "ldr q10, [x22, x28]\n"
-    "ldp x26, x22, [x13, #0x0]\n"
-    "fmla v30.4s, v3.4s, v9.4s\n"
-    "fmla v31.4s, v5.4s, v10.4s\n"
-    "ldp x25, x24, [x13, #0x10]\n"
-    "ldr x23, [x13, #0x20]\n"
-    "ldr q13, [x23, x16]\n"
-    "fmla v28.4s, v3.4s, v11.4s\n"
-    "ldr q11, [x21, x28]\n"
-    "fmla v29.4s, v5.4s, v12.4s\n"
-    "ldr q12, [x20, x28]\n"
+    "fmla v24.4s, v8.4s, v20.4s\n"
+    "fmla v23.4s, v7.4s, v20.4s\n"
+    "ldr q18, [x20, x28]\n"
+    "ldp x24, x23, [x13, #0x0]\n"
+    "fmla v22.4s, v3.4s, v19.4s\n"
+    "fmla v21.4s, v5.4s, v18.4s\n"
+    "ldp x22, x21, [x13, #0x10]\n"
+    "ldr x20, [x13, #0x20]\n"
+    "ldr q13, [x20, x16]\n"
+    "fmla v24.4s, v3.4s, v17.4s\n"
+    "ldr q17, [x26, x28]\n"
+    "fmla v23.4s, v5.4s, v16.4s\n"
+    "ldr q16, [x25, x28]\n"
     "ldr q3, [x14, #0x40]\n"
-    "fmla v30.4s, v7.4s, v11.4s\n"
-    "fmla v31.4s, v6.4s, v11.4s\n"
-    "ldr q11, [x25, x16]\n"
+    "fmla v22.4s, v7.4s, v17.4s\n"
+    "fmla v21.4s, v6.4s, v17.4s\n"
+    "ldr q11, [x22, x16]\n"
     "ldr q5, [x14, #0x60]\n"
-    "fmla v28.4s, v6.4s, v9.4s\n"
-    "fmla v29.4s, v8.4s, v10.4s\n"
-    "ldr q9, [x26, x16]\n"
-    "ldr q10, [x22, x16]\n"
-    "fmla v30.4s, v8.4s, v12.4s\n"
-    "fmla v31.4s, v7.4s, v12.4s\n"
-    "ldr q12, [x24, x16]\n"
+    "fmla v24.4s, v6.4s, v19.4s\n"
+    "fmla v23.4s, v8.4s, v18.4s\n"
+    "ldr q9, [x24, x16]\n"
+    "ldr q10, [x23, x16]\n"
+    "fmla v22.4s, v8.4s, v16.4s\n"
+    "fmla v21.4s, v7.4s, v16.4s\n"
+    "ldr q12, [x21, x16]\n"
     "ldr q6, [x14, #0x70]\n"
-    "fmax v28.4s, v28.4s, v18.4s\n"
-    "fmax v29.4s, v29.4s, v18.4s\n"
+    "fmax v24.4s, v24.4s, v27.4s\n"
+    "fmax v23.4s, v23.4s, v27.4s\n"
     "ldr q7, [x14, #0x80]\n"
     "ldr q8, [x14, #0x90]\n"
-    "fmax v30.4s, v30.4s, v18.4s\n"
-    "fmax v31.4s, v31.4s, v18.4s\n"
+    "fmax v22.4s, v22.4s, v27.4s\n"
+    "fmax v21.4s, v21.4s, v27.4s\n"
     "add x16, x16, #0x10\n"
     "add x27, x27, #0x10\n"
-    "fmin v28.4s, v28.4s, v17.4s\n"
-    "fmin v29.4s, v29.4s, v17.4s\n"
+    "fmin v24.4s, v24.4s, v26.4s\n"
+    "fmin v23.4s, v23.4s, v26.4s\n"
     "cmp x16, x15, LSL #4\n"
-    "fmin v30.4s, v30.4s, v17.4s\n"
-    "fmin v31.4s, v31.4s, v17.4s\n"
+    "fmin v22.4s, v22.4s, v26.4s\n"
+    "fmin v21.4s, v21.4s, v26.4s\n"
     "add x28, x28, #0x10\n"
-    "str q28, [x12, x27]\n"
+    "str q24, [x12, x27]\n"
     "add x14, x14, #0xa0\n"
-    "str q29, [x11, x27]\n"
-    "str q30, [x10, x27]\n"
-    "str q31, [x9, x27]\n"
+    "str q23, [x11, x27]\n"
+    "str q22, [x10, x27]\n"
+    "str q21, [x9, x27]\n"
     "blt 1b\n"
     "2:"  // Channel tail
-    "mov v28.16b, v16.16b\n fmla v28.4s, v4.4s, v9.4s\n"
-    "mov v29.16b, v16.16b\n fmla v29.4s, v3.4s, v9.4s\n"
-    "ldr x22, [x13, #0x28]\n"
-    "ldr x21, [x13, #0x30]\n"
-    "mov v30.16b, v16.16b\n fmla v30.4s, v1.4s, v9.4s\n"
-    "mov v31.16b, v16.16b\n fmla v31.4s, v0.4s, v9.4s\n"
-    "ldr q9, [x22, x28]\n"
-    "ldr x20, [x13, #0x38]\n"
-    "fmla v28.4s, v0.4s, v10.4s\n"
-    "fmla v29.4s, v2.4s, v11.4s\n"
-    "ldr q11, [x21, x28]\n"
-    "ldr x22, [x13, #0x48]\n"
-    "ldr q10, [x22, x28]\n"
-    "fmla v30.4s, v2.4s, v12.4s\n"
-    "fmla v31.4s, v1.4s, v12.4s\n"
-    "ldr x26, [x13, #0x40]\n"
-    "fmla v28.4s, v5.4s, v12.4s\n"
-    "fmla v29.4s, v4.4s, v12.4s\n"
-    "ldr q12, [x20, x28]\n"
-    "ldr x25, [x13, #0x50]\n"
-    "fmla v30.4s, v6.4s, v9.4s\n"
-    "ldr q9, [x26, x28]\n"
-    "fmla v31.4s, v3.4s, v13.4s\n"
-    "ldr x24, [x13, #0x58]\n"
-    "fmla v28.4s, v7.4s, v13.4s\n"
-    "fmla v29.4s, v6.4s, v13.4s\n"
+    "mov v24.16b, v25.16b\n fmla v24.4s, v4.4s, v9.4s\n"
+    "mov v23.16b, v25.16b\n fmla v23.4s, v3.4s, v9.4s\n"
+    "ldr x21, [x13, #0x28]\n"
+    "ldr x20, [x13, #0x30]\n"
+    "mov v22.16b, v25.16b\n fmla v22.4s, v1.4s, v9.4s\n"
+    "mov v21.16b, v25.16b\n fmla v21.4s, v0.4s, v9.4s\n"
+    "ldr q18, [x21, x28]\n"
+    "ldr x21, [x13, #0x38]\n"
+    "fmla v24.4s, v0.4s, v10.4s\n"
+    "fmla v23.4s, v2.4s, v11.4s\n"
+    "ldr q17, [x20, x28]\n"
+    "ldr x20, [x13, #0x48]\n"
+    "ldr q20, [x20, x28]\n"
+    "fmla v22.4s, v2.4s, v12.4s\n"
+    "fmla v21.4s, v1.4s, v12.4s\n"
+    "ldr x20, [x13, #0x40]\n"
+    "fmla v24.4s, v5.4s, v12.4s\n"
+    "fmla v23.4s, v4.4s, v12.4s\n"
+    "ldr q16, [x21, x28]\n"
+    "ldr x21, [x13, #0x50]\n"
+    "fmla v22.4s, v6.4s, v18.4s\n"
+    "ldr q18, [x20, x28]\n"
+    "fmla v21.4s, v3.4s, v13.4s\n"
+    "ldr x20, [x13, #0x58]\n"
+    "fmla v24.4s, v7.4s, v13.4s\n"
+    "fmla v23.4s, v6.4s, v13.4s\n"
     "ldr x23, [x13, #0x60]\n"
     "ldr x22, [x13, #0x68]\n"
-    "fmla v30.4s, v4.4s, v13.4s\n"
-    "fmla v31.4s, v8.4s, v11.4s\n"
-    "ldr q11, [x25, x28]\n"
+    "fmla v22.4s, v4.4s, v13.4s\n"
+    "fmla v21.4s, v8.4s, v17.4s\n"
+    "ldr q17, [x21, x28]\n"
     "ldr x21, [x13, #0x70]\n"
-    "fmla v28.4s, v1.4s, v12.4s\n"
-    "fmla v29.4s, v0.4s, v12.4s\n"
-    "ldr q12, [x24, x28]\n"
+    "fmla v24.4s, v1.4s, v16.4s\n"
+    "fmla v23.4s, v0.4s, v16.4s\n"
+    "ldr q16, [x20, x28]\n"
     "ldr x20, [x13, #0x78]\n"
-    "fmla v30.4s, v5.4s, v10.4s\n"
-    "fmla v31.4s, v4.4s, v10.4s\n"
+    "fmla v22.4s, v5.4s, v20.4s\n"
+    "fmla v21.4s, v4.4s, v20.4s\n"
     "add x27, x27, #0x10\n"
-    "fmla v28.4s, v2.4s, v9.4s\n"
-    "fmla v29.4s, v1.4s, v9.4s\n"
-    "ldr q9, [x23, x28]\n"
-    "fmla v30.4s, v0.4s, v11.4s\n"
-    "fmla v31.4s, v2.4s, v12.4s\n"
-    "fmla v28.4s, v8.4s, v10.4s\n"
-    "fmla v29.4s, v7.4s, v10.4s\n"
-    "ldr q10, [x22, x28]\n"
-    "fmla v30.4s, v3.4s, v9.4s\n"
-    "fmla v31.4s, v5.4s, v10.4s\n"
-    "fmla v28.4s, v3.4s, v11.4s\n"
-    "ldr q11, [x21, x28]\n"
-    "fmla v29.4s, v5.4s, v12.4s\n"
-    "ldr q12, [x20, x28]\n"
-    "fmla v30.4s, v7.4s, v11.4s\n"
-    "fmla v31.4s, v6.4s, v11.4s\n"
+    "fmla v24.4s, v2.4s, v18.4s\n"
+    "fmla v23.4s, v1.4s, v18.4s\n"
+    "ldr q19, [x23, x28]\n"
+    "fmla v22.4s, v0.4s, v17.4s\n"
+    "fmla v21.4s, v2.4s, v16.4s\n"
+    "fmla v24.4s, v8.4s, v20.4s\n"
+    "fmla v23.4s, v7.4s, v20.4s\n"
+    "ldr q18, [x22, x28]\n"
+    "fmla v22.4s, v3.4s, v19.4s\n"
+    "fmla v21.4s, v5.4s, v18.4s\n"
+    "fmla v24.4s, v3.4s, v17.4s\n"
+    "ldr q17, [x21, x28]\n"
+    "fmla v23.4s, v5.4s, v16.4s\n"
+    "ldr q16, [x20, x28]\n"
+    "fmla v22.4s, v7.4s, v17.4s\n"
+    "fmla v21.4s, v6.4s, v17.4s\n"
     "add x28, x28, #0x10\n"
-    "fmla v28.4s, v6.4s, v9.4s\n"
-    "fmla v29.4s, v8.4s, v10.4s\n"
-    "fmax v28.4s, v28.4s, v18.4s\n"
-    "fmla v30.4s, v8.4s, v12.4s\n"
-    "fmla v31.4s, v7.4s, v12.4s\n"
-    "fmax v29.4s, v29.4s, v18.4s\n"
-    "fmax v30.4s, v30.4s, v18.4s\n"
-    "fmax v31.4s, v31.4s, v18.4s\n"
-    "fmin v28.4s, v28.4s, v17.4s\n"
-    "fmin v29.4s, v29.4s, v17.4s\n"
-    "str q28, [x12, x27]\n"
-    "fmin v30.4s, v30.4s, v17.4s\n"
-    "fmin v31.4s, v31.4s, v17.4s\n"
-    "str q29, [x11, x27]\n"
-    "str q30, [x10, x27]\n"
-    "str q31, [x9, x27]\n"
+    "fmla v24.4s, v6.4s, v19.4s\n"
+    "fmla v23.4s, v8.4s, v18.4s\n"
+    "fmax v24.4s, v24.4s, v27.4s\n"
+    "fmla v22.4s, v8.4s, v16.4s\n"
+    "fmla v21.4s, v7.4s, v16.4s\n"
+    "fmax v23.4s, v23.4s, v27.4s\n"
+    "fmax v22.4s, v22.4s, v27.4s\n"
+    "fmax v21.4s, v21.4s, v27.4s\n"
+    "fmin v24.4s, v24.4s, v26.4s\n"
+    "fmin v23.4s, v23.4s, v26.4s\n"
+    "str q24, [x12, x27]\n"
+    "fmin v22.4s, v22.4s, v26.4s\n"
+    "fmin v21.4s, v21.4s, v26.4s\n"
+    "str q23, [x11, x27]\n"
+    "str q22, [x10, x27]\n"
+    "str q21, [x9, x27]\n"
     "3:"  // Oddments
     "tst %x[n_channels], #0x3\n"
     "beq 30f\n"
-    "ldr q16, [x14, #0x0]\n"
+    "ldr q25, [x14, #0x0]\n"
     "ldr q0, [x14, #0x10]\n"
-    "mov x27, x28\n"
-    "add x12, x12, x27\n"
+    "mov x20, x28\n"
+    "add x12, x12, x20\n"
     "ldr q1, [x14, #0x20]\n"
     "ldr q2, [x14, #0x30]\n"
-    "add x11, x11, x27\n"
-    "add x10, x10, x27\n"
+    "add x11, x11, x20\n"
+    "add x10, x10, x20\n"
     "ldr q3, [x14, #0x40]\n"
     "ldr q4, [x14, #0x50]\n"
-    "add x9, x9, x27\n"
+    "add x9, x9, x20\n"
     "ldr q5, [x14, #0x60]\n"
     "ldr q6, [x14, #0x70]\n"
     "ldr q7, [x14, #0x80]\n"
@@ -329,12 +329,12 @@ void a64_fp32_nhwc_3x3_s1_output2x2_mla_depthfirst_indirect_impl(
     "ld1 { v12.s }[0], [x21], #0x4\n"
     "ld1 { v13.s }[0], [x20], #0x4\n"
     "5:"  // Oddments: Load inputs (1, 1), (0, 0), (0, 3), (1, 2), (2, 1): Bit 1: End
-    "mov v28.16b, v16.16b\n fmla v28.4s, v4.4s, v9.4s\n"
-    "mov v29.16b, v16.16b\n fmla v29.4s, v3.4s, v9.4s\n"
+    "mov v28.16b, v25.16b\n fmla v28.4s, v4.4s, v9.4s\n"
+    "mov v29.16b, v25.16b\n fmla v29.4s, v3.4s, v9.4s\n"
     "ldr x20, [x13, #0x28]\n"
     "add x20, x20, x28\n"
-    "mov v30.16b, v16.16b\n fmla v30.4s, v1.4s, v9.4s\n"
-    "mov v31.16b, v16.16b\n fmla v31.4s, v0.4s, v9.4s\n"
+    "mov v30.16b, v25.16b\n fmla v30.4s, v1.4s, v9.4s\n"
+    "mov v31.16b, v25.16b\n fmla v31.4s, v0.4s, v9.4s\n"
     "fmla v28.4s, v0.4s, v10.4s\n"
     "fmla v29.4s, v2.4s, v11.4s\n"
     "fmla v28.4s, v5.4s, v12.4s\n"
@@ -475,14 +475,14 @@ void a64_fp32_nhwc_3x3_s1_output2x2_mla_depthfirst_indirect_impl(
     "27:"  // Oddments: Load input (3, 2): Bit 1: End
     "fmla v30.4s, v8.4s, v12.4s\n"
     "fmla v31.4s, v7.4s, v12.4s\n"
-    "fmax v28.4s, v28.4s, v18.4s\n"
-    "fmax v29.4s, v29.4s, v18.4s\n"
-    "fmax v30.4s, v30.4s, v18.4s\n"
-    "fmax v31.4s, v31.4s, v18.4s\n"
-    "fmin v28.4s, v28.4s, v17.4s\n"
-    "fmin v29.4s, v29.4s, v17.4s\n"
-    "fmin v30.4s, v30.4s, v17.4s\n"
-    "fmin v31.4s, v31.4s, v17.4s\n"
+    "fmax v28.4s, v28.4s, v27.4s\n"
+    "fmax v29.4s, v29.4s, v27.4s\n"
+    "fmax v30.4s, v30.4s, v27.4s\n"
+    "fmax v31.4s, v31.4s, v27.4s\n"
+    "fmin v28.4s, v28.4s, v26.4s\n"
+    "fmin v29.4s, v29.4s, v26.4s\n"
+    "fmin v30.4s, v30.4s, v26.4s\n"
+    "fmin v31.4s, v31.4s, v26.4s\n"
     "tbz %x[n_channels], #1, 28f\n"
     "st1 { v28.d }[0], [x12], #0x8\n"
     "st1 { v29.d }[0], [x11], #0x8\n"
@@ -503,11 +503,11 @@ void a64_fp32_nhwc_3x3_s1_output2x2_mla_depthfirst_indirect_impl(
     "30:"  // End
     :
     : [n_channels] "r" ((unsigned long) n_channels), [offsetof_Args_inptrs] "I" (offsetof(Args, inptrs)), [offsetof_args_max] "I" (offsetof(Args, max)), [offsetof_args_min] "I" (offsetof(Args, min)), [offsetof_args_outptrs] "I" (offsetof(Args, outptrs)), [offsetof_args_params] "I" (offsetof(Args, params)), [params_struct] "r" (&params_struct)
-    : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v16", "v17", "v18", "v28", "v29", "v30", "v31", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28"
+    : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28"
   );
 }
 
 }  // namespace depthwise
 }  // namespace arm_conv
 
-#endif  // __aarch64__
+#endif  // defined(__aarch64__)
-- 
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