From d02d5edfa15ba6c04a9986a8a362a945cb38ac31 Mon Sep 17 00:00:00 2001 From: Michele Di Giorgio Date: Fri, 22 Jan 2021 09:47:04 +0000 Subject: Integrate improved CPU depthwise convolution kernels * Replace assembly kernels for depthwise convolution with more optimized ones. * Add int8 assembly kernels. * Fix implicit padding on optimized kernels Resolves: COMPMID-3867, COMPMID-4361 Change-Id: I0b0867e05f61be4f368f62190d55e14d0ab3ebf2 Signed-off-by: Michele Di Giorgio Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/5622 Tested-by: Arm Jenkins Reviewed-by: Georgios Pinitas --- .../kernels/arm_conv/depthwise/depthwise_fp16.cpp | 224 +++++++++++++++++++++ 1 file changed, 224 insertions(+) create mode 100644 src/core/NEON/kernels/arm_conv/depthwise/depthwise_fp16.cpp (limited to 'src/core/NEON/kernels/arm_conv/depthwise/depthwise_fp16.cpp') diff --git a/src/core/NEON/kernels/arm_conv/depthwise/depthwise_fp16.cpp b/src/core/NEON/kernels/arm_conv/depthwise/depthwise_fp16.cpp new file mode 100644 index 0000000000..fdb36fc1d1 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/depthwise/depthwise_fp16.cpp @@ -0,0 +1,224 @@ +/* + * Copyright (c) 2021 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "arm_gemm_local.hpp" + +#include "depthwise_implementation.hpp" +#include "depthwise_depthfirst.hpp" +#include "depthwise_depthfirst_generic.hpp" +#include "depthwise_depthfirst_multiplier.hpp" +#include "depthwise_depthfirst_generic_multiplier.hpp" + +#include "depthwise_implementation_constraints.hpp" + +#if defined(__aarch64__) +#if defined(__ARM_FEATURE_SVE) +#include "kernels/sve_fp16_nhwc_3x3_s1_output4x4_mla_depthfirst.hpp" +#include "kernels/sve_fp16_nhwc_3x3_s1_output3x3_mla_depthfirst.hpp" +#include "kernels/sve_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst.hpp" +#include "kernels/sve_fp16_nhwc_3x3_s2_output2x2_mla_depthfirst.hpp" +#include "kernels/sve_fp16_nhwc_5x5_s1_output2x2_mla_depthfirst.hpp" +#endif // defined(__ARM_FEATURE_SVE) +#include "kernels/a64_fp16_nhwc_3x3_s1_output4x4_mla_depthfirst.hpp" +#include "kernels/a64_fp16_nhwc_3x3_s1_output3x3_mla_depthfirst.hpp" +#include "kernels/a64_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst.hpp" +#include "kernels/a64_fp16_nhwc_3x3_s2_output2x2_mla_depthfirst.hpp" +#include "kernels/a64_fp16_nhwc_5x5_s1_output2x2_mla_depthfirst.hpp" +#include "kernels/a64_fp16_nhwc_generic_output9_mla_depthfirst.hpp" +#include "kernels/a64_fp16_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst.hpp" +#endif // defined(__aarch64__) + +namespace arm_conv { +namespace depthwise { + +namespace +{ + template + unsigned int cycle_estimate(const DepthwiseArgs &args, const Nothing &) + { + // First-pass: compute the number of output pixels which will be computed. + return arm_gemm::roundup(args.output_rows, Strategy::output_rows) * + arm_gemm::roundup(args.output_cols, Strategy::output_cols) * + arm_gemm::iceildiv( + (long unsigned) args.input_channels * args.channel_multiplier, + arm_gemm::utils::get_vector_length(Strategy::vl_type) + ); + } + +#if defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + unsigned int not_preferred(const DepthwiseArgs &, const Nothing &) + { + return std::numeric_limits::max(); + } + + unsigned int not_preferred_if_no_multiplier(const DepthwiseArgs &args, const Nothing &) + { + return args.channel_multiplier > 1 ? 0 : std::numeric_limits::max(); + } +#endif // defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +} + +#if defined(__ARM_FP16_ARGS) + +static const DepthwiseImplementation<__fp16, __fp16> depthwise_fp16_methods[] = { +#if defined(__aarch64__) +#if defined(__ARM_FEATURE_SVE) + { + DepthwiseMethod::DEPTHFIRST, + "sve_fp16_nhwc_3x3_s1_output4x4_mla_depthfirst", + constraint(is_supported, + has_no_channel_multiplier), + cycle_estimate, + [] (const DepthwiseArgs &args, const Nothing &) -> DepthwiseCommon<__fp16, __fp16, __fp16> * { + return new DepthwiseDepthfirst(args); + }, + }, + { + DepthwiseMethod::DEPTHFIRST, + "sve_fp16_nhwc_3x3_s1_output3x3_mla_depthfirst", + constraint(is_supported, + has_no_channel_multiplier), + cycle_estimate, + [] (const DepthwiseArgs &args, const Nothing &) -> DepthwiseCommon<__fp16, __fp16, __fp16> * { + return new DepthwiseDepthfirst(args); + }, + }, + { + DepthwiseMethod::DEPTHFIRST, + "sve_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst", + constraint(is_supported, + has_no_channel_multiplier), + cycle_estimate, + [] (const DepthwiseArgs &args, const Nothing &) -> DepthwiseCommon<__fp16, __fp16, __fp16> * { + return new DepthwiseDepthfirst(args); + }, + }, + { + DepthwiseMethod::DEPTHFIRST, + "sve_fp16_nhwc_3x3_s2_output2x2_mla_depthfirst", + constraint(is_supported, + has_no_channel_multiplier), + cycle_estimate, + [] (const DepthwiseArgs &args, const Nothing &) -> DepthwiseCommon<__fp16, __fp16, __fp16> * { + return new DepthwiseDepthfirst(args); + }, + }, + { + DepthwiseMethod::DEPTHFIRST, + "sve_fp16_nhwc_5x5_s1_output2x2_mla_depthfirst", + constraint(is_supported, + has_no_channel_multiplier), + cycle_estimate, + [] (const DepthwiseArgs &args, const Nothing &) -> DepthwiseCommon<__fp16, __fp16, __fp16> * { + return new DepthwiseDepthfirst(args); + }, + }, +#endif // defined(__ARM_FEATURE_SVE) +#if defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) + { + DepthwiseMethod::DEPTHFIRST, + "a64_fp16_nhwc_3x3_s1_output4x4_mla_depthfirst", + constraint(is_supported, + has_no_channel_multiplier), + cycle_estimate, + [] (const DepthwiseArgs &args, const Nothing &) -> DepthwiseCommon<__fp16, __fp16, __fp16> * { + return new DepthwiseDepthfirst(args); + }, + }, + { + DepthwiseMethod::DEPTHFIRST, + "a64_fp16_nhwc_3x3_s1_output3x3_mla_depthfirst", + constraint(is_supported, + has_no_channel_multiplier), + cycle_estimate, + [] (const DepthwiseArgs &args, const Nothing &) -> DepthwiseCommon<__fp16, __fp16, __fp16> * { + return new DepthwiseDepthfirst(args); + }, + }, + { + DepthwiseMethod::DEPTHFIRST, + "a64_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst", + constraint(is_supported, + has_no_channel_multiplier), + cycle_estimate, + [] (const DepthwiseArgs &args, const Nothing &) -> DepthwiseCommon<__fp16, __fp16, __fp16> * { + return new DepthwiseDepthfirst(args); + }, + }, + { + DepthwiseMethod::DEPTHFIRST, + "a64_fp16_nhwc_3x3_s2_output2x2_mla_depthfirst", + constraint(is_supported, + has_no_channel_multiplier), + cycle_estimate, + [] (const DepthwiseArgs &args, const Nothing &) -> DepthwiseCommon<__fp16, __fp16, __fp16> * { + return new DepthwiseDepthfirst(args); + }, + }, + { + DepthwiseMethod::DEPTHFIRST, + "a64_fp16_nhwc_5x5_s1_output2x2_mla_depthfirst", + constraint(is_supported, + has_no_channel_multiplier), + cycle_estimate, + [] (const DepthwiseArgs &args, const Nothing &) -> DepthwiseCommon<__fp16, __fp16, __fp16> * { + return new DepthwiseDepthfirst(args); + }, + }, + { + DepthwiseMethod::DEPTHFIRST, + "a64_fp16_nhwc_generic_output3x3_mla_depthfirst", + constraint(has_no_channel_multiplier), + not_preferred, + [] (const DepthwiseArgs &args, const Nothing &) -> DepthwiseCommon<__fp16, __fp16, __fp16> * { + return new DepthwiseDepthfirstGeneric(args); + }, + }, + { + DepthwiseMethod::DEPTHFIRST, + "a64_fp16_nhwc_generic_with_multiplier_output2x8_mla_depthfirst", + nullptr, + not_preferred_if_no_multiplier, + [] (const DepthwiseArgs &args, const Nothing &) -> DepthwiseCommon<__fp16, __fp16, __fp16> * { + return new DepthwiseDepthfirstGenericWithMultiplier(args); + }, + }, +#endif // defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +#endif // defined(__aarch64__) + { DepthwiseMethod::DEFAULT, "", nullptr, nullptr, nullptr }, // End of list +}; + +template <> +const DepthwiseImplementation<__fp16> *depthwise_implementation_list() +{ + return depthwise_fp16_methods; +} + +template UniqueDepthwiseCommon<__fp16> depthwise(const DepthwiseArgs &, const Nothing &); +template std::vector get_compatible_kernels<__fp16>(const DepthwiseArgs &, const Nothing &); + +#endif // defined(__ARM_FP16_ARGS) + +} // namespace depthwise +} // namespace arm_conv -- cgit v1.2.1