From 9d0b5f82c2734444145718f12788f2dde436ef45 Mon Sep 17 00:00:00 2001
From: Michalis Spyrou <michalis.spyrou@arm.com>
Date: Wed, 1 May 2019 13:03:59 +0100
Subject: COMPMID-2177 Fix clang warnings

Change-Id: I78039db8c58d7b14a042c41e54c25fb9cb509bf7
Signed-off-by: Michalis Spyrou <michalis.spyrou@arm.com>
Reviewed-on: https://review.mlplatform.org/c/1092
Reviewed-by: VidhyaSudhan Loganathan <vidhyasudhan.loganathan@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
---
 src/core/CL/kernels/CLComparisonKernel.cpp           |  4 ++--
 src/core/CL/kernels/CLElementwiseOperationKernel.cpp |  4 ++--
 src/core/CL/kernels/CLGaussian5x5Kernel.cpp          | 12 ++++++------
 src/core/CL/kernels/CLGaussianPyramidKernel.cpp      |  6 +++---
 src/core/CL/kernels/CLMinMaxLayerKernel.cpp          |  4 ++--
 5 files changed, 15 insertions(+), 15 deletions(-)

(limited to 'src/core/CL/kernels')

diff --git a/src/core/CL/kernels/CLComparisonKernel.cpp b/src/core/CL/kernels/CLComparisonKernel.cpp
index f5f5a0fbd6..4f44851ef8 100644
--- a/src/core/CL/kernels/CLComparisonKernel.cpp
+++ b/src/core/CL/kernels/CLComparisonKernel.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018 ARM Limited.
+ * Copyright (c) 2018-2019 ARM Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -219,6 +219,6 @@ BorderSize CLComparisonKernel::border_size() const
 
     const unsigned int replicateSize = _output->info()->dimension(0) - std::min(_input1->info()->dimension(0), _input2->info()->dimension(0));
     const unsigned int border        = std::min<unsigned int>(num_elems_processed_per_iteration - 1U, replicateSize);
-    return BorderSize(0, border, 0, 0);
+    return BorderSize{ 0, border, 0, 0 };
 }
 } // namespace arm_compute
diff --git a/src/core/CL/kernels/CLElementwiseOperationKernel.cpp b/src/core/CL/kernels/CLElementwiseOperationKernel.cpp
index 37eeeb78bf..63c9244961 100644
--- a/src/core/CL/kernels/CLElementwiseOperationKernel.cpp
+++ b/src/core/CL/kernels/CLElementwiseOperationKernel.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018 ARM Limited.
+ * Copyright (c) 2018-2019 ARM Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -281,7 +281,7 @@ BorderSize CLElementwiseOperationKernel::border_size() const
 {
     const unsigned int replicateSize = _output->info()->dimension(0) - std::min(_input1->info()->dimension(0), _input2->info()->dimension(0));
     const unsigned int border        = std::min<unsigned int>(num_elems_processed_per_iteration - 1U, replicateSize);
-    return BorderSize(0, border, 0, 0);
+    return BorderSize{ 0, border, 0, 0 };
 }
 
 /** Arithmetic operations with saturation*/
diff --git a/src/core/CL/kernels/CLGaussian5x5Kernel.cpp b/src/core/CL/kernels/CLGaussian5x5Kernel.cpp
index bd523c883d..3b45b07ed9 100644
--- a/src/core/CL/kernels/CLGaussian5x5Kernel.cpp
+++ b/src/core/CL/kernels/CLGaussian5x5Kernel.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, 2017 ARM Limited.
+ * Copyright (c) 2016-2019 ARM Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -29,17 +29,17 @@ using namespace arm_compute;
 
 void CLGaussian5x5HorKernel::configure(const ICLTensor *input, ICLTensor *output, bool border_undefined)
 {
-    const int16_t matrix[] = { 1, 4, 6, 4, 1 };
+    const std::array<int16_t, 5> matrix = { 1, 4, 6, 4, 1 };
 
     // Set arguments
-    CLSeparableConvolution5x5HorKernel::configure(input, output, matrix, border_undefined);
+    CLSeparableConvolution5x5HorKernel::configure(input, output, matrix.data(), border_undefined);
 }
 
 void CLGaussian5x5VertKernel::configure(const ICLTensor *input, ICLTensor *output, bool border_undefined)
 {
-    const uint32_t scale    = 256;
-    const int16_t  matrix[] = { 1, 4, 6, 4, 1 };
+    const uint32_t scale = 256;
+    const std::array<int16_t, 5> matrix = { 1, 4, 6, 4, 1 };
 
     // Set arguments
-    CLSeparableConvolution5x5VertKernel::configure(input, output, matrix, scale, border_undefined);
+    CLSeparableConvolution5x5VertKernel::configure(input, output, matrix.data(), scale, border_undefined);
 }
diff --git a/src/core/CL/kernels/CLGaussianPyramidKernel.cpp b/src/core/CL/kernels/CLGaussianPyramidKernel.cpp
index 6b729c8585..c9c7bf39a9 100644
--- a/src/core/CL/kernels/CLGaussianPyramidKernel.cpp
+++ b/src/core/CL/kernels/CLGaussianPyramidKernel.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018 ARM Limited.
+ * Copyright (c) 2017-2019 ARM Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -38,7 +38,7 @@ CLGaussianPyramidHorKernel::CLGaussianPyramidHorKernel()
 
 BorderSize CLGaussianPyramidHorKernel::border_size() const
 {
-    return BorderSize(0, 2);
+    return BorderSize{ 0, 2 };
 }
 
 void CLGaussianPyramidHorKernel::configure(const ICLTensor *input, ICLTensor *output)
@@ -130,7 +130,7 @@ CLGaussianPyramidVertKernel::CLGaussianPyramidVertKernel()
 
 BorderSize CLGaussianPyramidVertKernel::border_size() const
 {
-    return BorderSize(2, 0);
+    return BorderSize{ 2, 0 };
 }
 
 void CLGaussianPyramidVertKernel::configure(const ICLTensor *input, ICLTensor *output)
diff --git a/src/core/CL/kernels/CLMinMaxLayerKernel.cpp b/src/core/CL/kernels/CLMinMaxLayerKernel.cpp
index fa7b678e86..92b5f8d505 100644
--- a/src/core/CL/kernels/CLMinMaxLayerKernel.cpp
+++ b/src/core/CL/kernels/CLMinMaxLayerKernel.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018 ARM Limited.
+ * Copyright (c) 2017-2019 ARM Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -127,7 +127,7 @@ void CLMinMaxLayerKernel::reset(cl::CommandQueue &queue)
     Iterator output(_output, window_output);
 
     // Reset output
-    execute_window_loop(window_output, [&](const Coordinates & id)
+    execute_window_loop(window_output, [&](const Coordinates &)
     {
         auto *ptr = reinterpret_cast<float *>(output.ptr());
         ptr[0]    = std::numeric_limits<float>::max();
-- 
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