From 5a5945387e70f62e6e1e95a177fae261d7570443 Mon Sep 17 00:00:00 2001 From: Georgios Pinitas Date: Mon, 3 Dec 2018 14:30:05 +0000 Subject: COMPMID-1809: Remove padding in NEGEMMConvolutionLayer 64-bit path. Change-Id: I1806591a2c73a1f057f13d8c6107d7b9796a82c8 Reviewed-on: https://review.mlplatform.org/370 Tested-by: Arm Jenkins Reviewed-by: Michalis Spyrou --- arm_compute/core/NEON/NEMath.inl | 34 ++-------- .../core/NEON/kernels/NEActivationLayerKernel.h | 14 ++-- .../core/NEON/kernels/NEArithmeticAdditionKernel.h | 7 +- .../kernels/detail/NEActivationFunctionDetail.h | 4 +- arm_compute/core/NEON/wrapper/intrinsics/abs.h | 75 ++++++++++++++++++++++ arm_compute/core/NEON/wrapper/intrinsics/add.h | 37 ++++++++++- arm_compute/core/NEON/wrapper/intrinsics/bsl.h | 40 ++++++------ arm_compute/core/NEON/wrapper/intrinsics/cgt.h | 8 +-- .../core/NEON/wrapper/intrinsics/intrinsics.h | 3 + arm_compute/core/NEON/wrapper/intrinsics/log.h | 47 ++++++++++++++ arm_compute/core/NEON/wrapper/intrinsics/neg.h | 39 +++++------ arm_compute/core/NEON/wrapper/intrinsics/tanh.h | 47 ++++++++++++++ arm_compute/core/NEON/wrapper/scalar/add.h | 62 ++++++++++++++++++ arm_compute/core/NEON/wrapper/scalar/scalar.h | 29 +++++++++ arm_compute/core/NEON/wrapper/wrapper.h | 3 +- arm_compute/core/utils/misc/Traits.h | 9 ++- 16 files changed, 364 insertions(+), 94 deletions(-) create mode 100644 arm_compute/core/NEON/wrapper/intrinsics/abs.h create mode 100644 arm_compute/core/NEON/wrapper/intrinsics/log.h create mode 100644 arm_compute/core/NEON/wrapper/intrinsics/tanh.h create mode 100644 arm_compute/core/NEON/wrapper/scalar/add.h create mode 100644 arm_compute/core/NEON/wrapper/scalar/scalar.h (limited to 'arm_compute') diff --git a/arm_compute/core/NEON/NEMath.inl b/arm_compute/core/NEON/NEMath.inl index 4de80509f0..27b4fc2c1b 100644 --- a/arm_compute/core/NEON/NEMath.inl +++ b/arm_compute/core/NEON/NEMath.inl @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018 ARM Limited. + * Copyright (c) 2016-2019 ARM Limited. * * SPDX-License-Identifier: MIT * @@ -255,34 +255,12 @@ inline float16x8_t vexpq_f16(float16x8_t x) inline float16x8_t vlogq_f16(float16x8_t x) { - static const std::array log_tab_f16 = - { - { - vdupq_n_f16(-2.29561495781f), - vdupq_n_f16(-2.47071170807f), - vdupq_n_f16(-5.68692588806f), - vdupq_n_f16(-0.165253549814f), - vdupq_n_f16(5.17591238022f), - vdupq_n_f16(0.844007015228f), - vdupq_n_f16(4.58445882797f), - vdupq_n_f16(0.0141278216615f), - } - }; - - static const int16x8_t CONST_127 = vdupq_n_s16(127); // 127 - static const float16x8_t CONST_LN2 = vdupq_n_f16(0.6931471805f); // ln(2) - - // Extract exponent - const int16x8_t m = vsubq_s16(vreinterpretq_s16_u16(vshrq_n_u16(vreinterpretq_u16_f16(x), 9)), CONST_127); - const float16x8_t val = vreinterpretq_f16_s16(vsubq_s16(vreinterpretq_s16_f16(x), vshlq_n_s16(m, 9))); - - // Polynomial Approximation - float16x8_t poly = vtaylor_polyq_f16(val, log_tab_f16); - - // Reconstruct - poly = vaddq_f16(poly, vmulq_f16(vcvtq_f16_s16(m), CONST_LN2)); + // TODO (COMPMID-1535) : Revisit FP16 approximations + const float32x4_t x_high = vcvt_f32_f16(vget_high_f16(x)); + const float32x4_t x_low = vcvt_f32_f16(vget_low_f16(x)); - return poly; + const float16x8_t res = vcvt_high_f16_f32(vcvt_f16_f32(vlogq_f32(x_low)), vlogq_f32(x_high)); + return res; } inline float16x8_t vpowq_f16(float16x8_t val, float16x8_t n) diff --git a/arm_compute/core/NEON/kernels/NEActivationLayerKernel.h b/arm_compute/core/NEON/kernels/NEActivationLayerKernel.h index 0290e32085..447f4880ee 100644 --- a/arm_compute/core/NEON/kernels/NEActivationLayerKernel.h +++ b/arm_compute/core/NEON/kernels/NEActivationLayerKernel.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018 ARM Limited. + * Copyright (c) 2017-2019 ARM Limited. * * SPDX-License-Identifier: MIT * @@ -26,6 +26,7 @@ #include "arm_compute/core/NEON/INEKernel.h" #include "arm_compute/core/QAsymm8.h" +#include "arm_compute/core/utils/misc/Traits.h" #ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC #include @@ -89,15 +90,8 @@ private: * @param[in] window Region on which to execute the kernel */ template - typename std::enable_if::value, void>::type activation(const Window &window); -#ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC - /** Function to apply an activation function on a tensor. - * - * @param[in] window Region on which to execute the kernel - */ - template - typename std::enable_if::value, void>::type activation(const Window &window); -#endif /* __ARM_FEATURE_FP16_VECTOR_ARITHMETIC */ + typename std::enable_if::value, void>::type + activation(const Window &window); /** Function to apply an activation function on a tensor. * * @param[in] window Region on which to execute the kernel diff --git a/arm_compute/core/NEON/kernels/NEArithmeticAdditionKernel.h b/arm_compute/core/NEON/kernels/NEArithmeticAdditionKernel.h index 73beca6ded..872c3a5b6b 100644 --- a/arm_compute/core/NEON/kernels/NEArithmeticAdditionKernel.h +++ b/arm_compute/core/NEON/kernels/NEArithmeticAdditionKernel.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018 ARM Limited. + * Copyright (c) 2016-2019 ARM Limited. * * SPDX-License-Identifier: MIT * @@ -84,7 +84,6 @@ public: // Inherited methods overridden: void run(const Window &window, const ThreadInfo &info) override; - BorderSize border_size() const override; private: /** Common signature for all the specialised add functions @@ -92,14 +91,16 @@ private: * @param[in] input1 An input tensor. Data types supported: U8/QASYMM8/S16/F16/F32 * @param[in] input2 An input tensor. Data types supported: U8/QASYMM8/S16/F16/F32 * @param[out] output The output tensor. Data types supported: U8/QASYMM8/S16/F16/F32. + * @param[in] policy Overflow policy. * @param[in] window Region on which to execute the kernel. */ - using AddFunction = void(const ITensor *input1, const ITensor *input2, ITensor *output, const Window &window); + using AddFunction = void(const ITensor *input1, const ITensor *input2, ITensor *output, ConvertPolicy policy, const Window &window); /** Add function to use for the particular tensor types passed to configure() */ AddFunction *_func; const ITensor *_input1; const ITensor *_input2; ITensor *_output; + ConvertPolicy _policy; }; } // namespace arm_compute #endif /*__ARM_COMPUTE_NEARITHMETICADDITIONKERNEL_H__ */ diff --git a/arm_compute/core/NEON/kernels/detail/NEActivationFunctionDetail.h b/arm_compute/core/NEON/kernels/detail/NEActivationFunctionDetail.h index 9344235d09..bde3ac82e7 100644 --- a/arm_compute/core/NEON/kernels/detail/NEActivationFunctionDetail.h +++ b/arm_compute/core/NEON/kernels/detail/NEActivationFunctionDetail.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 ARM Limited. + * Copyright (c) 2018-2019 ARM Limited. * * SPDX-License-Identifier: MIT * @@ -139,7 +139,7 @@ struct logistic */ void operator()(ExactType &vval) { - vval = wrapper::vinv(wrapper::vadd(vone, wrapper::vexpq(wrapper::vnegq(vval)))); + vval = wrapper::vinv(wrapper::vadd(vone, wrapper::vexpq(wrapper::vneg(vval)))); } /** Vector of ones. */ diff --git a/arm_compute/core/NEON/wrapper/intrinsics/abs.h b/arm_compute/core/NEON/wrapper/intrinsics/abs.h new file mode 100644 index 0000000000..97d11e951e --- /dev/null +++ b/arm_compute/core/NEON/wrapper/intrinsics/abs.h @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2018-2019 ARM Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef __ARM_COMPUTE_WRAPPER_ABS_H__ +#define __ARM_COMPUTE_WRAPPER_ABS_H__ + +#include + +namespace arm_compute +{ +namespace wrapper +{ +#define VABS_IMPL(stype, vtype, prefix, postfix) \ + inline vtype vabs(const vtype &a) \ + { \ + return prefix##_##postfix(a); \ + } + +#define VQABS_IMPL(stype, vtype, prefix, postfix) \ + inline vtype vqabs(const vtype &a) \ + { \ + return prefix##_##postfix(a); \ + } + +// Absolute: vabs{q}_. Vd[i] = |Va[i]| +VABS_IMPL(int8x8_t, int8x8_t, vabs, s8) +VABS_IMPL(int16x4_t, int16x4_t, vabs, s16) +VABS_IMPL(int32x2_t, int32x2_t, vabs, s32) +VABS_IMPL(float32x2_t, float32x2_t, vabs, f32) +#ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC +VABS_IMPL(float16x4_t, float16x4_t, vabs, f16) +#endif // __ARM_FEATURE_FP16_VECTOR_ARITHMETIC + +VABS_IMPL(int8x16_t, int8x16_t, vabsq, s8) +VABS_IMPL(int16x8_t, int16x8_t, vabsq, s16) +VABS_IMPL(int32x4_t, int32x4_t, vabsq, s32) +VABS_IMPL(float32x4_t, float32x4_t, vabsq, f32) +#ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC +VABS_IMPL(float16x8_t, float16x8_t, vabsq, f16) +#endif // __ARM_FEATURE_FP16_VECTOR_ARITHMETIC + +// Saturating absolute: vqabs{q}_. Vd[i] = sat(|Va[i]|) +VQABS_IMPL(int8x8_t, int8x8_t, vqabs, s8) +VQABS_IMPL(int16x4_t, int16x4_t, vqabs, s16) +VQABS_IMPL(int32x2_t, int32x2_t, vqabs, s32) + +VQABS_IMPL(int8x16_t, int8x16_t, vqabsq, s8) +VQABS_IMPL(int16x8_t, int16x8_t, vqabsq, s16) +VQABS_IMPL(int32x4_t, int32x4_t, vqabsq, s32) + +#undef VABS_IMPL +#undef VQABS_IMPL +} // namespace wrapper +} // namespace arm_compute +#endif /* __ARM_COMPUTE_WRAPPER_ABS_H__ */ diff --git a/arm_compute/core/NEON/wrapper/intrinsics/add.h b/arm_compute/core/NEON/wrapper/intrinsics/add.h index da730f133c..4f4d244489 100644 --- a/arm_compute/core/NEON/wrapper/intrinsics/add.h +++ b/arm_compute/core/NEON/wrapper/intrinsics/add.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 ARM Limited. + * Copyright (c) 2018-2019 ARM Limited. * * SPDX-License-Identifier: MIT * @@ -61,8 +61,41 @@ VADD_IMPL(float32x4_t, float32x4_t, vaddq, f32) #ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC VADD_IMPL(float16x8_t, float16x8_t, vaddq, f16) #endif // __ARM_FEATURE_FP16_VECTOR_ARITHMETIC - #undef VADD_IMPL + +#define VQADD_IMPL(stype, vtype, prefix, postfix) \ + inline vtype vqadd(const vtype &a, const vtype &b) \ + { \ + return prefix##_##postfix(a, b); \ + } + +// VQADD: Vector saturating add (No notion of saturation for floating point) +VQADD_IMPL(uint8x8_t, uint8x8_t, vqadd, u8) +VQADD_IMPL(int8x8_t, int8x8_t, vqadd, s8) +VQADD_IMPL(uint16x4_t, uint16x4_t, vqadd, u16) +VQADD_IMPL(int16x4_t, int16x4_t, vqadd, s16) +VQADD_IMPL(uint32x2_t, uint32x2_t, vqadd, u32) +VQADD_IMPL(int32x2_t, int32x2_t, vqadd, s32) +VQADD_IMPL(uint64x1_t, uint64x1_t, vqadd, u64) +VQADD_IMPL(int64x1_t, int64x1_t, vqadd, s64) +VQADD_IMPL(float32x2_t, float32x2_t, vadd, f32) +#ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC +VQADD_IMPL(float16x4_t, float16x4_t, vadd, f16) +#endif // __ARM_FEATURE_FP16_VECTOR_ARITHMETIC + +VQADD_IMPL(uint8x16_t, uint8x16_t, vqaddq, u8) +VQADD_IMPL(int8x16_t, int8x16_t, vqaddq, s8) +VQADD_IMPL(uint16x8_t, uint16x8_t, vqaddq, u16) +VQADD_IMPL(int16x8_t, int16x8_t, vqaddq, s16) +VQADD_IMPL(uint32x4_t, uint32x4_t, vqaddq, u32) +VQADD_IMPL(int32x4_t, int32x4_t, vqaddq, s32) +VQADD_IMPL(uint64x2_t, uint64x2_t, vqaddq, u64) +VQADD_IMPL(int64x2_t, int64x2_t, vqaddq, s64) +VQADD_IMPL(float32x4_t, float32x4_t, vaddq, f32) +#ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC +VQADD_IMPL(float16x8_t, float16x8_t, vaddq, f16) +#endif // __ARM_FEATURE_FP16_VECTOR_ARITHMETIC +#undef VQADD_IMPL } // namespace wrapper } // namespace arm_compute #endif /* __ARM_COMPUTE_WRAPPER_ADD_H__ */ diff --git a/arm_compute/core/NEON/wrapper/intrinsics/bsl.h b/arm_compute/core/NEON/wrapper/intrinsics/bsl.h index 9831b4b842..38f9d5f171 100644 --- a/arm_compute/core/NEON/wrapper/intrinsics/bsl.h +++ b/arm_compute/core/NEON/wrapper/intrinsics/bsl.h @@ -30,32 +30,32 @@ namespace arm_compute { namespace wrapper { -#define VBSL_IMPL(vctype, vtype, prefix, postfix) \ - inline vtype vbsl(const vctype &a, const vtype &b, const vtype &c) \ - { \ - return prefix##_##postfix(a, b, c); \ +#define VBSL_IMPL(stype, vtype, ctype, prefix, postfix) \ + inline vtype vbsl(const ctype &a, const vtype &b, const vtype &c) \ + { \ + return prefix##_##postfix(a, b, c); \ } -VBSL_IMPL(uint8x8_t, uint8x8_t, vbsl, u8) -VBSL_IMPL(uint8x8_t, int8x8_t, vbsl, s8) -VBSL_IMPL(uint16x4_t, uint16x4_t, vbsl, u16) -VBSL_IMPL(uint16x4_t, int16x4_t, vbsl, s16) -VBSL_IMPL(uint32x2_t, uint32x2_t, vbsl, u32) -VBSL_IMPL(uint32x2_t, int32x2_t, vbsl, s32) -VBSL_IMPL(uint32x2_t, float32x2_t, vbsl, f32) +VBSL_IMPL(uint8_t, uint8x8_t, uint8x8_t, vbsl, u8) +VBSL_IMPL(int8_t, int8x8_t, uint8x8_t, vbsl, s8) +VBSL_IMPL(uint16_t, uint16x4_t, uint16x4_t, vbsl, u16) +VBSL_IMPL(int16_t, int16x4_t, uint16x4_t, vbsl, s16) +VBSL_IMPL(uint32_t, uint32x2_t, uint32x2_t, vbsl, u32) +VBSL_IMPL(int32_t, int32x2_t, uint32x2_t, vbsl, s32) +VBSL_IMPL(float32x2_t, float32x2_t, uint32x2_t, vbsl, f32) #ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC -VBSL_IMPL(uint16x4_t, float16x4_t, vbsl, f16) +VBSL_IMPL(float16x4_t, float16x4_t, uint16x4_t, vbsl, f16) #endif // __ARM_FEATURE_FP16_VECTOR_ARITHMETIC -VBSL_IMPL(uint8x16_t, uint8x16_t, vbslq, u8) -VBSL_IMPL(uint8x16_t, int8x16_t, vbslq, s8) -VBSL_IMPL(uint16x8_t, uint16x8_t, vbslq, u16) -VBSL_IMPL(uint16x8_t, int16x8_t, vbslq, s16) -VBSL_IMPL(uint32x4_t, uint32x4_t, vbslq, u32) -VBSL_IMPL(uint32x4_t, int32x4_t, vbslq, s32) -VBSL_IMPL(uint32x4_t, float32x4_t, vbslq, f32) +VBSL_IMPL(uint8_t, uint8x16_t, uint8x16_t, vbslq, u8) +VBSL_IMPL(int8_t, int8x16_t, uint8x16_t, vbslq, s8) +VBSL_IMPL(uint16_t, uint16x8_t, uint16x8_t, vbslq, u16) +VBSL_IMPL(int16_t, int16x8_t, uint16x8_t, vbslq, s16) +VBSL_IMPL(uint32_t, uint32x4_t, uint32x4_t, vbslq, u32) +VBSL_IMPL(int32_t, int32x4_t, uint32x4_t, vbslq, s32) +VBSL_IMPL(float32x4_t, float32x4_t, uint32x4_t, vbslq, f32) #ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC -VBSL_IMPL(uint16x8_t, float16x8_t, vbslq, f16) +VBSL_IMPL(float16x8_t, float16x8_t, uint16x8_t, vbslq, f16) #endif // __ARM_FEATURE_FP16_VECTOR_ARITHMETIC #undef VBSL_IMPL diff --git a/arm_compute/core/NEON/wrapper/intrinsics/cgt.h b/arm_compute/core/NEON/wrapper/intrinsics/cgt.h index c2ed9df1dc..9563b0cd12 100644 --- a/arm_compute/core/NEON/wrapper/intrinsics/cgt.h +++ b/arm_compute/core/NEON/wrapper/intrinsics/cgt.h @@ -30,10 +30,10 @@ namespace arm_compute { namespace wrapper { -#define VCGT_IMPL(votype, vtype, prefix, postfix) \ - inline votype vcgt(const vtype &a, const vtype &b) \ - { \ - return prefix##_##postfix(a, b); \ +#define VCGT_IMPL(rtype, vtype, prefix, postfix) \ + inline rtype vcgt(const vtype &a, const vtype &b) \ + { \ + return prefix##_##postfix(a, b); \ } VCGT_IMPL(uint8x8_t, uint8x8_t, vcgt, u8) diff --git a/arm_compute/core/NEON/wrapper/intrinsics/intrinsics.h b/arm_compute/core/NEON/wrapper/intrinsics/intrinsics.h index 896e5106ab..a0193ee3d2 100644 --- a/arm_compute/core/NEON/wrapper/intrinsics/intrinsics.h +++ b/arm_compute/core/NEON/wrapper/intrinsics/intrinsics.h @@ -24,6 +24,7 @@ #ifndef __ARM_COMPUTE_WRAPPER_INTRINSICS_H__ #define __ARM_COMPUTE_WRAPPER_INTRINSICS_H__ +#include "arm_compute/core/NEON/wrapper/intrinsics/abs.h" #include "arm_compute/core/NEON/wrapper/intrinsics/add.h" #include "arm_compute/core/NEON/wrapper/intrinsics/and.h" #include "arm_compute/core/NEON/wrapper/intrinsics/bsl.h" @@ -39,6 +40,7 @@ #include "arm_compute/core/NEON/wrapper/intrinsics/inv.h" #include "arm_compute/core/NEON/wrapper/intrinsics/invsqrt.h" #include "arm_compute/core/NEON/wrapper/intrinsics/load.h" +#include "arm_compute/core/NEON/wrapper/intrinsics/log.h" #include "arm_compute/core/NEON/wrapper/intrinsics/max.h" #include "arm_compute/core/NEON/wrapper/intrinsics/min.h" #include "arm_compute/core/NEON/wrapper/intrinsics/mla.h" @@ -55,5 +57,6 @@ #include "arm_compute/core/NEON/wrapper/intrinsics/setlane.h" #include "arm_compute/core/NEON/wrapper/intrinsics/store.h" #include "arm_compute/core/NEON/wrapper/intrinsics/sub.h" +#include "arm_compute/core/NEON/wrapper/intrinsics/tanh.h" #endif /* __ARM_COMPUTE_WRAPPER_INTRINSICS_H__ */ diff --git a/arm_compute/core/NEON/wrapper/intrinsics/log.h b/arm_compute/core/NEON/wrapper/intrinsics/log.h new file mode 100644 index 0000000000..5367afb858 --- /dev/null +++ b/arm_compute/core/NEON/wrapper/intrinsics/log.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2018-2019 ARM Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef __ARM_COMPUTE_WRAPPER_LOG_H__ +#define __ARM_COMPUTE_WRAPPER_LOG_H__ + +#include "arm_compute/core/NEON/NEMath.h" +#include + +namespace arm_compute +{ +namespace wrapper +{ +#define VLOG_IMPL(vtype, prefix, postfix) \ + inline vtype vlog(const vtype &a) \ + { \ + return prefix##_##postfix(a); \ + } + +VLOG_IMPL(float32x4_t, vlogq, f32) +#ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC +VLOG_IMPL(float16x8_t, vlogq, f16) +#endif // __ARM_FEATURE_FP16_VECTOR_ARITHMETIC +#undef VLOG_IMPL +} // namespace wrapper +} // namespace arm_compute +#endif /* __ARM_COMPUTE_WRAPPER_LOG_H__ */ diff --git a/arm_compute/core/NEON/wrapper/intrinsics/neg.h b/arm_compute/core/NEON/wrapper/intrinsics/neg.h index 0ea1d429fe..7072866003 100644 --- a/arm_compute/core/NEON/wrapper/intrinsics/neg.h +++ b/arm_compute/core/NEON/wrapper/intrinsics/neg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 ARM Limited. + * Copyright (c) 2018-2019 ARM Limited. * * SPDX-License-Identifier: MIT * @@ -30,36 +30,29 @@ namespace arm_compute { namespace wrapper { -#define VNEG_IMPL(vtype, postfix) \ - inline vtype vneg(const vtype &a) \ - { \ - return vneg_##postfix(a); \ +#define VNEG_IMPL(vtype, prefix, postfix) \ + inline vtype vneg(const vtype &a) \ + { \ + return prefix##_##postfix(a); \ } -VNEG_IMPL(int8x8_t, s8) -VNEG_IMPL(int16x4_t, s16) -VNEG_IMPL(int32x2_t, s32) -VNEG_IMPL(float32x2_t, f32) +VNEG_IMPL(int8x8_t, vneg, s8) +VNEG_IMPL(int16x4_t, vneg, s16) +VNEG_IMPL(int32x2_t, vneg, s32) +VNEG_IMPL(float32x2_t, vneg, f32) #ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC -VNEG_IMPL(float16x4_t, f16) +VNEG_IMPL(float16x4_t, vneg, f16) #endif // __ARM_FEATURE_FP16_VECTOR_ARITHMETIC -#undef VNEG_IMPL -#define VNEGQ_IMPL(vtype, postfix) \ - inline vtype vnegq(const vtype &a) \ - { \ - return vnegq_##postfix(a); \ - } - -VNEGQ_IMPL(int8x16_t, s8) -VNEGQ_IMPL(int16x8_t, s16) -VNEGQ_IMPL(int32x4_t, s32) -VNEGQ_IMPL(float32x4_t, f32) +VNEG_IMPL(int8x16_t, vnegq, s8) +VNEG_IMPL(int16x8_t, vnegq, s16) +VNEG_IMPL(int32x4_t, vnegq, s32) +VNEG_IMPL(float32x4_t, vnegq, f32) #ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC -VNEGQ_IMPL(float16x8_t, f16) +VNEG_IMPL(float16x8_t, vnegq, f16) #endif // __ARM_FEATURE_FP16_VECTOR_ARITHMETIC -#undef VNEGQ_IMPL +#undef VNEG_IMPL } // namespace wrapper } // namespace arm_compute #endif /* __ARM_COMPUTE_WRAPPER_NEG_H__ */ diff --git a/arm_compute/core/NEON/wrapper/intrinsics/tanh.h b/arm_compute/core/NEON/wrapper/intrinsics/tanh.h new file mode 100644 index 0000000000..8a6978a767 --- /dev/null +++ b/arm_compute/core/NEON/wrapper/intrinsics/tanh.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2018-2019 ARM Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef __ARM_COMPUTE_WRAPPER_TANH_H__ +#define __ARM_COMPUTE_WRAPPER_TANH_H__ + +#include "arm_compute/core/NEON/NEMath.h" +#include + +namespace arm_compute +{ +namespace wrapper +{ +#define VTANH_IMPL(vtype, prefix, postfix) \ + inline vtype vtanh(const vtype &a) \ + { \ + return prefix##_##postfix(a); \ + } + +VTANH_IMPL(float32x4_t, vtanhq, f32) +#ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC +VTANH_IMPL(float16x8_t, vtanhq, f16) +#endif // __ARM_FEATURE_FP16_VECTOR_ARITHMETIC +#undef VTANH_IMPL +} // namespace wrapper +} // namespace arm_compute +#endif /* __ARM_COMPUTE_WRAPPER_TANH_H__ */ diff --git a/arm_compute/core/NEON/wrapper/scalar/add.h b/arm_compute/core/NEON/wrapper/scalar/add.h new file mode 100644 index 0000000000..cfb9040281 --- /dev/null +++ b/arm_compute/core/NEON/wrapper/scalar/add.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2018-2019 ARM Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef __ARM_COMPUTE_WRAPPER_SCALAR_ADD_H__ +#define __ARM_COMPUTE_WRAPPER_SCALAR_ADD_H__ + +#include + +namespace arm_compute +{ +namespace wrapper +{ +inline uint8_t add_sat(const uint8_t &a, const uint8_t &b) +{ + const uint8x8_t va = { a, 0, 0, 0, 0, 0, 0, 0 }; + const uint8x8_t vb = { b, 0, 0, 0, 0, 0, 0, 0 }; + return vget_lane_u8(vqadd_u8(va, vb), 0); +} + +inline int16_t add_sat(const int16_t &a, const int16_t &b) +{ + const int16x4_t va = { a, 0, 0, 0 }; + const int16x4_t vb = { b, 0, 0, 0 }; + return vget_lane_s16(vqadd_s16(va, vb), 0); +} + +inline float add_sat(const float &a, const float &b) +{ + // No notion of saturation exists in floating point + return a + b; +} + +#ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC +inline float16_t add_sat(const float16_t &a, const float16_t &b) +{ + // No notion of saturation exists in floating point + return a + b; +} +#endif // __ARM_FEATURE_FP16_VECTOR_ARITHMETIC +} // namespace wrapper +} // namespace arm_compute +#endif /* __ARM_COMPUTE_WRAPPER_SCALAR_ADD_H__ */ diff --git a/arm_compute/core/NEON/wrapper/scalar/scalar.h b/arm_compute/core/NEON/wrapper/scalar/scalar.h new file mode 100644 index 0000000000..a52e0ceb28 --- /dev/null +++ b/arm_compute/core/NEON/wrapper/scalar/scalar.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2018-2019 ARM Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef __ARM_COMPUTE_WRAPPER_SCALAR_H__ +#define __ARM_COMPUTE_WRAPPER_SCALAR_H__ + +#include "arm_compute/core/NEON/wrapper/scalar/add.h" + +#endif /* __ARM_COMPUTE_WRAPPER_SCALAR_H__ */ diff --git a/arm_compute/core/NEON/wrapper/wrapper.h b/arm_compute/core/NEON/wrapper/wrapper.h index 61dc42a69b..60dba5c022 100644 --- a/arm_compute/core/NEON/wrapper/wrapper.h +++ b/arm_compute/core/NEON/wrapper/wrapper.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 ARM Limited. + * Copyright (c) 2018-2019 ARM Limited. * * SPDX-License-Identifier: MIT * @@ -29,5 +29,6 @@ // Intrinsics Overloads #include "arm_compute/core/NEON/wrapper/intrinsics/intrinsics.h" +#include "arm_compute/core/NEON/wrapper/scalar/scalar.h" #endif /* __ARM_COMPUTE_WRAPPER_H__ */ diff --git a/arm_compute/core/utils/misc/Traits.h b/arm_compute/core/utils/misc/Traits.h index 9d86dd1b3c..9f6e49a452 100644 --- a/arm_compute/core/utils/misc/Traits.h +++ b/arm_compute/core/utils/misc/Traits.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 ARM Limited. + * Copyright (c) 2018-2019 ARM Limited. * * SPDX-License-Identifier: MIT * @@ -41,6 +41,13 @@ template <> struct is_floating_point : public std::true_type { }; + +#ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC +template <> +struct is_floating_point<__fp16> : public std::true_type +{ +}; +#endif /* __ARM_FEATURE_FP16_VECTOR_ARITHMETIC*/ } // namespace traits } // namespace utils } // namespace arm_compute -- cgit v1.2.1