From 171fc3d160736e10f859c6f2a24d1c7a59bcd9e3 Mon Sep 17 00:00:00 2001 From: Adnan AlSinan Date: Tue, 15 Mar 2022 18:46:42 +0000 Subject: Add CPU Pool3d FP16/32 implementation - Add implementation for the CPU pooling 3d layer. - NDHWC data layout support - Support FP32/FP16. - Add Pool3d to the operator list. - Fix CL Pool3d kernel comments to generate the operator list. Resolves: COMPMID-4671 Signed-off-by: Adnan AlSinan Change-Id: I92478a154beb12541525b648ed3dd5a58c8f27fa Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/7311 Tested-by: Arm Jenkins Reviewed-by: Giorgio Arena Reviewed-by: Gunes Bayir Comments-Addressed: Arm Jenkins (cherry picked from commit 572659a0e5dd1086b1c7d16fe331ff73d2acd93a) --- arm_compute/runtime/CL/functions/CLPooling3dLayer.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arm_compute/runtime/CL') diff --git a/arm_compute/runtime/CL/functions/CLPooling3dLayer.h b/arm_compute/runtime/CL/functions/CLPooling3dLayer.h index 2e4823756d..8bad449c6f 100644 --- a/arm_compute/runtime/CL/functions/CLPooling3dLayer.h +++ b/arm_compute/runtime/CL/functions/CLPooling3dLayer.h @@ -54,7 +54,7 @@ public: CLPooling3dLayer &operator=(CLPooling3dLayer &&) = default; /** Set the input and output tensors. * - * Valid data layout: + * Valid data layouts: * - NDHWC * * Valid data type configurations: -- cgit v1.2.1