From 5ae8d804d67f57fbfa793800ddcc21a5aff954dd Mon Sep 17 00:00:00 2001 From: Giorgio Arena Date: Thu, 18 Nov 2021 18:02:13 +0000 Subject: Enable kernel selection testing (Phase #1) Change-Id: I1d65fb9d3a7583cf8d4163ca7c0fbee27dc52633 Signed-off-by: Yair Schwarzbaum Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6767 Reviewed-by: Giorgio Arena Tested-by: Arm Jenkins Comments-Addressed: Arm Jenkins --- arm_compute/core/CPP/CPPTypes.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'arm_compute/core/CPP/CPPTypes.h') diff --git a/arm_compute/core/CPP/CPPTypes.h b/arm_compute/core/CPP/CPPTypes.h index 82a6a6c324..a021bdf5e4 100644 --- a/arm_compute/core/CPP/CPPTypes.h +++ b/arm_compute/core/CPP/CPPTypes.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2021 Arm Limited. + * Copyright (c) 2017-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -30,6 +30,11 @@ namespace arm_compute { +namespace cpuinfo +{ +struct CpuIsaInfo; +} // namespace cpuinfo + #define ARM_COMPUTE_CPU_MODEL_LIST \ X(GENERIC) \ X(GENERIC_FP16) \ @@ -134,6 +139,11 @@ public: * @return Current thread's @ref CPUModel */ CPUModel get_cpu_model() const; + /** Gets the current cpu's ISA information + * + * @return Current cpu's ISA information + */ + cpuinfo::CpuIsaInfo get_isa() const; /** Gets the L1 cache size * * @return the size of the L1 cache -- cgit v1.2.1