From 16cdf89eec95986d1b386312ccf3b221f6a1bad4 Mon Sep 17 00:00:00 2001 From: Jaroslaw Rzepecki Date: Fri, 27 Oct 2017 13:15:03 +0100 Subject: IVGCVSW-657 : fix asymmetric padding for 3x3 depthwise conv Change-Id: Ied6b3c41d988b9ff6a93f938117dc29ad4c85e9f Reviewed-on: http://mpd-gerrit.cambridge.arm.com/93421 Reviewed-by: Georgios Pinitas Tested-by: Kaizen --- arm_compute/core/CL/kernels/CLDepthwiseConvolution3x3Kernel.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arm_compute/core/CL') diff --git a/arm_compute/core/CL/kernels/CLDepthwiseConvolution3x3Kernel.h b/arm_compute/core/CL/kernels/CLDepthwiseConvolution3x3Kernel.h index b3d1eaf3af..4d4c288533 100644 --- a/arm_compute/core/CL/kernels/CLDepthwiseConvolution3x3Kernel.h +++ b/arm_compute/core/CL/kernels/CLDepthwiseConvolution3x3Kernel.h @@ -68,8 +68,8 @@ private: const ICLTensor *_biases; unsigned int _conv_stride_x; unsigned int _conv_stride_y; - unsigned int _conv_pad_x; - unsigned int _conv_pad_y; + unsigned int _conv_pad_left; + unsigned int _conv_pad_top; }; } // namespace arm_compute #endif /*__ARM_COMPUTE_CLDEPTHWISECONVOLUTIONKERNEL3x3_H__ */ -- cgit v1.2.1