From a5cb79f18685292bf5b63a0c484a58945320823d Mon Sep 17 00:00:00 2001 From: Gian Marco Iodice Date: Wed, 28 Dec 2022 13:53:51 +0000 Subject: Update the ClConv2d heuristic MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - Update the ClConv2d heuristic to call indirect convolution on Arm® Mali™-G77 Gpus - Implement the indirect conv2d heuristic for selecting the block size Resolves COMPMID-5713 Change-Id: If6ad49124561207153685c6abd4f54950a376fbc Signed-off-by: Gian Marco Iodice Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/8886 Benchmark: Arm Jenkins Tested-by: Arm Jenkins Reviewed-by: Gunes Bayir Comments-Addressed: Arm Jenkins --- Android.bp | 1 + arm_compute/core/Types.h | 1 + filelist.json | 3 +- src/gpu/cl/operators/ClConv2d.cpp | 45 +++++- src/gpu/cl/operators/ClConv2d.h | 1 + src/gpu/cl/operators/ClIndirectConv2d.cpp | 15 +- src/runtime/CL/functions/CLConvolutionLayer.cpp | 4 +- .../ClIndirectConvDefaultConfigValhall.cpp | 161 +++++++++++++++++++++ .../ClIndirectConvDefaultConfigValhall.h | 52 +++++++ .../indirect_conv/ClIndirectConvKernelConfig.h | 61 ++++++++ .../indirect_conv/IClIndirectConvKernelConfig.h | 108 ++++++++++++++ 11 files changed, 435 insertions(+), 17 deletions(-) create mode 100644 src/runtime/heuristics/indirect_conv/ClIndirectConvDefaultConfigValhall.cpp create mode 100644 src/runtime/heuristics/indirect_conv/ClIndirectConvDefaultConfigValhall.h create mode 100644 src/runtime/heuristics/indirect_conv/ClIndirectConvKernelConfig.h create mode 100644 src/runtime/heuristics/indirect_conv/IClIndirectConvKernelConfig.h diff --git a/Android.bp b/Android.bp index 27c87b6b90..bf6ee147f6 100644 --- a/Android.bp +++ b/Android.bp @@ -957,6 +957,7 @@ cc_library_static { "src/runtime/Utils.cpp", "src/runtime/heuristics/direct_conv/ClDirectConvDefaultConfigBifrost.cpp", "src/runtime/heuristics/direct_conv/ClDirectConvDefaultConfigValhall.cpp", + "src/runtime/heuristics/indirect_conv/ClIndirectConvDefaultConfigValhall.cpp", "utils/CommonGraphOptions.cpp", "utils/GraphUtils.cpp", "utils/Utils.cpp", diff --git a/arm_compute/core/Types.h b/arm_compute/core/Types.h index d5a4125c88..24ef931e88 100644 --- a/arm_compute/core/Types.h +++ b/arm_compute/core/Types.h @@ -136,6 +136,7 @@ enum class ConvolutionMethod GEMM, /**< Convolution using GEMM */ GEMM_CONV2D, /**< Direct 2D GEMM convolution */ DIRECT, /**< Direct convolution */ + INDIRECT, /**< Indirect convolution */ WINOGRAD, /**< Convolution using Winograd */ FFT /**< Convolution using FFT */ }; diff --git a/filelist.json b/filelist.json index c3582bc563..5828b43ec1 100644 --- a/filelist.json +++ b/filelist.json @@ -501,7 +501,8 @@ "src/runtime/CL/functions/CLGEMMLowpMatrixMultiplyCore.cpp", "src/runtime/CL/functions/CLGEMMLowpOutputStage.cpp", "src/runtime/heuristics/direct_conv/ClDirectConvDefaultConfigBifrost.cpp", - "src/runtime/heuristics/direct_conv/ClDirectConvDefaultConfigValhall.cpp" + "src/runtime/heuristics/direct_conv/ClDirectConvDefaultConfigValhall.cpp", + "src/runtime/heuristics/indirect_conv/ClIndirectConvDefaultConfigValhall.cpp" ] } }, diff --git a/src/gpu/cl/operators/ClConv2d.cpp b/src/gpu/cl/operators/ClConv2d.cpp index 54e5d002da..51248d4a7a 100644 --- a/src/gpu/cl/operators/ClConv2d.cpp +++ b/src/gpu/cl/operators/ClConv2d.cpp @@ -23,15 +23,13 @@ */ #include "src/gpu/cl/operators/ClConv2d.h" -#include "arm_compute/core/PixelValue.h" -#include "arm_compute/core/Utils.h" #include "arm_compute/core/Validate.h" #include "arm_compute/core/utils/misc/ShapeCalculator.h" -#include "arm_compute/core/utils/quantization/AsymmHelpers.h" #include "arm_compute/runtime/CL/CLScheduler.h" #include "arm_compute/runtime/CL/functions/CLFFTConvolutionLayer.h" #include "src/gpu/cl/operators/ClDirectConv2d.h" #include "src/gpu/cl/operators/ClGemmConv2d.h" +#include "src/gpu/cl/operators/ClIndirectConv2d.h" #include "src/gpu/cl/operators/ClWinogradConv2d.h" #include "src/common/utils/Log.h" @@ -107,6 +105,15 @@ void ClConv2d::configure(const CLCompileContext &compile_context, ITensorInfo *s _operator = std::move(f); break; } + case ConvolutionMethod::INDIRECT: + { + ARM_COMPUTE_ERROR_ON(conv2d_info.num_groups != 1); + ARM_COMPUTE_ERROR_ON(conv2d_info.post_ops.size() > 0); + auto f = std::make_unique(); + f->configure(compile_context, src, weights, biases, dst, conv2d_info.conv_info, conv2d_info.act_info); + _operator = std::move(f); + break; + } case ConvolutionMethod::GEMM: { auto f = std::make_unique(); @@ -147,6 +154,14 @@ Status ClConv2d::validate(const ITensorInfo *src, const ITensorInfo *weights, co ARM_COMPUTE_RETURN_ON_ERROR(ClDirectConv2d::validate(src, weights, biases, dst, conv2d_info.conv_info, conv2d_info.act_info)); break; } + case ConvolutionMethod::INDIRECT: + { + // Validate indirect convolution layer + ARM_COMPUTE_RETURN_ERROR_ON_MSG(conv2d_info.num_groups != 1, "Grouping (num_groups != 1) with ClIndirectConv2d is not supported"); + ARM_COMPUTE_RETURN_ERROR_ON_MSG(conv2d_info.post_ops.size() > 0, "ClIndirectConv2d does not support PostOps"); + ARM_COMPUTE_RETURN_ON_ERROR(ClIndirectConv2d::validate(src, weights, biases, dst, conv2d_info.conv_info, conv2d_info.act_info)); + break; + } case ConvolutionMethod::GEMM: { // Validate gemm-based convolution layer @@ -266,6 +281,7 @@ ConvolutionMethod ClConv2d::get_convolution_method(const ITensorInfo *src, const const bool is_ifm_gt_ofm = src->dimension(idx_c) > weights->dimension(3U); const bool is_m_one = output_shape[1] * output_shape[2] == 1; const bool is_unit_stride = (conv2d_info.conv_info.stride().first == 1) && (conv2d_info.conv_info.stride().second == 1); + const int32_t kernel_sz = weights->dimension(idx_w) * weights->dimension(idx_h); // Run Winograd if valid and IFM >= 8 if(is_wino_valid && is_ifm_ge_8) @@ -302,25 +318,40 @@ ConvolutionMethod ClConv2d::get_convolution_method(const ITensorInfo *src, const } else { - // Direct convolution used for the first layer of the network + ConvolutionMethod preferred_conv_method = ConvolutionMethod::DIRECT; + + const bool is_indirect_valid = bool(ClIndirectConv2d::validate(src, weights, nullptr, dst, conv_info, act_info)); + + // indirect conv2d should be called when: + // 1- When the kernel size is greater than 1x1 and less than or equal to 9x9 (81) + // 2- When the kernel size is odd + // 3- When the Gpu target is Arm Mali-G77 + if(is_indirect_valid) + { + const bool is_kernel_sz_odd = kernel_sz % 2; + const bool is_g77 = gpu_target == GPUTarget::G77; + preferred_conv_method = (kernel_sz > 1) && (kernel_sz <= 81) && is_kernel_sz_odd && is_g77? ConvolutionMethod::INDIRECT : ConvolutionMethod::DIRECT; + } + + // Direct/indirect convolution used for the first layer of the network if(workload_gte_8192 && !is_ifm_ge_16 && !is_unit_stride && is_ofm_lt_64) { // In general, the question we should ask for the first convolution layer of a model is: // when the execution time of im2col + gemm < direct?. Since im2col does not depend on the OFM, it means that // when OFM is big enough, the contribution of im2col is small and the GEMM approach is preferable. // From internal experiments, the OFM threshold is 64 (is_ofm_lt_64) - return ConvolutionMethod::DIRECT; + return preferred_conv_method; } if((is_large_kernel_sz || is_m_one) && workload_gte_8192 && is_ifm_ge_16) { - return ConvolutionMethod::DIRECT; + return preferred_conv_method; } // Direct convolution used for the last layer of the network if(is_ofm_lte_8) { - return ConvolutionMethod::DIRECT; + return preferred_conv_method; } } } diff --git a/src/gpu/cl/operators/ClConv2d.h b/src/gpu/cl/operators/ClConv2d.h index 1c3a81c77a..c6c366a762 100644 --- a/src/gpu/cl/operators/ClConv2d.h +++ b/src/gpu/cl/operators/ClConv2d.h @@ -38,6 +38,7 @@ namespace opencl * * -# @ref opencl::ClGemmConv2d * -# @ref opencl::ClWinogradConv2d + * -# @ref opencl::ClIndirectConv2d * -# @ref opencl::ClDirectConv2d * -# @ref CLFFTConvolutionLayer * diff --git a/src/gpu/cl/operators/ClIndirectConv2d.cpp b/src/gpu/cl/operators/ClIndirectConv2d.cpp index ae62dc8ce0..b900974574 100644 --- a/src/gpu/cl/operators/ClIndirectConv2d.cpp +++ b/src/gpu/cl/operators/ClIndirectConv2d.cpp @@ -27,18 +27,17 @@ #include "arm_compute/core/Types.h" #include "arm_compute/core/utils/misc/ShapeCalculator.h" #include "arm_compute/runtime/CL/CLScheduler.h" -#include "src/core/helpers/AutoConfiguration.h" #include "src/gpu/cl/kernels/ClIndirectConv2dAddressPrecalculationKernel.h" #include "src/gpu/cl/kernels/ClIndirectConv2dKernel.h" -#include "src/runtime/heuristics/direct_conv/ClDirectConvKernelConfig.h" -#include "src/runtime/heuristics/direct_conv/IClDirectConvKernelConfig.h" +#include "src/runtime/heuristics/indirect_conv/ClIndirectConvKernelConfig.h" +#include "src/runtime/heuristics/indirect_conv/IClIndirectConvKernelConfig.h" #include "src/core/helpers/MemoryHelpers.h" #include "src/gpu/cl/utils/ClAuxTensorHandler.h" #include "src/common/utils/Log.h" -using namespace arm_compute::cl_direct_conv; +using namespace arm_compute::cl_indirect_conv; namespace arm_compute { @@ -48,12 +47,12 @@ using namespace arm_compute::experimental; namespace { -DirectConvComputeKernelInfo config_direct_convolution_nhwc(const ITensorInfo *src, const ITensorInfo *weights, const PadStrideInfo &conv_info) +DirectConvComputeKernelInfo config_indirect_convolution_nhwc(const ITensorInfo *src, const ITensorInfo *weights, const PadStrideInfo &conv_info) { // Get GPU target GPUTarget gpu_target = CLScheduler::get().target(); - std::unique_ptr t = ClDirectConvKernelConfigurationFactory::create(gpu_target); + std::unique_ptr t = ClIndirectConvKernelConfigurationFactory::create(gpu_target); return t->configure(src, weights, conv_info); } @@ -67,7 +66,7 @@ void ClIndirectConv2d::configure(const CLCompileContext &compile_context, ITenso ARM_COMPUTE_LOG_PARAMS(src, weights, biases, dst, conv_info, act_info); // Reuse the direct convolution descriptor - const DirectConvComputeKernelInfo desc = config_direct_convolution_nhwc(src, weights, conv_info); + const DirectConvComputeKernelInfo desc = config_indirect_convolution_nhwc(src, weights, conv_info); // Configure indirect convolution kernels auto k0 = std::make_unique(); @@ -94,7 +93,7 @@ Status ClIndirectConv2d::validate(const ITensorInfo *src, const ITensorInfo *wei const PadStrideInfo &conv_info, const ActivationLayerInfo &act_info) { // Initialize the direct convolution descriptor - const DirectConvComputeKernelInfo desc = config_direct_convolution_nhwc(src, weights, conv_info); + const DirectConvComputeKernelInfo desc = config_indirect_convolution_nhwc(src, weights, conv_info); TensorShape ind_buffer_shape = misc::shape_calculator::compute_indirect_buffer_shape(src->tensor_shape(), src->data_layout(), diff --git a/src/runtime/CL/functions/CLConvolutionLayer.cpp b/src/runtime/CL/functions/CLConvolutionLayer.cpp index 20d7292d38..384249fc63 100644 --- a/src/runtime/CL/functions/CLConvolutionLayer.cpp +++ b/src/runtime/CL/functions/CLConvolutionLayer.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2021 Arm Limited. + * Copyright (c) 2017-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -87,6 +87,7 @@ void CLConvolutionLayer::configure(const CLCompileContext &compile_context, ICLT { case ConvolutionMethod::WINOGRAD: case ConvolutionMethod::DIRECT: + case ConvolutionMethod::INDIRECT: case ConvolutionMethod::GEMM: { auto f = std::make_unique(); @@ -138,6 +139,7 @@ Status CLConvolutionLayer::validate(const ITensorInfo *input, const ITensorInfo { case ConvolutionMethod::WINOGRAD: case ConvolutionMethod::DIRECT: + case ConvolutionMethod::INDIRECT: case ConvolutionMethod::GEMM: { ARM_COMPUTE_RETURN_ON_ERROR(opencl::ClConv2d::validate(input, weights, biases, output, conv2d_info, weights_info)); diff --git a/src/runtime/heuristics/indirect_conv/ClIndirectConvDefaultConfigValhall.cpp b/src/runtime/heuristics/indirect_conv/ClIndirectConvDefaultConfigValhall.cpp new file mode 100644 index 0000000000..5d3dbf3146 --- /dev/null +++ b/src/runtime/heuristics/indirect_conv/ClIndirectConvDefaultConfigValhall.cpp @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#include "src/runtime/heuristics/indirect_conv/ClIndirectConvDefaultConfigValhall.h" + +#include "arm_compute/core/CL/CLHelpers.h" +#include "arm_compute/core/GPUTarget.h" +#include "arm_compute/core/TensorInfo.h" +#include "arm_compute/core/TensorShape.h" +#include "arm_compute/core/utils/misc/ShapeCalculator.h" + +namespace arm_compute +{ +namespace cl_indirect_conv +{ +using namespace arm_compute::misc::shape_calculator; + +ClIndirectConvDefaultConfigValhall::ClIndirectConvDefaultConfigValhall(GPUTarget gpu) + : IClIndirectConvKernelConfig(gpu) +{ +} + +DirectConvComputeKernelInfo ClIndirectConvDefaultConfigValhall::configure(const ITensorInfo *src, const ITensorInfo *wei, const PadStrideInfo &conv_info) +{ + using ConfigurationFunctionExecutorPtr = DirectConvComputeKernelInfo (ClIndirectConvDefaultConfigValhall::*)(const ITensorInfo *src, const ITensorInfo *wei, const PadStrideInfo &conv_info); + + ClIndirectConvConfigArray configs_G77(&ClIndirectConvDefaultConfigValhall::configure_G77_f32, + &ClIndirectConvDefaultConfigValhall::configure_G77_f16); + + // Important note: Indirect convolution should not be used when the kernel size is 1x1 (pointwise). The reason is because the indirect buffer makes + // indirect convolution less efficient than direct convolution or gemm. For this reason, the heuristic of indirect convolution has not been tuned + // for the pointwise convolution cases. + + ConfigurationFunctionExecutorPtr func = configs_G77.get_function(src->data_type()); + + ARM_COMPUTE_ERROR_ON_MSG(func == nullptr, "Data type not supported for indirect convolution"); + return (this->*func)(src, wei, conv_info); +} + +DirectConvComputeKernelInfo ClIndirectConvDefaultConfigValhall::configure_G77_f32(const ITensorInfo *src, const ITensorInfo *wei, const PadStrideInfo &conv_info) +{ + DirectConvComputeKernelInfo desc; + + if(src->data_layout() == DataLayout::NHWC) + { + const TensorShape dst_shape = misc::shape_calculator::compute_deep_convolution_shape(*src, *wei, conv_info); + const bool export_weights_to_cl_image = export_to_cl_image(wei); + const int32_t stride_x = conv_info.stride().first; + const int32_t stride_y = conv_info.stride().second; + const int32_t ofm = dst_shape[0]; + const int32_t m = (dst_shape[1]/ stride_x) * (dst_shape[2] / stride_y); + + desc.export_weights_to_cl_image = export_weights_to_cl_image; + + if(ofm <= 4) + { + desc.m0 = 1; + desc.n0 = 2; + desc.k0 = 16; + } + else + { + // The 16000 threshold value has been identified as the right + // one for using the biggest block size allowed on F32: 5x4x4 + if(m < 16000) + { + desc.m0 = 4; + desc.n0 = 4; + desc.k0 = 4; + } + else + { + desc.m0 = 5; + desc.n0 = 4; + desc.k0 = 4; + } + } + } + + return desc; +} + +DirectConvComputeKernelInfo ClIndirectConvDefaultConfigValhall::configure_G77_f16(const ITensorInfo *src, const ITensorInfo *wei, const PadStrideInfo &conv_info) +{ + DirectConvComputeKernelInfo desc; + + if(src->data_layout() == DataLayout::NHWC) + { + const TensorShape wei_shape = wei->tensor_shape(); + const TensorShape dst_shape = misc::shape_calculator::compute_deep_convolution_shape(*src, *wei, conv_info); + const bool export_weights_to_cl_image = export_to_cl_image(wei); + + const int32_t ofm = dst_shape[0]; + const int32_t m = dst_shape[1] * dst_shape[2]; + const int32_t k = wei_shape[0]; + + desc.export_weights_to_cl_image = export_weights_to_cl_image; + + if(ofm <= 4) + { + // k0 should be as larger as possible. However, we should avoid + // having left-over for loops that make the implementation slower. + if((k % 16) == 0) + { + desc.k0 = 16; + } + else if((k % 8) == 0) + { + desc.k0 = 8; + } + else + { + desc.k0 = 4; + } + + desc.m0 = 1; + desc.n0 = ofm; + } + else + { + // The 16000 threshold value has been identified as the right + // one for using the biggest block size allowed on F16: 8x4 + if(m >= 16000 && k < 4) + { + desc.m0 = 8; + desc.n0 = 4; + desc.k0 = 4; // k0 is clamped to k inside the kernel when k is less than 4 + } + else + { + desc.m0 = 5; + desc.n0 = 4; + desc.k0 = 8; + } + } + } + + return desc; +} +} // namespace opencl +} // namespace arm_compute diff --git a/src/runtime/heuristics/indirect_conv/ClIndirectConvDefaultConfigValhall.h b/src/runtime/heuristics/indirect_conv/ClIndirectConvDefaultConfigValhall.h new file mode 100644 index 0000000000..cd9a6a5c37 --- /dev/null +++ b/src/runtime/heuristics/indirect_conv/ClIndirectConvDefaultConfigValhall.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef SRC_RUNTIME_HEURISTICS_INDIRECT_CONV_CLINDIRECTCONVDEFAULTCONFIGVALHALL +#define SRC_RUNTIME_HEURISTICS_INDIRECT_CONV_CLINDIRECTCONVDEFAULTCONFIGVALHALL + +#include "src/runtime/heuristics/indirect_conv/IClIndirectConvKernelConfig.h" + +namespace arm_compute +{ +namespace cl_indirect_conv +{ +/** Valhall based OpenCL indirect convolution configuration */ +class ClIndirectConvDefaultConfigValhall final : public IClIndirectConvKernelConfig +{ +public: + /** Constructor + * + * @param[in] gpu GPU target + */ + ClIndirectConvDefaultConfigValhall(GPUTarget gpu); + + // Inherited overridden method + DirectConvComputeKernelInfo configure(const ITensorInfo *src, const ITensorInfo *wei, const PadStrideInfo &conv_info) override; + +private: + DirectConvComputeKernelInfo configure_G77_f32(const ITensorInfo *src, const ITensorInfo *wei, const PadStrideInfo &conv_info); + DirectConvComputeKernelInfo configure_G77_f16(const ITensorInfo *src, const ITensorInfo *wei, const PadStrideInfo &conv_info); +}; +} // namespace opencl +} // namespace arm_compute +#endif /* SRC_RUNTIME_HEURISTICS_INDIRECT_CONV_CLINDIRECTCONVDEFAULTCONFIGVALHALL */ diff --git a/src/runtime/heuristics/indirect_conv/ClIndirectConvKernelConfig.h b/src/runtime/heuristics/indirect_conv/ClIndirectConvKernelConfig.h new file mode 100644 index 0000000000..13716efb5f --- /dev/null +++ b/src/runtime/heuristics/indirect_conv/ClIndirectConvKernelConfig.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef SRC_RUNTIME_HEURISTICS_INDIRECT_CONV_CLINDIRECTCONVKERNELCONFIG +#define SRC_RUNTIME_HEURISTICS_INDIRECT_CONV_CLINDIRECTCONVKERNELCONFIG + +#include "src/runtime/heuristics/indirect_conv/ClIndirectConvDefaultConfigValhall.h" +#include "src/runtime/heuristics/indirect_conv/IClIndirectConvKernelConfig.h" + +#include + +namespace arm_compute +{ +namespace cl_indirect_conv +{ +/** ClIndirectConvolution factory class */ +class ClIndirectConvKernelConfigurationFactory final +{ +public: + /** Static method to call the ClIndirectConvolution kernel configuration class accordingly with the GPU target + * + * @param[in] gpu GPU target + * + * @return IClIndirectConvKernelConfig + */ + static std::unique_ptr create(GPUTarget gpu) + { + switch(get_arch_from_target(gpu)) + { + case GPUTarget::MIDGARD: + case GPUTarget::BIFROST: + case GPUTarget::VALHALL: + return std::make_unique(gpu); + default: + ARM_COMPUTE_ERROR("Not supported GPU target"); + } + } +}; +} // namespace opencl +} // namespace arm_compute +#endif /* SRC_RUNTIME_HEURISTICS_INDIRECT_CONV_CLINDIRECTCONVKERNELCONFIG */ diff --git a/src/runtime/heuristics/indirect_conv/IClIndirectConvKernelConfig.h b/src/runtime/heuristics/indirect_conv/IClIndirectConvKernelConfig.h new file mode 100644 index 0000000000..e722488c3b --- /dev/null +++ b/src/runtime/heuristics/indirect_conv/IClIndirectConvKernelConfig.h @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef SRC_RUNTIME_HEURISTICS_INDIRECT_CONV_ICLINDIRECTCONVKERNELCONFIG +#define SRC_RUNTIME_HEURISTICS_INDIRECT_CONV_ICLINDIRECTCONVKERNELCONFIG + +#include "arm_compute/core/GPUTarget.h" +#include "arm_compute/core/KernelDescriptors.h" +#include "arm_compute/core/Types.h" +#include "src/core/common/Macros.h" + +namespace arm_compute +{ +namespace cl_indirect_conv +{ +/** Basic container for the OpenCL indirect convolution configuration functions */ +template +class ClIndirectConvConfigArray +{ +public: + /** Alias for F32 index */ + static constexpr size_t DT_F32 = 0; + /** Alias for F16 index */ + static constexpr size_t DT_F16 = 1; + + /** Constructor + * + * @param[in] func_f32 Function to call for direct convolution F32 + * @param[in] func_f16 Function to call for direct convolution F16 + * + */ + ClIndirectConvConfigArray(T func_f32, T func_f16) + : _configs{ func_f32, func_f16} + { + } + + /** Method to return the indirect convolution configuration function based on data type + * + * @param[in] data_type Input data type + * + * @return the valid function otherwise it returns nullptr if the data type is not valid + */ + T get_function(DataType data_type) + { + switch(data_type) + { + case DataType::F32: + return _configs.at(DT_F32); + case DataType::F16: + return _configs.at(DT_F16); + default: + return nullptr; + } + } + +private: + std::array _configs; +}; + +/** Basic interface for the indirect convolution kernel configuration */ +class IClIndirectConvKernelConfig +{ +public: + /** Constructor + * + * @param[in] arch GPU target + */ + IClIndirectConvKernelConfig(GPUTarget arch) + : _target(arch) + { + } + ARM_COMPUTE_DISALLOW_COPY_ALLOW_MOVE(IClIndirectConvKernelConfig); + /** Virtual destructor */ + virtual ~IClIndirectConvKernelConfig() = default; + /** This method returns the @ref DirectConvComputeKernelInfo for the given inputs + * + * @param[in] src Source tensor (activation tensor) + * @param[in] wei Weights tensor + * @param[in] conv_info Convolution info + */ + virtual DirectConvComputeKernelInfo configure(const ITensorInfo *src, const ITensorInfo *wei, const PadStrideInfo &conv_info) = 0; + +protected: + GPUTarget _target; +}; +} // namespace opencl +} // namespace arm_compute +#endif /* SRC_RUNTIME_HEURISTICS_INDIRECT_CONV_ICLINDIRECTCONVKERNELCONFIG */ -- cgit v1.2.1