From 9aa153ae5d60fd08ec165280621f1e4fa7602048 Mon Sep 17 00:00:00 2001 From: Pablo Marquez Tello Date: Tue, 10 Oct 2023 12:18:48 +0100 Subject: Fix build error * Build error when using data_layout_support=nhwc * Some kernels need to be guarded by ENABLE_NCHW_KERNELS Change-Id: I9fb6cf0e204531f81b0dff3572a1740ba94cde0e Signed-off-by: Pablo Marquez Tello Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/10460 Reviewed-by: Viet-Hoa Do Comments-Addressed: Arm Jenkins Benchmark: Arm Jenkins Tested-by: Arm Jenkins --- src/cpu/kernels/pool2d/neon/fp16.cpp | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/cpu/kernels/pool2d/neon/fp16.cpp b/src/cpu/kernels/pool2d/neon/fp16.cpp index 95ff7b7d69..9d24d79afb 100644 --- a/src/cpu/kernels/pool2d/neon/fp16.cpp +++ b/src/cpu/kernels/pool2d/neon/fp16.cpp @@ -37,6 +37,8 @@ namespace arm_compute { namespace cpu { +#ifdef ENABLE_NCHW_KERNELS + namespace { float16x4_t @@ -148,6 +150,7 @@ void pooling3_fp16_neon_nchw(const ITensor *src, }, in, out); } +#endif // ENABLE_NCHW_KERNELS void pooling2_f16_maxpool_indices(const ITensor *src, ITensor *dst0, @@ -278,6 +281,7 @@ void pooling2_f16_maxpool_indices(const ITensor *src, }, in, out, indices); } +#ifdef ENABLE_NCHW_KERNELS void pooling2_fp16_neon_nchw(const ITensor *src, ITensor *dst0, @@ -461,6 +465,7 @@ void poolingMxN_fp16_neon_nchw(const ITensor *src, }, in, out); } +#endif // ENABLE_NCHW_KERNELS void poolingMxN_fp16_neon_nhwc(const ITensor *src, ITensor *dst0, -- cgit v1.2.1