From 7191aaa184992ca1fa8bdbbe5a9d8f9cd093ad5b Mon Sep 17 00:00:00 2001
From: Georgios Pinitas <georgios.pinitas@arm.com>
Date: Wed, 3 Apr 2019 17:01:26 +0100
Subject: COMPMID-2101: DenseNet issue on NHWC

Workaround data layout issue for WinogradOutputTransform.

Change-Id: If9ced178eccbb36d959862da09339ba5c52b0f6d
Signed-off-by: Georgios Pinitas <georgios.pinitas@arm.com>
Reviewed-on: https://review.mlplatform.org/c/943
Reviewed-by: Pablo Marquez <pablo.tello@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
---
 .../core/CL/kernels/CLWinogradOutputTransformKernel.h       |  3 ++-
 src/core/CL/kernels/CLWinogradOutputTransformKernel.cpp     | 13 +++++++------
 2 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/arm_compute/core/CL/kernels/CLWinogradOutputTransformKernel.h b/arm_compute/core/CL/kernels/CLWinogradOutputTransformKernel.h
index bdb230d645..2bcd292ac7 100644
--- a/arm_compute/core/CL/kernels/CLWinogradOutputTransformKernel.h
+++ b/arm_compute/core/CL/kernels/CLWinogradOutputTransformKernel.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018 ARM Limited.
+ * Copyright (c) 2018-2019 ARM Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -99,6 +99,7 @@ private:
     const ICLTensor *_input;
     const ICLTensor *_bias;
     ICLTensor       *_output;
+    bool             _is_nhwc;
 };
 } // namespace arm_compute
 #endif /*__ARM_COMPUTE_CLWINOGRADOUTPUTTRANSFORMKERNEL_H__ */
diff --git a/src/core/CL/kernels/CLWinogradOutputTransformKernel.cpp b/src/core/CL/kernels/CLWinogradOutputTransformKernel.cpp
index 84b5ea23f1..bf3a00d199 100644
--- a/src/core/CL/kernels/CLWinogradOutputTransformKernel.cpp
+++ b/src/core/CL/kernels/CLWinogradOutputTransformKernel.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018 ARM Limited.
+ * Copyright (c) 2018-2019 ARM Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -139,7 +139,7 @@ std::pair<Status, Window> validate_and_configure_window(ITensorInfo *input, ITen
 } // namespace
 
 CLWinogradOutputTransformKernel::CLWinogradOutputTransformKernel()
-    : _input(nullptr), _bias(nullptr), _output(nullptr)
+    : _input(nullptr), _bias(nullptr), _output(nullptr), _is_nhwc(false)
 {
 }
 
@@ -152,9 +152,10 @@ void CLWinogradOutputTransformKernel::configure(const ICLTensor *input, const IC
 
     ARM_COMPUTE_ERROR_THROW_ON(validate_arguments(input->info(), (bias != nullptr ? bias->info() : nullptr), output->info(), winograd_info, act_info));
 
-    _input  = input;
-    _bias   = bias;
-    _output = output;
+    _input   = input;
+    _bias    = bias;
+    _output  = output;
+    _is_nhwc = winograd_info.output_data_layout == DataLayout::NHWC;
 
     // Compute num_tiles_x
     const Size2D        input_dimensions = winograd_info.input_dimensions;
@@ -253,7 +254,7 @@ void CLWinogradOutputTransformKernel::run(const Window &window, cl::CommandQueue
         add_1D_tensor_argument(idx1, _bias, slice_biases);
     }
 
-    if(_output->info()->data_layout() == DataLayout::NHWC)
+    if(_is_nhwc)
     {
         unsigned int idx2 = 2 * num_arguments_per_4D_tensor() + ((_bias != nullptr) ? num_arguments_per_1D_tensor() : 0);
         _kernel.setArg(idx2, static_cast<int>(_output->info()->total_size() - _output->info()->strides_in_bytes().y()));
-- 
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