From 5801a5508aecc91df7d669f086d6977d70059c65 Mon Sep 17 00:00:00 2001 From: George Wort Date: Thu, 13 Dec 2018 17:50:26 +0000 Subject: COMPMID-1767: NEON: Implement Where/Select Change-Id: If8a1ab6d6a029a5c547b726e0692eecef9a2e97d Reviewed-on: https://review.mlplatform.org/415 Tested-by: Arm Jenkins Reviewed-by: Georgios Pinitas --- arm_compute/core/NEON/NEKernels.h | 1 + arm_compute/core/NEON/kernels/NESelectKernel.h | 102 ++++++++ .../core/NEON/wrapper/intrinsics/bitselect.h | 64 +++++ .../core/NEON/wrapper/intrinsics/greaterthan.h | 64 +++++ .../core/NEON/wrapper/intrinsics/intrinsics.h | 2 + arm_compute/runtime/NEON/NEFunctions.h | 1 + arm_compute/runtime/NEON/functions/NESelect.h | 59 +++++ src/core/NEON/kernels/NESelectKernel.cpp | 264 +++++++++++++++++++++ src/runtime/NEON/functions/NESelect.cpp | 44 ++++ tests/validation/NEON/Select.cpp | 188 +++++++++++++++ 10 files changed, 789 insertions(+) create mode 100644 arm_compute/core/NEON/kernels/NESelectKernel.h create mode 100644 arm_compute/core/NEON/wrapper/intrinsics/bitselect.h create mode 100644 arm_compute/core/NEON/wrapper/intrinsics/greaterthan.h create mode 100644 arm_compute/runtime/NEON/functions/NESelect.h create mode 100644 src/core/NEON/kernels/NESelectKernel.cpp create mode 100644 src/runtime/NEON/functions/NESelect.cpp create mode 100644 tests/validation/NEON/Select.cpp diff --git a/arm_compute/core/NEON/NEKernels.h b/arm_compute/core/NEON/NEKernels.h index 57a1d4d52c..e859519d94 100644 --- a/arm_compute/core/NEON/NEKernels.h +++ b/arm_compute/core/NEON/NEKernels.h @@ -110,6 +110,7 @@ #include "arm_compute/core/NEON/kernels/NEReshapeLayerKernel.h" #include "arm_compute/core/NEON/kernels/NEScaleKernel.h" #include "arm_compute/core/NEON/kernels/NEScharr3x3Kernel.h" +#include "arm_compute/core/NEON/kernels/NESelectKernel.h" #include "arm_compute/core/NEON/kernels/NESobel3x3Kernel.h" #include "arm_compute/core/NEON/kernels/NESobel5x5Kernel.h" #include "arm_compute/core/NEON/kernels/NESobel7x7Kernel.h" diff --git a/arm_compute/core/NEON/kernels/NESelectKernel.h b/arm_compute/core/NEON/kernels/NESelectKernel.h new file mode 100644 index 0000000000..215dc2f5ee --- /dev/null +++ b/arm_compute/core/NEON/kernels/NESelectKernel.h @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2018 ARM Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INNEUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY NEAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef __ARM_COMPUTE_NESELECTKERNEL_H__ +#define __ARM_COMPUTE_NESELECTKERNEL_H__ + +#include "arm_compute/core/NEON/INEKernel.h" +#include "arm_compute/core/Types.h" + +namespace arm_compute +{ +class ITensor; + +/** Interface for the select kernel + * + * Select is computed by: + * @f[ output(i) = condition(i) ? x(i) : y(i) @f] + * + */ +class NESelectKernel : public INEKernel +{ +public: + const char *name() const override + { + return "NESelectKernel"; + } + /** Default constructor */ + NESelectKernel(); + /** Prevent instances of this class from being copied (As this class contains pointers) */ + NESelectKernel(const NESelectKernel &) = delete; + /** Prevent instances of this class from being copied (As this class contains pointers) */ + NESelectKernel &operator=(const NESelectKernel &) = delete; + /** Allow instances of this class to be moved */ + NESelectKernel(NESelectKernel &&) = default; + /** Allow instances of this class to be moved */ + NESelectKernel &operator=(NESelectKernel &&) = default; + /** Default destructor */ + ~NESelectKernel() = default; + + /** Common signature for all the specialised elementwise functions + * + * @param[in] c Condition input tensor. Data types supported: U8. + * @param[in] x First input tensor. Data types supported: U8/S8/U16/S16/U32/S32/F16/F32. + * @param[out] y Second input tensor. Data types supported: Same as @p x + * @param[in] output Output tensor. Data types supported: Same as @p x + */ + void configure(const ITensor *c, const ITensor *x, const ITensor *y, ITensor *output); + + /** Validate the argument passed to the kernel + * + * @param[in] c Condition input tensor. Data types supported: U8. + * @param[in] x First input tensor. Data types supported: U8/S8/U16/S16/U32/S32/F16/F32. + * @param[in] y Second input tensor. Data types supported: Same as @p x + * @param[in] output Output tensor. Data types supported: Same as @p x. + * + * @return a status + */ + static Status validate(const ITensorInfo *c, const ITensorInfo *x, const ITensorInfo *y, const ITensorInfo *output); + + // Inherited methods overridden: + void run(const Window &window, const ThreadInfo &info) override; + +private: + /** Common signature for all the specialised select functions + * + * @param[in] c Condition input tensor. Data types supported: U8. + * @param[in] x First input tensor. Data types supported: U8/S8/U16/S16/U32/S32/F16/F32. + * @param[in] y Second input tensor. Data types supported: Same as @p x + * @param[in] output Output tensor. Data types supported: Same as @p x. + */ + using SelectFunction = void(const ITensor *c, const ITensor *x, const ITensor *y, ITensor *output, const Window &window); + + /** Select function to use for the particular tensor types passed to configure() */ + SelectFunction *_function; + const ITensor *_c; /**< Condition tensor */ + const ITensor *_x; /**< Source tensor 1 */ + const ITensor *_y; /**< Source tensor 2 */ + ITensor *_output; /**< Destination tensor */ + bool _has_same_rank; /**< Flag that indicates if condition tensor and other inputs have the same rank */ +}; +} // namespace arm_compute +#endif /* __ARM_COMPUTE_NESELECTKERNEL_H__ */ diff --git a/arm_compute/core/NEON/wrapper/intrinsics/bitselect.h b/arm_compute/core/NEON/wrapper/intrinsics/bitselect.h new file mode 100644 index 0000000000..8223f6d463 --- /dev/null +++ b/arm_compute/core/NEON/wrapper/intrinsics/bitselect.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2018 ARM Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT SELECT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef __ARM_COMPUTE_WRAPPER_BITSELECT_H__ +#define __ARM_COMPUTE_WRAPPER_BITSELECT_H__ + +#include + +namespace arm_compute +{ +namespace wrapper +{ +#define VBITSELECT_IMPL(stype, vtype, ctype, prefix, postfix) \ + inline vtype vbitselect(const ctype &a, const vtype &b, const vtype &c) \ + { \ + return prefix##_##postfix(a, b, c); \ + } + +VBITSELECT_IMPL(uint8_t, uint8x8_t, uint8x8_t, vbsl, u8) +VBITSELECT_IMPL(int8_t, int8x8_t, uint8x8_t, vbsl, s8) +VBITSELECT_IMPL(uint16_t, uint16x4_t, uint16x4_t, vbsl, u16) +VBITSELECT_IMPL(int16_t, int16x4_t, uint16x4_t, vbsl, s16) +VBITSELECT_IMPL(uint32_t, uint32x2_t, uint32x2_t, vbsl, u32) +VBITSELECT_IMPL(int32_t, int32x2_t, uint32x2_t, vbsl, s32) +VBITSELECT_IMPL(float32x2_t, float32x2_t, uint32x2_t, vbsl, f32) +#ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC +VBITSELECT_IMPL(float16x4_t, float16x4_t, uint16x4_t, vbsl, f16) +#endif // __ARM_FEATURE_FP16_VECTOR_ARITHMETIC + +VBITSELECT_IMPL(uint8_t, uint8x16_t, uint8x16_t, vbslq, u8) +VBITSELECT_IMPL(int8_t, int8x16_t, uint8x16_t, vbslq, s8) +VBITSELECT_IMPL(uint16_t, uint16x8_t, uint16x8_t, vbslq, u16) +VBITSELECT_IMPL(int16_t, int16x8_t, uint16x8_t, vbslq, s16) +VBITSELECT_IMPL(uint32_t, uint32x4_t, uint32x4_t, vbslq, u32) +VBITSELECT_IMPL(int32_t, int32x4_t, uint32x4_t, vbslq, s32) +VBITSELECT_IMPL(float32x4_t, float32x4_t, uint32x4_t, vbslq, f32) +#ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC +VBITSELECT_IMPL(float16x8_t, float16x8_t, uint16x8_t, vbslq, f16) +#endif // __ARM_FEATURE_FP16_VECTOR_ARITHMETIC + +#undef VBITSELECT_IMPL +} // namespace wrapper +} // namespace arm_compute +#endif /* __ARM_COMPUTE_WRAPPER_BITSELECT_H__ */ diff --git a/arm_compute/core/NEON/wrapper/intrinsics/greaterthan.h b/arm_compute/core/NEON/wrapper/intrinsics/greaterthan.h new file mode 100644 index 0000000000..5ee7516a4e --- /dev/null +++ b/arm_compute/core/NEON/wrapper/intrinsics/greaterthan.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2018 ARM Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef __ARM_COMPUTE_WRAPPER_CGT_H__ +#define __ARM_COMPUTE_WRAPPER_CGT_H__ + +#include + +namespace arm_compute +{ +namespace wrapper +{ +#define VCGT_IMPL(stype, vtype, rtype, prefix, postfix) \ + inline rtype vgreaterthan(const vtype &a, const vtype &b) \ + { \ + return prefix##_##postfix(a, b); \ + } + +VCGT_IMPL(uint8_t, uint8x8_t, uint8x8_t, vcgt, u8) +VCGT_IMPL(int8_t, int8x8_t, uint8x8_t, vcgt, s8) +VCGT_IMPL(uint16_t, uint16x4_t, uint16x4_t, vcgt, u16) +VCGT_IMPL(int16_t, int16x4_t, uint16x4_t, vcgt, s16) +VCGT_IMPL(uint32_t, uint32x2_t, uint32x2_t, vcgt, u32) +VCGT_IMPL(int32_t, int32x2_t, uint32x2_t, vcgt, s32) +VCGT_IMPL(float32x2_t, float32x2_t, uint32x2_t, vcgt, f32) +#ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC +VCGT_IMPL(float16x4_t, float16x4_t, uint16x4_t, vcgt, f16) +#endif // __ARM_FEATURE_FP16_VECTOR_ARITHMETIC + +VCGT_IMPL(uint8_t, uint8x16_t, uint8x16_t, vcgtq, u8) +VCGT_IMPL(int8_t, int8x16_t, uint8x16_t, vcgtq, s8) +VCGT_IMPL(uint16_t, uint16x8_t, uint16x8_t, vcgtq, u16) +VCGT_IMPL(int16_t, int16x8_t, uint16x8_t, vcgtq, s16) +VCGT_IMPL(uint32_t, uint32x4_t, uint32x4_t, vcgtq, u32) +VCGT_IMPL(int32_t, int32x4_t, uint32x4_t, vcgtq, s32) +VCGT_IMPL(float32x4_t, float32x4_t, uint32x4_t, vcgtq, f32) +#ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC +VCGT_IMPL(float16x8_t, float16x8_t, uint16x8_t, vcgtq, f16) +#endif // __ARM_FEATURE_FP16_VECTOR_ARITHMETIC + +#undef VCGT_IMPL +} // namespace wrapper +} // namespace arm_compute +#endif /* __ARM_COMPUTE_WRAPPER_CGT_H__ */ diff --git a/arm_compute/core/NEON/wrapper/intrinsics/intrinsics.h b/arm_compute/core/NEON/wrapper/intrinsics/intrinsics.h index 46c8937adc..f65ce85021 100644 --- a/arm_compute/core/NEON/wrapper/intrinsics/intrinsics.h +++ b/arm_compute/core/NEON/wrapper/intrinsics/intrinsics.h @@ -26,11 +26,13 @@ #include "arm_compute/core/NEON/wrapper/intrinsics/add.h" #include "arm_compute/core/NEON/wrapper/intrinsics/and.h" +#include "arm_compute/core/NEON/wrapper/intrinsics/bitselect.h" #include "arm_compute/core/NEON/wrapper/intrinsics/dup_n.h" #include "arm_compute/core/NEON/wrapper/intrinsics/exp.h" #include "arm_compute/core/NEON/wrapper/intrinsics/gethigh.h" #include "arm_compute/core/NEON/wrapper/intrinsics/getlane.h" #include "arm_compute/core/NEON/wrapper/intrinsics/getlow.h" +#include "arm_compute/core/NEON/wrapper/intrinsics/greaterthan.h" #include "arm_compute/core/NEON/wrapper/intrinsics/inv.h" #include "arm_compute/core/NEON/wrapper/intrinsics/invsqrt.h" #include "arm_compute/core/NEON/wrapper/intrinsics/load.h" diff --git a/arm_compute/runtime/NEON/NEFunctions.h b/arm_compute/runtime/NEON/NEFunctions.h index 2ffd92d541..bfecbcf65e 100644 --- a/arm_compute/runtime/NEON/NEFunctions.h +++ b/arm_compute/runtime/NEON/NEFunctions.h @@ -112,6 +112,7 @@ #include "arm_compute/runtime/NEON/functions/NEReshapeLayer.h" #include "arm_compute/runtime/NEON/functions/NEScale.h" #include "arm_compute/runtime/NEON/functions/NEScharr3x3.h" +#include "arm_compute/runtime/NEON/functions/NESelect.h" #include "arm_compute/runtime/NEON/functions/NESimpleAssemblyFunction.h" #include "arm_compute/runtime/NEON/functions/NESobel3x3.h" #include "arm_compute/runtime/NEON/functions/NESobel5x5.h" diff --git a/arm_compute/runtime/NEON/functions/NESelect.h b/arm_compute/runtime/NEON/functions/NESelect.h new file mode 100644 index 0000000000..1529cd6963 --- /dev/null +++ b/arm_compute/runtime/NEON/functions/NESelect.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2018 ARM Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef __ARM_COMPUTE_NESELECT_H__ +#define __ARM_COMPUTE_NESELECT_H__ + +#include "arm_compute/core/Types.h" +#include "arm_compute/runtime/NEON/INESimpleFunction.h" + +namespace arm_compute +{ +// Forward declarations +class ITensor; + +/** Basic function to run @ref NESelect */ +class NESelect : public INESimpleFunction +{ +public: + /** Initialise the kernel's inputs and output. + * + * @param[in] c Condition input tensor. Data types supported: U8. + * @param[in] x First input tensor. Data types supported: U8/S8/QASYMM8/U16/S16/U32/S32/F16/F32. + * @param[in] y Second input tensor. Data types supported: Same as @p x + * @param[out] output Output tensor. Data types supported: Same as @p x. + */ + void configure(const ITensor *c, const ITensor *x, const ITensor *y, ITensor *output); + /** Static function to check if given info will lead to a valid configuration of @ref NESelect + * + * @param[in] c Condition input tensor. Data types supported: U8. + * @param[in] x First input tensor. Data types supported: U8/S8/QASYMM8/U16/S16/U32/S32/F16/F32. + * @param[in] y Second input tensor. Data types supported: Same as @p x + * @param[in] output Output tensor. Data types supported: Same as @p x. + * + * @return a status + */ + static Status validate(const ITensorInfo *c, const ITensorInfo *x, const ITensorInfo *y, const ITensorInfo *output); +}; +} // namespace arm_compute +#endif /* __ARM_COMPUTE_NESELECT_H__ */ diff --git a/src/core/NEON/kernels/NESelectKernel.cpp b/src/core/NEON/kernels/NESelectKernel.cpp new file mode 100644 index 0000000000..0c134c00ed --- /dev/null +++ b/src/core/NEON/kernels/NESelectKernel.cpp @@ -0,0 +1,264 @@ +/* + * Copyright (c) 2018 ARM Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INNEUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY NEAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#include "arm_compute/core/NEON/kernels/NESelectKernel.h" + +#include "arm_compute/core/CPP/Validate.h" +#include "arm_compute/core/Error.h" +#include "arm_compute/core/Helpers.h" +#include "arm_compute/core/IAccessWindow.h" +#include "arm_compute/core/ITensor.h" +#include "arm_compute/core/NEON/wrapper/wrapper.h" +#include "arm_compute/core/TensorInfo.h" +#include "arm_compute/core/Types.h" +#include "arm_compute/core/Validate.h" +#include "utils/TypePrinter.h" + +#include +#include +#include + +namespace arm_compute +{ +namespace +{ +template +void select_op(const ITensor *cond, const ITensor *in1, const ITensor *in2, ITensor *out, const Window &window, + const int window_step_x, const int window_start_x, const int window_end_x, const int limit, VectorType (*condition_conversion)(const uint8_t *)) +{ + Window win = window; + win.set(Window::DimX, Window::Dimension(0, 1, 1)); + + Iterator condition(cond, win); + Iterator input1(in1, win); + Iterator input2(in2, win); + Iterator output(out, win); + + execute_window_loop(win, [&](const Coordinates & id) + { + auto output_ptr = reinterpret_cast(output.ptr()); + const auto condition_ptr = reinterpret_cast(condition.ptr()); + const auto input1_ptr = reinterpret_cast(input1.ptr()); + const auto input2_ptr = reinterpret_cast(input2.ptr()); + + int x = window_start_x; + for(; x <= limit; x += window_step_x) + { + const auto c = (*condition_conversion)(condition_ptr + x); + const auto a = wrapper::vloadq(input1_ptr + x); + const auto b = wrapper::vloadq(input2_ptr + x); + wrapper::vstore(output_ptr + x, wrapper::vbitselect(c, a, b)); + } + for(; x < window_end_x; ++x) + { + const auto c = *(condition_ptr + x); + const auto a = *(input1_ptr + x); + const auto b = *(input2_ptr + x); + *(output_ptr + x) = static_cast(c) ? a : b; + } + }, + condition, input1, input2, output); +} + +template +void select_op_8(const ITensor *cond, const ITensor *in1, const ITensor *in2, ITensor *out, const Window &window) +{ + const auto window_step_x = 16 / sizeof(ScalarType); + const auto window_start_x = static_cast(window.x().start()); + const auto window_end_x = static_cast(window.x().end()); + + select_op(cond, in1, in2, out, window, window_step_x, window_start_x, window_end_x, window_end_x - window_step_x, [](const uint8_t *condition_ptr) + { + static const auto zero = wrapper::vdup_n(static_cast(0), arm_compute::wrapper::traits::vector_128_tag()); + return wrapper::vgreaterthan(wrapper::vloadq(condition_ptr), zero); + }); +} + +template +void select_op_16(const ITensor *cond, const ITensor *in1, const ITensor *in2, ITensor *out, const Window &window) +{ + const auto window_step_x = 16 / sizeof(ScalarType); + const auto window_start_x = static_cast(window.x().start()); + const auto window_end_x = static_cast(window.x().end()); + + select_op(cond, in1, in2, out, window, window_step_x, window_start_x, window_end_x, window_end_x - window_step_x, [](const uint8_t *condition_ptr) + { + static const auto zero = wrapper::vdup_n(static_cast(0), arm_compute::wrapper::traits::vector_128_tag()); + return wrapper::vgreaterthan(wrapper::vmovl(wrapper::vload(condition_ptr)), zero); + }); +} + +template +void select_op_32(const ITensor *cond, const ITensor *in1, const ITensor *in2, ITensor *out, const Window &window) +{ + const auto window_step_x = 16 / sizeof(ScalarType); + const auto window_start_x = static_cast(window.x().start()); + const auto window_end_x = static_cast(window.x().end()); + + select_op(cond, in1, in2, out, window, window_step_x, window_start_x, window_end_x, window_end_x - window_step_x, [](const uint8_t *condition_ptr) + { + static const auto zero = wrapper::vdup_n(static_cast(0), arm_compute::wrapper::traits::vector_128_tag()); + return wrapper::vgreaterthan(wrapper::vmovl(wrapper::vgetlow(wrapper::vmovl(wrapper::vload(condition_ptr)))), zero); + }); +} + +template +void select_op_not_same_rank(const ITensor *cond, const ITensor *in1, const ITensor *in2, ITensor *out, const Window &window) +{ + ARM_COMPUTE_UNUSED(window); + + auto output_ptr = reinterpret_cast(out->buffer()); + const auto condition_ptr = reinterpret_cast(cond->buffer()); + const auto input1_ptr = reinterpret_cast(in1->buffer()); + const auto input2_ptr = reinterpret_cast(in2->buffer()); + + const int outer_size = cond->info()->total_size() / cond->info()->element_size(); + const int inner_size = (in1->info()->total_size() / in1->info()->element_size()) / outer_size; + int offset = 0; + const int step = 16 / in1->info()->element_size(); + + for(int i = 0; i < outer_size; ++i) + { + int x = offset; + const auto input_ptr = static_cast(*(condition_ptr + i)) ? input1_ptr : input2_ptr; + for(; x <= offset + inner_size - step; x += step) + { + wrapper::vstore(output_ptr + x, wrapper::vloadq(input_ptr + x)); + } + if(x <= offset + inner_size - (step / 2)) + { + wrapper::vstore(output_ptr + x, wrapper::vload(input_ptr + x)); + x += step / 2; + } + for(; x < offset + inner_size; ++x) + { + *(output_ptr + x) = *(input_ptr + x); + } + offset += inner_size; + } +} +} // namespace + +NESelectKernel::NESelectKernel() + : _function(nullptr), _c(nullptr), _x(nullptr), _y(nullptr), _output(nullptr), _has_same_rank(false) +{ +} + +void NESelectKernel::configure(const ITensor *c, const ITensor *x, const ITensor *y, ITensor *output) +{ + ARM_COMPUTE_ERROR_ON_NULLPTR(c, x, y, output); + + // Auto initialize output if not initialized + auto_init_if_empty(*output->info(), x->info()->tensor_shape(), 1, x->info()->data_type()); + ARM_COMPUTE_ERROR_THROW_ON(validate(c->info(), x->info(), y->info(), output->info())); + + _c = c; + _x = x; + _y = y; + _output = output; + _has_same_rank = (c->info()->tensor_shape().num_dimensions() == x->info()->tensor_shape().num_dimensions()); + + std::string function_to_call("op_"); + function_to_call += string_from_data_type(x->info()->data_type()); + + static std::map map_function; + + if(_has_same_rank) + { + map_function = + { + { "op_S8", &select_op_8 }, + { "op_S16", &select_op_16 }, + { "op_S32", &select_op_32 }, + { "op_U8", &select_op_8 }, + { "op_U16", &select_op_16 }, + { "op_U32", &select_op_32 }, + { "op_F32", &select_op_32 } + }; +#ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC + map_function["op_F16"] = &select_op_16; +#endif /* ARM_COMPUTE_AARCH64_V8_2 */ + } + else + { + map_function = + { + { "op_S8", &select_op_not_same_rank }, + { "op_S16", &select_op_not_same_rank }, + { "op_S32", &select_op_not_same_rank }, + { "op_U8", &select_op_not_same_rank }, + { "op_U16", &select_op_not_same_rank }, + { "op_U32", &select_op_not_same_rank }, + { "op_F32", &select_op_not_same_rank } + }; +#ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC + map_function["op_F16"] = &select_op_not_same_rank; +#endif /* ARM_COMPUTE_AARCH64_V8_2 */ + } + + auto it = map_function.find(function_to_call); + + if(it != map_function.end()) + { + _function = it->second; + } + + Window win = calculate_max_window(x->info()->valid_region()); + INEKernel::configure(win); +} + +Status NESelectKernel::validate(const ITensorInfo *c, const ITensorInfo *x, const ITensorInfo *y, const ITensorInfo *output) +{ + ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(x); + ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(x, + 1, + DataType::U8, DataType::S8, + DataType::U16, DataType::S16, + DataType::U32, DataType::S32, + DataType::F16, DataType::F32); + ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_SHAPES(x, y); + ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(x, y); + ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(c, 1, DataType::U8); + + const bool is_same_rank = (c->tensor_shape().num_dimensions() == x->tensor_shape().num_dimensions()); + ARM_COMPUTE_RETURN_ERROR_ON(is_same_rank && (x->tensor_shape() != c->tensor_shape())); + ARM_COMPUTE_RETURN_ERROR_ON(!is_same_rank && ((c->tensor_shape().num_dimensions() > 1) || (c->tensor_shape().x() != x->tensor_shape()[x->tensor_shape().num_dimensions() - 1]))); + + if(output != nullptr && output->total_size() != 0) + { + ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_SHAPES(x, output); + ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(x, output); + } + + return Status{}; +} + +void NESelectKernel::run(const Window &window, const ThreadInfo &info) +{ + ARM_COMPUTE_UNUSED(info); + ARM_COMPUTE_ERROR_ON_UNCONFIGURED_KERNEL(this); + ARM_COMPUTE_ERROR_ON_INVALID_SUBWINDOW(INEKernel::window(), window); + ARM_COMPUTE_ERROR_ON(_function == nullptr); + _function(_c, _x, _y, _output, window); +} +} // namespace arm_compute diff --git a/src/runtime/NEON/functions/NESelect.cpp b/src/runtime/NEON/functions/NESelect.cpp new file mode 100644 index 0000000000..509bbaa24e --- /dev/null +++ b/src/runtime/NEON/functions/NESelect.cpp @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2018 ARM Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#include "arm_compute/runtime/NEON/functions/NESelect.h" + +#include "arm_compute/core/NEON/kernels/NESelectKernel.h" +#include "arm_compute/core/Types.h" + +using namespace arm_compute; + +namespace arm_compute +{ +void NESelect::configure(const ITensor *c, const ITensor *x, const ITensor *y, ITensor *output) +{ + auto k = arm_compute::support::cpp14::make_unique(); + k->configure(c, x, y, output); + _kernel = std::move(k); +} + +Status NESelect::validate(const ITensorInfo *c, const ITensorInfo *x, const ITensorInfo *y, const ITensorInfo *output) +{ + return NESelectKernel::validate(c, x, y, output); +} +} // namespace arm_compute diff --git a/tests/validation/NEON/Select.cpp b/tests/validation/NEON/Select.cpp new file mode 100644 index 0000000000..9ac7a6f013 --- /dev/null +++ b/tests/validation/NEON/Select.cpp @@ -0,0 +1,188 @@ +/* + * Copyright (c) 2018 ARM Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONCLCTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#include "arm_compute/core/Types.h" +#include "arm_compute/runtime/NEON/functions/NESelect.h" +#include "arm_compute/runtime/Tensor.h" +#include "arm_compute/runtime/TensorAllocator.h" +#include "tests/NEON/Accessor.h" +#include "tests/datasets/ShapeDatasets.h" +#include "tests/framework/Asserts.h" +#include "tests/framework/Macros.h" +#include "tests/framework/datasets/Datasets.h" +#include "tests/validation/Validation.h" +#include "tests/validation/fixtures/SelectFixture.h" + +namespace arm_compute +{ +namespace test +{ +namespace validation +{ +namespace +{ +auto configuration_dataset = combine(framework::dataset::concat(datasets::SmallShapes(), datasets::LargeShapes()), + framework::dataset::make("has_same_rank", { false, true })); +auto run_small_dataset = combine(datasets::SmallShapes(), framework::dataset::make("has_same_rank", { false, true })); +auto run_large_dataset = combine(datasets::LargeShapes(), framework::dataset::make("has_same_rank", { false, true })); +} // namespace + +TEST_SUITE(NEON) +TEST_SUITE(Select) + +// *INDENT-OFF* +// clang-format off +DATA_TEST_CASE(Validate, framework::DatasetMode::ALL, zip(zip(zip(zip( + framework::dataset::make("CInfo", { TensorInfo(TensorShape(32U, 13U, 2U), 1, DataType::S8), // Invalid condition datatype + TensorInfo(TensorShape(32U, 13U, 2U), 1, DataType::U8), // Invalid output datatype + TensorInfo(TensorShape(13U), 1, DataType::U8), // Invalid c shape + TensorInfo(TensorShape(32U, 13U, 2U), 1, DataType::U8), // Mismatching shapes + TensorInfo(TensorShape(32U, 13U, 2U), 1, DataType::U8), + TensorInfo(TensorShape(2U), 1, DataType::U8), + }), + framework::dataset::make("XInfo",{ TensorInfo(TensorShape(32U, 13U, 2U), 1, DataType::U8), + TensorInfo(TensorShape(32U, 13U, 2U), 1, DataType::U8), + TensorInfo(TensorShape(32U, 13U, 2U), 1, DataType::U8), + TensorInfo(TensorShape(32U, 10U, 2U), 1, DataType::F32), + TensorInfo(TensorShape(32U, 13U, 2U), 1, DataType::F32), + TensorInfo(TensorShape(32U, 13U, 2U), 1, DataType::F32), + })), + framework::dataset::make("YInfo",{ TensorInfo(TensorShape(32U, 13U, 2U), 1, DataType::U8), + TensorInfo(TensorShape(32U, 13U, 2U), 1, DataType::U8), + TensorInfo(TensorShape(32U, 13U, 2U), 1, DataType::U8), + TensorInfo(TensorShape(32U, 13U, 2U), 1, DataType::F32), + TensorInfo(TensorShape(32U, 13U, 2U), 1, DataType::F32), + TensorInfo(TensorShape(32U, 13U, 2U), 1, DataType::F32), + })), + framework::dataset::make("OutputInfo",{ TensorInfo(TensorShape(32U, 13U, 2U), 1, DataType::U8), + TensorInfo(TensorShape(32U, 13U, 2U), 1, DataType::S8), + TensorInfo(TensorShape(32U, 13U, 2U), 1, DataType::U8), + TensorInfo(TensorShape(32U, 13U, 2U), 1, DataType::F32), + TensorInfo(TensorShape(32U, 13U, 2U), 1, DataType::F32), + TensorInfo(TensorShape(32U, 13U, 2U), 1, DataType::F32), + })), + framework::dataset::make("Expected", { false, false, false, false, true, true})), + c_info, x_info, y_info, output_info, expected) +{ + Status s = NESelect::validate(&c_info.clone()->set_is_resizable(false), + &x_info.clone()->set_is_resizable(false), + &y_info.clone()->set_is_resizable(false), + &output_info.clone()->set_is_resizable(false)); + ARM_COMPUTE_EXPECT(bool(s) == expected, framework::LogLevel::ERRORS); +} +// clang-format on +// *INDENT-ON* + +template +using NESelectFixture = SelectValidationFixture; + +TEST_SUITE(Float) + +#ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC +TEST_SUITE(F16) +DATA_TEST_CASE(Configuration, framework::DatasetMode::ALL, configuration_dataset, + shape, same_rank) +{ + const DataType dt = DataType::F16; + + // Create tensors + Tensor ref_c = create_tensor(detail::select_condition_shape(shape, same_rank), DataType::U8); + Tensor ref_x = create_tensor(shape, dt); + Tensor ref_y = create_tensor(shape, dt); + Tensor dst = create_tensor(shape, dt); + + // Create and Configure function + NESelect select; + select.configure(&ref_c, &ref_x, &ref_y, &dst); + + // Validate valid region + const ValidRegion valid_region = shape_to_valid_region(shape); + validate(dst.info()->valid_region(), valid_region); +} + +FIXTURE_DATA_TEST_CASE(RunSmall, + NESelectFixture, + framework::DatasetMode::PRECOMMIT, + combine(run_small_dataset, framework::dataset::make("DataType", DataType::F16))) +{ + // Validate output + validate(Accessor(_target), _reference); +} + +FIXTURE_DATA_TEST_CASE(RunLarge, + NESelectFixture, + framework::DatasetMode::NIGHTLY, + combine(run_large_dataset, framework::dataset::make("DataType", DataType::F16))) +{ + // Validate output + validate(Accessor(_target), _reference); +} +TEST_SUITE_END() // F16 +#endif /* __ARM_FEATURE_FP16_VECTOR_ARITHMETIC */ + +TEST_SUITE(FP32) +DATA_TEST_CASE(Configuration, framework::DatasetMode::ALL, configuration_dataset, + shape, same_rank) +{ + const DataType dt = DataType::F32; + + // Create tensors + Tensor ref_c = create_tensor(detail::select_condition_shape(shape, same_rank), DataType::U8); + Tensor ref_x = create_tensor(shape, dt); + Tensor ref_y = create_tensor(shape, dt); + Tensor dst = create_tensor(shape, dt); + + // Create and Configure function + NESelect select; + select.configure(&ref_c, &ref_x, &ref_y, &dst); + + // Validate valid region + const ValidRegion valid_region = shape_to_valid_region(shape); + validate(dst.info()->valid_region(), valid_region); +} + +FIXTURE_DATA_TEST_CASE(RunSmall, + NESelectFixture, + framework::DatasetMode::PRECOMMIT, + combine(run_small_dataset, framework::dataset::make("DataType", DataType::F32))) +{ + // Validate output + validate(Accessor(_target), _reference); +} + +FIXTURE_DATA_TEST_CASE(RunLarge, + NESelectFixture, + framework::DatasetMode::NIGHTLY, + combine(run_large_dataset, framework::dataset::make("DataType", DataType::F32))) +{ + // Validate output + validate(Accessor(_target), _reference); +} +TEST_SUITE_END() // FP32 +TEST_SUITE_END() // Float + +TEST_SUITE_END() // Select +TEST_SUITE_END() // NEON +} // namespace validation +} // namespace test +} // namespace arm_compute -- cgit v1.2.1