From 4cbcb840caca1346de5f2271b67e4ede17b72734 Mon Sep 17 00:00:00 2001 From: alerah01 Date: Mon, 28 Feb 2022 06:38:08 +0200 Subject: Removing SVE / SVE2 guards from decoupled kernels Jira: COMPMID-5172 Signed-off-by: alerah01 Change-Id: I1b9ace8e573f85830f29728a27adfe39a0cab113 Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/7241 Tested-by: Arm Jenkins Reviewed-by: Giorgio Arena Comments-Addressed: Arm Jenkins --- src/cpu/kernels/activation/generic/sve/fp16.cpp | 8 +++++--- src/cpu/kernels/activation/generic/sve/fp32.cpp | 5 ++--- src/cpu/kernels/activation/generic/sve2/qasymm8.cpp | 5 ++--- src/cpu/kernels/activation/generic/sve2/qasymm8_signed.cpp | 4 +--- src/cpu/kernels/activation/generic/sve2/qsymm16.cpp | 4 +--- src/cpu/kernels/add/generic/sve/fp16.cpp | 3 +-- src/cpu/kernels/add/generic/sve/fp32.cpp | 3 +-- src/cpu/kernels/add/generic/sve/impl.cpp | 3 +-- src/cpu/kernels/add/generic/sve/impl.h | 3 +-- src/cpu/kernels/add/generic/sve/integer.cpp | 3 +-- src/cpu/kernels/add/generic/sve2/qasymm8.cpp | 3 +-- src/cpu/kernels/add/generic/sve2/qasymm8_signed.cpp | 3 +-- src/cpu/kernels/add/generic/sve2/qsymm16.cpp | 3 +-- src/cpu/kernels/elementwise_binary/generic/sve/fp16.cpp | 7 +++++-- src/cpu/kernels/elementwise_binary/generic/sve/fp32.cpp | 3 +-- src/cpu/kernels/elementwise_binary/generic/sve/impl.cpp | 3 +-- src/cpu/kernels/elementwise_binary/generic/sve/impl.h | 2 -- src/cpu/kernels/elementwise_binary/generic/sve/integer.cpp | 3 +-- src/cpu/kernels/elementwise_binary/generic/sve2/impl.h | 2 -- src/cpu/kernels/elementwise_binary/generic/sve2/qasymm8.cpp | 3 +-- .../kernels/elementwise_binary/generic/sve2/qasymm8_signed.cpp | 3 +-- src/cpu/kernels/elementwise_unary/generic/sve/fp16.cpp | 4 ++-- src/cpu/kernels/elementwise_unary/generic/sve/fp32.cpp | 3 +-- src/cpu/kernels/elementwise_unary/generic/sve/impl.cpp | 3 +-- src/cpu/kernels/elementwise_unary/generic/sve/impl.h | 4 ++-- src/cpu/kernels/elementwise_unary/generic/sve/integer.cpp | 3 +-- src/cpu/kernels/gemm_matrix_add/generic/neon/fp16.cpp | 4 ++-- src/cpu/kernels/scale/neon/fp16.cpp | 7 ++++--- src/cpu/kernels/scale/sve/fp16.cpp | 8 ++++---- src/cpu/kernels/scale/sve/fp32.cpp | 6 ++---- src/cpu/kernels/scale/sve/integer.cpp | 6 ++---- src/cpu/kernels/scale/sve/qasymm8.cpp | 6 ++---- src/cpu/kernels/scale/sve/qasymm8_signed.cpp | 6 ++---- src/cpu/kernels/softmax/generic/sve/fp16.cpp | 4 ++-- src/cpu/kernels/softmax/generic/sve/fp32.cpp | 3 +-- src/cpu/kernels/softmax/generic/sve/impl.cpp | 3 +-- src/cpu/kernels/softmax/generic/sve/impl.h | 2 -- src/cpu/kernels/softmax/generic/sve/qasymm8.cpp | 3 +-- src/cpu/kernels/softmax/generic/sve/qasymm8_signed.cpp | 3 +-- src/cpu/kernels/softmax/generic/sve2/qasymm8.cpp | 3 +-- src/cpu/kernels/softmax/generic/sve2/qasymm8_signed.cpp | 3 +-- 41 files changed, 62 insertions(+), 98 deletions(-) diff --git a/src/cpu/kernels/activation/generic/sve/fp16.cpp b/src/cpu/kernels/activation/generic/sve/fp16.cpp index 47d9fabb55..5730a361d9 100644 --- a/src/cpu/kernels/activation/generic/sve/fp16.cpp +++ b/src/cpu/kernels/activation/generic/sve/fp16.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021 Arm Limited. + * Copyright (c) 2020-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -21,7 +21,9 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ -#if defined(__ARM_FEATURE_SVE) + +#if defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(ENABLE_FP16_KERNELS) + #include "arm_compute/core/Helpers.h" #include "arm_compute/core/ITensorPack.h" #include "arm_compute/core/Window.h" @@ -127,4 +129,4 @@ void sve_fp16_activation(const ITensor *src, ITensor *dst, const ActivationLayer } } // namespace cpu } // namespace arm_compute -#endif /* defined(__ARM_FEATURE_SVE) */ \ No newline at end of file +#endif /* defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(ENABLE_FP16_KERNELS) */ \ No newline at end of file diff --git a/src/cpu/kernels/activation/generic/sve/fp32.cpp b/src/cpu/kernels/activation/generic/sve/fp32.cpp index 1685b0f669..7ce2046730 100644 --- a/src/cpu/kernels/activation/generic/sve/fp32.cpp +++ b/src/cpu/kernels/activation/generic/sve/fp32.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021 Arm Limited. + * Copyright (c) 2020-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -21,7 +21,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ -#if defined(__ARM_FEATURE_SVE) + #include "arm_compute/core/Helpers.h" #include "arm_compute/core/ITensorPack.h" #include "arm_compute/core/Window.h" @@ -128,4 +128,3 @@ void sve_fp32_activation(const ITensor *src, ITensor *dst, const ActivationLayer } } // namespace cpu } // namespace arm_compute -#endif /* defined(__ARM_FEATURE_SVE) */ \ No newline at end of file diff --git a/src/cpu/kernels/activation/generic/sve2/qasymm8.cpp b/src/cpu/kernels/activation/generic/sve2/qasymm8.cpp index 3b99c0f120..de513679d5 100644 --- a/src/cpu/kernels/activation/generic/sve2/qasymm8.cpp +++ b/src/cpu/kernels/activation/generic/sve2/qasymm8.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021 Arm Limited. + * Copyright (c) 2020-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -21,7 +21,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SVE2) + #include "arm_compute/core/Helpers.h" #include "arm_compute/core/Window.h" @@ -250,4 +250,3 @@ void sve2_qasymm8_activation(const ITensor *src, ITensor *dst, const ActivationL } } // namespace cpu } // namespace arm_compute -#endif /* defined(ARM_COMPUTE_ENABLE_SVE2) */ \ No newline at end of file diff --git a/src/cpu/kernels/activation/generic/sve2/qasymm8_signed.cpp b/src/cpu/kernels/activation/generic/sve2/qasymm8_signed.cpp index 24415145d3..906ec877f9 100644 --- a/src/cpu/kernels/activation/generic/sve2/qasymm8_signed.cpp +++ b/src/cpu/kernels/activation/generic/sve2/qasymm8_signed.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021 Arm Limited. + * Copyright (c) 2020-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -28,7 +28,6 @@ #include #include -#if defined(ARM_COMPUTE_ENABLE_SVE2) #include "src/core/NEON/SVEAsymm.h" #include "src/core/NEON/SVEMath.h" #include @@ -250,4 +249,3 @@ void sve2_qasymm8_signed_activation(const ITensor *src, ITensor *dst, const Acti } } // namespace cpu } // namespace arm_compute -#endif /* defined(ARM_COMPUTE_ENABLE_SVE2) */ diff --git a/src/cpu/kernels/activation/generic/sve2/qsymm16.cpp b/src/cpu/kernels/activation/generic/sve2/qsymm16.cpp index 0eecfa618f..41b5555448 100644 --- a/src/cpu/kernels/activation/generic/sve2/qsymm16.cpp +++ b/src/cpu/kernels/activation/generic/sve2/qsymm16.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021 Arm Limited. + * Copyright (c) 2020-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -29,7 +29,6 @@ #include #include -#if defined(ARM_COMPUTE_ENABLE_SVE2) #include "src/core/NEON/SVEMath.h" #include "src/core/NEON/SVESymm.h" #include @@ -117,4 +116,3 @@ void sve2_qsymm16_activation(const ITensor *src, ITensor *dst, const ActivationL } } // namespace cpu } // namespace arm_compute -#endif /* defined(ARM_COMPUTE_ENABLE_SVE2) */ diff --git a/src/cpu/kernels/add/generic/sve/fp16.cpp b/src/cpu/kernels/add/generic/sve/fp16.cpp index 7dc3142d3d..65a1369bfc 100644 --- a/src/cpu/kernels/add/generic/sve/fp16.cpp +++ b/src/cpu/kernels/add/generic/sve/fp16.cpp @@ -21,7 +21,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SVE) + #if defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(ENABLE_FP16_KERNELS) #include "src/cpu/kernels/add/generic/sve/impl.h" @@ -37,4 +37,3 @@ void add_fp16_sve(const ITensor *src0, const ITensor *src1, ITensor *dst, const } } // namespace arm_compute #endif /* (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(ENABLE_FP16_KERNELS) */ -#endif /* #if defined(ARM_COMPUTE_ENABLE_SVE) */ \ No newline at end of file diff --git a/src/cpu/kernels/add/generic/sve/fp32.cpp b/src/cpu/kernels/add/generic/sve/fp32.cpp index 5383b887ba..b37799113a 100644 --- a/src/cpu/kernels/add/generic/sve/fp32.cpp +++ b/src/cpu/kernels/add/generic/sve/fp32.cpp @@ -21,7 +21,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SVE) + #include "arm_compute/core/Helpers.h" #include "arm_compute/core/ITensor.h" #include "src/cpu/kernels/add/generic/sve/impl.h" @@ -36,4 +36,3 @@ void add_fp32_sve(const ITensor *src0, const ITensor *src1, ITensor *dst, const } } } // namespace arm_compute -#endif //ARM_COMPUTE_ENABLE_SVE \ No newline at end of file diff --git a/src/cpu/kernels/add/generic/sve/impl.cpp b/src/cpu/kernels/add/generic/sve/impl.cpp index 615f346dff..e8606436fd 100644 --- a/src/cpu/kernels/add/generic/sve/impl.cpp +++ b/src/cpu/kernels/add/generic/sve/impl.cpp @@ -21,7 +21,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SVE) + #include "src/cpu/kernels/add/generic/sve/impl.h" #include "arm_compute/core/Helpers.h" #include "arm_compute/core/utils/misc/Traits.h" @@ -133,4 +133,3 @@ template void add_same_sve(const ITensor *src0, const ITensor *src1, #endif /* (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(ENABLE_FP16_KERNELS) */ } // namespace cpu } // namespace arm_compute -#endif // ARM_COMPUTE_ENABLE_SVE \ No newline at end of file diff --git a/src/cpu/kernels/add/generic/sve/impl.h b/src/cpu/kernels/add/generic/sve/impl.h index 219dbc9b2e..0136f14246 100644 --- a/src/cpu/kernels/add/generic/sve/impl.h +++ b/src/cpu/kernels/add/generic/sve/impl.h @@ -21,7 +21,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SVE) + #ifndef SRC_CORE_SVE_KERNELS_ADD_IMPL_H #define SRC_CORE_SVE_KERNELS_ADD_IMPL_H #include "arm_compute/core/ITensor.h" @@ -37,4 +37,3 @@ void add_same_sve(const ITensor *src0, const ITensor *src1, ITensor *dst, const } // namespace cpu } // namespace arm_compute #endif // SRC_CORE_SVE_KERNELS_ADD_IMPL_H -#endif // ARM_COMPUTE_ENABLE_SVE \ No newline at end of file diff --git a/src/cpu/kernels/add/generic/sve/integer.cpp b/src/cpu/kernels/add/generic/sve/integer.cpp index 1d25d3463a..3642dccd7b 100644 --- a/src/cpu/kernels/add/generic/sve/integer.cpp +++ b/src/cpu/kernels/add/generic/sve/integer.cpp @@ -21,7 +21,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SVE) + #include "arm_compute/core/Helpers.h" #include "arm_compute/core/ITensor.h" #include "src/cpu/kernels/add/generic/sve/impl.h" @@ -46,4 +46,3 @@ void add_s32_sve(const ITensor *src0, const ITensor *src1, ITensor *dst, const C } } } // namespace arm_compute -#endif //(ARM_COMPUTE_ENABLE_SVE) \ No newline at end of file diff --git a/src/cpu/kernels/add/generic/sve2/qasymm8.cpp b/src/cpu/kernels/add/generic/sve2/qasymm8.cpp index 5fe9b95a48..1dec214aa0 100644 --- a/src/cpu/kernels/add/generic/sve2/qasymm8.cpp +++ b/src/cpu/kernels/add/generic/sve2/qasymm8.cpp @@ -21,7 +21,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SVE2) + #include "arm_compute/core/Helpers.h" #include "arm_compute/core/ITensor.h" #include "arm_compute/core/Types.h" @@ -179,4 +179,3 @@ void add_qasymm8_sve2(const ITensor *src0, const ITensor *src1, ITensor *dst, co } } // namespace cpu } // namespace arm_compute -#endif //ARM_COMPUTE_ENABLE_SVE2 \ No newline at end of file diff --git a/src/cpu/kernels/add/generic/sve2/qasymm8_signed.cpp b/src/cpu/kernels/add/generic/sve2/qasymm8_signed.cpp index 9135dfdcf6..dae8899753 100644 --- a/src/cpu/kernels/add/generic/sve2/qasymm8_signed.cpp +++ b/src/cpu/kernels/add/generic/sve2/qasymm8_signed.cpp @@ -21,7 +21,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SVE2) + #include "arm_compute/core/Helpers.h" #include "arm_compute/core/ITensor.h" #include "arm_compute/core/Types.h" @@ -178,4 +178,3 @@ void add_qasymm8_signed_sve2(const ITensor *src0, const ITensor *src1, ITensor * } } // namespace cpu } // namespace arm_compute -#endif //(ARM_COMPUTE_ENABLE_SVE2) \ No newline at end of file diff --git a/src/cpu/kernels/add/generic/sve2/qsymm16.cpp b/src/cpu/kernels/add/generic/sve2/qsymm16.cpp index 723d2a6c98..8c48ded942 100644 --- a/src/cpu/kernels/add/generic/sve2/qsymm16.cpp +++ b/src/cpu/kernels/add/generic/sve2/qsymm16.cpp @@ -21,7 +21,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SVE2) + #include "arm_compute/core/Helpers.h" #include "arm_compute/core/ITensor.h" #include "arm_compute/core/Types.h" @@ -153,4 +153,3 @@ void add_qsymm16_sve2(const ITensor *src0, const ITensor *src1, ITensor *dst, co } } // namespace cpu } // namespace arm_compute -#endif //ARM_COMPUTE_ENABLE_SVE2 \ No newline at end of file diff --git a/src/cpu/kernels/elementwise_binary/generic/sve/fp16.cpp b/src/cpu/kernels/elementwise_binary/generic/sve/fp16.cpp index d764f56623..8adacbfe67 100644 --- a/src/cpu/kernels/elementwise_binary/generic/sve/fp16.cpp +++ b/src/cpu/kernels/elementwise_binary/generic/sve/fp16.cpp @@ -21,7 +21,9 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SVE) + +#if defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(ENABLE_FP16_KERNELS) + #include "arm_compute/core/Helpers.h" #include "src/cpu/kernels/elementwise_binary/generic/sve/impl.h" namespace arm_compute @@ -58,4 +60,5 @@ template void sve_fp16_comparison_elementwise_binary @@ -312,4 +312,3 @@ svint16_t elementwise_div(svbool_t &pg, const svint16_t &a, const svi } // namespace cpu } // namespace arm_compute -#endif /* defined(ARM_COMPUTE_ENABLE_SVE) */ diff --git a/src/cpu/kernels/elementwise_binary/generic/sve/impl.h b/src/cpu/kernels/elementwise_binary/generic/sve/impl.h index b7425c8626..606090d417 100644 --- a/src/cpu/kernels/elementwise_binary/generic/sve/impl.h +++ b/src/cpu/kernels/elementwise_binary/generic/sve/impl.h @@ -23,7 +23,6 @@ */ #ifndef SRC_CORE_SVE_KERNELS_ELEMENTWISE_LIST_H #define SRC_CORE_SVE_KERNELS_ELEMENTWISE_LIST_H -#if defined(ARM_COMPUTE_ENABLE_SVE) #include "arm_compute/core/Helpers.h" #include "src/core/NEON/wrapper/intrinsics/intrinsics.h" @@ -161,5 +160,4 @@ template (const ITensor *in, ITensor *out, const } // namespace cpu } // namespace arm_compute -#endif //defined(ARM_COMPUTE_ENABLE_SVE) diff --git a/src/cpu/kernels/elementwise_unary/generic/sve/impl.h b/src/cpu/kernels/elementwise_unary/generic/sve/impl.h index 08f4438696..f2068dc63f 100644 --- a/src/cpu/kernels/elementwise_unary/generic/sve/impl.h +++ b/src/cpu/kernels/elementwise_unary/generic/sve/impl.h @@ -23,7 +23,7 @@ */ #ifndef SRC_CORE_SVE_KERNELS_ELEMENTWISE_UNARY_LIST_H #define SRC_CORE_SVE_KERNELS_ELEMENTWISE_UNARY_LIST_H -#if defined(ARM_COMPUTE_ENABLE_SVE) + namespace arm_compute { namespace cpu @@ -32,5 +32,5 @@ template void elementwise_sve_op(const ITensor *in, ITensor *out, const Window &window, ElementWiseUnary op); } // namespace cpu } // namespace arm_compute -#endif // defined(ARM_COMPUTE_ENABLE_SVE) + #endif // SRC_CORE_NEON_KERNELS_ELEMENTWISE_UNARY_LIST_H \ No newline at end of file diff --git a/src/cpu/kernels/elementwise_unary/generic/sve/integer.cpp b/src/cpu/kernels/elementwise_unary/generic/sve/integer.cpp index c3e3adfc9e..984056a426 100644 --- a/src/cpu/kernels/elementwise_unary/generic/sve/integer.cpp +++ b/src/cpu/kernels/elementwise_unary/generic/sve/integer.cpp @@ -21,7 +21,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SVE) + #include "arm_compute/core/Helpers.h" #include "src/cpu/kernels/elementwise_unary/generic/sve/impl.h" @@ -35,4 +35,3 @@ void sve_s32_elementwise_unary(const ITensor *in, ITensor *out, const Window &wi } } } // namespace arm_compute -#endif //ARM_COMPUTE_ENABLE_SVE diff --git a/src/cpu/kernels/gemm_matrix_add/generic/neon/fp16.cpp b/src/cpu/kernels/gemm_matrix_add/generic/neon/fp16.cpp index 3098416ada..2d61b72078 100644 --- a/src/cpu/kernels/gemm_matrix_add/generic/neon/fp16.cpp +++ b/src/cpu/kernels/gemm_matrix_add/generic/neon/fp16.cpp @@ -21,7 +21,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ -#ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC +#if defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(ENABLE_FP16_KERNELS) #include "src/cpu/kernels/gemm_matrix_add/generic/neon/impl.h" @@ -35,4 +35,4 @@ void neon_fp16_gemm_matrix_add(const ITensor *src, ITensor *dst, const Window &w } } // namespace cpu } // namespace arm_compute -#endif //__ARM_FEATURE_FP16_VECTOR_ARITHMETIC +#endif /* defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(ENABLE_FP16_KERNELS) */ diff --git a/src/cpu/kernels/scale/neon/fp16.cpp b/src/cpu/kernels/scale/neon/fp16.cpp index 0ad66cab1c..895f42215e 100644 --- a/src/cpu/kernels/scale/neon/fp16.cpp +++ b/src/cpu/kernels/scale/neon/fp16.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -21,6 +21,9 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ + +#if defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(ENABLE_FP16_KERNELS) + #include "arm_compute/core/Helpers.h" #include "arm_compute/core/ITensorPack.h" #include "arm_compute/core/Window.h" @@ -34,8 +37,6 @@ #include #include -#if defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(ENABLE_FP16_KERNELS) - namespace arm_compute { namespace diff --git a/src/cpu/kernels/scale/sve/fp16.cpp b/src/cpu/kernels/scale/sve/fp16.cpp index 76e7735b8a..d08bfd8cdf 100644 --- a/src/cpu/kernels/scale/sve/fp16.cpp +++ b/src/cpu/kernels/scale/sve/fp16.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -22,7 +22,8 @@ * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SVE) +#if defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(ENABLE_FP16_KERNELS) + #include "arm_compute/core/Helpers.h" #include "arm_compute/core/ITensorPack.h" #include "arm_compute/core/Window.h" @@ -172,5 +173,4 @@ void fp16_sve_scale(const ITensor *src, ITensor *dst, const ITensor *offsets, co } } // namespace cpu } // namespace arm_compute - -#endif // ARM_COMPUTE_ENABLE_SVE \ No newline at end of file +#endif /* defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(ENABLE_FP16_KERNELS) */ \ No newline at end of file diff --git a/src/cpu/kernels/scale/sve/fp32.cpp b/src/cpu/kernels/scale/sve/fp32.cpp index 030e109cdf..98b343870f 100644 --- a/src/cpu/kernels/scale/sve/fp32.cpp +++ b/src/cpu/kernels/scale/sve/fp32.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -21,7 +21,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SVE) + #include "arm_compute/core/Helpers.h" #include "arm_compute/core/ITensorPack.h" #include "arm_compute/core/Window.h" @@ -170,5 +170,3 @@ void fp32_sve_scale(const ITensor *src, ITensor *dst, const ITensor *offsets, co } } // namespace cpu } // namespace arm_compute - -#endif // ARM_COMPUTE_ENABLE_SVE \ No newline at end of file diff --git a/src/cpu/kernels/scale/sve/integer.cpp b/src/cpu/kernels/scale/sve/integer.cpp index 486c674612..00a43922d9 100644 --- a/src/cpu/kernels/scale/sve/integer.cpp +++ b/src/cpu/kernels/scale/sve/integer.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -21,7 +21,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SVE) + #include "arm_compute/core/Helpers.h" #include "arm_compute/core/ITensorPack.h" #include "arm_compute/core/Window.h" @@ -296,5 +296,3 @@ void s16_sve_scale(const ITensor *src, ITensor *dst, const ITensor *offsets, con } } // namespace cpu } // namespace arm_compute - -#endif // ARM_COMPUTE_ENABLE_SVE \ No newline at end of file diff --git a/src/cpu/kernels/scale/sve/qasymm8.cpp b/src/cpu/kernels/scale/sve/qasymm8.cpp index c9122ad40b..09ef00a783 100644 --- a/src/cpu/kernels/scale/sve/qasymm8.cpp +++ b/src/cpu/kernels/scale/sve/qasymm8.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -21,7 +21,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SVE) + #include "arm_compute/core/Helpers.h" #include "arm_compute/core/ITensorPack.h" #include "arm_compute/core/Window.h" @@ -203,5 +203,3 @@ void qasymm8_sve_scale(const ITensor *src, ITensor *dst, const ITensor *offsets, } } // namespace cpu } // namespace arm_compute - -#endif // defined(ARM_COMPUTE_ENABLE_SVE) \ No newline at end of file diff --git a/src/cpu/kernels/scale/sve/qasymm8_signed.cpp b/src/cpu/kernels/scale/sve/qasymm8_signed.cpp index 0843e61fd4..63f515442b 100644 --- a/src/cpu/kernels/scale/sve/qasymm8_signed.cpp +++ b/src/cpu/kernels/scale/sve/qasymm8_signed.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -21,7 +21,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SVE) + #include "arm_compute/core/Helpers.h" #include "arm_compute/core/ITensorPack.h" #include "arm_compute/core/Window.h" @@ -203,5 +203,3 @@ void qasymm8_signed_sve_scale(const ITensor *src, ITensor *dst, const ITensor *o } } // namespace cpu } // namespace arm_compute - -#endif // ARM_COMPUTE_ENABLE_SVE \ No newline at end of file diff --git a/src/cpu/kernels/softmax/generic/sve/fp16.cpp b/src/cpu/kernels/softmax/generic/sve/fp16.cpp index 89be6c5244..7aefcb1441 100644 --- a/src/cpu/kernels/softmax/generic/sve/fp16.cpp +++ b/src/cpu/kernels/softmax/generic/sve/fp16.cpp @@ -21,7 +21,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SVE) +#if defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(ENABLE_FP16_KERNELS) #include "arm_compute/core/Helpers.h" #include "src/cpu/kernels/softmax/generic/sve/impl.h" namespace arm_compute @@ -40,4 +40,4 @@ void sve_fp16_logits(const ITensor *in, ITensor *out, const Window &window) } } } // namespace arm_compute -#endif //ARM_COMPUTE_ENABLE_SVE +#endif /* defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(ENABLE_FP16_KERNELS) */ diff --git a/src/cpu/kernels/softmax/generic/sve/fp32.cpp b/src/cpu/kernels/softmax/generic/sve/fp32.cpp index 79130bf35b..55c4aee426 100644 --- a/src/cpu/kernels/softmax/generic/sve/fp32.cpp +++ b/src/cpu/kernels/softmax/generic/sve/fp32.cpp @@ -21,7 +21,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SVE) + #include "arm_compute/core/Helpers.h" #include "src/cpu/kernels/softmax/generic/sve/impl.h" @@ -41,4 +41,3 @@ void sve_fp32_logits(const ITensor *in, ITensor *out, const Window &window) } } } // namespace arm_compute -#endif //ARM_COMPUTE_ENABLE_SVE diff --git a/src/cpu/kernels/softmax/generic/sve/impl.cpp b/src/cpu/kernels/softmax/generic/sve/impl.cpp index f17e50e77d..f1442224e8 100644 --- a/src/cpu/kernels/softmax/generic/sve/impl.cpp +++ b/src/cpu/kernels/softmax/generic/sve/impl.cpp @@ -21,7 +21,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SVE) + #include "src/cpu/kernels/softmax/generic/sve/impl.h" #include "src/core/NEON/wrapper/intrinsics/intrinsics.h" @@ -176,4 +176,3 @@ template void sve_softmax_logits_1d_float(const ITensor *in, const IT ITensor *out, const float beta, bool is_log, const Window &window); } // namespace cpu } // namespace arm_compute -#endif /* defined(ARM_COMPUTE_ENABLE_SVE) */ diff --git a/src/cpu/kernels/softmax/generic/sve/impl.h b/src/cpu/kernels/softmax/generic/sve/impl.h index 1051f59ff5..4f76ec6a26 100644 --- a/src/cpu/kernels/softmax/generic/sve/impl.h +++ b/src/cpu/kernels/softmax/generic/sve/impl.h @@ -24,7 +24,6 @@ #ifndef SRC_CORE_SVE_KERNELS_SOFTMAX_IMPL_H #define SRC_CORE_SVE_KERNELS_SOFTMAX_IMPL_H -#if defined(ARM_COMPUTE_ENABLE_SVE) #include "arm_compute/core/Helpers.h" namespace arm_compute { @@ -38,6 +37,5 @@ void sve_softmax_logits_1d_float(const ITensor *in, const ITensor *max, void *co ITensor *out, const float beta, bool is_log, const Window &window); } // namespace cpu } // namespace arm_compute -#endif /* defined(ARM_COMPUTE_ENABLE_SVE) */ #endif /* SRC_CORE_SVE_KERNELS_SOFTMAX_IMPL_H */ diff --git a/src/cpu/kernels/softmax/generic/sve/qasymm8.cpp b/src/cpu/kernels/softmax/generic/sve/qasymm8.cpp index 62afe4bf74..e9044d5fc9 100644 --- a/src/cpu/kernels/softmax/generic/sve/qasymm8.cpp +++ b/src/cpu/kernels/softmax/generic/sve/qasymm8.cpp @@ -21,7 +21,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SVE) + #include "arm_compute/core/Helpers.h" #include "src/cpu/kernels/softmax/generic/sve/impl.h" @@ -35,4 +35,3 @@ void sve_qasymm8_logits(const ITensor *in, ITensor *out, const Window &window) } } } // namespace arm_compute -#endif //defined(ARM_COMPUTE_ENABLE_SVE) diff --git a/src/cpu/kernels/softmax/generic/sve/qasymm8_signed.cpp b/src/cpu/kernels/softmax/generic/sve/qasymm8_signed.cpp index 5547cc902f..ab45ce598d 100644 --- a/src/cpu/kernels/softmax/generic/sve/qasymm8_signed.cpp +++ b/src/cpu/kernels/softmax/generic/sve/qasymm8_signed.cpp @@ -21,7 +21,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SVE) + #include "arm_compute/core/Helpers.h" #include "src/cpu/kernels/softmax/generic/sve/impl.h" @@ -35,4 +35,3 @@ void sve_qasymm8_signed_logits(const ITensor *in, ITensor *out, const Window &wi } } } // namespace arm_compute -#endif //defined(ARM_COMPUTE_ENABLE_SVE) diff --git a/src/cpu/kernels/softmax/generic/sve2/qasymm8.cpp b/src/cpu/kernels/softmax/generic/sve2/qasymm8.cpp index 8566a51432..810035eb9c 100644 --- a/src/cpu/kernels/softmax/generic/sve2/qasymm8.cpp +++ b/src/cpu/kernels/softmax/generic/sve2/qasymm8.cpp @@ -21,7 +21,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SVE2) + #include "arm_compute/core/Helpers.h" #include "src/cpu/kernels/softmax/generic/sve2/impl.h" @@ -36,4 +36,3 @@ void sve2_qasymm8_softmax(const ITensor *in, const ITensor *max, void *const tmp } } } // namespace arm_compute -#endif //defined(ARM_COMPUTE_ENABLE_SVE2) diff --git a/src/cpu/kernels/softmax/generic/sve2/qasymm8_signed.cpp b/src/cpu/kernels/softmax/generic/sve2/qasymm8_signed.cpp index c2bdc50119..283b55e9ce 100644 --- a/src/cpu/kernels/softmax/generic/sve2/qasymm8_signed.cpp +++ b/src/cpu/kernels/softmax/generic/sve2/qasymm8_signed.cpp @@ -21,7 +21,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SVE2) + #include "arm_compute/core/Helpers.h" #include "src/cpu/kernels/softmax/generic/sve2/impl.h" @@ -36,4 +36,3 @@ void sve2_qasymm8_signed_softmax(const ITensor *in, const ITensor *max, void *co } } } // namespace arm_compute -#endif //defined(ARM_COMPUTE_ENABLE_SVE2) -- cgit v1.2.1