From 421405b6a21b124288a750e2da26dc01eb7391cb Mon Sep 17 00:00:00 2001 From: Georgios Pinitas Date: Fri, 26 Oct 2018 19:05:32 +0100 Subject: COMPMID-1675: Add SVE support Change-Id: I86679adff556b6ffc9929b35cbf1b59b3958bdb1 --- SConscript | 2 + SConstruct | 26 +- examples/neon_sgemm.cpp | 192 +++ src/core/NEON/kernels/arm_gemm/gemm_fp16.cpp | 18 +- src/core/NEON/kernels/arm_gemm/gemm_fp32.cpp | 14 +- src/core/NEON/kernels/arm_gemm/gemm_int16.cpp | 2 +- src/core/NEON/kernels/arm_gemm/gemm_int8.cpp | 14 + src/core/NEON/kernels/arm_gemm/gemm_uint8.cpp | 12 + .../kernels/sve_interleaved_fp16_mla_3VLx8.hpp | 72 + .../sve_interleaved_fp16_mla_3VLx8/generic.cpp | 324 ++++ .../kernels/sve_interleaved_fp32_mla_3VLx8.hpp | 72 + .../sve_interleaved_fp32_mla_3VLx8/generic.cpp | 333 +++++ .../kernels/sve_interleaved_s8s32_dot_3VLx8.hpp | 72 + .../sve_interleaved_s8s32_dot_3VLx8/generic.cpp | 334 +++++ .../kernels/sve_interleaved_u8u32_dot_3VLx8.hpp | 72 + .../sve_interleaved_u8u32_dot_3VLx8/generic.cpp | 328 ++++ .../kernels/arm_gemm/kernels/sve_sgemm_3VLx8.hpp | 75 + .../arm_gemm/kernels/sve_sgemm_3VLx8/generic.cpp | 366 +++++ src/core/NEON/kernels/arm_gemm/merges/list.hpp | 2 + .../arm_gemm/merges/sve_merge_fp32_2VLx8.hpp | 1208 +++++++++++++++ .../arm_gemm/merges/sve_merge_fp32_3VLx8.hpp | 1564 ++++++++++++++++++++ .../NEON/kernels/arm_gemm/std_transforms_sve.hpp | 71 + src/core/NEON/kernels/arm_gemm/transform.hpp | 2 +- src/core/NEON/kernels/arm_gemm/transforms/list.hpp | 10 +- .../transforms/sve_interleave_8way_32bit.hpp | 596 ++++++++ .../sve_interleave_8way_block2_16bit.hpp | 632 ++++++++ .../sve_interleave_8way_block2_32bit.hpp | 632 ++++++++ .../sve_interleave_8way_block4_16bit.hpp | 632 ++++++++ .../transforms/sve_interleave_8way_block4_8bit.hpp | 596 ++++++++ src/core/NEON/kernels/arm_gemm/utils.hpp | 24 +- .../kernels/assembly/NEGEMMInterleavedStrategies.h | 28 + .../NEON/functions/NEDeconvolutionLayer.cpp | 4 +- support/Semaphore.h | 5 +- tests/AssetsLibrary.cpp | 4 +- tests/AssetsLibrary.h | 4 +- tests/SConscript | 2 +- tests/TensorCache.h | 14 +- tests/framework/instruments/Instruments.h | 2 + 38 files changed, 8318 insertions(+), 42 deletions(-) create mode 100644 examples/neon_sgemm.cpp create mode 100644 src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp16_mla_3VLx8.hpp create mode 100644 src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp16_mla_3VLx8/generic.cpp create mode 100644 src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp32_mla_3VLx8.hpp create mode 100644 src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp32_mla_3VLx8/generic.cpp create mode 100644 src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_s8s32_dot_3VLx8.hpp create mode 100644 src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_s8s32_dot_3VLx8/generic.cpp create mode 100644 src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_u8u32_dot_3VLx8.hpp create mode 100644 src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_u8u32_dot_3VLx8/generic.cpp create mode 100644 src/core/NEON/kernels/arm_gemm/kernels/sve_sgemm_3VLx8.hpp create mode 100644 src/core/NEON/kernels/arm_gemm/kernels/sve_sgemm_3VLx8/generic.cpp create mode 100644 src/core/NEON/kernels/arm_gemm/merges/sve_merge_fp32_2VLx8.hpp create mode 100644 src/core/NEON/kernels/arm_gemm/merges/sve_merge_fp32_3VLx8.hpp create mode 100644 src/core/NEON/kernels/arm_gemm/std_transforms_sve.hpp create mode 100644 src/core/NEON/kernels/arm_gemm/transforms/sve_interleave_8way_32bit.hpp create mode 100644 src/core/NEON/kernels/arm_gemm/transforms/sve_interleave_8way_block2_16bit.hpp create mode 100644 src/core/NEON/kernels/arm_gemm/transforms/sve_interleave_8way_block2_32bit.hpp create mode 100644 src/core/NEON/kernels/arm_gemm/transforms/sve_interleave_8way_block4_16bit.hpp create mode 100644 src/core/NEON/kernels/arm_gemm/transforms/sve_interleave_8way_block4_8bit.hpp diff --git a/SConscript b/SConscript index 86f2789de5..7d0717b27e 100644 --- a/SConscript +++ b/SConscript @@ -210,6 +210,8 @@ if env['neon']: if "arm64-v8" in env['arch']: core_files += Glob('src/core/NEON/kernels/arm_gemm/kernels/a64_*/*.cpp') + if "sve" in env['arch']: + core_files += Glob('src/core/NEON/kernels/arm_gemm/kernels/sve_*/*.cpp') runtime_files += Glob('src/runtime/NEON/*.cpp') runtime_files += Glob('src/runtime/NEON/functions/*.cpp') diff --git a/SConstruct b/SConstruct index c1d1f716a8..5f20589aae 100644 --- a/SConstruct +++ b/SConstruct @@ -40,7 +40,7 @@ vars.AddVariables( BoolVariable("debug", "Debug", False), BoolVariable("asserts", "Enable asserts (this flag is forced to 1 for debug=1)", False), BoolVariable("logging", "Logging (this flag is forced to 1 for debug=1)", False), - EnumVariable("arch", "Target Architecture", "armv7a", allowed_values=("armv7a", "arm64-v8a", "arm64-v8.2-a", "x86_32", "x86_64")), + EnumVariable("arch", "Target Architecture", "armv7a", allowed_values=("armv7a", "arm64-v8a", "arm64-v8.2-a", "arm64-v8.2-a-sve", "x86_32", "x86_64")), EnumVariable("os", "Target OS", "linux", allowed_values=("linux", "android", "bare_metal")), EnumVariable("build", "Build type", "cross_compile", allowed_values=("native", "cross_compile", "embed_only")), BoolVariable("examples", "Build example programs", True), @@ -58,6 +58,7 @@ vars.AddVariables( #FIXME Remove before release (And remove all references to INTERNAL_ONLY) BoolVariable("internal_only", "Enable ARM internal only tests", False), ("extra_cxx_flags", "Extra CXX flags to be appended to the build command", ""), + ("extra_link_flags", "Extra LD flags to be appended to the build command", ""), ("compiler_cache", "Command to prefix to the C and C++ compiler (e.g ccache)", "") ) @@ -174,17 +175,23 @@ elif env['arch'] == 'arm64-v8a': prefix = "aarch64-linux-android-" if 'clang++' in cpp_compiler: env.Append(CXXFLAGS = ['-no-integrated-as']) -elif env['arch'] == 'arm64-v8.2-a': - env.Append(CXXFLAGS = ['-march=armv8.2-a+fp16']) # explicitly enable fp16 extension otherwise __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is undefined +elif 'arm64-v8.2-a' in env['arch']: + if env['arch'] == 'arm64-v8.2-a-sve': + if env['os'] != 'bare_metal': + print("Only bare metal SVE is supported at the moment") + Exit(1) + env.Append(CXXFLAGS = ['-march=armv8.2-a+sve+fp16+dotprod']) + else: + env.Append(CXXFLAGS = ['-march=armv8.2-a+fp16']) # explicitly enable fp16 extension otherwise __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is undefined + if env['os'] == 'linux': + prefix = "aarch64-linux-gnu-" + elif env['os'] == 'bare_metal': + prefix = "aarch64-elf-" + elif env['os'] == 'android': + prefix = "aarch64-linux-android-" env.Append(CPPDEFINES = ['ARM_COMPUTE_AARCH64_V8_2','NO_DOT_IN_TOOLCHAIN']) if 'clang++' in cpp_compiler: env.Append(CXXFLAGS = ['-no-integrated-as']) - if env['os'] == 'linux': - prefix = "aarch64-linux-gnu-" - elif env['os'] == 'bare_metal': - prefix = "aarch64-elf-" - elif env['os'] == 'android': - prefix = "aarch64-linux-android-" elif env['arch'] == 'x86_32': env.Append(CCFLAGS = ['-m32']) env.Append(LINKFLAGS = ['-m32']) @@ -274,6 +281,7 @@ if env['logging']: env.Append(CPPPATH = ['#/include', "#"]) env.Append(CXXFLAGS = env['extra_cxx_flags']) +env.Append(LINKFLAGS = env['extra_link_flags']) Default( install_include("arm_compute")) diff --git a/examples/neon_sgemm.cpp b/examples/neon_sgemm.cpp new file mode 100644 index 0000000000..f6f93dd507 --- /dev/null +++ b/examples/neon_sgemm.cpp @@ -0,0 +1,192 @@ +/* + * Copyright (c) 2018 ARM Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#include "arm_compute/core/Types.h" +#include "arm_compute/runtime/NEON/NEFunctions.h" +#include "arm_compute/runtime/NEON/NEScheduler.h" +#include "utils/Utils.h" + +#include + +using namespace arm_compute; +using namespace utils; + +class NESGEMMExample : public Example +{ +public: + bool do_setup(int argc, char **argv) override + { + NPYLoader npy0, npy1, npy2; + alpha = 1.0f; + beta = 0.0f; + + std::ifstream stream; + if(argc > 1) + { + stream.open(argv[1], std::fstream::in); + } + + if(argc < 3 || (argc < 4 && stream.bad())) + { + // Print help + std::cout << "Usage: 1) ./build/neon_sgemm input_matrix_1.npy input_matrix_2.npy [input_matrix_3.npy] [alpha = 1] [beta = 0]\n"; + std::cout << " 2) ./build/neon_sgemm M N K [alpha = 1.0f] [beta = 0.0f]\n\n"; + std::cout << "Too few or no input_matrices provided. Using M=7, N=3, K=5, alpha=1.0f and beta=0.0f\n\n"; + + src0.allocator()->init(TensorInfo(TensorShape(5U, 7U), 1, DataType::F32)); + src1.allocator()->init(TensorInfo(TensorShape(3U, 5U), 1, DataType::F32)); + src2.allocator()->init(TensorInfo(TensorShape(3U, 7U), 1, DataType::F32)); + } + else + { + if(stream.good()) /* case file1.npy file2.npy [file3.npy] [alpha = 1.0f] [beta = 0.0f] */ + { + npy0.open(argv[1]); + npy0.init_tensor(src0, DataType::F32); + npy1.open(argv[2]); + npy1.init_tensor(src1, DataType::F32); + + if(argc > 3) + { + stream.close(); + stream.clear(); + stream.open(argv[3], std::fstream::in); + if(stream.good()) /* case with third file */ + { + npy2.open(argv[3]); + npy2.init_tensor(src2, DataType::F32); + + if(argc > 4) + { + // Convert string to float + alpha = strtof(argv[4], nullptr); + + if(argc > 5) + { + // Convert string to float + beta = strtof(argv[5], nullptr); + } + } + } + else /* case without third file */ + { + alpha = strtof(argv[3], nullptr); + + if(argc > 4) + { + beta = strtof(argv[4], nullptr); + } + } + } + } + else /* case M N K [alpha = 1.0f] [beta = 0.0f] */ + { + size_t M = strtol(argv[1], nullptr, 10); + size_t N = strtol(argv[2], nullptr, 10); + size_t K = strtol(argv[3], nullptr, 10); + + src0.allocator()->init(TensorInfo(TensorShape(K, M), 1, DataType::F32)); + src1.allocator()->init(TensorInfo(TensorShape(N, K), 1, DataType::F32)); + src2.allocator()->init(TensorInfo(TensorShape(N, M), 1, DataType::F32)); + + if(argc > 4) + { + alpha = strtof(argv[4], nullptr); + + if(argc > 5) + { + beta = strtof(argv[5], nullptr); + } + } + } + } + + init_sgemm_output(dst, src0, src1, DataType::F32); + + // Configure function + sgemm.configure(&src0, &src1, nullptr, &dst, alpha, beta); + + // Allocate all the images + src0.allocator()->allocate(); + src1.allocator()->allocate(); + dst.allocator()->allocate(); + + // Fill the input images with either the data provided or random data + if(npy0.is_open()) + { + npy0.fill_tensor(src0); + npy1.fill_tensor(src1); + + output_filename = "sgemm_out.npy"; + is_fortran = npy0.is_fortran(); + + if(npy2.is_open()) + { + src2.allocator()->allocate(); + npy2.fill_tensor(src2); + } + } + else + { + src2.allocator()->allocate(); + + fill_random_tensor(src0, -1.f, 1.f); + fill_random_tensor(src1, -1.f, 1.f); + fill_random_tensor(src2, -1.f, 1.f); + } + + // Dummy run for CLTuner + sgemm.run(); + + return true; + } + void do_run() override + { + // Execute the function + sgemm.run(); + } + void do_teardown() override + { + if(!output_filename.empty()) /* Save to .npy file */ + { + save_to_npy(dst, output_filename, is_fortran); + } + } + +private: + Tensor src0{}, src1{}, src2{}, dst{}; + NEGEMM sgemm{}; + float alpha{}, beta{}; + bool is_fortran{}; + std::string output_filename{}; +}; + +/** Main program for sgemm test + * + * @param[in] argc Number of arguments + * @param[in] argv Arguments ( [optional] Matrix A, [optional] Matrix B, [optional] Matrix C, [optional] alpha, [optional] beta ) + */ +int main(int argc, char **argv) +{ + return utils::run_example(argc, argv); +} diff --git a/src/core/NEON/kernels/arm_gemm/gemm_fp16.cpp b/src/core/NEON/kernels/arm_gemm/gemm_fp16.cpp index 4579ebd307..9194bdd4d4 100644 --- a/src/core/NEON/kernels/arm_gemm/gemm_fp16.cpp +++ b/src/core/NEON/kernels/arm_gemm/gemm_fp16.cpp @@ -34,10 +34,22 @@ #include "kernels/a64_hgemm_24x8.hpp" #include "kernels/a64_sgemm_12x8.hpp" #include "kernels/a32_sgemm_8x6.hpp" +#include "kernels/sve_interleaved_fp16_mla_3VLx8.hpp" namespace arm_gemm { -#ifdef __aarch64__ +#ifdef __ARM_FEATURE_SVE +class GemmImpl_gemm_fp16_interleaved_fp16 : public GemmImplementation<__fp16, __fp16> { +public: + + UniqueGemmCommon<__fp16, __fp16> instantiate(const GemmArgs<__fp16> &args) override { + return UniqueGemmCommon<__fp16, __fp16>(new GemmInterleaved(args)); + } + + GemmImpl_gemm_fp16_interleaved_fp16() : GemmImplementation<__fp16, __fp16>(GemmMethod::GEMM_INTERLEAVED_FP16) { } +}; + +#elif defined(__aarch64__) #if defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) || defined(FP16_KERNELS) class GemmImpl_gemm_fp16_interleaved_fp16 : public GemmImplementation<__fp16, __fp16> { @@ -73,13 +85,13 @@ public: GemmImpl_gemm_fp16_interleaved() : GemmImplementation<__fp16, __fp16>(GemmMethod::GEMM_INTERLEAVED) { } }; -#if defined(__aarch64__) && (defined(__ARM_FEATURE_VECTOR_ARITHMETIC) || defined(FP16_KERNELS)) +#if defined(__aarch64__) && (defined(__ARM_FEATURE_VECTOR_ARITHMETIC) || defined(FP16_KERNELS) || defined(__ARM_FEATURE_SVE)) static GemmImpl_gemm_fp16_interleaved_fp16 gemm_fp16_interleaved_fp16_impl{}; #endif static GemmImpl_gemm_fp16_interleaved gemm_fp16_interleaved_impl{}; static std::vector *> gemm_fp16_methods = { -#if defined(__aarch64__) && (defined(__ARM_FEATURE_VECTOR_ARITHMETIC) || defined(FP16_KERNELS)) +#if defined(__aarch64__) && (defined(__ARM_FEATURE_VECTOR_ARITHMETIC) || defined(FP16_KERNELS) || defined(__ARM_FEATURE_SVE)) &gemm_fp16_interleaved_fp16_impl, #endif &gemm_fp16_interleaved_impl diff --git a/src/core/NEON/kernels/arm_gemm/gemm_fp32.cpp b/src/core/NEON/kernels/arm_gemm/gemm_fp32.cpp index e840e90eec..7d14971b70 100644 --- a/src/core/NEON/kernels/arm_gemm/gemm_fp32.cpp +++ b/src/core/NEON/kernels/arm_gemm/gemm_fp32.cpp @@ -36,10 +36,12 @@ #include "kernels/a64_sgemv_pretransposed.hpp" #include "kernels/a64_sgemm_native_16x4.hpp" +#include "kernels/sve_interleaved_fp32_mla_3VLx8.hpp" + namespace arm_gemm { -#ifdef __aarch64__ -// SGEMM implementations for AArch64 +#if defined(__aarch64__) && !defined(__ARM_FEATURE_SVE) +// SGEMM implementations for AArch64 without SVE // Pretransposed GEMV class GemmImpl_sgemm_gemv_pretransposed : public GemmImplementation { @@ -92,7 +94,9 @@ public: class GemmImpl_sgemm_gemm_interleaved : public GemmImplementation { public: UniqueGemmCommon instantiate(const GemmArgs &args) override { -#ifdef __aarch64__ +#ifdef __ARM_FEATURE_SVE + return UniqueGemmCommon (new GemmInterleaved(args)); +#elif defined(__aarch64__) return UniqueGemmCommon (new GemmInterleaved(args)); #elif defined(__arm__) return UniqueGemmCommon (new GemmInterleaved(args)); @@ -105,7 +109,7 @@ public: }; static GemmImpl_gemv_batched gemv_batched_impl{}; -#ifdef __aarch64__ +#if defined(__aarch64__) && !defined(__ARM_FEATURE_SVE) static GemmImpl_sgemm_gemv_pretransposed sgemm_gemv_pretransposed_impl{}; static GemmImpl_sgemm_gemv_native_transposed sgemm_gemv_native_transposed_impl{}; static GemmImpl_sgemm_gemm_native sgemm_gemm_native_impl{}; @@ -115,7 +119,7 @@ static GemmImpl_sgemm_gemm_interleaved sgemm_gemm_interleaved_impl{}; /* List of implementations (order matters) */ static std::vector *> SGemmMethods = { &gemv_batched_impl, -#ifdef __aarch64__ +#if defined(__aarch64__) && !defined(__ARM_FEATURE_SVE) &sgemm_gemv_pretransposed_impl, &sgemm_gemv_native_transposed_impl, &sgemm_gemm_native_impl, diff --git a/src/core/NEON/kernels/arm_gemm/gemm_int16.cpp b/src/core/NEON/kernels/arm_gemm/gemm_int16.cpp index b7e8fa21af..ad171a7f9a 100644 --- a/src/core/NEON/kernels/arm_gemm/gemm_int16.cpp +++ b/src/core/NEON/kernels/arm_gemm/gemm_int16.cpp @@ -59,4 +59,4 @@ template bool method_is_compatible(GemmMethod method, GemmArgs } // namespace arm_gemm -#endif // __aarch64__ +#endif // __aarch64__ \ No newline at end of file diff --git a/src/core/NEON/kernels/arm_gemm/gemm_int8.cpp b/src/core/NEON/kernels/arm_gemm/gemm_int8.cpp index dffa056adc..627d8abdb9 100644 --- a/src/core/NEON/kernels/arm_gemm/gemm_int8.cpp +++ b/src/core/NEON/kernels/arm_gemm/gemm_int8.cpp @@ -31,9 +31,21 @@ #include "kernels/a64_gemm_s16_12x8.hpp" #include "kernels/a64_gemm_s8_12x8.hpp" #include "kernels/a64_gemm_s8_4x4.hpp" +#include "kernels/sve_interleaved_s8s32_dot_3VLx8.hpp" namespace arm_gemm { +#ifdef __ARM_FEATURE_SVE +class GemmImpl_gemm_s8_interleaved_dot : public GemmImplementation { +public: + UniqueGemmCommon instantiate(const GemmArgs &args) override { + return UniqueGemmCommon(new GemmInterleaved(args)); + } + + GemmImpl_gemm_s8_interleaved_dot() : GemmImplementation(GemmMethod::GEMM_INTERLEAVED_DOT) { } +}; +#else + class GemmImpl_gemm_s8_interleaved_dot : public GemmImplementation { public: bool is_supported(const GemmArgs &args) override { @@ -47,6 +59,8 @@ public: GemmImpl_gemm_s8_interleaved_dot() : GemmImplementation(GemmMethod::GEMM_INTERLEAVED_DOT) { } }; +#endif + class GemmImpl_gemm_s8_interleaved : public GemmImplementation { public: UniqueGemmCommon instantiate(const GemmArgs &args) override { diff --git a/src/core/NEON/kernels/arm_gemm/gemm_uint8.cpp b/src/core/NEON/kernels/arm_gemm/gemm_uint8.cpp index 60b7954db3..b7c1bab6bd 100644 --- a/src/core/NEON/kernels/arm_gemm/gemm_uint8.cpp +++ b/src/core/NEON/kernels/arm_gemm/gemm_uint8.cpp @@ -31,9 +31,20 @@ #include "kernels/a64_gemm_u16_12x8.hpp" #include "kernels/a64_gemm_u8_12x8.hpp" #include "kernels/a64_gemm_u8_4x4.hpp" +#include "kernels/sve_interleaved_u8u32_dot_3VLx8.hpp" namespace arm_gemm { +#ifdef __ARM_FEATURE_SVE +class GemmImpl_gemm_u8_interleaved_dot : public GemmImplementation { +public: + UniqueGemmCommon instantiate(const GemmArgs &args) override { + return UniqueGemmCommon(new GemmInterleaved(args)); + } + + GemmImpl_gemm_u8_interleaved_dot() : GemmImplementation(GemmMethod::GEMM_INTERLEAVED_DOT) { } +}; +#else class GemmImpl_gemm_u8_interleaved_dot : public GemmImplementation { public: bool is_supported(const GemmArgs &args) override { @@ -46,6 +57,7 @@ public: GemmImpl_gemm_u8_interleaved_dot() : GemmImplementation(GemmMethod::GEMM_INTERLEAVED_DOT) { } }; +#endif class GemmImpl_gemm_u8_interleaved : public GemmImplementation { public: diff --git a/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp16_mla_3VLx8.hpp b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp16_mla_3VLx8.hpp new file mode 100644 index 0000000000..3fd738e673 --- /dev/null +++ b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp16_mla_3VLx8.hpp @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2018 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#pragma once + +#ifdef __ARM_FEATURE_SVE + + +#include "../std_transforms_sve.hpp" + +namespace arm_gemm { + +// Actual kernel implementations +void sve_interleaved_fp16_mla_3VLx8(const __fp16 *, const __fp16 *, __fp16 *, int, int, int); + +class interleaved_fp16_mla_3VLx8 { +public: + typedef __fp16 operand_type; + typedef __fp16 result_type; + + typedef void (*kern_type)(const __fp16 *, const __fp16 *, __fp16 *, int, int, int); + + /* Kernel blocking parameters */ + static int out_width() + { + return svcnth() * 3; + } + + static int out_height() + { + return 8; + } + + static int k_unroll() + { + return 1; + } + + // Use the standard fixed size transforms. + StdTransformsSVE transforms = {}; + + kern_type kernel=sve_interleaved_fp16_mla_3VLx8; + + interleaved_fp16_mla_3VLx8(const CPUInfo *ci) + { + + } +}; + +} // namespace arm_gemm + +#endif // __ARM_FEATURE_SVE diff --git a/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp16_mla_3VLx8/generic.cpp b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp16_mla_3VLx8/generic.cpp new file mode 100644 index 0000000000..92ec888244 --- /dev/null +++ b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp16_mla_3VLx8/generic.cpp @@ -0,0 +1,324 @@ +/* + * Copyright (c) 2018 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifdef __ARM_FEATURE_SVE + + +#include "../../asmlib.hpp" + +namespace arm_gemm { + +void sve_interleaved_fp16_mla_3VLx8(const __fp16 *Apanel, const __fp16 *Bpanel, __fp16 *Cpanel, int ablocks, int bblocks, int K) { + const __fp16 *a_ptr = Apanel; + __fp16 *c_ptr = Cpanel; + + const long loops_count = (K / 2) - 1; + const long tails_count = K % 2; + + for (int yb=0; yb transforms = {}; + + kern_type kernel=sve_interleaved_fp32_mla_3VLx8; + + interleaved_fp32_mla_3VLx8(const CPUInfo *ci) + { + + } +}; + +} // namespace arm_gemm + +#endif // __ARM_FEATURE_SVE diff --git a/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp32_mla_3VLx8/generic.cpp b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp32_mla_3VLx8/generic.cpp new file mode 100644 index 0000000000..bb08fc7cb0 --- /dev/null +++ b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp32_mla_3VLx8/generic.cpp @@ -0,0 +1,333 @@ +/* + * Copyright (c) 2018 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifdef __ARM_FEATURE_SVE + + +#include "../../asmlib.hpp" + +namespace arm_gemm { + +void sve_interleaved_fp32_mla_3VLx8(const float *Apanel, const float *Bpanel, float *Cpanel, int ablocks, int bblocks, int K) { + const float *a_ptr = Apanel; + float *c_ptr = Cpanel; + + const long loops_count = (K / 2) - 1; + const long tails_count = K % 2; + + for (int yb=0; yb +#include "../std_transforms_sve.hpp" + +namespace arm_gemm { + +// Actual kernel implementations +void sve_interleaved_s8s32_dot_3VLx8(const int8_t *, const int8_t *, int32_t *, int, int, int); + +class interleaved_s8s32_dot_3VLx8 { +public: + typedef int8_t operand_type; + typedef int32_t result_type; + + typedef void (*kern_type)(const int8_t *, const int8_t *, int32_t *, int, int, int); + + /* Kernel blocking parameters */ + static int out_width() + { + return svcntw() * 3; + } + + static int out_height() + { + return 8; + } + + static int k_unroll() + { + return 4; + } + + // Use the standard fixed size transforms. + StdTransformsSVE transforms = {}; + + kern_type kernel=sve_interleaved_s8s32_dot_3VLx8; + + interleaved_s8s32_dot_3VLx8(const CPUInfo *ci) + { + + } +}; + +} // namespace arm_gemm + +#endif // __ARM_FEATURE_SVE diff --git a/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_s8s32_dot_3VLx8/generic.cpp b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_s8s32_dot_3VLx8/generic.cpp new file mode 100644 index 0000000000..2e994a13f3 --- /dev/null +++ b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_s8s32_dot_3VLx8/generic.cpp @@ -0,0 +1,334 @@ +/* + * Copyright (c) 2018 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifdef __ARM_FEATURE_SVE + +#include +#include "../../asmlib.hpp" + +namespace arm_gemm { + +void sve_interleaved_s8s32_dot_3VLx8(const int8_t *Apanel, const int8_t *Bpanel, int32_t *Cpanel, int ablocks, int bblocks, int K) { + const int8_t *a_ptr = Apanel; + int32_t *c_ptr = Cpanel; + + K /= 4; + const long loops_count = (K / 2) - 1; + const long tails_count = K % 2; + + for (int yb=0; yb +#include "../std_transforms_sve.hpp" + +namespace arm_gemm { + +// Actual kernel implementations +void sve_interleaved_u8u32_dot_3VLx8(const uint8_t *, const uint8_t *, uint32_t *, int, int, int); + +class interleaved_u8u32_dot_3VLx8 { +public: + typedef uint8_t operand_type; + typedef uint32_t result_type; + + typedef void (*kern_type)(const uint8_t *, const uint8_t *, uint32_t *, int, int, int); + + /* Kernel blocking parameters */ + static int out_width() + { + return svcntw() * 3; + } + + static int out_height() + { + return 8; + } + + static int k_unroll() + { + return 4; + } + + // Use the standard fixed size transforms. + StdTransformsSVE transforms = {}; + + kern_type kernel=sve_interleaved_u8u32_dot_3VLx8; + + interleaved_u8u32_dot_3VLx8(const CPUInfo *ci) + { + + } +}; + +} // namespace arm_gemm + +#endif // __ARM_FEATURE_SVE diff --git a/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_u8u32_dot_3VLx8/generic.cpp b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_u8u32_dot_3VLx8/generic.cpp new file mode 100644 index 0000000000..f4d33a9efa --- /dev/null +++ b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_u8u32_dot_3VLx8/generic.cpp @@ -0,0 +1,328 @@ +/* + * Copyright (c) 2018 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifdef __ARM_FEATURE_SVE + +#include +#include "../../asmlib.hpp" + +namespace arm_gemm { + +void sve_interleaved_u8u32_dot_3VLx8(const uint8_t *Apanel, const uint8_t *Bpanel, uint32_t *Cpanel, int ablocks, int bblocks, int K) { + const uint8_t *a_ptr = Apanel; + uint32_t *c_ptr = Cpanel; + + K /= 4; + const long loops_count = (K / 2) - 1; + const long tails_count = K % 2; + + for (int yb=0; yb transforms; + + kern_type kernel=sve_sgemm_3VLx8; + + sgemm_3VLx8(const CPUInfo *ci) { } +}; + +} // namespace arm_gemm + +#endif // __ARM_FEATURE_SVE diff --git a/src/core/NEON/kernels/arm_gemm/kernels/sve_sgemm_3VLx8/generic.cpp b/src/core/NEON/kernels/arm_gemm/kernels/sve_sgemm_3VLx8/generic.cpp new file mode 100644 index 0000000000..fd6f0b7f98 --- /dev/null +++ b/src/core/NEON/kernels/arm_gemm/kernels/sve_sgemm_3VLx8/generic.cpp @@ -0,0 +1,366 @@ +/* + * Copyright (c) 2017-2018 ARM Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifdef __ARM_FEATURE_SVE + +#include +#include + +#include "../../asmlib.hpp" + +// Kernel implementation. +// +// Assume that "Apanel" points to a chunk of A blocks (each size 8xK) in read-order. +// Assume that "Bpanel" points to a chunk of B blocks (each size 3VLxK) in read-order. +// Assume that "Cpanel" points to a chunk of C output blocks (each size +// 3VLx8), the chunks being arranged in a row major fashion. +// +// Note that the intent of this is that either ablocks or bblocks will be 1 +// - this construction allows the output loop to proceed in either order. + +namespace arm_gemm { + +void sve_sgemm_3VLx8(const float *Apanel, const float *Bpanel, float *Cpanel, int ablocks, int bblocks, int K) { + const float *a_ptr = Apanel; + float *c_ptr = Cpanel; + + // There's no predication inside the kernel, so get a true predicate to use everywhere. + svbool_t ptrue = svptrue_b32(); + + for (int yb=0; yb +inline void MergeResults<2, 8, true>(float *out, const float *in, const int ldout, const int y0, const int ymax, const int x0, const int xmax, const float alpha, const float beta) +{ + const float *inptr = in; + + for (int y=y0; y())) { + if (beta==0.0f) + { + switch(height) { + case 1: + { + long w = xmax - i; + long p = 0; + /* Optimized routine to copy an entire block */ + __asm __volatile ( + "mov z2.s, %s[alpha]\n" + "addvl x8, %[inptr], #16\n" + "mov z3.s, %s[beta]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z4.s, p0/z, [%[inptr]]\n" + "incw %[p], all, mul #1\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0]]\n" + "prfm PLDL1KEEP, [%[inptr], #0x100]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z5.s, p0/z, [%[inptr], #1, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr0], #0x40]\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr0], #1, MUL VL]\n" + "addvl %[outptr0], %[outptr0], #2\n" + "1:\n" + "addvl %[inptr], %[inptr], #16\n" + : [outptr0] "+r" (outptr0), [outptr1] "+r" (outptr1), [outptr2] "+r" (outptr2), [outptr3] "+r" (outptr3), [outptr4] "+r" (outptr4), [outptr5] "+r" (outptr5), [outptr6] "+r" (outptr6), [outptr7] "+r" (outptr7), + [inptr] "+r" (inptr), [p] "+r" (p) + : [alpha] "w" (alpha), [beta] "w" (beta), [w] "r" (w) + : "x8", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "memory", "cc" + ); + } + break; + + case 2: + { + long w = xmax - i; + long p = 0; + /* Optimized routine to copy an entire block */ + __asm __volatile ( + "mov z2.s, %s[alpha]\n" + "addvl x8, %[inptr], #16\n" + "mov z3.s, %s[beta]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z4.s, p0/z, [%[inptr]]\n" + "incw %[p], all, mul #1\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0]]\n" + "ld1w z5.s, p0/z, [%[inptr], #2, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x100]\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1]]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z6.s, p0/z, [%[inptr], #1, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr0], #0x40]\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr0], #1, MUL VL]\n" + "ld1w z7.s, p0/z, [%[inptr], #3, MUL VL]\n" + "addvl %[outptr0], %[outptr0], #2\n" + "fmul z11.s, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr1], #1, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr1], #0x40]\n" + "addvl %[outptr1], %[outptr1], #2\n" + "1:\n" + "addvl %[inptr], %[inptr], #16\n" + : [outptr0] "+r" (outptr0), [outptr1] "+r" (outptr1), [outptr2] "+r" (outptr2), [outptr3] "+r" (outptr3), [outptr4] "+r" (outptr4), [outptr5] "+r" (outptr5), [outptr6] "+r" (outptr6), [outptr7] "+r" (outptr7), + [inptr] "+r" (inptr), [p] "+r" (p) + : [alpha] "w" (alpha), [beta] "w" (beta), [w] "r" (w) + : "x8", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "memory", "cc" + ); + } + break; + + case 3: + { + long w = xmax - i; + long p = 0; + /* Optimized routine to copy an entire block */ + __asm __volatile ( + "mov z2.s, %s[alpha]\n" + "addvl x8, %[inptr], #16\n" + "mov z3.s, %s[beta]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z4.s, p0/z, [%[inptr]]\n" + "incw %[p], all, mul #1\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0]]\n" + "ld1w z5.s, p0/z, [%[inptr], #2, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x100]\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1]]\n" + "ld1w z6.s, p0/z, [%[inptr], #4, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x140]\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr2]]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z7.s, p0/z, [%[inptr], #1, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr0], #0x40]\n" + "fmul z11.s, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr0], #1, MUL VL]\n" + "ld1w z4.s, p0/z, [%[inptr], #3, MUL VL]\n" + "addvl %[outptr0], %[outptr0], #2\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr1], #1, MUL VL]\n" + "ld1w z5.s, p0/z, [%[inptr], #5, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr1], #0x40]\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr2], #1, MUL VL]\n" + "addvl %[outptr1], %[outptr1], #2\n" + "prfm PSTL1KEEP, [%[outptr2], #0x40]\n" + "addvl %[outptr2], %[outptr2], #2\n" + "1:\n" + "addvl %[inptr], %[inptr], #16\n" + : [outptr0] "+r" (outptr0), [outptr1] "+r" (outptr1), [outptr2] "+r" (outptr2), [outptr3] "+r" (outptr3), [outptr4] "+r" (outptr4), [outptr5] "+r" (outptr5), [outptr6] "+r" (outptr6), [outptr7] "+r" (outptr7), + [inptr] "+r" (inptr), [p] "+r" (p) + : [alpha] "w" (alpha), [beta] "w" (beta), [w] "r" (w) + : "x8", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "memory", "cc" + ); + } + break; + + case 4: + { + long w = xmax - i; + long p = 0; + /* Optimized routine to copy an entire block */ + __asm __volatile ( + "mov z2.s, %s[alpha]\n" + "addvl x8, %[inptr], #16\n" + "mov z3.s, %s[beta]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z4.s, p0/z, [%[inptr]]\n" + "incw %[p], all, mul #1\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0]]\n" + "ld1w z5.s, p0/z, [%[inptr], #2, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x100]\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1]]\n" + "ld1w z6.s, p0/z, [%[inptr], #4, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x140]\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr2]]\n" + "ld1w z7.s, p0/z, [%[inptr], #6, MUL VL]\n" + "fmul z11.s, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr3]]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z4.s, p0/z, [%[inptr], #1, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr0], #0x40]\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0], #1, MUL VL]\n" + "ld1w z5.s, p0/z, [%[inptr], #3, MUL VL]\n" + "addvl %[outptr0], %[outptr0], #2\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1], #1, MUL VL]\n" + "ld1w z6.s, p0/z, [%[inptr], #5, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr1], #0x40]\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr2], #1, MUL VL]\n" + "ld1w z7.s, p0/z, [%[inptr], #7, MUL VL]\n" + "addvl %[outptr1], %[outptr1], #2\n" + "fmul z11.s, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr3], #1, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr2], #0x40]\n" + "addvl %[outptr2], %[outptr2], #2\n" + "prfm PSTL1KEEP, [%[outptr3], #0x40]\n" + "addvl %[outptr3], %[outptr3], #2\n" + "1:\n" + "addvl %[inptr], %[inptr], #16\n" + : [outptr0] "+r" (outptr0), [outptr1] "+r" (outptr1), [outptr2] "+r" (outptr2), [outptr3] "+r" (outptr3), [outptr4] "+r" (outptr4), [outptr5] "+r" (outptr5), [outptr6] "+r" (outptr6), [outptr7] "+r" (outptr7), + [inptr] "+r" (inptr), [p] "+r" (p) + : [alpha] "w" (alpha), [beta] "w" (beta), [w] "r" (w) + : "x8", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "memory", "cc" + ); + } + break; + + case 5: + { + long w = xmax - i; + long p = 0; + /* Optimized routine to copy an entire block */ + __asm __volatile ( + "mov z2.s, %s[alpha]\n" + "addvl x8, %[inptr], #16\n" + "mov z3.s, %s[beta]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z4.s, p0/z, [%[inptr]]\n" + "incw %[p], all, mul #1\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0]]\n" + "ld1w z5.s, p0/z, [%[inptr], #2, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x100]\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1]]\n" + "ld1w z6.s, p0/z, [%[inptr], #4, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x140]\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr2]]\n" + "ld1w z7.s, p0/z, [%[inptr], #6, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x180]\n" + "fmul z11.s, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr3]]\n" + "ld1w z4.s, p0/z, [x8, #-8, MUL VL]\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr4]]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z5.s, p0/z, [%[inptr], #1, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr0], #0x40]\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr0], #1, MUL VL]\n" + "ld1w z6.s, p0/z, [%[inptr], #3, MUL VL]\n" + "addvl %[outptr0], %[outptr0], #2\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr1], #1, MUL VL]\n" + "ld1w z7.s, p0/z, [%[inptr], #5, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr1], #0x40]\n" + "fmul z11.s, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr2], #1, MUL VL]\n" + "ld1w z4.s, p0/z, [%[inptr], #7, MUL VL]\n" + "addvl %[outptr1], %[outptr1], #2\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr3], #1, MUL VL]\n" + "ld1w z5.s, p0/z, [x8, #-7, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr2], #0x40]\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr4], #1, MUL VL]\n" + "addvl %[outptr2], %[outptr2], #2\n" + "prfm PSTL1KEEP, [%[outptr3], #0x40]\n" + "addvl %[outptr3], %[outptr3], #2\n" + "prfm PSTL1KEEP, [%[outptr4], #0x40]\n" + "addvl %[outptr4], %[outptr4], #2\n" + "1:\n" + "addvl %[inptr], %[inptr], #16\n" + : [outptr0] "+r" (outptr0), [outptr1] "+r" (outptr1), [outptr2] "+r" (outptr2), [outptr3] "+r" (outptr3), [outptr4] "+r" (outptr4), [outptr5] "+r" (outptr5), [outptr6] "+r" (outptr6), [outptr7] "+r" (outptr7), + [inptr] "+r" (inptr), [p] "+r" (p) + : [alpha] "w" (alpha), [beta] "w" (beta), [w] "r" (w) + : "x8", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "memory", "cc" + ); + } + break; + + case 6: + { + long w = xmax - i; + long p = 0; + /* Optimized routine to copy an entire block */ + __asm __volatile ( + "mov z2.s, %s[alpha]\n" + "addvl x8, %[inptr], #16\n" + "mov z3.s, %s[beta]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z4.s, p0/z, [%[inptr]]\n" + "incw %[p], all, mul #1\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0]]\n" + "ld1w z5.s, p0/z, [%[inptr], #2, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x100]\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1]]\n" + "ld1w z6.s, p0/z, [%[inptr], #4, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x140]\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr2]]\n" + "ld1w z7.s, p0/z, [%[inptr], #6, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x180]\n" + "fmul z11.s, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr3]]\n" + "ld1w z4.s, p0/z, [x8, #-8, MUL VL]\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr4]]\n" + "ld1w z5.s, p0/z, [x8, #-6, MUL VL]\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr5]]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z6.s, p0/z, [%[inptr], #1, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr0], #0x40]\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr0], #1, MUL VL]\n" + "ld1w z7.s, p0/z, [%[inptr], #3, MUL VL]\n" + "addvl %[outptr0], %[outptr0], #2\n" + "fmul z11.s, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr1], #1, MUL VL]\n" + "ld1w z4.s, p0/z, [%[inptr], #5, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr1], #0x40]\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr2], #1, MUL VL]\n" + "ld1w z5.s, p0/z, [%[inptr], #7, MUL VL]\n" + "addvl %[outptr1], %[outptr1], #2\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr3], #1, MUL VL]\n" + "ld1w z6.s, p0/z, [x8, #-7, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr2], #0x40]\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr4], #1, MUL VL]\n" + "ld1w z7.s, p0/z, [x8, #-5, MUL VL]\n" + "addvl %[outptr2], %[outptr2], #2\n" + "fmul z11.s, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr5], #1, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr3], #0x40]\n" + "addvl %[outptr3], %[outptr3], #2\n" + "prfm PSTL1KEEP, [%[outptr4], #0x40]\n" + "addvl %[outptr4], %[outptr4], #2\n" + "prfm PSTL1KEEP, [%[outptr5], #0x40]\n" + "addvl %[outptr5], %[outptr5], #2\n" + "1:\n" + "addvl %[inptr], %[inptr], #16\n" + : [outptr0] "+r" (outptr0), [outptr1] "+r" (outptr1), [outptr2] "+r" (outptr2), [outptr3] "+r" (outptr3), [outptr4] "+r" (outptr4), [outptr5] "+r" (outptr5), [outptr6] "+r" (outptr6), [outptr7] "+r" (outptr7), + [inptr] "+r" (inptr), [p] "+r" (p) + : [alpha] "w" (alpha), [beta] "w" (beta), [w] "r" (w) + : "x8", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "memory", "cc" + ); + } + break; + + case 7: + { + long w = xmax - i; + long p = 0; + /* Optimized routine to copy an entire block */ + __asm __volatile ( + "mov z2.s, %s[alpha]\n" + "addvl x8, %[inptr], #16\n" + "mov z3.s, %s[beta]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z4.s, p0/z, [%[inptr]]\n" + "incw %[p], all, mul #1\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0]]\n" + "ld1w z5.s, p0/z, [%[inptr], #2, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x100]\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1]]\n" + "ld1w z6.s, p0/z, [%[inptr], #4, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x140]\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr2]]\n" + "ld1w z7.s, p0/z, [%[inptr], #6, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x180]\n" + "fmul z11.s, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr3]]\n" + "ld1w z4.s, p0/z, [x8, #-8, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x1c0]\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr4]]\n" + "ld1w z5.s, p0/z, [x8, #-6, MUL VL]\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr5]]\n" + "ld1w z6.s, p0/z, [x8, #-4, MUL VL]\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr6]]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z7.s, p0/z, [%[inptr], #1, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr0], #0x40]\n" + "fmul z11.s, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr0], #1, MUL VL]\n" + "ld1w z4.s, p0/z, [%[inptr], #3, MUL VL]\n" + "addvl %[outptr0], %[outptr0], #2\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr1], #1, MUL VL]\n" + "ld1w z5.s, p0/z, [%[inptr], #5, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr1], #0x40]\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr2], #1, MUL VL]\n" + "ld1w z6.s, p0/z, [%[inptr], #7, MUL VL]\n" + "addvl %[outptr1], %[outptr1], #2\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr3], #1, MUL VL]\n" + "ld1w z7.s, p0/z, [x8, #-7, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr2], #0x40]\n" + "fmul z11.s, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr4], #1, MUL VL]\n" + "ld1w z4.s, p0/z, [x8, #-5, MUL VL]\n" + "addvl %[outptr2], %[outptr2], #2\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr5], #1, MUL VL]\n" + "ld1w z5.s, p0/z, [x8, #-3, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr3], #0x40]\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr6], #1, MUL VL]\n" + "addvl %[outptr3], %[outptr3], #2\n" + "prfm PSTL1KEEP, [%[outptr4], #0x40]\n" + "addvl %[outptr4], %[outptr4], #2\n" + "prfm PSTL1KEEP, [%[outptr5], #0x40]\n" + "addvl %[outptr5], %[outptr5], #2\n" + "prfm PSTL1KEEP, [%[outptr6], #0x40]\n" + "addvl %[outptr6], %[outptr6], #2\n" + "1:\n" + "addvl %[inptr], %[inptr], #16\n" + : [outptr0] "+r" (outptr0), [outptr1] "+r" (outptr1), [outptr2] "+r" (outptr2), [outptr3] "+r" (outptr3), [outptr4] "+r" (outptr4), [outptr5] "+r" (outptr5), [outptr6] "+r" (outptr6), [outptr7] "+r" (outptr7), + [inptr] "+r" (inptr), [p] "+r" (p) + : [alpha] "w" (alpha), [beta] "w" (beta), [w] "r" (w) + : "x8", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "memory", "cc" + ); + } + break; + + default: + case 8: + { + long w = xmax - i; + long p = 0; + /* Optimized routine to copy an entire block */ + __asm __volatile ( + "mov z2.s, %s[alpha]\n" + "addvl x8, %[inptr], #16\n" + "mov z3.s, %s[beta]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z4.s, p0/z, [%[inptr]]\n" + "incw %[p], all, mul #1\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0]]\n" + "ld1w z5.s, p0/z, [%[inptr], #2, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x100]\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1]]\n" + "ld1w z6.s, p0/z, [%[inptr], #4, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x140]\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr2]]\n" + "ld1w z7.s, p0/z, [%[inptr], #6, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x180]\n" + "fmul z11.s, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr3]]\n" + "ld1w z4.s, p0/z, [x8, #-8, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x1c0]\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr4]]\n" + "ld1w z5.s, p0/z, [x8, #-6, MUL VL]\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr5]]\n" + "ld1w z6.s, p0/z, [x8, #-4, MUL VL]\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr6]]\n" + "ld1w z7.s, p0/z, [x8, #-2, MUL VL]\n" + "fmul z11.s, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr7]]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z4.s, p0/z, [%[inptr], #1, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr0], #0x40]\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0], #1, MUL VL]\n" + "ld1w z5.s, p0/z, [%[inptr], #3, MUL VL]\n" + "addvl %[outptr0], %[outptr0], #2\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1], #1, MUL VL]\n" + "ld1w z6.s, p0/z, [%[inptr], #5, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr1], #0x40]\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr2], #1, MUL VL]\n" + "ld1w z7.s, p0/z, [%[inptr], #7, MUL VL]\n" + "addvl %[outptr1], %[outptr1], #2\n" + "fmul z11.s, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr3], #1, MUL VL]\n" + "ld1w z4.s, p0/z, [x8, #-7, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr2], #0x40]\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr4], #1, MUL VL]\n" + "ld1w z5.s, p0/z, [x8, #-5, MUL VL]\n" + "addvl %[outptr2], %[outptr2], #2\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr5], #1, MUL VL]\n" + "ld1w z6.s, p0/z, [x8, #-3, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr3], #0x40]\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr6], #1, MUL VL]\n" + "ld1w z7.s, p0/z, [x8, #-1, MUL VL]\n" + "addvl %[outptr3], %[outptr3], #2\n" + "fmul z11.s, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr7], #1, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr4], #0x40]\n" + "addvl %[outptr4], %[outptr4], #2\n" + "prfm PSTL1KEEP, [%[outptr5], #0x40]\n" + "addvl %[outptr5], %[outptr5], #2\n" + "prfm PSTL1KEEP, [%[outptr6], #0x40]\n" + "addvl %[outptr6], %[outptr6], #2\n" + "prfm PSTL1KEEP, [%[outptr7], #0x40]\n" + "addvl %[outptr7], %[outptr7], #2\n" + "1:\n" + "addvl %[inptr], %[inptr], #16\n" + : [outptr0] "+r" (outptr0), [outptr1] "+r" (outptr1), [outptr2] "+r" (outptr2), [outptr3] "+r" (outptr3), [outptr4] "+r" (outptr4), [outptr5] "+r" (outptr5), [outptr6] "+r" (outptr6), [outptr7] "+r" (outptr7), + [inptr] "+r" (inptr), [p] "+r" (p) + : [alpha] "w" (alpha), [beta] "w" (beta), [w] "r" (w) + : "x8", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "memory", "cc" + ); + } + break; + + + } + } + else + { + switch(height) { + case 1: + { + long w = xmax - i; + long p = 0; + /* Optimized routine to copy an entire block */ + __asm __volatile ( + "mov z2.s, %s[alpha]\n" + "addvl x8, %[inptr], #16\n" + "mov z3.s, %s[beta]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z8.s, p0/z, [%[outptr0]]\n" + "incw %[p], all, mul #1\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [%[inptr]]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0]]\n" + "prfm PLDL1KEEP, [%[inptr], #0x100]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z9.s, p0/z, [%[outptr0], #1, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr0], #0x40]\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [%[inptr], #1, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr0], #1, MUL VL]\n" + "addvl %[outptr0], %[outptr0], #2\n" + "1:\n" + "addvl %[inptr], %[inptr], #16\n" + : [outptr0] "+r" (outptr0), [outptr1] "+r" (outptr1), [outptr2] "+r" (outptr2), [outptr3] "+r" (outptr3), [outptr4] "+r" (outptr4), [outptr5] "+r" (outptr5), [outptr6] "+r" (outptr6), [outptr7] "+r" (outptr7), + [inptr] "+r" (inptr), [p] "+r" (p) + : [alpha] "w" (alpha), [beta] "w" (beta), [w] "r" (w) + : "x8", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "memory", "cc" + ); + } + break; + + case 2: + { + long w = xmax - i; + long p = 0; + /* Optimized routine to copy an entire block */ + __asm __volatile ( + "mov z2.s, %s[alpha]\n" + "addvl x8, %[inptr], #16\n" + "mov z3.s, %s[beta]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z8.s, p0/z, [%[outptr0]]\n" + "incw %[p], all, mul #1\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [%[inptr]]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0]]\n" + "ld1w z9.s, p0/z, [%[outptr1]]\n" + "prfm PLDL1KEEP, [%[inptr], #0x100]\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [%[inptr], #2, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1]]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z10.s, p0/z, [%[outptr0], #1, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr0], #0x40]\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [%[inptr], #1, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr0], #1, MUL VL]\n" + "ld1w z11.s, p0/z, [%[outptr1], #1, MUL VL]\n" + "addvl %[outptr0], %[outptr0], #2\n" + "fmul z11.s, z11.s, z3.s\n" + "ld1w z7.s, p0/z, [%[inptr], #3, MUL VL]\n" + "fmla z11.s, p0/m, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr1], #1, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr1], #0x40]\n" + "addvl %[outptr1], %[outptr1], #2\n" + "1:\n" + "addvl %[inptr], %[inptr], #16\n" + : [outptr0] "+r" (outptr0), [outptr1] "+r" (outptr1), [outptr2] "+r" (outptr2), [outptr3] "+r" (outptr3), [outptr4] "+r" (outptr4), [outptr5] "+r" (outptr5), [outptr6] "+r" (outptr6), [outptr7] "+r" (outptr7), + [inptr] "+r" (inptr), [p] "+r" (p) + : [alpha] "w" (alpha), [beta] "w" (beta), [w] "r" (w) + : "x8", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "memory", "cc" + ); + } + break; + + case 3: + { + long w = xmax - i; + long p = 0; + /* Optimized routine to copy an entire block */ + __asm __volatile ( + "mov z2.s, %s[alpha]\n" + "addvl x8, %[inptr], #16\n" + "mov z3.s, %s[beta]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z8.s, p0/z, [%[outptr0]]\n" + "incw %[p], all, mul #1\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [%[inptr]]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0]]\n" + "ld1w z9.s, p0/z, [%[outptr1]]\n" + "prfm PLDL1KEEP, [%[inptr], #0x100]\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [%[inptr], #2, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1]]\n" + "ld1w z10.s, p0/z, [%[outptr2]]\n" + "prfm PLDL1KEEP, [%[inptr], #0x140]\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [%[inptr], #4, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr2]]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z11.s, p0/z, [%[outptr0], #1, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr0], #0x40]\n" + "fmul z11.s, z11.s, z3.s\n" + "ld1w z7.s, p0/z, [%[inptr], #1, MUL VL]\n" + "fmla z11.s, p0/m, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr0], #1, MUL VL]\n" + "ld1w z8.s, p0/z, [%[outptr1], #1, MUL VL]\n" + "addvl %[outptr0], %[outptr0], #2\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [%[inptr], #3, MUL VL]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr1], #1, MUL VL]\n" + "ld1w z9.s, p0/z, [%[outptr2], #1, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr1], #0x40]\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [%[inptr], #5, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr2], #1, MUL VL]\n" + "addvl %[outptr1], %[outptr1], #2\n" + "prfm PLDL1KEEP, [%[outptr2], #0x40]\n" + "addvl %[outptr2], %[outptr2], #2\n" + "1:\n" + "addvl %[inptr], %[inptr], #16\n" + : [outptr0] "+r" (outptr0), [outptr1] "+r" (outptr1), [outptr2] "+r" (outptr2), [outptr3] "+r" (outptr3), [outptr4] "+r" (outptr4), [outptr5] "+r" (outptr5), [outptr6] "+r" (outptr6), [outptr7] "+r" (outptr7), + [inptr] "+r" (inptr), [p] "+r" (p) + : [alpha] "w" (alpha), [beta] "w" (beta), [w] "r" (w) + : "x8", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "memory", "cc" + ); + } + break; + + case 4: + { + long w = xmax - i; + long p = 0; + /* Optimized routine to copy an entire block */ + __asm __volatile ( + "mov z2.s, %s[alpha]\n" + "addvl x8, %[inptr], #16\n" + "mov z3.s, %s[beta]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z8.s, p0/z, [%[outptr0]]\n" + "incw %[p], all, mul #1\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [%[inptr]]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0]]\n" + "ld1w z9.s, p0/z, [%[outptr1]]\n" + "prfm PLDL1KEEP, [%[inptr], #0x100]\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [%[inptr], #2, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1]]\n" + "ld1w z10.s, p0/z, [%[outptr2]]\n" + "prfm PLDL1KEEP, [%[inptr], #0x140]\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [%[inptr], #4, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr2]]\n" + "ld1w z11.s, p0/z, [%[outptr3]]\n" + "fmul z11.s, z11.s, z3.s\n" + "ld1w z7.s, p0/z, [%[inptr], #6, MUL VL]\n" + "fmla z11.s, p0/m, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr3]]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z8.s, p0/z, [%[outptr0], #1, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr0], #0x40]\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [%[inptr], #1, MUL VL]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0], #1, MUL VL]\n" + "ld1w z9.s, p0/z, [%[outptr1], #1, MUL VL]\n" + "addvl %[outptr0], %[outptr0], #2\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [%[inptr], #3, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1], #1, MUL VL]\n" + "ld1w z10.s, p0/z, [%[outptr2], #1, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr1], #0x40]\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [%[inptr], #5, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr2], #1, MUL VL]\n" + "ld1w z11.s, p0/z, [%[outptr3], #1, MUL VL]\n" + "addvl %[outptr1], %[outptr1], #2\n" + "fmul z11.s, z11.s, z3.s\n" + "ld1w z7.s, p0/z, [%[inptr], #7, MUL VL]\n" + "fmla z11.s, p0/m, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr3], #1, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr2], #0x40]\n" + "addvl %[outptr2], %[outptr2], #2\n" + "prfm PLDL1KEEP, [%[outptr3], #0x40]\n" + "addvl %[outptr3], %[outptr3], #2\n" + "1:\n" + "addvl %[inptr], %[inptr], #16\n" + : [outptr0] "+r" (outptr0), [outptr1] "+r" (outptr1), [outptr2] "+r" (outptr2), [outptr3] "+r" (outptr3), [outptr4] "+r" (outptr4), [outptr5] "+r" (outptr5), [outptr6] "+r" (outptr6), [outptr7] "+r" (outptr7), + [inptr] "+r" (inptr), [p] "+r" (p) + : [alpha] "w" (alpha), [beta] "w" (beta), [w] "r" (w) + : "x8", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "memory", "cc" + ); + } + break; + + case 5: + { + long w = xmax - i; + long p = 0; + /* Optimized routine to copy an entire block */ + __asm __volatile ( + "mov z2.s, %s[alpha]\n" + "addvl x8, %[inptr], #16\n" + "mov z3.s, %s[beta]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z8.s, p0/z, [%[outptr0]]\n" + "incw %[p], all, mul #1\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [%[inptr]]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0]]\n" + "ld1w z9.s, p0/z, [%[outptr1]]\n" + "prfm PLDL1KEEP, [%[inptr], #0x100]\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [%[inptr], #2, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1]]\n" + "ld1w z10.s, p0/z, [%[outptr2]]\n" + "prfm PLDL1KEEP, [%[inptr], #0x140]\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [%[inptr], #4, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr2]]\n" + "ld1w z11.s, p0/z, [%[outptr3]]\n" + "prfm PLDL1KEEP, [%[inptr], #0x180]\n" + "fmul z11.s, z11.s, z3.s\n" + "ld1w z7.s, p0/z, [%[inptr], #6, MUL VL]\n" + "fmla z11.s, p0/m, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr3]]\n" + "ld1w z8.s, p0/z, [%[outptr4]]\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [x8, #-8, MUL VL]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr4]]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z9.s, p0/z, [%[outptr0], #1, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr0], #0x40]\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [%[inptr], #1, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr0], #1, MUL VL]\n" + "ld1w z10.s, p0/z, [%[outptr1], #1, MUL VL]\n" + "addvl %[outptr0], %[outptr0], #2\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [%[inptr], #3, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr1], #1, MUL VL]\n" + "ld1w z11.s, p0/z, [%[outptr2], #1, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr1], #0x40]\n" + "fmul z11.s, z11.s, z3.s\n" + "ld1w z7.s, p0/z, [%[inptr], #5, MUL VL]\n" + "fmla z11.s, p0/m, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr2], #1, MUL VL]\n" + "ld1w z8.s, p0/z, [%[outptr3], #1, MUL VL]\n" + "addvl %[outptr1], %[outptr1], #2\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [%[inptr], #7, MUL VL]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr3], #1, MUL VL]\n" + "ld1w z9.s, p0/z, [%[outptr4], #1, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr2], #0x40]\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [x8, #-7, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr4], #1, MUL VL]\n" + "addvl %[outptr2], %[outptr2], #2\n" + "prfm PLDL1KEEP, [%[outptr3], #0x40]\n" + "addvl %[outptr3], %[outptr3], #2\n" + "prfm PLDL1KEEP, [%[outptr4], #0x40]\n" + "addvl %[outptr4], %[outptr4], #2\n" + "1:\n" + "addvl %[inptr], %[inptr], #16\n" + : [outptr0] "+r" (outptr0), [outptr1] "+r" (outptr1), [outptr2] "+r" (outptr2), [outptr3] "+r" (outptr3), [outptr4] "+r" (outptr4), [outptr5] "+r" (outptr5), [outptr6] "+r" (outptr6), [outptr7] "+r" (outptr7), + [inptr] "+r" (inptr), [p] "+r" (p) + : [alpha] "w" (alpha), [beta] "w" (beta), [w] "r" (w) + : "x8", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "memory", "cc" + ); + } + break; + + case 6: + { + long w = xmax - i; + long p = 0; + /* Optimized routine to copy an entire block */ + __asm __volatile ( + "mov z2.s, %s[alpha]\n" + "addvl x8, %[inptr], #16\n" + "mov z3.s, %s[beta]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z8.s, p0/z, [%[outptr0]]\n" + "incw %[p], all, mul #1\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [%[inptr]]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0]]\n" + "ld1w z9.s, p0/z, [%[outptr1]]\n" + "prfm PLDL1KEEP, [%[inptr], #0x100]\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [%[inptr], #2, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1]]\n" + "ld1w z10.s, p0/z, [%[outptr2]]\n" + "prfm PLDL1KEEP, [%[inptr], #0x140]\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [%[inptr], #4, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr2]]\n" + "ld1w z11.s, p0/z, [%[outptr3]]\n" + "prfm PLDL1KEEP, [%[inptr], #0x180]\n" + "fmul z11.s, z11.s, z3.s\n" + "ld1w z7.s, p0/z, [%[inptr], #6, MUL VL]\n" + "fmla z11.s, p0/m, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr3]]\n" + "ld1w z8.s, p0/z, [%[outptr4]]\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [x8, #-8, MUL VL]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr4]]\n" + "ld1w z9.s, p0/z, [%[outptr5]]\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [x8, #-6, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr5]]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z10.s, p0/z, [%[outptr0], #1, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr0], #0x40]\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [%[inptr], #1, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr0], #1, MUL VL]\n" + "ld1w z11.s, p0/z, [%[outptr1], #1, MUL VL]\n" + "addvl %[outptr0], %[outptr0], #2\n" + "fmul z11.s, z11.s, z3.s\n" + "ld1w z7.s, p0/z, [%[inptr], #3, MUL VL]\n" + "fmla z11.s, p0/m, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr1], #1, MUL VL]\n" + "ld1w z8.s, p0/z, [%[outptr2], #1, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr1], #0x40]\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [%[inptr], #5, MUL VL]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr2], #1, MUL VL]\n" + "ld1w z9.s, p0/z, [%[outptr3], #1, MUL VL]\n" + "addvl %[outptr1], %[outptr1], #2\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [%[inptr], #7, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr3], #1, MUL VL]\n" + "ld1w z10.s, p0/z, [%[outptr4], #1, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr2], #0x40]\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [x8, #-7, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr4], #1, MUL VL]\n" + "ld1w z11.s, p0/z, [%[outptr5], #1, MUL VL]\n" + "addvl %[outptr2], %[outptr2], #2\n" + "fmul z11.s, z11.s, z3.s\n" + "ld1w z7.s, p0/z, [x8, #-5, MUL VL]\n" + "fmla z11.s, p0/m, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr5], #1, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr3], #0x40]\n" + "addvl %[outptr3], %[outptr3], #2\n" + "prfm PLDL1KEEP, [%[outptr4], #0x40]\n" + "addvl %[outptr4], %[outptr4], #2\n" + "prfm PLDL1KEEP, [%[outptr5], #0x40]\n" + "addvl %[outptr5], %[outptr5], #2\n" + "1:\n" + "addvl %[inptr], %[inptr], #16\n" + : [outptr0] "+r" (outptr0), [outptr1] "+r" (outptr1), [outptr2] "+r" (outptr2), [outptr3] "+r" (outptr3), [outptr4] "+r" (outptr4), [outptr5] "+r" (outptr5), [outptr6] "+r" (outptr6), [outptr7] "+r" (outptr7), + [inptr] "+r" (inptr), [p] "+r" (p) + : [alpha] "w" (alpha), [beta] "w" (beta), [w] "r" (w) + : "x8", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "memory", "cc" + ); + } + break; + + case 7: + { + long w = xmax - i; + long p = 0; + /* Optimized routine to copy an entire block */ + __asm __volatile ( + "mov z2.s, %s[alpha]\n" + "addvl x8, %[inptr], #16\n" + "mov z3.s, %s[beta]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z8.s, p0/z, [%[outptr0]]\n" + "incw %[p], all, mul #1\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [%[inptr]]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0]]\n" + "ld1w z9.s, p0/z, [%[outptr1]]\n" + "prfm PLDL1KEEP, [%[inptr], #0x100]\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [%[inptr], #2, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1]]\n" + "ld1w z10.s, p0/z, [%[outptr2]]\n" + "prfm PLDL1KEEP, [%[inptr], #0x140]\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [%[inptr], #4, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr2]]\n" + "ld1w z11.s, p0/z, [%[outptr3]]\n" + "prfm PLDL1KEEP, [%[inptr], #0x180]\n" + "fmul z11.s, z11.s, z3.s\n" + "ld1w z7.s, p0/z, [%[inptr], #6, MUL VL]\n" + "fmla z11.s, p0/m, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr3]]\n" + "ld1w z8.s, p0/z, [%[outptr4]]\n" + "prfm PLDL1KEEP, [%[inptr], #0x1c0]\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [x8, #-8, MUL VL]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr4]]\n" + "ld1w z9.s, p0/z, [%[outptr5]]\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [x8, #-6, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr5]]\n" + "ld1w z10.s, p0/z, [%[outptr6]]\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [x8, #-4, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr6]]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z11.s, p0/z, [%[outptr0], #1, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr0], #0x40]\n" + "fmul z11.s, z11.s, z3.s\n" + "ld1w z7.s, p0/z, [%[inptr], #1, MUL VL]\n" + "fmla z11.s, p0/m, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr0], #1, MUL VL]\n" + "ld1w z8.s, p0/z, [%[outptr1], #1, MUL VL]\n" + "addvl %[outptr0], %[outptr0], #2\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [%[inptr], #3, MUL VL]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr1], #1, MUL VL]\n" + "ld1w z9.s, p0/z, [%[outptr2], #1, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr1], #0x40]\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [%[inptr], #5, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr2], #1, MUL VL]\n" + "ld1w z10.s, p0/z, [%[outptr3], #1, MUL VL]\n" + "addvl %[outptr1], %[outptr1], #2\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [%[inptr], #7, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr3], #1, MUL VL]\n" + "ld1w z11.s, p0/z, [%[outptr4], #1, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr2], #0x40]\n" + "fmul z11.s, z11.s, z3.s\n" + "ld1w z7.s, p0/z, [x8, #-7, MUL VL]\n" + "fmla z11.s, p0/m, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr4], #1, MUL VL]\n" + "ld1w z8.s, p0/z, [%[outptr5], #1, MUL VL]\n" + "addvl %[outptr2], %[outptr2], #2\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [x8, #-5, MUL VL]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr5], #1, MUL VL]\n" + "ld1w z9.s, p0/z, [%[outptr6], #1, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr3], #0x40]\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [x8, #-3, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr6], #1, MUL VL]\n" + "addvl %[outptr3], %[outptr3], #2\n" + "prfm PLDL1KEEP, [%[outptr4], #0x40]\n" + "addvl %[outptr4], %[outptr4], #2\n" + "prfm PLDL1KEEP, [%[outptr5], #0x40]\n" + "addvl %[outptr5], %[outptr5], #2\n" + "prfm PLDL1KEEP, [%[outptr6], #0x40]\n" + "addvl %[outptr6], %[outptr6], #2\n" + "1:\n" + "addvl %[inptr], %[inptr], #16\n" + : [outptr0] "+r" (outptr0), [outptr1] "+r" (outptr1), [outptr2] "+r" (outptr2), [outptr3] "+r" (outptr3), [outptr4] "+r" (outptr4), [outptr5] "+r" (outptr5), [outptr6] "+r" (outptr6), [outptr7] "+r" (outptr7), + [inptr] "+r" (inptr), [p] "+r" (p) + : [alpha] "w" (alpha), [beta] "w" (beta), [w] "r" (w) + : "x8", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "memory", "cc" + ); + } + break; + + default: + case 8: + { + long w = xmax - i; + long p = 0; + /* Optimized routine to copy an entire block */ + __asm __volatile ( + "mov z2.s, %s[alpha]\n" + "addvl x8, %[inptr], #16\n" + "mov z3.s, %s[beta]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z8.s, p0/z, [%[outptr0]]\n" + "incw %[p], all, mul #1\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [%[inptr]]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0]]\n" + "ld1w z9.s, p0/z, [%[outptr1]]\n" + "prfm PLDL1KEEP, [%[inptr], #0x100]\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [%[inptr], #2, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1]]\n" + "ld1w z10.s, p0/z, [%[outptr2]]\n" + "prfm PLDL1KEEP, [%[inptr], #0x140]\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [%[inptr], #4, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr2]]\n" + "ld1w z11.s, p0/z, [%[outptr3]]\n" + "prfm PLDL1KEEP, [%[inptr], #0x180]\n" + "fmul z11.s, z11.s, z3.s\n" + "ld1w z7.s, p0/z, [%[inptr], #6, MUL VL]\n" + "fmla z11.s, p0/m, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr3]]\n" + "ld1w z8.s, p0/z, [%[outptr4]]\n" + "prfm PLDL1KEEP, [%[inptr], #0x1c0]\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [x8, #-8, MUL VL]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr4]]\n" + "ld1w z9.s, p0/z, [%[outptr5]]\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [x8, #-6, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr5]]\n" + "ld1w z10.s, p0/z, [%[outptr6]]\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [x8, #-4, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr6]]\n" + "ld1w z11.s, p0/z, [%[outptr7]]\n" + "fmul z11.s, z11.s, z3.s\n" + "ld1w z7.s, p0/z, [x8, #-2, MUL VL]\n" + "fmla z11.s, p0/m, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr7]]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z8.s, p0/z, [%[outptr0], #1, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr0], #0x40]\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [%[inptr], #1, MUL VL]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0], #1, MUL VL]\n" + "ld1w z9.s, p0/z, [%[outptr1], #1, MUL VL]\n" + "addvl %[outptr0], %[outptr0], #2\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [%[inptr], #3, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1], #1, MUL VL]\n" + "ld1w z10.s, p0/z, [%[outptr2], #1, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr1], #0x40]\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [%[inptr], #5, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr2], #1, MUL VL]\n" + "ld1w z11.s, p0/z, [%[outptr3], #1, MUL VL]\n" + "addvl %[outptr1], %[outptr1], #2\n" + "fmul z11.s, z11.s, z3.s\n" + "ld1w z7.s, p0/z, [%[inptr], #7, MUL VL]\n" + "fmla z11.s, p0/m, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr3], #1, MUL VL]\n" + "ld1w z8.s, p0/z, [%[outptr4], #1, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr2], #0x40]\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [x8, #-7, MUL VL]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr4], #1, MUL VL]\n" + "ld1w z9.s, p0/z, [%[outptr5], #1, MUL VL]\n" + "addvl %[outptr2], %[outptr2], #2\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [x8, #-5, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr5], #1, MUL VL]\n" + "ld1w z10.s, p0/z, [%[outptr6], #1, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr3], #0x40]\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [x8, #-3, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr6], #1, MUL VL]\n" + "ld1w z11.s, p0/z, [%[outptr7], #1, MUL VL]\n" + "addvl %[outptr3], %[outptr3], #2\n" + "fmul z11.s, z11.s, z3.s\n" + "ld1w z7.s, p0/z, [x8, #-1, MUL VL]\n" + "fmla z11.s, p0/m, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr7], #1, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr4], #0x40]\n" + "addvl %[outptr4], %[outptr4], #2\n" + "prfm PLDL1KEEP, [%[outptr5], #0x40]\n" + "addvl %[outptr5], %[outptr5], #2\n" + "prfm PLDL1KEEP, [%[outptr6], #0x40]\n" + "addvl %[outptr6], %[outptr6], #2\n" + "prfm PLDL1KEEP, [%[outptr7], #0x40]\n" + "addvl %[outptr7], %[outptr7], #2\n" + "1:\n" + "addvl %[inptr], %[inptr], #16\n" + : [outptr0] "+r" (outptr0), [outptr1] "+r" (outptr1), [outptr2] "+r" (outptr2), [outptr3] "+r" (outptr3), [outptr4] "+r" (outptr4), [outptr5] "+r" (outptr5), [outptr6] "+r" (outptr6), [outptr7] "+r" (outptr7), + [inptr] "+r" (inptr), [p] "+r" (p) + : [alpha] "w" (alpha), [beta] "w" (beta), [w] "r" (w) + : "x8", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "memory", "cc" + ); + } + break; + + + } + } + } + } +} + +#endif // __ARM_FEATURE_SVE diff --git a/src/core/NEON/kernels/arm_gemm/merges/sve_merge_fp32_3VLx8.hpp b/src/core/NEON/kernels/arm_gemm/merges/sve_merge_fp32_3VLx8.hpp new file mode 100644 index 0000000000..27084c3598 --- /dev/null +++ b/src/core/NEON/kernels/arm_gemm/merges/sve_merge_fp32_3VLx8.hpp @@ -0,0 +1,1564 @@ +/* + * Copyright (c) 2018 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#pragma once + +#ifdef __ARM_FEATURE_SVE + +template<> +inline void MergeResults<3, 8, true>(float *out, const float *in, const int ldout, const int y0, const int ymax, const int x0, const int xmax, const float alpha, const float beta) +{ + const float *inptr = in; + + for (int y=y0; y())) { + if (beta==0.0f) + { + switch(height) { + case 1: + { + long w = xmax - i; + long p = 0; + /* Optimized routine to copy an entire block */ + __asm __volatile ( + "mov z2.s, %s[alpha]\n" + "addvl x8, %[inptr], #16\n" + "mov z3.s, %s[beta]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z4.s, p0/z, [%[inptr]]\n" + "incw %[p], all, mul #1\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0]]\n" + "prfm PLDL1KEEP, [%[inptr], #0x180]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z5.s, p0/z, [%[inptr], #1, MUL VL]\n" + "incw %[p], all, mul #1\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr0], #1, MUL VL]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z6.s, p0/z, [%[inptr], #2, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr0], #0x60]\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr0], #2, MUL VL]\n" + "addvl %[outptr0], %[outptr0], #3\n" + "1:\n" + "addvl %[inptr], %[inptr], #24\n" + : [outptr0] "+r" (outptr0), [outptr1] "+r" (outptr1), [outptr2] "+r" (outptr2), [outptr3] "+r" (outptr3), [outptr4] "+r" (outptr4), [outptr5] "+r" (outptr5), [outptr6] "+r" (outptr6), [outptr7] "+r" (outptr7), + [inptr] "+r" (inptr), [p] "+r" (p) + : [alpha] "w" (alpha), [beta] "w" (beta), [w] "r" (w) + : "x8", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "memory", "cc" + ); + } + break; + + case 2: + { + long w = xmax - i; + long p = 0; + /* Optimized routine to copy an entire block */ + __asm __volatile ( + "mov z2.s, %s[alpha]\n" + "addvl x8, %[inptr], #16\n" + "mov z3.s, %s[beta]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z4.s, p0/z, [%[inptr]]\n" + "incw %[p], all, mul #1\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0]]\n" + "ld1w z5.s, p0/z, [%[inptr], #3, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x180]\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1]]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z6.s, p0/z, [%[inptr], #1, MUL VL]\n" + "incw %[p], all, mul #1\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr0], #1, MUL VL]\n" + "ld1w z7.s, p0/z, [%[inptr], #4, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x1c0]\n" + "fmul z11.s, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr1], #1, MUL VL]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z4.s, p0/z, [%[inptr], #2, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr0], #0x60]\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0], #2, MUL VL]\n" + "ld1w z5.s, p0/z, [%[inptr], #5, MUL VL]\n" + "addvl %[outptr0], %[outptr0], #3\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1], #2, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr1], #0x60]\n" + "addvl %[outptr1], %[outptr1], #3\n" + "1:\n" + "addvl %[inptr], %[inptr], #24\n" + : [outptr0] "+r" (outptr0), [outptr1] "+r" (outptr1), [outptr2] "+r" (outptr2), [outptr3] "+r" (outptr3), [outptr4] "+r" (outptr4), [outptr5] "+r" (outptr5), [outptr6] "+r" (outptr6), [outptr7] "+r" (outptr7), + [inptr] "+r" (inptr), [p] "+r" (p) + : [alpha] "w" (alpha), [beta] "w" (beta), [w] "r" (w) + : "x8", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "memory", "cc" + ); + } + break; + + case 3: + { + long w = xmax - i; + long p = 0; + /* Optimized routine to copy an entire block */ + __asm __volatile ( + "mov z2.s, %s[alpha]\n" + "addvl x8, %[inptr], #16\n" + "mov z3.s, %s[beta]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z4.s, p0/z, [%[inptr]]\n" + "incw %[p], all, mul #1\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0]]\n" + "ld1w z5.s, p0/z, [%[inptr], #3, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x180]\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1]]\n" + "ld1w z6.s, p0/z, [%[inptr], #6, MUL VL]\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr2]]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z7.s, p0/z, [%[inptr], #1, MUL VL]\n" + "incw %[p], all, mul #1\n" + "fmul z11.s, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr0], #1, MUL VL]\n" + "ld1w z4.s, p0/z, [%[inptr], #4, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x1c0]\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr1], #1, MUL VL]\n" + "ld1w z5.s, p0/z, [%[inptr], #7, MUL VL]\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr2], #1, MUL VL]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z6.s, p0/z, [%[inptr], #2, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr0], #0x60]\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr0], #2, MUL VL]\n" + "ld1w z7.s, p0/z, [%[inptr], #5, MUL VL]\n" + "addvl %[outptr0], %[outptr0], #3\n" + "fmul z11.s, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr1], #2, MUL VL]\n" + "ld1w z4.s, p0/z, [x8, #-8, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr1], #0x60]\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr2], #2, MUL VL]\n" + "addvl %[outptr1], %[outptr1], #3\n" + "prfm PLDL1KEEP, [%[inptr], #0x200]\n" + "prfm PSTL1KEEP, [%[outptr2], #0x60]\n" + "addvl %[outptr2], %[outptr2], #3\n" + "1:\n" + "addvl %[inptr], %[inptr], #24\n" + : [outptr0] "+r" (outptr0), [outptr1] "+r" (outptr1), [outptr2] "+r" (outptr2), [outptr3] "+r" (outptr3), [outptr4] "+r" (outptr4), [outptr5] "+r" (outptr5), [outptr6] "+r" (outptr6), [outptr7] "+r" (outptr7), + [inptr] "+r" (inptr), [p] "+r" (p) + : [alpha] "w" (alpha), [beta] "w" (beta), [w] "r" (w) + : "x8", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "memory", "cc" + ); + } + break; + + case 4: + { + long w = xmax - i; + long p = 0; + /* Optimized routine to copy an entire block */ + __asm __volatile ( + "mov z2.s, %s[alpha]\n" + "addvl x8, %[inptr], #16\n" + "mov z3.s, %s[beta]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z4.s, p0/z, [%[inptr]]\n" + "incw %[p], all, mul #1\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0]]\n" + "ld1w z5.s, p0/z, [%[inptr], #3, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x180]\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1]]\n" + "ld1w z6.s, p0/z, [%[inptr], #6, MUL VL]\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr2]]\n" + "ld1w z7.s, p0/z, [x8, #-7, MUL VL]\n" + "fmul z11.s, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr3]]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z4.s, p0/z, [%[inptr], #1, MUL VL]\n" + "incw %[p], all, mul #1\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0], #1, MUL VL]\n" + "ld1w z5.s, p0/z, [%[inptr], #4, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x1c0]\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1], #1, MUL VL]\n" + "ld1w z6.s, p0/z, [%[inptr], #7, MUL VL]\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr2], #1, MUL VL]\n" + "ld1w z7.s, p0/z, [x8, #-6, MUL VL]\n" + "fmul z11.s, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr3], #1, MUL VL]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z4.s, p0/z, [%[inptr], #2, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr0], #0x60]\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0], #2, MUL VL]\n" + "ld1w z5.s, p0/z, [%[inptr], #5, MUL VL]\n" + "addvl %[outptr0], %[outptr0], #3\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1], #2, MUL VL]\n" + "ld1w z6.s, p0/z, [x8, #-8, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr1], #0x60]\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr2], #2, MUL VL]\n" + "ld1w z7.s, p0/z, [x8, #-5, MUL VL]\n" + "addvl %[outptr1], %[outptr1], #3\n" + "fmul z11.s, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr3], #2, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x200]\n" + "prfm PSTL1KEEP, [%[outptr2], #0x60]\n" + "addvl %[outptr2], %[outptr2], #3\n" + "prfm PSTL1KEEP, [%[outptr3], #0x60]\n" + "addvl %[outptr3], %[outptr3], #3\n" + "1:\n" + "addvl %[inptr], %[inptr], #24\n" + : [outptr0] "+r" (outptr0), [outptr1] "+r" (outptr1), [outptr2] "+r" (outptr2), [outptr3] "+r" (outptr3), [outptr4] "+r" (outptr4), [outptr5] "+r" (outptr5), [outptr6] "+r" (outptr6), [outptr7] "+r" (outptr7), + [inptr] "+r" (inptr), [p] "+r" (p) + : [alpha] "w" (alpha), [beta] "w" (beta), [w] "r" (w) + : "x8", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "memory", "cc" + ); + } + break; + + case 5: + { + long w = xmax - i; + long p = 0; + /* Optimized routine to copy an entire block */ + __asm __volatile ( + "mov z2.s, %s[alpha]\n" + "addvl x8, %[inptr], #16\n" + "mov z3.s, %s[beta]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z4.s, p0/z, [%[inptr]]\n" + "incw %[p], all, mul #1\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0]]\n" + "ld1w z5.s, p0/z, [%[inptr], #3, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x180]\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1]]\n" + "ld1w z6.s, p0/z, [%[inptr], #6, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x240]\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr2]]\n" + "ld1w z7.s, p0/z, [x8, #-7, MUL VL]\n" + "fmul z11.s, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr3]]\n" + "ld1w z4.s, p0/z, [x8, #-4, MUL VL]\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr4]]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z5.s, p0/z, [%[inptr], #1, MUL VL]\n" + "incw %[p], all, mul #1\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr0], #1, MUL VL]\n" + "ld1w z6.s, p0/z, [%[inptr], #4, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x1c0]\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr1], #1, MUL VL]\n" + "ld1w z7.s, p0/z, [%[inptr], #7, MUL VL]\n" + "fmul z11.s, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr2], #1, MUL VL]\n" + "ld1w z4.s, p0/z, [x8, #-6, MUL VL]\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr3], #1, MUL VL]\n" + "ld1w z5.s, p0/z, [x8, #-3, MUL VL]\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr4], #1, MUL VL]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z6.s, p0/z, [%[inptr], #2, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr0], #0x60]\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr0], #2, MUL VL]\n" + "ld1w z7.s, p0/z, [%[inptr], #5, MUL VL]\n" + "addvl %[outptr0], %[outptr0], #3\n" + "fmul z11.s, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr1], #2, MUL VL]\n" + "ld1w z4.s, p0/z, [x8, #-8, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr1], #0x60]\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr2], #2, MUL VL]\n" + "ld1w z5.s, p0/z, [x8, #-5, MUL VL]\n" + "addvl %[outptr1], %[outptr1], #3\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr3], #2, MUL VL]\n" + "ld1w z6.s, p0/z, [x8, #-2, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x200]\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr4], #2, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr2], #0x60]\n" + "addvl %[outptr2], %[outptr2], #3\n" + "prfm PSTL1KEEP, [%[outptr3], #0x60]\n" + "addvl %[outptr3], %[outptr3], #3\n" + "prfm PSTL1KEEP, [%[outptr4], #0x60]\n" + "addvl %[outptr4], %[outptr4], #3\n" + "1:\n" + "addvl %[inptr], %[inptr], #24\n" + : [outptr0] "+r" (outptr0), [outptr1] "+r" (outptr1), [outptr2] "+r" (outptr2), [outptr3] "+r" (outptr3), [outptr4] "+r" (outptr4), [outptr5] "+r" (outptr5), [outptr6] "+r" (outptr6), [outptr7] "+r" (outptr7), + [inptr] "+r" (inptr), [p] "+r" (p) + : [alpha] "w" (alpha), [beta] "w" (beta), [w] "r" (w) + : "x8", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "memory", "cc" + ); + } + break; + + case 6: + { + long w = xmax - i; + long p = 0; + /* Optimized routine to copy an entire block */ + __asm __volatile ( + "mov z2.s, %s[alpha]\n" + "addvl x8, %[inptr], #16\n" + "mov z3.s, %s[beta]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z4.s, p0/z, [%[inptr]]\n" + "incw %[p], all, mul #1\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0]]\n" + "ld1w z5.s, p0/z, [%[inptr], #3, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x180]\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1]]\n" + "ld1w z6.s, p0/z, [%[inptr], #6, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x240]\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr2]]\n" + "ld1w z7.s, p0/z, [x8, #-7, MUL VL]\n" + "fmul z11.s, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr3]]\n" + "ld1w z4.s, p0/z, [x8, #-4, MUL VL]\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr4]]\n" + "ld1w z5.s, p0/z, [x8, #-1, MUL VL]\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr5]]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z6.s, p0/z, [%[inptr], #1, MUL VL]\n" + "incw %[p], all, mul #1\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr0], #1, MUL VL]\n" + "ld1w z7.s, p0/z, [%[inptr], #4, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x1c0]\n" + "fmul z11.s, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr1], #1, MUL VL]\n" + "ld1w z4.s, p0/z, [%[inptr], #7, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x280]\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr2], #1, MUL VL]\n" + "ld1w z5.s, p0/z, [x8, #-6, MUL VL]\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr3], #1, MUL VL]\n" + "ld1w z6.s, p0/z, [x8, #-3, MUL VL]\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr4], #1, MUL VL]\n" + "ld1w z7.s, p0/z, [x8]\n" + "fmul z11.s, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr5], #1, MUL VL]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z4.s, p0/z, [%[inptr], #2, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr0], #0x60]\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0], #2, MUL VL]\n" + "ld1w z5.s, p0/z, [%[inptr], #5, MUL VL]\n" + "addvl %[outptr0], %[outptr0], #3\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1], #2, MUL VL]\n" + "ld1w z6.s, p0/z, [x8, #-8, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr1], #0x60]\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr2], #2, MUL VL]\n" + "ld1w z7.s, p0/z, [x8, #-5, MUL VL]\n" + "addvl %[outptr1], %[outptr1], #3\n" + "fmul z11.s, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr3], #2, MUL VL]\n" + "ld1w z4.s, p0/z, [x8, #-2, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x200]\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr4], #2, MUL VL]\n" + "ld1w z5.s, p0/z, [x8, #1, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr2], #0x60]\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr5], #2, MUL VL]\n" + "addvl %[outptr2], %[outptr2], #3\n" + "prfm PSTL1KEEP, [%[outptr3], #0x60]\n" + "addvl %[outptr3], %[outptr3], #3\n" + "prfm PSTL1KEEP, [%[outptr4], #0x60]\n" + "addvl %[outptr4], %[outptr4], #3\n" + "prfm PSTL1KEEP, [%[outptr5], #0x60]\n" + "addvl %[outptr5], %[outptr5], #3\n" + "1:\n" + "addvl %[inptr], %[inptr], #24\n" + : [outptr0] "+r" (outptr0), [outptr1] "+r" (outptr1), [outptr2] "+r" (outptr2), [outptr3] "+r" (outptr3), [outptr4] "+r" (outptr4), [outptr5] "+r" (outptr5), [outptr6] "+r" (outptr6), [outptr7] "+r" (outptr7), + [inptr] "+r" (inptr), [p] "+r" (p) + : [alpha] "w" (alpha), [beta] "w" (beta), [w] "r" (w) + : "x8", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "memory", "cc" + ); + } + break; + + case 7: + { + long w = xmax - i; + long p = 0; + /* Optimized routine to copy an entire block */ + __asm __volatile ( + "mov z2.s, %s[alpha]\n" + "addvl x8, %[inptr], #16\n" + "mov z3.s, %s[beta]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z4.s, p0/z, [%[inptr]]\n" + "incw %[p], all, mul #1\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0]]\n" + "ld1w z5.s, p0/z, [%[inptr], #3, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x180]\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1]]\n" + "ld1w z6.s, p0/z, [%[inptr], #6, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x240]\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr2]]\n" + "ld1w z7.s, p0/z, [x8, #-7, MUL VL]\n" + "fmul z11.s, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr3]]\n" + "ld1w z4.s, p0/z, [x8, #-4, MUL VL]\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr4]]\n" + "ld1w z5.s, p0/z, [x8, #-1, MUL VL]\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr5]]\n" + "ld1w z6.s, p0/z, [x8, #2, MUL VL]\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr6]]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z7.s, p0/z, [%[inptr], #1, MUL VL]\n" + "incw %[p], all, mul #1\n" + "fmul z11.s, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr0], #1, MUL VL]\n" + "ld1w z4.s, p0/z, [%[inptr], #4, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x1c0]\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr1], #1, MUL VL]\n" + "ld1w z5.s, p0/z, [%[inptr], #7, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x280]\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr2], #1, MUL VL]\n" + "ld1w z6.s, p0/z, [x8, #-6, MUL VL]\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr3], #1, MUL VL]\n" + "ld1w z7.s, p0/z, [x8, #-3, MUL VL]\n" + "fmul z11.s, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr4], #1, MUL VL]\n" + "ld1w z4.s, p0/z, [x8]\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr5], #1, MUL VL]\n" + "ld1w z5.s, p0/z, [x8, #3, MUL VL]\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr6], #1, MUL VL]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z6.s, p0/z, [%[inptr], #2, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr0], #0x60]\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr0], #2, MUL VL]\n" + "ld1w z7.s, p0/z, [%[inptr], #5, MUL VL]\n" + "addvl %[outptr0], %[outptr0], #3\n" + "fmul z11.s, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr1], #2, MUL VL]\n" + "ld1w z4.s, p0/z, [x8, #-8, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr1], #0x60]\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr2], #2, MUL VL]\n" + "ld1w z5.s, p0/z, [x8, #-5, MUL VL]\n" + "addvl %[outptr1], %[outptr1], #3\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr3], #2, MUL VL]\n" + "ld1w z6.s, p0/z, [x8, #-2, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x200]\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr4], #2, MUL VL]\n" + "ld1w z7.s, p0/z, [x8, #1, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr2], #0x60]\n" + "fmul z11.s, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr5], #2, MUL VL]\n" + "ld1w z4.s, p0/z, [x8, #4, MUL VL]\n" + "addvl %[outptr2], %[outptr2], #3\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr6], #2, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr3], #0x60]\n" + "addvl %[outptr3], %[outptr3], #3\n" + "prfm PSTL1KEEP, [%[outptr4], #0x60]\n" + "addvl %[outptr4], %[outptr4], #3\n" + "prfm PSTL1KEEP, [%[outptr5], #0x60]\n" + "addvl %[outptr5], %[outptr5], #3\n" + "prfm PLDL1KEEP, [%[inptr], #0x2c0]\n" + "prfm PSTL1KEEP, [%[outptr6], #0x60]\n" + "addvl %[outptr6], %[outptr6], #3\n" + "1:\n" + "addvl %[inptr], %[inptr], #24\n" + : [outptr0] "+r" (outptr0), [outptr1] "+r" (outptr1), [outptr2] "+r" (outptr2), [outptr3] "+r" (outptr3), [outptr4] "+r" (outptr4), [outptr5] "+r" (outptr5), [outptr6] "+r" (outptr6), [outptr7] "+r" (outptr7), + [inptr] "+r" (inptr), [p] "+r" (p) + : [alpha] "w" (alpha), [beta] "w" (beta), [w] "r" (w) + : "x8", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "memory", "cc" + ); + } + break; + + default: + case 8: + { + long w = xmax - i; + long p = 0; + /* Optimized routine to copy an entire block */ + __asm __volatile ( + "mov z2.s, %s[alpha]\n" + "addvl x8, %[inptr], #16\n" + "mov z3.s, %s[beta]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z4.s, p0/z, [%[inptr]]\n" + "incw %[p], all, mul #1\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0]]\n" + "ld1w z5.s, p0/z, [%[inptr], #3, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x180]\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1]]\n" + "ld1w z6.s, p0/z, [%[inptr], #6, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x240]\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr2]]\n" + "ld1w z7.s, p0/z, [x8, #-7, MUL VL]\n" + "fmul z11.s, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr3]]\n" + "ld1w z4.s, p0/z, [x8, #-4, MUL VL]\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr4]]\n" + "ld1w z5.s, p0/z, [x8, #-1, MUL VL]\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr5]]\n" + "ld1w z6.s, p0/z, [x8, #2, MUL VL]\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr6]]\n" + "ld1w z7.s, p0/z, [x8, #5, MUL VL]\n" + "fmul z11.s, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr7]]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z4.s, p0/z, [%[inptr], #1, MUL VL]\n" + "incw %[p], all, mul #1\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0], #1, MUL VL]\n" + "ld1w z5.s, p0/z, [%[inptr], #4, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x1c0]\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1], #1, MUL VL]\n" + "ld1w z6.s, p0/z, [%[inptr], #7, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x280]\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr2], #1, MUL VL]\n" + "ld1w z7.s, p0/z, [x8, #-6, MUL VL]\n" + "fmul z11.s, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr3], #1, MUL VL]\n" + "ld1w z4.s, p0/z, [x8, #-3, MUL VL]\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr4], #1, MUL VL]\n" + "ld1w z5.s, p0/z, [x8]\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr5], #1, MUL VL]\n" + "ld1w z6.s, p0/z, [x8, #3, MUL VL]\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr6], #1, MUL VL]\n" + "ld1w z7.s, p0/z, [x8, #6, MUL VL]\n" + "fmul z11.s, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr7], #1, MUL VL]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z4.s, p0/z, [%[inptr], #2, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr0], #0x60]\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0], #2, MUL VL]\n" + "ld1w z5.s, p0/z, [%[inptr], #5, MUL VL]\n" + "addvl %[outptr0], %[outptr0], #3\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1], #2, MUL VL]\n" + "ld1w z6.s, p0/z, [x8, #-8, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr1], #0x60]\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr2], #2, MUL VL]\n" + "ld1w z7.s, p0/z, [x8, #-5, MUL VL]\n" + "addvl %[outptr1], %[outptr1], #3\n" + "fmul z11.s, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr3], #2, MUL VL]\n" + "ld1w z4.s, p0/z, [x8, #-2, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x200]\n" + "fmul z8.s, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr4], #2, MUL VL]\n" + "ld1w z5.s, p0/z, [x8, #1, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr2], #0x60]\n" + "fmul z9.s, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr5], #2, MUL VL]\n" + "ld1w z6.s, p0/z, [x8, #4, MUL VL]\n" + "addvl %[outptr2], %[outptr2], #3\n" + "fmul z10.s, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr6], #2, MUL VL]\n" + "ld1w z7.s, p0/z, [x8, #7, MUL VL]\n" + "prfm PSTL1KEEP, [%[outptr3], #0x60]\n" + "fmul z11.s, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr7], #2, MUL VL]\n" + "addvl %[outptr3], %[outptr3], #3\n" + "prfm PSTL1KEEP, [%[outptr4], #0x60]\n" + "addvl %[outptr4], %[outptr4], #3\n" + "prfm PSTL1KEEP, [%[outptr5], #0x60]\n" + "addvl %[outptr5], %[outptr5], #3\n" + "prfm PLDL1KEEP, [%[inptr], #0x2c0]\n" + "prfm PSTL1KEEP, [%[outptr6], #0x60]\n" + "addvl %[outptr6], %[outptr6], #3\n" + "prfm PSTL1KEEP, [%[outptr7], #0x60]\n" + "addvl %[outptr7], %[outptr7], #3\n" + "1:\n" + "addvl %[inptr], %[inptr], #24\n" + : [outptr0] "+r" (outptr0), [outptr1] "+r" (outptr1), [outptr2] "+r" (outptr2), [outptr3] "+r" (outptr3), [outptr4] "+r" (outptr4), [outptr5] "+r" (outptr5), [outptr6] "+r" (outptr6), [outptr7] "+r" (outptr7), + [inptr] "+r" (inptr), [p] "+r" (p) + : [alpha] "w" (alpha), [beta] "w" (beta), [w] "r" (w) + : "x8", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "memory", "cc" + ); + } + break; + + + } + } + else + { + switch(height) { + case 1: + { + long w = xmax - i; + long p = 0; + /* Optimized routine to copy an entire block */ + __asm __volatile ( + "mov z2.s, %s[alpha]\n" + "addvl x8, %[inptr], #16\n" + "mov z3.s, %s[beta]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z8.s, p0/z, [%[outptr0]]\n" + "incw %[p], all, mul #1\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [%[inptr]]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0]]\n" + "prfm PLDL1KEEP, [%[inptr], #0x180]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z9.s, p0/z, [%[outptr0], #1, MUL VL]\n" + "incw %[p], all, mul #1\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [%[inptr], #1, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr0], #1, MUL VL]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z10.s, p0/z, [%[outptr0], #2, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr0], #0x60]\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [%[inptr], #2, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr0], #2, MUL VL]\n" + "addvl %[outptr0], %[outptr0], #3\n" + "1:\n" + "addvl %[inptr], %[inptr], #24\n" + : [outptr0] "+r" (outptr0), [outptr1] "+r" (outptr1), [outptr2] "+r" (outptr2), [outptr3] "+r" (outptr3), [outptr4] "+r" (outptr4), [outptr5] "+r" (outptr5), [outptr6] "+r" (outptr6), [outptr7] "+r" (outptr7), + [inptr] "+r" (inptr), [p] "+r" (p) + : [alpha] "w" (alpha), [beta] "w" (beta), [w] "r" (w) + : "x8", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "memory", "cc" + ); + } + break; + + case 2: + { + long w = xmax - i; + long p = 0; + /* Optimized routine to copy an entire block */ + __asm __volatile ( + "mov z2.s, %s[alpha]\n" + "addvl x8, %[inptr], #16\n" + "mov z3.s, %s[beta]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z8.s, p0/z, [%[outptr0]]\n" + "incw %[p], all, mul #1\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [%[inptr]]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0]]\n" + "ld1w z9.s, p0/z, [%[outptr1]]\n" + "prfm PLDL1KEEP, [%[inptr], #0x180]\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [%[inptr], #3, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1]]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z10.s, p0/z, [%[outptr0], #1, MUL VL]\n" + "incw %[p], all, mul #1\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [%[inptr], #1, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr0], #1, MUL VL]\n" + "ld1w z11.s, p0/z, [%[outptr1], #1, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x1c0]\n" + "fmul z11.s, z11.s, z3.s\n" + "ld1w z7.s, p0/z, [%[inptr], #4, MUL VL]\n" + "fmla z11.s, p0/m, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr1], #1, MUL VL]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z8.s, p0/z, [%[outptr0], #2, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr0], #0x60]\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [%[inptr], #2, MUL VL]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0], #2, MUL VL]\n" + "ld1w z9.s, p0/z, [%[outptr1], #2, MUL VL]\n" + "addvl %[outptr0], %[outptr0], #3\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [%[inptr], #5, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1], #2, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr1], #0x60]\n" + "addvl %[outptr1], %[outptr1], #3\n" + "1:\n" + "addvl %[inptr], %[inptr], #24\n" + : [outptr0] "+r" (outptr0), [outptr1] "+r" (outptr1), [outptr2] "+r" (outptr2), [outptr3] "+r" (outptr3), [outptr4] "+r" (outptr4), [outptr5] "+r" (outptr5), [outptr6] "+r" (outptr6), [outptr7] "+r" (outptr7), + [inptr] "+r" (inptr), [p] "+r" (p) + : [alpha] "w" (alpha), [beta] "w" (beta), [w] "r" (w) + : "x8", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "memory", "cc" + ); + } + break; + + case 3: + { + long w = xmax - i; + long p = 0; + /* Optimized routine to copy an entire block */ + __asm __volatile ( + "mov z2.s, %s[alpha]\n" + "addvl x8, %[inptr], #16\n" + "mov z3.s, %s[beta]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z8.s, p0/z, [%[outptr0]]\n" + "incw %[p], all, mul #1\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [%[inptr]]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0]]\n" + "ld1w z9.s, p0/z, [%[outptr1]]\n" + "prfm PLDL1KEEP, [%[inptr], #0x180]\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [%[inptr], #3, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1]]\n" + "ld1w z10.s, p0/z, [%[outptr2]]\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [%[inptr], #6, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr2]]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z11.s, p0/z, [%[outptr0], #1, MUL VL]\n" + "incw %[p], all, mul #1\n" + "fmul z11.s, z11.s, z3.s\n" + "ld1w z7.s, p0/z, [%[inptr], #1, MUL VL]\n" + "fmla z11.s, p0/m, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr0], #1, MUL VL]\n" + "ld1w z8.s, p0/z, [%[outptr1], #1, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x1c0]\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [%[inptr], #4, MUL VL]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr1], #1, MUL VL]\n" + "ld1w z9.s, p0/z, [%[outptr2], #1, MUL VL]\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [%[inptr], #7, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr2], #1, MUL VL]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z10.s, p0/z, [%[outptr0], #2, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr0], #0x60]\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [%[inptr], #2, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr0], #2, MUL VL]\n" + "ld1w z11.s, p0/z, [%[outptr1], #2, MUL VL]\n" + "addvl %[outptr0], %[outptr0], #3\n" + "fmul z11.s, z11.s, z3.s\n" + "ld1w z7.s, p0/z, [%[inptr], #5, MUL VL]\n" + "fmla z11.s, p0/m, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr1], #2, MUL VL]\n" + "ld1w z8.s, p0/z, [%[outptr2], #2, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr1], #0x60]\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [x8, #-8, MUL VL]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr2], #2, MUL VL]\n" + "addvl %[outptr1], %[outptr1], #3\n" + "prfm PLDL1KEEP, [%[inptr], #0x200]\n" + "prfm PLDL1KEEP, [%[outptr2], #0x60]\n" + "addvl %[outptr2], %[outptr2], #3\n" + "1:\n" + "addvl %[inptr], %[inptr], #24\n" + : [outptr0] "+r" (outptr0), [outptr1] "+r" (outptr1), [outptr2] "+r" (outptr2), [outptr3] "+r" (outptr3), [outptr4] "+r" (outptr4), [outptr5] "+r" (outptr5), [outptr6] "+r" (outptr6), [outptr7] "+r" (outptr7), + [inptr] "+r" (inptr), [p] "+r" (p) + : [alpha] "w" (alpha), [beta] "w" (beta), [w] "r" (w) + : "x8", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "memory", "cc" + ); + } + break; + + case 4: + { + long w = xmax - i; + long p = 0; + /* Optimized routine to copy an entire block */ + __asm __volatile ( + "mov z2.s, %s[alpha]\n" + "addvl x8, %[inptr], #16\n" + "mov z3.s, %s[beta]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z8.s, p0/z, [%[outptr0]]\n" + "incw %[p], all, mul #1\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [%[inptr]]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0]]\n" + "ld1w z9.s, p0/z, [%[outptr1]]\n" + "prfm PLDL1KEEP, [%[inptr], #0x180]\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [%[inptr], #3, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1]]\n" + "ld1w z10.s, p0/z, [%[outptr2]]\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [%[inptr], #6, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr2]]\n" + "ld1w z11.s, p0/z, [%[outptr3]]\n" + "fmul z11.s, z11.s, z3.s\n" + "ld1w z7.s, p0/z, [x8, #-7, MUL VL]\n" + "fmla z11.s, p0/m, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr3]]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z8.s, p0/z, [%[outptr0], #1, MUL VL]\n" + "incw %[p], all, mul #1\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [%[inptr], #1, MUL VL]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0], #1, MUL VL]\n" + "ld1w z9.s, p0/z, [%[outptr1], #1, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x1c0]\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [%[inptr], #4, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1], #1, MUL VL]\n" + "ld1w z10.s, p0/z, [%[outptr2], #1, MUL VL]\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [%[inptr], #7, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr2], #1, MUL VL]\n" + "ld1w z11.s, p0/z, [%[outptr3], #1, MUL VL]\n" + "fmul z11.s, z11.s, z3.s\n" + "ld1w z7.s, p0/z, [x8, #-6, MUL VL]\n" + "fmla z11.s, p0/m, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr3], #1, MUL VL]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z8.s, p0/z, [%[outptr0], #2, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr0], #0x60]\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [%[inptr], #2, MUL VL]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0], #2, MUL VL]\n" + "ld1w z9.s, p0/z, [%[outptr1], #2, MUL VL]\n" + "addvl %[outptr0], %[outptr0], #3\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [%[inptr], #5, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1], #2, MUL VL]\n" + "ld1w z10.s, p0/z, [%[outptr2], #2, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr1], #0x60]\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [x8, #-8, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr2], #2, MUL VL]\n" + "ld1w z11.s, p0/z, [%[outptr3], #2, MUL VL]\n" + "addvl %[outptr1], %[outptr1], #3\n" + "fmul z11.s, z11.s, z3.s\n" + "ld1w z7.s, p0/z, [x8, #-5, MUL VL]\n" + "fmla z11.s, p0/m, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr3], #2, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x200]\n" + "prfm PLDL1KEEP, [%[outptr2], #0x60]\n" + "addvl %[outptr2], %[outptr2], #3\n" + "prfm PLDL1KEEP, [%[outptr3], #0x60]\n" + "addvl %[outptr3], %[outptr3], #3\n" + "1:\n" + "addvl %[inptr], %[inptr], #24\n" + : [outptr0] "+r" (outptr0), [outptr1] "+r" (outptr1), [outptr2] "+r" (outptr2), [outptr3] "+r" (outptr3), [outptr4] "+r" (outptr4), [outptr5] "+r" (outptr5), [outptr6] "+r" (outptr6), [outptr7] "+r" (outptr7), + [inptr] "+r" (inptr), [p] "+r" (p) + : [alpha] "w" (alpha), [beta] "w" (beta), [w] "r" (w) + : "x8", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "memory", "cc" + ); + } + break; + + case 5: + { + long w = xmax - i; + long p = 0; + /* Optimized routine to copy an entire block */ + __asm __volatile ( + "mov z2.s, %s[alpha]\n" + "addvl x8, %[inptr], #16\n" + "mov z3.s, %s[beta]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z8.s, p0/z, [%[outptr0]]\n" + "incw %[p], all, mul #1\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [%[inptr]]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0]]\n" + "ld1w z9.s, p0/z, [%[outptr1]]\n" + "prfm PLDL1KEEP, [%[inptr], #0x180]\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [%[inptr], #3, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1]]\n" + "ld1w z10.s, p0/z, [%[outptr2]]\n" + "prfm PLDL1KEEP, [%[inptr], #0x240]\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [%[inptr], #6, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr2]]\n" + "ld1w z11.s, p0/z, [%[outptr3]]\n" + "fmul z11.s, z11.s, z3.s\n" + "ld1w z7.s, p0/z, [x8, #-7, MUL VL]\n" + "fmla z11.s, p0/m, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr3]]\n" + "ld1w z8.s, p0/z, [%[outptr4]]\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [x8, #-4, MUL VL]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr4]]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z9.s, p0/z, [%[outptr0], #1, MUL VL]\n" + "incw %[p], all, mul #1\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [%[inptr], #1, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr0], #1, MUL VL]\n" + "ld1w z10.s, p0/z, [%[outptr1], #1, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x1c0]\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [%[inptr], #4, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr1], #1, MUL VL]\n" + "ld1w z11.s, p0/z, [%[outptr2], #1, MUL VL]\n" + "fmul z11.s, z11.s, z3.s\n" + "ld1w z7.s, p0/z, [%[inptr], #7, MUL VL]\n" + "fmla z11.s, p0/m, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr2], #1, MUL VL]\n" + "ld1w z8.s, p0/z, [%[outptr3], #1, MUL VL]\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [x8, #-6, MUL VL]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr3], #1, MUL VL]\n" + "ld1w z9.s, p0/z, [%[outptr4], #1, MUL VL]\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [x8, #-3, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr4], #1, MUL VL]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z10.s, p0/z, [%[outptr0], #2, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr0], #0x60]\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [%[inptr], #2, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr0], #2, MUL VL]\n" + "ld1w z11.s, p0/z, [%[outptr1], #2, MUL VL]\n" + "addvl %[outptr0], %[outptr0], #3\n" + "fmul z11.s, z11.s, z3.s\n" + "ld1w z7.s, p0/z, [%[inptr], #5, MUL VL]\n" + "fmla z11.s, p0/m, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr1], #2, MUL VL]\n" + "ld1w z8.s, p0/z, [%[outptr2], #2, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr1], #0x60]\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [x8, #-8, MUL VL]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr2], #2, MUL VL]\n" + "ld1w z9.s, p0/z, [%[outptr3], #2, MUL VL]\n" + "addvl %[outptr1], %[outptr1], #3\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [x8, #-5, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr3], #2, MUL VL]\n" + "ld1w z10.s, p0/z, [%[outptr4], #2, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x200]\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [x8, #-2, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr4], #2, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr2], #0x60]\n" + "addvl %[outptr2], %[outptr2], #3\n" + "prfm PLDL1KEEP, [%[outptr3], #0x60]\n" + "addvl %[outptr3], %[outptr3], #3\n" + "prfm PLDL1KEEP, [%[outptr4], #0x60]\n" + "addvl %[outptr4], %[outptr4], #3\n" + "1:\n" + "addvl %[inptr], %[inptr], #24\n" + : [outptr0] "+r" (outptr0), [outptr1] "+r" (outptr1), [outptr2] "+r" (outptr2), [outptr3] "+r" (outptr3), [outptr4] "+r" (outptr4), [outptr5] "+r" (outptr5), [outptr6] "+r" (outptr6), [outptr7] "+r" (outptr7), + [inptr] "+r" (inptr), [p] "+r" (p) + : [alpha] "w" (alpha), [beta] "w" (beta), [w] "r" (w) + : "x8", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "memory", "cc" + ); + } + break; + + case 6: + { + long w = xmax - i; + long p = 0; + /* Optimized routine to copy an entire block */ + __asm __volatile ( + "mov z2.s, %s[alpha]\n" + "addvl x8, %[inptr], #16\n" + "mov z3.s, %s[beta]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z8.s, p0/z, [%[outptr0]]\n" + "incw %[p], all, mul #1\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [%[inptr]]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0]]\n" + "ld1w z9.s, p0/z, [%[outptr1]]\n" + "prfm PLDL1KEEP, [%[inptr], #0x180]\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [%[inptr], #3, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1]]\n" + "ld1w z10.s, p0/z, [%[outptr2]]\n" + "prfm PLDL1KEEP, [%[inptr], #0x240]\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [%[inptr], #6, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr2]]\n" + "ld1w z11.s, p0/z, [%[outptr3]]\n" + "fmul z11.s, z11.s, z3.s\n" + "ld1w z7.s, p0/z, [x8, #-7, MUL VL]\n" + "fmla z11.s, p0/m, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr3]]\n" + "ld1w z8.s, p0/z, [%[outptr4]]\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [x8, #-4, MUL VL]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr4]]\n" + "ld1w z9.s, p0/z, [%[outptr5]]\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [x8, #-1, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr5]]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z10.s, p0/z, [%[outptr0], #1, MUL VL]\n" + "incw %[p], all, mul #1\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [%[inptr], #1, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr0], #1, MUL VL]\n" + "ld1w z11.s, p0/z, [%[outptr1], #1, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x1c0]\n" + "fmul z11.s, z11.s, z3.s\n" + "ld1w z7.s, p0/z, [%[inptr], #4, MUL VL]\n" + "fmla z11.s, p0/m, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr1], #1, MUL VL]\n" + "ld1w z8.s, p0/z, [%[outptr2], #1, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x280]\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [%[inptr], #7, MUL VL]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr2], #1, MUL VL]\n" + "ld1w z9.s, p0/z, [%[outptr3], #1, MUL VL]\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [x8, #-6, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr3], #1, MUL VL]\n" + "ld1w z10.s, p0/z, [%[outptr4], #1, MUL VL]\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [x8, #-3, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr4], #1, MUL VL]\n" + "ld1w z11.s, p0/z, [%[outptr5], #1, MUL VL]\n" + "fmul z11.s, z11.s, z3.s\n" + "ld1w z7.s, p0/z, [x8]\n" + "fmla z11.s, p0/m, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr5], #1, MUL VL]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z8.s, p0/z, [%[outptr0], #2, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr0], #0x60]\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [%[inptr], #2, MUL VL]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0], #2, MUL VL]\n" + "ld1w z9.s, p0/z, [%[outptr1], #2, MUL VL]\n" + "addvl %[outptr0], %[outptr0], #3\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [%[inptr], #5, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1], #2, MUL VL]\n" + "ld1w z10.s, p0/z, [%[outptr2], #2, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr1], #0x60]\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [x8, #-8, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr2], #2, MUL VL]\n" + "ld1w z11.s, p0/z, [%[outptr3], #2, MUL VL]\n" + "addvl %[outptr1], %[outptr1], #3\n" + "fmul z11.s, z11.s, z3.s\n" + "ld1w z7.s, p0/z, [x8, #-5, MUL VL]\n" + "fmla z11.s, p0/m, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr3], #2, MUL VL]\n" + "ld1w z8.s, p0/z, [%[outptr4], #2, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x200]\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [x8, #-2, MUL VL]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr4], #2, MUL VL]\n" + "ld1w z9.s, p0/z, [%[outptr5], #2, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr2], #0x60]\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [x8, #1, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr5], #2, MUL VL]\n" + "addvl %[outptr2], %[outptr2], #3\n" + "prfm PLDL1KEEP, [%[outptr3], #0x60]\n" + "addvl %[outptr3], %[outptr3], #3\n" + "prfm PLDL1KEEP, [%[outptr4], #0x60]\n" + "addvl %[outptr4], %[outptr4], #3\n" + "prfm PLDL1KEEP, [%[outptr5], #0x60]\n" + "addvl %[outptr5], %[outptr5], #3\n" + "1:\n" + "addvl %[inptr], %[inptr], #24\n" + : [outptr0] "+r" (outptr0), [outptr1] "+r" (outptr1), [outptr2] "+r" (outptr2), [outptr3] "+r" (outptr3), [outptr4] "+r" (outptr4), [outptr5] "+r" (outptr5), [outptr6] "+r" (outptr6), [outptr7] "+r" (outptr7), + [inptr] "+r" (inptr), [p] "+r" (p) + : [alpha] "w" (alpha), [beta] "w" (beta), [w] "r" (w) + : "x8", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "memory", "cc" + ); + } + break; + + case 7: + { + long w = xmax - i; + long p = 0; + /* Optimized routine to copy an entire block */ + __asm __volatile ( + "mov z2.s, %s[alpha]\n" + "addvl x8, %[inptr], #16\n" + "mov z3.s, %s[beta]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z8.s, p0/z, [%[outptr0]]\n" + "incw %[p], all, mul #1\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [%[inptr]]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0]]\n" + "ld1w z9.s, p0/z, [%[outptr1]]\n" + "prfm PLDL1KEEP, [%[inptr], #0x180]\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [%[inptr], #3, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1]]\n" + "ld1w z10.s, p0/z, [%[outptr2]]\n" + "prfm PLDL1KEEP, [%[inptr], #0x240]\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [%[inptr], #6, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr2]]\n" + "ld1w z11.s, p0/z, [%[outptr3]]\n" + "fmul z11.s, z11.s, z3.s\n" + "ld1w z7.s, p0/z, [x8, #-7, MUL VL]\n" + "fmla z11.s, p0/m, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr3]]\n" + "ld1w z8.s, p0/z, [%[outptr4]]\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [x8, #-4, MUL VL]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr4]]\n" + "ld1w z9.s, p0/z, [%[outptr5]]\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [x8, #-1, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr5]]\n" + "ld1w z10.s, p0/z, [%[outptr6]]\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [x8, #2, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr6]]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z11.s, p0/z, [%[outptr0], #1, MUL VL]\n" + "incw %[p], all, mul #1\n" + "fmul z11.s, z11.s, z3.s\n" + "ld1w z7.s, p0/z, [%[inptr], #1, MUL VL]\n" + "fmla z11.s, p0/m, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr0], #1, MUL VL]\n" + "ld1w z8.s, p0/z, [%[outptr1], #1, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x1c0]\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [%[inptr], #4, MUL VL]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr1], #1, MUL VL]\n" + "ld1w z9.s, p0/z, [%[outptr2], #1, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x280]\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [%[inptr], #7, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr2], #1, MUL VL]\n" + "ld1w z10.s, p0/z, [%[outptr3], #1, MUL VL]\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [x8, #-6, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr3], #1, MUL VL]\n" + "ld1w z11.s, p0/z, [%[outptr4], #1, MUL VL]\n" + "fmul z11.s, z11.s, z3.s\n" + "ld1w z7.s, p0/z, [x8, #-3, MUL VL]\n" + "fmla z11.s, p0/m, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr4], #1, MUL VL]\n" + "ld1w z8.s, p0/z, [%[outptr5], #1, MUL VL]\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [x8]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr5], #1, MUL VL]\n" + "ld1w z9.s, p0/z, [%[outptr6], #1, MUL VL]\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [x8, #3, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr6], #1, MUL VL]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z10.s, p0/z, [%[outptr0], #2, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr0], #0x60]\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [%[inptr], #2, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr0], #2, MUL VL]\n" + "ld1w z11.s, p0/z, [%[outptr1], #2, MUL VL]\n" + "addvl %[outptr0], %[outptr0], #3\n" + "fmul z11.s, z11.s, z3.s\n" + "ld1w z7.s, p0/z, [%[inptr], #5, MUL VL]\n" + "fmla z11.s, p0/m, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr1], #2, MUL VL]\n" + "ld1w z8.s, p0/z, [%[outptr2], #2, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr1], #0x60]\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [x8, #-8, MUL VL]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr2], #2, MUL VL]\n" + "ld1w z9.s, p0/z, [%[outptr3], #2, MUL VL]\n" + "addvl %[outptr1], %[outptr1], #3\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [x8, #-5, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr3], #2, MUL VL]\n" + "ld1w z10.s, p0/z, [%[outptr4], #2, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x200]\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [x8, #-2, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr4], #2, MUL VL]\n" + "ld1w z11.s, p0/z, [%[outptr5], #2, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr2], #0x60]\n" + "fmul z11.s, z11.s, z3.s\n" + "ld1w z7.s, p0/z, [x8, #1, MUL VL]\n" + "fmla z11.s, p0/m, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr5], #2, MUL VL]\n" + "ld1w z8.s, p0/z, [%[outptr6], #2, MUL VL]\n" + "addvl %[outptr2], %[outptr2], #3\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [x8, #4, MUL VL]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr6], #2, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr3], #0x60]\n" + "addvl %[outptr3], %[outptr3], #3\n" + "prfm PLDL1KEEP, [%[outptr4], #0x60]\n" + "addvl %[outptr4], %[outptr4], #3\n" + "prfm PLDL1KEEP, [%[outptr5], #0x60]\n" + "addvl %[outptr5], %[outptr5], #3\n" + "prfm PLDL1KEEP, [%[inptr], #0x2c0]\n" + "prfm PLDL1KEEP, [%[outptr6], #0x60]\n" + "addvl %[outptr6], %[outptr6], #3\n" + "1:\n" + "addvl %[inptr], %[inptr], #24\n" + : [outptr0] "+r" (outptr0), [outptr1] "+r" (outptr1), [outptr2] "+r" (outptr2), [outptr3] "+r" (outptr3), [outptr4] "+r" (outptr4), [outptr5] "+r" (outptr5), [outptr6] "+r" (outptr6), [outptr7] "+r" (outptr7), + [inptr] "+r" (inptr), [p] "+r" (p) + : [alpha] "w" (alpha), [beta] "w" (beta), [w] "r" (w) + : "x8", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "memory", "cc" + ); + } + break; + + default: + case 8: + { + long w = xmax - i; + long p = 0; + /* Optimized routine to copy an entire block */ + __asm __volatile ( + "mov z2.s, %s[alpha]\n" + "addvl x8, %[inptr], #16\n" + "mov z3.s, %s[beta]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z8.s, p0/z, [%[outptr0]]\n" + "incw %[p], all, mul #1\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [%[inptr]]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0]]\n" + "ld1w z9.s, p0/z, [%[outptr1]]\n" + "prfm PLDL1KEEP, [%[inptr], #0x180]\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [%[inptr], #3, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1]]\n" + "ld1w z10.s, p0/z, [%[outptr2]]\n" + "prfm PLDL1KEEP, [%[inptr], #0x240]\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [%[inptr], #6, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr2]]\n" + "ld1w z11.s, p0/z, [%[outptr3]]\n" + "fmul z11.s, z11.s, z3.s\n" + "ld1w z7.s, p0/z, [x8, #-7, MUL VL]\n" + "fmla z11.s, p0/m, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr3]]\n" + "ld1w z8.s, p0/z, [%[outptr4]]\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [x8, #-4, MUL VL]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr4]]\n" + "ld1w z9.s, p0/z, [%[outptr5]]\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [x8, #-1, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr5]]\n" + "ld1w z10.s, p0/z, [%[outptr6]]\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [x8, #2, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr6]]\n" + "ld1w z11.s, p0/z, [%[outptr7]]\n" + "fmul z11.s, z11.s, z3.s\n" + "ld1w z7.s, p0/z, [x8, #5, MUL VL]\n" + "fmla z11.s, p0/m, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr7]]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z8.s, p0/z, [%[outptr0], #1, MUL VL]\n" + "incw %[p], all, mul #1\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [%[inptr], #1, MUL VL]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0], #1, MUL VL]\n" + "ld1w z9.s, p0/z, [%[outptr1], #1, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x1c0]\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [%[inptr], #4, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1], #1, MUL VL]\n" + "ld1w z10.s, p0/z, [%[outptr2], #1, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x280]\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [%[inptr], #7, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr2], #1, MUL VL]\n" + "ld1w z11.s, p0/z, [%[outptr3], #1, MUL VL]\n" + "fmul z11.s, z11.s, z3.s\n" + "ld1w z7.s, p0/z, [x8, #-6, MUL VL]\n" + "fmla z11.s, p0/m, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr3], #1, MUL VL]\n" + "ld1w z8.s, p0/z, [%[outptr4], #1, MUL VL]\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [x8, #-3, MUL VL]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr4], #1, MUL VL]\n" + "ld1w z9.s, p0/z, [%[outptr5], #1, MUL VL]\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [x8]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr5], #1, MUL VL]\n" + "ld1w z10.s, p0/z, [%[outptr6], #1, MUL VL]\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [x8, #3, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr6], #1, MUL VL]\n" + "ld1w z11.s, p0/z, [%[outptr7], #1, MUL VL]\n" + "fmul z11.s, z11.s, z3.s\n" + "ld1w z7.s, p0/z, [x8, #6, MUL VL]\n" + "fmla z11.s, p0/m, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr7], #1, MUL VL]\n" + "whilelt p0.s, %[p], %[w]\n" + "b.none 1f\n" + "ld1w z8.s, p0/z, [%[outptr0], #2, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr0], #0x60]\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [%[inptr], #2, MUL VL]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr0], #2, MUL VL]\n" + "ld1w z9.s, p0/z, [%[outptr1], #2, MUL VL]\n" + "addvl %[outptr0], %[outptr0], #3\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [%[inptr], #5, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr1], #2, MUL VL]\n" + "ld1w z10.s, p0/z, [%[outptr2], #2, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr1], #0x60]\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [x8, #-8, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr2], #2, MUL VL]\n" + "ld1w z11.s, p0/z, [%[outptr3], #2, MUL VL]\n" + "addvl %[outptr1], %[outptr1], #3\n" + "fmul z11.s, z11.s, z3.s\n" + "ld1w z7.s, p0/z, [x8, #-5, MUL VL]\n" + "fmla z11.s, p0/m, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr3], #2, MUL VL]\n" + "ld1w z8.s, p0/z, [%[outptr4], #2, MUL VL]\n" + "prfm PLDL1KEEP, [%[inptr], #0x200]\n" + "fmul z8.s, z8.s, z3.s\n" + "ld1w z4.s, p0/z, [x8, #-2, MUL VL]\n" + "fmla z8.s, p0/m, z4.s, z2.s\n" + "st1w z8.s, p0, [%[outptr4], #2, MUL VL]\n" + "ld1w z9.s, p0/z, [%[outptr5], #2, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr2], #0x60]\n" + "fmul z9.s, z9.s, z3.s\n" + "ld1w z5.s, p0/z, [x8, #1, MUL VL]\n" + "fmla z9.s, p0/m, z5.s, z2.s\n" + "st1w z9.s, p0, [%[outptr5], #2, MUL VL]\n" + "ld1w z10.s, p0/z, [%[outptr6], #2, MUL VL]\n" + "addvl %[outptr2], %[outptr2], #3\n" + "fmul z10.s, z10.s, z3.s\n" + "ld1w z6.s, p0/z, [x8, #4, MUL VL]\n" + "fmla z10.s, p0/m, z6.s, z2.s\n" + "st1w z10.s, p0, [%[outptr6], #2, MUL VL]\n" + "ld1w z11.s, p0/z, [%[outptr7], #2, MUL VL]\n" + "prfm PLDL1KEEP, [%[outptr3], #0x60]\n" + "fmul z11.s, z11.s, z3.s\n" + "ld1w z7.s, p0/z, [x8, #7, MUL VL]\n" + "fmla z11.s, p0/m, z7.s, z2.s\n" + "st1w z11.s, p0, [%[outptr7], #2, MUL VL]\n" + "addvl %[outptr3], %[outptr3], #3\n" + "prfm PLDL1KEEP, [%[outptr4], #0x60]\n" + "addvl %[outptr4], %[outptr4], #3\n" + "prfm PLDL1KEEP, [%[outptr5], #0x60]\n" + "addvl %[outptr5], %[outptr5], #3\n" + "prfm PLDL1KEEP, [%[inptr], #0x2c0]\n" + "prfm PLDL1KEEP, [%[outptr6], #0x60]\n" + "addvl %[outptr6], %[outptr6], #3\n" + "prfm PLDL1KEEP, [%[outptr7], #0x60]\n" + "addvl %[outptr7], %[outptr7], #3\n" + "1:\n" + "addvl %[inptr], %[inptr], #24\n" + : [outptr0] "+r" (outptr0), [outptr1] "+r" (outptr1), [outptr2] "+r" (outptr2), [outptr3] "+r" (outptr3), [outptr4] "+r" (outptr4), [outptr5] "+r" (outptr5), [outptr6] "+r" (outptr6), [outptr7] "+r" (outptr7), + [inptr] "+r" (inptr), [p] "+r" (p) + : [alpha] "w" (alpha), [beta] "w" (beta), [w] "r" (w) + : "x8", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "memory", "cc" + ); + } + break; + + + } + } + } + } +} + +#endif // __ARM_FEATURE_SVE diff --git a/src/core/NEON/kernels/arm_gemm/std_transforms_sve.hpp b/src/core/NEON/kernels/arm_gemm/std_transforms_sve.hpp new file mode 100644 index 0000000000..b7323ebaea --- /dev/null +++ b/src/core/NEON/kernels/arm_gemm/std_transforms_sve.hpp @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2017-2018 ARM Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#pragma once + +#include "mergeresults.hpp" +#include "transform.hpp" + +namespace arm_gemm { + +/* + * Define "standard" transforms for the blocked GEMMs for SVE. + * + * This assumes that A is interleaved 'height' ways, B is interleaved + * 'width'xVL ways and transposed, and that the merge needs to work in + * 'height' x 'width'xVL blocks. + * + * The optional 'block' parameter is for kernels using dot-product type + * instructions like UDOT and SDOT. + */ +template +class StdTransformsSVE +{ +public: + template + void PrepareA(TOperand *out, const TIn *in, const int stride, const int y0, + const int ymax, const int k0, const int kmax, bool transposed) { + if (transposed) { + Transform(out, in, stride, y0, ymax, k0, kmax); + } else { + Transform(out, in, stride, y0, ymax, k0, kmax); + } + } + + template + void PrepareB(TOperand *out, const TIn *in, const int stride, const int x0, + const int xmax, const int k0, const int kmax, bool transposed) { + if (transposed) { + Transform(out, in, stride, x0, xmax, k0, kmax); + } else { + Transform(out, in, stride, x0, xmax, k0, kmax); + } + } + + template + void Merge(TOut *out, const TResult *in, int stride, int y0, int ymax, int x0, int xmax, const TOut alpha, const TOut beta) { + MergeResults(out, in, stride, y0, ymax, x0, xmax, alpha, beta); + } +}; + +} // namespace arm_gemm diff --git a/src/core/NEON/kernels/arm_gemm/transform.hpp b/src/core/NEON/kernels/arm_gemm/transform.hpp index 77d0d87a4d..e422b91c83 100644 --- a/src/core/NEON/kernels/arm_gemm/transform.hpp +++ b/src/core/NEON/kernels/arm_gemm/transform.hpp @@ -40,7 +40,7 @@ struct TransformImpl { static void Transform(TOut* out, const TIn* const in, const int stride, const int y0, const int ymax, const int x0, const int xmax) { // For SVE cases we multiply the interleave factor by the vector length. - const unsigned int IntBy = tIntBy * (sve ? get_vector_length() : 1); + const unsigned int IntBy = tIntBy * (sve ? get_vector_length() / BlockBy : 1); const int n_whole_y_blocks = (ymax - y0) / IntBy; const int y_remainders = (ymax - y0) % IntBy; diff --git a/src/core/NEON/kernels/arm_gemm/transforms/list.hpp b/src/core/NEON/kernels/arm_gemm/transforms/list.hpp index 8ad5b857fb..17328a5d6a 100644 --- a/src/core/NEON/kernels/arm_gemm/transforms/list.hpp +++ b/src/core/NEON/kernels/arm_gemm/transforms/list.hpp @@ -23,9 +23,17 @@ */ #include "a32_interleave_6way_32bit.hpp" #include "a32_transpose_interleave_8way_32bit.hpp" +#ifdef __ARM_FEATURE_SVE +#include "sve_interleave_8way_32bit.hpp" +#include "sve_interleave_8way_block2_16bit.hpp" +#include "sve_interleave_8way_block2_32bit.hpp" +#include "sve_interleave_8way_block4_16bit.hpp" +#include "sve_interleave_8way_block4_8bit.hpp" +#else +#include "a64_interleave_8way_32bit.hpp" +#endif #include "a64_block16_interleave4_8bit.hpp" #include "a64_interleave_8way_16bit.hpp" -#include "a64_interleave_8way_32bit.hpp" #include "a64_interleave_8way_half_to_float.hpp" #include "a64_transpose_interleave_12way_16bit.hpp" #include "a64_transpose_interleave_12way_half_to_float.hpp" diff --git a/src/core/NEON/kernels/arm_gemm/transforms/sve_interleave_8way_32bit.hpp b/src/core/NEON/kernels/arm_gemm/transforms/sve_interleave_8way_32bit.hpp new file mode 100644 index 0000000000..752e837f8d --- /dev/null +++ b/src/core/NEON/kernels/arm_gemm/transforms/sve_interleave_8way_32bit.hpp @@ -0,0 +1,596 @@ +/* + * Copyright (c) 2018 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#pragma once + +#ifdef __ARM_FEATURE_SVE + +template<> +template +inline void TransformImpl<8, 1, false, 4, 4, false>::Transform(T *out, const T *in, int ldin, int y0, int ymax, int k0, int kmax) +{ + uint32_t *master_outptr = reinterpret_cast(out); + const uint32_t *inptr = reinterpret_cast(in); + + for (int y=y0; y +template +inline void TransformImpl<8, 2, false, 2, 2, false>::Transform(T *out, const T *in, int ldin, int y0, int ymax, int k0, int kmax) +{ + uint16_t *master_outptr = reinterpret_cast(out); + const uint16_t *inptr = reinterpret_cast(in); + + for (int y=y0; y +template +inline void TransformImpl<8, 2, false, 4, 4, false>::Transform(T *out, const T *in, int ldin, int y0, int ymax, int k0, int kmax) +{ + uint32_t *master_outptr = reinterpret_cast(out); + const uint32_t *inptr = reinterpret_cast(in); + + for (int y=y0; y +template +inline void TransformImpl<8, 4, false, 2, 2, false>::Transform(T *out, const T *in, int ldin, int y0, int ymax, int k0, int kmax) +{ + uint16_t *master_outptr = reinterpret_cast(out); + const uint16_t *inptr = reinterpret_cast(in); + + for (int y=y0; y +template +inline void TransformImpl<8, 4, false, 1, 1, false>::Transform(T *out, const T *in, int ldin, int y0, int ymax, int k0, int kmax) +{ + uint8_t *master_outptr = reinterpret_cast(out); + const uint8_t *inptr = reinterpret_cast(in); + + for (int y=y0; y +#endif + // Macro for unreachable code (e.g. impossible default cases on switch) #define UNREACHABLE(why) __builtin_unreachable() @@ -31,23 +35,27 @@ // #define UNREACHABLE(why) assert(0 && why) inline int iceildiv(const int a, const int b) { - return (a + b - 1) / b; + return (a + b - 1) / b; } template inline T roundup(const T a, const T b) { - T rem = a % b; + T rem = a % b; - if (rem) { - return a + b - rem; - } else { - return a; - } + if (rem) { + return a + b - rem; + } else { + return a; + } } template inline unsigned long get_vector_length() { +#ifdef __ARM_FEATURE_SVE + const unsigned long length = svcntb(); +#else const unsigned long length = 16; +#endif return length / sizeof(T); -} +} \ No newline at end of file diff --git a/src/core/NEON/kernels/assembly/NEGEMMInterleavedStrategies.h b/src/core/NEON/kernels/assembly/NEGEMMInterleavedStrategies.h index 00e483c0f8..69842fec80 100644 --- a/src/core/NEON/kernels/assembly/NEGEMMInterleavedStrategies.h +++ b/src/core/NEON/kernels/assembly/NEGEMMInterleavedStrategies.h @@ -37,6 +37,10 @@ #include "../arm_gemm/kernels/a64_gemm_u8_4x4.hpp" #include "../arm_gemm/kernels/a64_hgemm_24x8.hpp" #include "../arm_gemm/kernels/a64_sgemm_12x8.hpp" +#include "../arm_gemm/kernels/sve_interleaved_fp16_mla_3VLx8.hpp" +#include "../arm_gemm/kernels/sve_interleaved_fp32_mla_3VLx8.hpp" +#include "../arm_gemm/kernels/sve_interleaved_s8s32_dot_3VLx8.hpp" +#include "../arm_gemm/kernels/sve_interleaved_u8u32_dot_3VLx8.hpp" namespace arm_compute { @@ -54,6 +58,29 @@ struct Kernel #define DEFINE_STRATEGY(strat) \ DEFINE_STRATEGY_SUFFIX(strat, "") +#ifdef __ARM_FEATURE_SVE +template <> +struct Kernel +{ + DEFINE_STRATEGY(interleaved_fp32_mla_3VLx8) +}; +template <> +struct Kernel +{ + DEFINE_STRATEGY(interleaved_fp16_mla_3VLx8) +}; +template +struct Kernel +{ + DEFINE_STRATEGY(interleaved_s8s32_dot_3VLx8) +}; +template +struct Kernel +{ + DEFINE_STRATEGY(interleaved_u8u32_dot_3VLx8) +}; +#else /* __ARM_FEATURE_SVE */ + #ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC template <> struct Kernel @@ -96,6 +123,7 @@ struct Kernel DEFINE_STRATEGY(sgemm_8x6) }; #endif /* __aarch64__ */ +#endif /* __ARM_FEATURE_SVE */ #undef DEFINE_STRATEGY #undef DEFINE_STRATEGY_SUFFIX diff --git a/src/runtime/NEON/functions/NEDeconvolutionLayer.cpp b/src/runtime/NEON/functions/NEDeconvolutionLayer.cpp index c2d7d6a9d9..6887a0a8cd 100644 --- a/src/runtime/NEON/functions/NEDeconvolutionLayer.cpp +++ b/src/runtime/NEON/functions/NEDeconvolutionLayer.cpp @@ -27,7 +27,7 @@ #include "arm_compute/core/Utils.h" #include "arm_compute/core/Validate.h" #include "arm_compute/core/utils/misc/ShapeCalculator.h" -#include "arm_compute/runtime/CPP/CPPScheduler.h" +#include "arm_compute/runtime/NEON/NEScheduler.h" using namespace arm_compute; using namespace arm_compute::misc::shape_calculator; @@ -166,7 +166,7 @@ void NEDeconvolutionLayer::prepare() // Run weights flipping and mark original weights tensor as unused _weights_flipped.allocator()->allocate(); - CPPScheduler::get().schedule(&_flip_weights, Window::DimZ); + NEScheduler::get().schedule(&_flip_weights, Window::DimZ); _original_weights->mark_as_unused(); // Prepare convolution diff --git a/support/Semaphore.h b/support/Semaphore.h index 6cdf196dee..636d5caf79 100644 --- a/support/Semaphore.h +++ b/support/Semaphore.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 ARM Limited. + * Copyright (c) 2017-2018 ARM Limited. * * SPDX-License-Identifier: MIT * @@ -74,14 +74,17 @@ public: Semaphore(int value = 0) : _value(value) { + (void)_value; } /** Signals a semaphore */ inline void signal() { + (void)_value; } /** Waits on a semaphore */ inline void wait() { + (void)_value; } private: diff --git a/tests/AssetsLibrary.cpp b/tests/AssetsLibrary.cpp index ee876f91e3..c6d86d1c1a 100644 --- a/tests/AssetsLibrary.cpp +++ b/tests/AssetsLibrary.cpp @@ -416,7 +416,7 @@ RawTensor AssetsLibrary::load_image(const std::string &name) const const RawTensor &AssetsLibrary::find_or_create_raw_tensor(const std::string &name, Format format) const { - std::lock_guard guard(_format_lock); + std::lock_guard guard(_format_lock); const RawTensor *ptr = _cache.find(std::forward_as_tuple(name, format)); @@ -440,7 +440,7 @@ const RawTensor &AssetsLibrary::find_or_create_raw_tensor(const std::string &nam const RawTensor &AssetsLibrary::find_or_create_raw_tensor(const std::string &name, Format format, Channel channel) const { - std::lock_guard guard(_channel_lock); + std::lock_guard guard(_channel_lock); const RawTensor *ptr = _cache.find(std::forward_as_tuple(name, format, channel)); diff --git a/tests/AssetsLibrary.h b/tests/AssetsLibrary.h index b1c8c430ad..7af036d256 100644 --- a/tests/AssetsLibrary.h +++ b/tests/AssetsLibrary.h @@ -414,8 +414,8 @@ private: const RawTensor &find_or_create_raw_tensor(const std::string &name, Format format, Channel channel) const; mutable TensorCache _cache{}; - mutable std::mutex _format_lock{}; - mutable std::mutex _channel_lock{}; + mutable arm_compute::Mutex _format_lock{}; + mutable arm_compute::Mutex _channel_lock{}; const std::string _library_path; std::random_device::result_type _seed; }; diff --git a/tests/SConscript b/tests/SConscript index ac826f848d..24714efa74 100644 --- a/tests/SConscript +++ b/tests/SConscript @@ -124,7 +124,7 @@ if env['gles_compute']: if env['os'] == 'android': test_env.Append(LIBS = ["log"]) -else: +elif env['os'] != 'bare_metal': test_env.Append(LIBS = ["rt"]) if test_env['benchmark_tests']: diff --git a/tests/TensorCache.h b/tests/TensorCache.h index 7cf64ffbe5..c8f21116d6 100644 --- a/tests/TensorCache.h +++ b/tests/TensorCache.h @@ -26,6 +26,8 @@ #include "RawTensor.h" +#include "support/Mutex.h" + #include #include #include @@ -84,10 +86,10 @@ private: using FormatMap = std::map, RawTensor>; using ChannelMap = std::map, RawTensor>; - FormatMap _raw_tensor_cache{}; - ChannelMap _raw_tensor_channel_cache{}; - std::mutex _raw_tensor_cache_mutex{}; - std::mutex _raw_tensor_channel_cache_mutex{}; + FormatMap _raw_tensor_cache{}; + ChannelMap _raw_tensor_channel_cache{}; + arm_compute::Mutex _raw_tensor_cache_mutex{}; + arm_compute::Mutex _raw_tensor_channel_cache_mutex{}; }; inline RawTensor *TensorCache::find(std::tuple key) @@ -104,13 +106,13 @@ inline RawTensor *TensorCache::find(std::tuple key, RawTensor raw) { - std::lock_guard lock(_raw_tensor_channel_cache_mutex); + std::lock_guard lock(_raw_tensor_cache_mutex); return std::get<0>(_raw_tensor_cache.emplace(std::move(key), std::move(raw)))->second; } inline RawTensor &TensorCache::add(std::tuple key, RawTensor raw) { - std::lock_guard lock(_raw_tensor_channel_cache_mutex); + std::lock_guard lock(_raw_tensor_channel_cache_mutex); return std::get<0>(_raw_tensor_channel_cache.emplace(std::move(key), std::move(raw)))->second; } } // namespace test diff --git a/tests/framework/instruments/Instruments.h b/tests/framework/instruments/Instruments.h index 705fc59b29..77c74b7b3e 100644 --- a/tests/framework/instruments/Instruments.h +++ b/tests/framework/instruments/Instruments.h @@ -24,10 +24,12 @@ #ifndef ARM_COMPUTE_TEST_INSTRUMENTS #define ARM_COMPUTE_TEST_INSTRUMENTS +#if !defined(BARE_METAL) #include "MaliCounter.h" #include "OpenCLMemoryUsage.h" #include "OpenCLTimer.h" #include "PMUCounter.h" +#endif /* !defined(BARE_METAL) */ #include "SchedulerTimer.h" #include "WallClockTimer.h" -- cgit v1.2.1