From 3f70cd053573cb6140990ab619ead865f55f3139 Mon Sep 17 00:00:00 2001 From: SiCong Li Date: Wed, 17 May 2023 13:46:13 +0100 Subject: Move lut kernel to sve2 category This specific Lut kernel uses sve2 instructions Resolves: COMPMID-6268 Signed-off-by: SiCong Li Change-Id: I44fa3812e96fa79b3d1e1e3a31d587581f59f0e1 Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/9675 Reviewed-by: Viet-Hoa Do Reviewed-by: Jakub Sujak Comments-Addressed: Arm Jenkins Benchmark: Arm Jenkins Tested-by: Arm Jenkins --- filelist.json | 22 +- src/BUILD.bazel | 8 +- src/CMakeLists.txt | 11 +- src/cpu/kernels/CpuActivationKernel.cpp | 8 +- src/cpu/kernels/CpuElementwiseUnaryKernel.cpp | 6 +- src/cpu/kernels/activation/generic/sve/lut.cpp | 51 -- src/cpu/kernels/activation/generic/sve2/lut.cpp | 51 ++ src/cpu/kernels/activation/list.h | 4 +- .../kernels/elementwise_unary/generic/sve/q8.cpp | 54 -- .../kernels/elementwise_unary/generic/sve2/q8.cpp | 54 ++ src/cpu/kernels/elementwise_unary/list.h | 2 +- src/cpu/kernels/lut/generic/sve/u8.cpp | 647 --------------------- src/cpu/kernels/lut/generic/sve2/u8.cpp | 646 ++++++++++++++++++++ src/cpu/kernels/lut/list.h | 2 +- 14 files changed, 784 insertions(+), 782 deletions(-) delete mode 100644 src/cpu/kernels/activation/generic/sve/lut.cpp create mode 100644 src/cpu/kernels/activation/generic/sve2/lut.cpp delete mode 100644 src/cpu/kernels/elementwise_unary/generic/sve/q8.cpp create mode 100644 src/cpu/kernels/elementwise_unary/generic/sve2/q8.cpp delete mode 100644 src/cpu/kernels/lut/generic/sve/u8.cpp create mode 100644 src/cpu/kernels/lut/generic/sve2/u8.cpp diff --git a/filelist.json b/filelist.json index 807000a623..c12873ad63 100644 --- a/filelist.json +++ b/filelist.json @@ -891,11 +891,13 @@ }, "sve": { "fp16": [ "src/cpu/kernels/activation/generic/sve/fp16.cpp" ], - "fp32": [ "src/cpu/kernels/activation/generic/sve/fp32.cpp" ], - "qasymm8": ["src/cpu/kernels/activation/generic/sve/lut.cpp"] + "fp32": [ "src/cpu/kernels/activation/generic/sve/fp32.cpp" ] }, "sve2":{ - "qasymm8": [ "src/cpu/kernels/activation/generic/sve2/qasymm8.cpp" ], + "qasymm8": [ + "src/cpu/kernels/activation/generic/sve2/qasymm8.cpp", + "src/cpu/kernels/activation/generic/sve2/lut.cpp" + ], "qasymm8_signed": [ "src/cpu/kernels/activation/generic/sve2/qasymm8_signed.cpp" ], "qsymm16": [ "src/cpu/kernels/activation/generic/sve2/qsymm16.cpp" ] } @@ -1454,9 +1456,11 @@ "common": ["src/cpu/kernels/elementwise_unary/generic/sve/impl.cpp" ], "integer": ["src/cpu/kernels/elementwise_unary/generic/sve/integer.cpp"], "fp32": ["src/cpu/kernels/elementwise_unary/generic/sve/fp32.cpp"], - "fp16": ["src/cpu/kernels/elementwise_unary/generic/sve/fp16.cpp"], - "qasymm8": ["src/cpu/kernels/elementwise_unary/generic/sve/q8.cpp"], - "qasymm8_signed": ["src/cpu/kernels/elementwise_unary/generic/sve/q8.cpp"] + "fp16": ["src/cpu/kernels/elementwise_unary/generic/sve/fp16.cpp"] + }, + "sve2": { + "qasymm8": ["src/cpu/kernels/elementwise_unary/generic/sve2/q8.cpp"], + "qasymm8_signed": ["src/cpu/kernels/elementwise_unary/generic/sve2/q8.cpp"] } } }, @@ -1802,9 +1806,9 @@ "qasymm8": ["src/cpu/kernels/lut/generic/neon/u8.cpp"], "qasymm8_signed": ["src/cpu/kernels/lut/generic/neon/u8.cpp"] }, - "sve": { - "qasymm8": ["src/cpu/kernels/lut/generic/sve/u8.cpp"], - "qasymm8_signed": ["src/cpu/kernels/lut/generic/sve/u8.cpp"] + "sve2": { + "qasymm8": ["src/cpu/kernels/lut/generic/sve2/u8.cpp"], + "qasymm8_signed": ["src/cpu/kernels/lut/generic/sve2/u8.cpp"] } } }, diff --git a/src/BUILD.bazel b/src/BUILD.bazel index 8f35c7a659..12dc1ca340 100644 --- a/src/BUILD.bazel +++ b/src/BUILD.bazel @@ -107,7 +107,8 @@ filegroup( filegroup( name = "arm_compute_sve2_srcs", - srcs = ["cpu/kernels/activation/generic/sve2/qasymm8.cpp", + srcs = ["cpu/kernels/activation/generic/sve2/lut.cpp", + "cpu/kernels/activation/generic/sve2/qasymm8.cpp", "cpu/kernels/activation/generic/sve2/qasymm8_signed.cpp", "cpu/kernels/activation/generic/sve2/qsymm16.cpp", "cpu/kernels/add/generic/sve2/qasymm8.cpp", @@ -115,6 +116,8 @@ filegroup( "cpu/kernels/add/generic/sve2/qsymm16.cpp", "cpu/kernels/elementwise_binary/generic/sve2/qasymm8.cpp", "cpu/kernels/elementwise_binary/generic/sve2/qasymm8_signed.cpp", + "cpu/kernels/elementwise_unary/generic/sve2/q8.cpp", + "cpu/kernels/lut/generic/sve2/u8.cpp", "cpu/kernels/softmax/generic/sve2/impl.cpp", "cpu/kernels/softmax/generic/sve2/qasymm8.cpp", "cpu/kernels/softmax/generic/sve2/qasymm8_signed.cpp"] + @@ -323,7 +326,6 @@ filegroup( "core/NEON/kernels/convolution/winograd/output_transforms/sme_fp32_mopa_4x4_3x3.cpp", "cpu/kernels/activation/generic/sve/fp16.cpp", "cpu/kernels/activation/generic/sve/fp32.cpp", - "cpu/kernels/activation/generic/sve/lut.cpp", "cpu/kernels/add/generic/sve/fp16.cpp", "cpu/kernels/add/generic/sve/fp32.cpp", "cpu/kernels/add/generic/sve/impl.cpp", @@ -336,8 +338,6 @@ filegroup( "cpu/kernels/elementwise_unary/generic/sve/fp32.cpp", "cpu/kernels/elementwise_unary/generic/sve/impl.cpp", "cpu/kernels/elementwise_unary/generic/sve/integer.cpp", - "cpu/kernels/elementwise_unary/generic/sve/q8.cpp", - "cpu/kernels/lut/generic/sve/u8.cpp", "cpu/kernels/scale/sve/fp16.cpp", "cpu/kernels/scale/sve/fp32.cpp", "cpu/kernels/scale/sve/integer.cpp", diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index cb48692a72..5d756da568 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -302,7 +302,6 @@ target_sources( core/NEON/kernels/convolution/winograd/output_transforms/sme_fp32_mopa_4x4_3x3.cpp cpu/kernels/activation/generic/sve/fp16.cpp cpu/kernels/activation/generic/sve/fp32.cpp - cpu/kernels/activation/generic/sve/lut.cpp cpu/kernels/add/generic/sve/fp16.cpp cpu/kernels/add/generic/sve/fp32.cpp cpu/kernels/add/generic/sve/impl.cpp @@ -315,8 +314,6 @@ target_sources( cpu/kernels/elementwise_unary/generic/sve/fp32.cpp cpu/kernels/elementwise_unary/generic/sve/impl.cpp cpu/kernels/elementwise_unary/generic/sve/integer.cpp - cpu/kernels/elementwise_unary/generic/sve/q8.cpp - cpu/kernels/lut/generic/sve/u8.cpp cpu/kernels/scale/sve/fp16.cpp cpu/kernels/scale/sve/fp32.cpp cpu/kernels/scale/sve/integer.cpp @@ -332,7 +329,8 @@ target_sources( target_sources( arm_compute_sve2 PRIVATE - cpu/kernels/activation/generic/sve2/qasymm8.cpp + cpu/kernels/activation/generic/sve2/lut.cpp + cpu/kernels/activation/generic/sve2/qasymm8.cpp cpu/kernels/activation/generic/sve2/qasymm8_signed.cpp cpu/kernels/activation/generic/sve2/qsymm16.cpp cpu/kernels/add/generic/sve2/qasymm8.cpp @@ -340,6 +338,8 @@ target_sources( cpu/kernels/add/generic/sve2/qsymm16.cpp cpu/kernels/elementwise_binary/generic/sve2/qasymm8.cpp cpu/kernels/elementwise_binary/generic/sve2/qasymm8_signed.cpp + cpu/kernels/elementwise_unary/generic/sve2/q8.cpp + cpu/kernels/lut/generic/sve2/u8.cpp cpu/kernels/softmax/generic/sve2/impl.cpp cpu/kernels/softmax/generic/sve2/qasymm8.cpp cpu/kernels/softmax/generic/sve2/qasymm8_signed.cpp @@ -976,5 +976,4 @@ target_sources( runtime/Tensor.cpp runtime/TensorAllocator.cpp runtime/Utils.cpp -) - \ No newline at end of file +) \ No newline at end of file diff --git a/src/cpu/kernels/CpuActivationKernel.cpp b/src/cpu/kernels/CpuActivationKernel.cpp index 04a9731f4a..20a8489cdd 100644 --- a/src/cpu/kernels/CpuActivationKernel.cpp +++ b/src/cpu/kernels/CpuActivationKernel.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2022 Arm Limited. + * Copyright (c) 2017-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -47,9 +47,9 @@ static const std::vector available_kernel { #ifdef ARM_COMPUTE_ENABLE_SVE { - "sve_q8_activation_lut", - [](const ActivationDataTypeISASelectorData & data) { return ActivationLayerInfo::is_lut_supported(data.f, data.dt) && data.cpumodel == CPUModel::A510 && data.isa.sve; }, - REGISTER_QASYMM8_SVE(arm_compute::cpu::sve_q8_activation_lut) + "sve2_q8_activation_lut", + [](const ActivationDataTypeISASelectorData & data) { return ActivationLayerInfo::is_lut_supported(data.f, data.dt) && data.cpumodel == CPUModel::A510 && data.isa.sve2; }, + REGISTER_QASYMM8_SVE2(arm_compute::cpu::sve2_q8_activation_lut) }, #endif // ARM_COMPUTE_ENABLE_SVE #ifdef __aarch64__ diff --git a/src/cpu/kernels/CpuElementwiseUnaryKernel.cpp b/src/cpu/kernels/CpuElementwiseUnaryKernel.cpp index dbb752aef3..04a7f15715 100644 --- a/src/cpu/kernels/CpuElementwiseUnaryKernel.cpp +++ b/src/cpu/kernels/CpuElementwiseUnaryKernel.cpp @@ -167,12 +167,12 @@ static const std::vector avai }, #ifdef __aarch64__ { - "sve_q8_elementwise_unary", + "sve2_q8_elementwise_unary", [](const DataTypeISASelectorData & data) { - return (data.dt == DataType::QASYMM8 || data.dt == DataType::QASYMM8_SIGNED) && data.isa.sve; + return (data.dt == DataType::QASYMM8 || data.dt == DataType::QASYMM8_SIGNED) && data.isa.sve2; }, - REGISTER_QASYMM8_SVE(sve_q8_elementwise_unary), + REGISTER_QASYMM8_SVE2(sve2_q8_elementwise_unary), &q8_prepare_lut, }, { diff --git a/src/cpu/kernels/activation/generic/sve/lut.cpp b/src/cpu/kernels/activation/generic/sve/lut.cpp deleted file mode 100644 index b4042662b9..0000000000 --- a/src/cpu/kernels/activation/generic/sve/lut.cpp +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2022-2023 Arm Limited. - * - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to - * deal in the Software without restriction, including without limitation the - * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -#include "arm_compute/core/Helpers.h" -#include "src/cpu/kernels/lut/list.h" - -namespace arm_compute -{ -namespace cpu -{ -#ifdef __aarch64__ -void sve_q8_activation_lut(const ITensor *src, ITensor *dst, const ActivationLayerInfo &act_info, const Window &window) -{ - ARM_COMPUTE_ERROR_ON(!ActivationLayerInfo::is_lut_supported(act_info.activation(), src->info()->data_type())); - const auto window_end_x = window.x().end(); - Window win_collapsed = window.collapse_if_possible(window, Window::DimZ); - win_collapsed.set(Window::DimX, Window::Dimension(0, 1, 1)); - Iterator input(src, win_collapsed); - Iterator output(dst, win_collapsed); - execute_window_loop(win_collapsed, [&](const Coordinates &) - { - const auto input_ptr = input.ptr(); - auto output_ptr = output.ptr(); - lut_u8_sve(act_info.lut().data(), 1u, window_end_x, &input_ptr, &output_ptr); - }, - input, output); -} -#endif // __aarch64__ -} // namespace cpu -} // namespace arm_compute diff --git a/src/cpu/kernels/activation/generic/sve2/lut.cpp b/src/cpu/kernels/activation/generic/sve2/lut.cpp new file mode 100644 index 0000000000..2e5975744b --- /dev/null +++ b/src/cpu/kernels/activation/generic/sve2/lut.cpp @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "arm_compute/core/Helpers.h" +#include "src/cpu/kernels/lut/list.h" + +namespace arm_compute +{ +namespace cpu +{ +#ifdef __aarch64__ +void sve2_q8_activation_lut(const ITensor *src, ITensor *dst, const ActivationLayerInfo &act_info, const Window &window) +{ + ARM_COMPUTE_ERROR_ON(!ActivationLayerInfo::is_lut_supported(act_info.activation(), src->info()->data_type())); + const auto window_end_x = window.x().end(); + Window win_collapsed = window.collapse_if_possible(window, Window::DimZ); + win_collapsed.set(Window::DimX, Window::Dimension(0, 1, 1)); + Iterator input(src, win_collapsed); + Iterator output(dst, win_collapsed); + execute_window_loop(win_collapsed, [&](const Coordinates &) + { + const auto input_ptr = input.ptr(); + auto output_ptr = output.ptr(); + lut_u8_sve2(act_info.lut().data(), 1u, window_end_x, &input_ptr, &output_ptr); + }, + input, output); +} +#endif // __aarch64__ +} // namespace cpu +} // namespace arm_compute diff --git a/src/cpu/kernels/activation/list.h b/src/cpu/kernels/activation/list.h index c2149b38ff..6550ddfeca 100644 --- a/src/cpu/kernels/activation/list.h +++ b/src/cpu/kernels/activation/list.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2022 Arm Limited. + * Copyright (c) 2020-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -34,7 +34,7 @@ namespace cpu #ifdef __aarch64__ DECLARE_ACTIVATION_KERNEL(neon_q8_activation_lut); #endif // __aarch64__ -DECLARE_ACTIVATION_KERNEL(sve_q8_activation_lut); +DECLARE_ACTIVATION_KERNEL(sve2_q8_activation_lut); DECLARE_ACTIVATION_KERNEL(neon_qasymm8_activation); DECLARE_ACTIVATION_KERNEL(sve2_qasymm8_activation); DECLARE_ACTIVATION_KERNEL(neon_qasymm8_signed_activation); diff --git a/src/cpu/kernels/elementwise_unary/generic/sve/q8.cpp b/src/cpu/kernels/elementwise_unary/generic/sve/q8.cpp deleted file mode 100644 index b68f691086..0000000000 --- a/src/cpu/kernels/elementwise_unary/generic/sve/q8.cpp +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) 2023 Arm Limited. - * - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to - * deal in the Software without restriction, including without limitation the - * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -#include "arm_compute/core/Helpers.h" -#include "src/cpu/kernels/lut/list.h" - -namespace arm_compute -{ -namespace cpu -{ - -void sve_q8_elementwise_unary(const ITensor *in, ITensor *out, const Window &window, ElementWiseUnary op, const uint8_t *lut) -{ - ARM_COMPUTE_UNUSED(op); - - auto win = window; - const auto window_end_x = window.x().end(); - win.set(0, Window::Dimension(0, 1, 1)); - - Iterator src_it(in, win); - Iterator dst_it(out, win); - - execute_window_loop(win, [&](const Coordinates &) { - const auto src_ptr = src_it.ptr(); - auto dst_ptr = dst_it.ptr(); - - lut_u8_sve(lut, 1, window_end_x, &src_ptr, &dst_ptr); - }, - src_it, dst_it); -} - -} // namespace cpu -} // namespace arm_compute diff --git a/src/cpu/kernels/elementwise_unary/generic/sve2/q8.cpp b/src/cpu/kernels/elementwise_unary/generic/sve2/q8.cpp new file mode 100644 index 0000000000..7e32f50132 --- /dev/null +++ b/src/cpu/kernels/elementwise_unary/generic/sve2/q8.cpp @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "arm_compute/core/Helpers.h" +#include "src/cpu/kernels/lut/list.h" + +namespace arm_compute +{ +namespace cpu +{ +void sve2_q8_elementwise_unary(const ITensor *in, ITensor *out, const Window &window, ElementWiseUnary op, const uint8_t *lut) +{ + ARM_COMPUTE_UNUSED(op); + + auto win = window; + const auto window_end_x = window.x().end(); + win.set(0, Window::Dimension(0, 1, 1)); + + Iterator src_it(in, win); + Iterator dst_it(out, win); + + execute_window_loop(win, [&](const Coordinates &) + { + const auto src_ptr = src_it.ptr(); + auto dst_ptr = dst_it.ptr(); + + lut_u8_sve2(lut, 1, window_end_x, &src_ptr, &dst_ptr); + }, + src_it, dst_it); +} + +} // namespace cpu +} // namespace arm_compute diff --git a/src/cpu/kernels/elementwise_unary/list.h b/src/cpu/kernels/elementwise_unary/list.h index 432fabf4af..a9701afdd8 100644 --- a/src/cpu/kernels/elementwise_unary/list.h +++ b/src/cpu/kernels/elementwise_unary/list.h @@ -37,7 +37,7 @@ namespace cpu DECLARE_ELEMETWISE_UNARY_KERNEL(sve_fp32_elementwise_unary); DECLARE_ELEMETWISE_UNARY_KERNEL(sve_fp16_elementwise_unary); DECLARE_ELEMETWISE_UNARY_KERNEL(sve_s32_elementwise_unary); -DECLARE_ELEMETWISE_UNARY_KERNEL(sve_q8_elementwise_unary); +DECLARE_ELEMETWISE_UNARY_KERNEL(sve2_q8_elementwise_unary); DECLARE_ELEMETWISE_UNARY_KERNEL(neon_fp32_elementwise_unary); DECLARE_ELEMETWISE_UNARY_KERNEL(neon_fp16_elementwise_unary); DECLARE_ELEMETWISE_UNARY_KERNEL(neon_s32_elementwise_unary); diff --git a/src/cpu/kernels/lut/generic/sve/u8.cpp b/src/cpu/kernels/lut/generic/sve/u8.cpp deleted file mode 100644 index 70f3a2e6fb..0000000000 --- a/src/cpu/kernels/lut/generic/sve/u8.cpp +++ /dev/null @@ -1,647 +0,0 @@ -/* - * Copyright (c) 2022-2023 Arm Limited. - * - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to - * deal in the Software without restriction, including without limitation the - * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -#include "src/cpu/kernels/lut/list.h" - -#ifdef __aarch64__ -#ifdef ARM_COMPUTE_ENABLE_SVE - -namespace arm_compute -{ -namespace cpu -{ - -void lut_u8_sve( - const uint8_t *table, - size_t num_strings, - size_t string_length, - const uint8_t *const *input, - uint8_t *const *output) -{ - __asm__ __volatile__( - "ptrue p0.b\n" - "cntd x25\n" - "addvl %x[table], %x[table], #8\n" - "ld1b { z16.b }, p0/Z, [%x[table], #-8, MUL VL]\n" - "tbnz x25, #5, 1f\n" - "ld1b { z17.b }, p0/Z, [%x[table], #-7, MUL VL]\n" - "tbnz x25, #4, 1f\n" - "ld1b { z18.b }, p0/Z, [%x[table], #-6, MUL VL]\n" - "ld1b { z19.b }, p0/Z, [%x[table], #-5, MUL VL]\n" - "tbnz x25, #3, 1f\n" - "ld1b { z20.b }, p0/Z, [%x[table], #-4, MUL VL]\n" - "ld1b { z21.b }, p0/Z, [%x[table], #-3, MUL VL]\n" - "ld1b { z22.b }, p0/Z, [%x[table], #-2, MUL VL]\n" - "ld1b { z23.b }, p0/Z, [%x[table], #-1, MUL VL]\n" - "tbnz x25, #2, 1f\n" - "ld1b { z24.b }, p0/Z, [%x[table]]\n" - "ld1b { z25.b }, p0/Z, [%x[table], #1, MUL VL]\n" - "ld1b { z26.b }, p0/Z, [%x[table], #2, MUL VL]\n" - "ld1b { z27.b }, p0/Z, [%x[table], #3, MUL VL]\n" - "ld1b { z28.b }, p0/Z, [%x[table], #4, MUL VL]\n" - "ld1b { z29.b }, p0/Z, [%x[table], #5, MUL VL]\n" - "ld1b { z30.b }, p0/Z, [%x[table], #6, MUL VL]\n" - "ld1b { z31.b }, p0/Z, [%x[table], #7, MUL VL]\n" - "1:" // Table load done - "mov x24, #0x0\n" - "2:" // string loop - "ldr x23, [%x[input], x24, LSL #0x3]\n" - "ldr x22, [%x[output], x24, LSL #0x3]\n" - "tbnz x25, #5, 14f\n" - "tbnz x25, #4, 11f\n" - "tbnz x25, #3, 8f\n" - "tbnz x25, #2, 5f\n" - "mov z12.b, #0x10\n" - "mov x21, %x[string_length]\n" - "ptrue p5.b\n" - "ptrue p4.b\n" - "ptrue p3.b\n" - "ptrue p2.b\n" - "ptrue p1.b\n" - "ptrue p0.b\n" - "3:" // 16 rounds: width loop - "addvl x20, x21, #-6\n" - "cmp x20, XZR\n" - "bge 4f\n" - "mov x20, #0x0\n" - "addvl x20, x20, #1\n" - "whilelt p5.b, XZR, x21\n" - "whilelt p4.b, x20, x21\n" - "addvl x20, x20, #1\n" - "whilelt p3.b, x20, x21\n" - "addvl x20, x20, #1\n" - "whilelt p2.b, x20, x21\n" - "addvl x20, x20, #1\n" - "whilelt p1.b, x20, x21\n" - "addvl x20, x20, #1\n" - "whilelt p0.b, x20, x21\n" - "4:" // 16 rounds: predicate OK - "ld1b { z11.b }, p5/Z, [x23]\n" - "ld1b { z10.b }, p4/Z, [x23, #1, MUL VL]\n" - "tbl z9.b, { z16.b }, z11.b\n" - "ld1b { z8.b }, p3/Z, [x23, #2, MUL VL]\n" - "ld1b { z7.b }, p2/Z, [x23, #3, MUL VL]\n" - "sub z11.b, z11.b, z12.b\n" - "ld1b { z6.b }, p1/Z, [x23, #4, MUL VL]\n" - "ld1b { z5.b }, p0/Z, [x23, #5, MUL VL]\n" - "tbl z4.b, { z16.b }, z10.b\n" - "sub z10.b, z10.b, z12.b\n" - "tbl z3.b, { z16.b }, z8.b\n" - "sub z8.b, z8.b, z12.b\n" - "tbl z2.b, { z16.b }, z7.b\n" - "sub z7.b, z7.b, z12.b\n" - "tbl z1.b, { z16.b }, z6.b\n" - "sub z6.b, z6.b, z12.b\n" - "tbl z0.b, { z16.b }, z5.b\n" - "sub z5.b, z5.b, z12.b\n" - ".inst 0x052b2e29 // tbx z9.b, z17.b, z11.b\n" - "sub z11.b, z11.b, z12.b\n" - ".inst 0x052a2e24 // tbx z4.b, z17.b, z10.b\n" - "sub z10.b, z10.b, z12.b\n" - ".inst 0x05282e23 // tbx z3.b, z17.b, z8.b\n" - "sub z8.b, z8.b, z12.b\n" - ".inst 0x05272e22 // tbx z2.b, z17.b, z7.b\n" - "sub z7.b, z7.b, z12.b\n" - ".inst 0x05262e21 // tbx z1.b, z17.b, z6.b\n" - "sub z6.b, z6.b, z12.b\n" - ".inst 0x05252e20 // tbx z0.b, z17.b, z5.b\n" - "sub z5.b, z5.b, z12.b\n" - ".inst 0x052b2e49 // tbx z9.b, z18.b, z11.b\n" - "sub z11.b, z11.b, z12.b\n" - ".inst 0x052a2e44 // tbx z4.b, z18.b, z10.b\n" - "sub z10.b, z10.b, z12.b\n" - ".inst 0x05282e43 // tbx z3.b, z18.b, z8.b\n" - "sub z8.b, z8.b, z12.b\n" - ".inst 0x05272e42 // tbx z2.b, z18.b, z7.b\n" - "sub z7.b, z7.b, z12.b\n" - ".inst 0x05262e41 // tbx z1.b, z18.b, z6.b\n" - "sub z6.b, z6.b, z12.b\n" - ".inst 0x05252e40 // tbx z0.b, z18.b, z5.b\n" - "sub z5.b, z5.b, z12.b\n" - ".inst 0x052b2e69 // tbx z9.b, z19.b, z11.b\n" - "sub z11.b, z11.b, z12.b\n" - ".inst 0x052a2e64 // tbx z4.b, z19.b, z10.b\n" - "sub z10.b, z10.b, z12.b\n" - ".inst 0x05282e63 // tbx z3.b, z19.b, z8.b\n" - "sub z8.b, z8.b, z12.b\n" - ".inst 0x05272e62 // tbx z2.b, z19.b, z7.b\n" - "sub z7.b, z7.b, z12.b\n" - ".inst 0x05262e61 // tbx z1.b, z19.b, z6.b\n" - "sub z6.b, z6.b, z12.b\n" - ".inst 0x05252e60 // tbx z0.b, z19.b, z5.b\n" - "sub z5.b, z5.b, z12.b\n" - ".inst 0x052b2e89 // tbx z9.b, z20.b, z11.b\n" - "sub z11.b, z11.b, z12.b\n" - ".inst 0x052a2e84 // tbx z4.b, z20.b, z10.b\n" - "sub z10.b, z10.b, z12.b\n" - ".inst 0x05282e83 // tbx z3.b, z20.b, z8.b\n" - "sub z8.b, z8.b, z12.b\n" - ".inst 0x05272e82 // tbx z2.b, z20.b, z7.b\n" - "sub z7.b, z7.b, z12.b\n" - ".inst 0x05262e81 // tbx z1.b, z20.b, z6.b\n" - "sub z6.b, z6.b, z12.b\n" - ".inst 0x05252e80 // tbx z0.b, z20.b, z5.b\n" - "sub z5.b, z5.b, z12.b\n" - ".inst 0x052b2ea9 // tbx z9.b, z21.b, z11.b\n" - "sub z11.b, z11.b, z12.b\n" - ".inst 0x052a2ea4 // tbx z4.b, z21.b, z10.b\n" - "sub z10.b, z10.b, z12.b\n" - ".inst 0x05282ea3 // tbx z3.b, z21.b, z8.b\n" - "sub z8.b, z8.b, z12.b\n" - ".inst 0x05272ea2 // tbx z2.b, z21.b, z7.b\n" - "sub z7.b, z7.b, z12.b\n" - ".inst 0x05262ea1 // tbx z1.b, z21.b, z6.b\n" - "sub z6.b, z6.b, z12.b\n" - ".inst 0x05252ea0 // tbx z0.b, z21.b, z5.b\n" - "sub z5.b, z5.b, z12.b\n" - ".inst 0x052b2ec9 // tbx z9.b, z22.b, z11.b\n" - "sub z11.b, z11.b, z12.b\n" - ".inst 0x052a2ec4 // tbx z4.b, z22.b, z10.b\n" - "sub z10.b, z10.b, z12.b\n" - ".inst 0x05282ec3 // tbx z3.b, z22.b, z8.b\n" - "sub z8.b, z8.b, z12.b\n" - ".inst 0x05272ec2 // tbx z2.b, z22.b, z7.b\n" - "sub z7.b, z7.b, z12.b\n" - ".inst 0x05262ec1 // tbx z1.b, z22.b, z6.b\n" - "sub z6.b, z6.b, z12.b\n" - ".inst 0x05252ec0 // tbx z0.b, z22.b, z5.b\n" - "sub z5.b, z5.b, z12.b\n" - ".inst 0x052b2ee9 // tbx z9.b, z23.b, z11.b\n" - "sub z11.b, z11.b, z12.b\n" - ".inst 0x052a2ee4 // tbx z4.b, z23.b, z10.b\n" - "sub z10.b, z10.b, z12.b\n" - ".inst 0x05282ee3 // tbx z3.b, z23.b, z8.b\n" - "sub z8.b, z8.b, z12.b\n" - ".inst 0x05272ee2 // tbx z2.b, z23.b, z7.b\n" - "sub z7.b, z7.b, z12.b\n" - ".inst 0x05262ee1 // tbx z1.b, z23.b, z6.b\n" - "sub z6.b, z6.b, z12.b\n" - ".inst 0x05252ee0 // tbx z0.b, z23.b, z5.b\n" - "sub z5.b, z5.b, z12.b\n" - ".inst 0x052b2f09 // tbx z9.b, z24.b, z11.b\n" - "sub z11.b, z11.b, z12.b\n" - ".inst 0x052a2f04 // tbx z4.b, z24.b, z10.b\n" - "sub z10.b, z10.b, z12.b\n" - ".inst 0x05282f03 // tbx z3.b, z24.b, z8.b\n" - "sub z8.b, z8.b, z12.b\n" - ".inst 0x05272f02 // tbx z2.b, z24.b, z7.b\n" - "sub z7.b, z7.b, z12.b\n" - ".inst 0x05262f01 // tbx z1.b, z24.b, z6.b\n" - "sub z6.b, z6.b, z12.b\n" - ".inst 0x05252f00 // tbx z0.b, z24.b, z5.b\n" - "sub z5.b, z5.b, z12.b\n" - ".inst 0x052b2f29 // tbx z9.b, z25.b, z11.b\n" - "sub z11.b, z11.b, z12.b\n" - ".inst 0x052a2f24 // tbx z4.b, z25.b, z10.b\n" - "sub z10.b, z10.b, z12.b\n" - ".inst 0x05282f23 // tbx z3.b, z25.b, z8.b\n" - "sub z8.b, z8.b, z12.b\n" - ".inst 0x05272f22 // tbx z2.b, z25.b, z7.b\n" - "sub z7.b, z7.b, z12.b\n" - ".inst 0x05262f21 // tbx z1.b, z25.b, z6.b\n" - "sub z6.b, z6.b, z12.b\n" - ".inst 0x05252f20 // tbx z0.b, z25.b, z5.b\n" - "sub z5.b, z5.b, z12.b\n" - ".inst 0x052b2f49 // tbx z9.b, z26.b, z11.b\n" - "sub z11.b, z11.b, z12.b\n" - ".inst 0x052a2f44 // tbx z4.b, z26.b, z10.b\n" - "sub z10.b, z10.b, z12.b\n" - ".inst 0x05282f43 // tbx z3.b, z26.b, z8.b\n" - "sub z8.b, z8.b, z12.b\n" - ".inst 0x05272f42 // tbx z2.b, z26.b, z7.b\n" - "sub z7.b, z7.b, z12.b\n" - ".inst 0x05262f41 // tbx z1.b, z26.b, z6.b\n" - "sub z6.b, z6.b, z12.b\n" - ".inst 0x05252f40 // tbx z0.b, z26.b, z5.b\n" - "sub z5.b, z5.b, z12.b\n" - ".inst 0x052b2f69 // tbx z9.b, z27.b, z11.b\n" - "sub z11.b, z11.b, z12.b\n" - ".inst 0x052a2f64 // tbx z4.b, z27.b, z10.b\n" - "sub z10.b, z10.b, z12.b\n" - ".inst 0x05282f63 // tbx z3.b, z27.b, z8.b\n" - "sub z8.b, z8.b, z12.b\n" - ".inst 0x05272f62 // tbx z2.b, z27.b, z7.b\n" - "sub z7.b, z7.b, z12.b\n" - ".inst 0x05262f61 // tbx z1.b, z27.b, z6.b\n" - "sub z6.b, z6.b, z12.b\n" - ".inst 0x05252f60 // tbx z0.b, z27.b, z5.b\n" - "sub z5.b, z5.b, z12.b\n" - ".inst 0x052b2f89 // tbx z9.b, z28.b, z11.b\n" - "sub z11.b, z11.b, z12.b\n" - ".inst 0x052a2f84 // tbx z4.b, z28.b, z10.b\n" - "sub z10.b, z10.b, z12.b\n" - ".inst 0x05282f83 // tbx z3.b, z28.b, z8.b\n" - "sub z8.b, z8.b, z12.b\n" - ".inst 0x05272f82 // tbx z2.b, z28.b, z7.b\n" - "sub z7.b, z7.b, z12.b\n" - ".inst 0x05262f81 // tbx z1.b, z28.b, z6.b\n" - "sub z6.b, z6.b, z12.b\n" - ".inst 0x05252f80 // tbx z0.b, z28.b, z5.b\n" - "sub z5.b, z5.b, z12.b\n" - ".inst 0x052b2fa9 // tbx z9.b, z29.b, z11.b\n" - "sub z11.b, z11.b, z12.b\n" - ".inst 0x052a2fa4 // tbx z4.b, z29.b, z10.b\n" - "sub z10.b, z10.b, z12.b\n" - ".inst 0x05282fa3 // tbx z3.b, z29.b, z8.b\n" - "sub z8.b, z8.b, z12.b\n" - ".inst 0x05272fa2 // tbx z2.b, z29.b, z7.b\n" - "sub z7.b, z7.b, z12.b\n" - ".inst 0x05262fa1 // tbx z1.b, z29.b, z6.b\n" - "sub z6.b, z6.b, z12.b\n" - ".inst 0x05252fa0 // tbx z0.b, z29.b, z5.b\n" - "sub z5.b, z5.b, z12.b\n" - "addvl x21, x21, #-6\n" - ".inst 0x052b2fc9 // tbx z9.b, z30.b, z11.b\n" - "sub z11.b, z11.b, z12.b\n" - ".inst 0x052a2fc4 // tbx z4.b, z30.b, z10.b\n" - "sub z10.b, z10.b, z12.b\n" - ".inst 0x05282fc3 // tbx z3.b, z30.b, z8.b\n" - "sub z8.b, z8.b, z12.b\n" - ".inst 0x05272fc2 // tbx z2.b, z30.b, z7.b\n" - "sub z7.b, z7.b, z12.b\n" - ".inst 0x05262fc1 // tbx z1.b, z30.b, z6.b\n" - "sub z6.b, z6.b, z12.b\n" - ".inst 0x05252fc0 // tbx z0.b, z30.b, z5.b\n" - "sub z5.b, z5.b, z12.b\n" - "cmp x21, XZR\n" - ".inst 0x052b2fe9 // tbx z9.b, z31.b, z11.b\n" - ".inst 0x052a2fe4 // tbx z4.b, z31.b, z10.b\n" - ".inst 0x05282fe3 // tbx z3.b, z31.b, z8.b\n" - "st1b { z9.b }, p5, [x22]\n" - ".inst 0x05272fe2 // tbx z2.b, z31.b, z7.b\n" - ".inst 0x05262fe1 // tbx z1.b, z31.b, z6.b\n" - "st1b { z4.b }, p4, [x22, #1, MUL VL]\n" - ".inst 0x05252fe0 // tbx z0.b, z31.b, z5.b\n" - "st1b { z3.b }, p3, [x22, #2, MUL VL]\n" - "addvl x23, x23, #6\n" - "st1b { z2.b }, p2, [x22, #3, MUL VL]\n" - "st1b { z1.b }, p1, [x22, #4, MUL VL]\n" - "st1b { z0.b }, p0, [x22, #5, MUL VL]\n" - "addvl x22, x22, #6\n" - "bgt 3b\n" - "b 17f\n" - "5:" // 256 bits - "mov z12.b, #0x20\n" - "mov x21, %x[string_length]\n" - "ptrue p5.b\n" - "ptrue p4.b\n" - "ptrue p3.b\n" - "ptrue p2.b\n" - "ptrue p1.b\n" - "ptrue p0.b\n" - "6:" // 8 rounds: width loop - "addvl x20, x21, #-6\n" - "cmp x20, XZR\n" - "bge 7f\n" - "mov x20, #0x0\n" - "addvl x20, x20, #1\n" - "whilelt p5.b, XZR, x21\n" - "whilelt p4.b, x20, x21\n" - "addvl x20, x20, #1\n" - "whilelt p3.b, x20, x21\n" - "addvl x20, x20, #1\n" - "whilelt p2.b, x20, x21\n" - "addvl x20, x20, #1\n" - "whilelt p1.b, x20, x21\n" - "addvl x20, x20, #1\n" - "whilelt p0.b, x20, x21\n" - "7:" // 8 rounds: predicate OK - "ld1b { z11.b }, p5/Z, [x23]\n" - "ld1b { z10.b }, p4/Z, [x23, #1, MUL VL]\n" - "tbl z9.b, { z16.b }, z11.b\n" - "ld1b { z8.b }, p3/Z, [x23, #2, MUL VL]\n" - "ld1b { z7.b }, p2/Z, [x23, #3, MUL VL]\n" - "sub z11.b, z11.b, z12.b\n" - "ld1b { z6.b }, p1/Z, [x23, #4, MUL VL]\n" - "ld1b { z5.b }, p0/Z, [x23, #5, MUL VL]\n" - "tbl z4.b, { z16.b }, z10.b\n" - "sub z10.b, z10.b, z12.b\n" - "tbl z3.b, { z16.b }, z8.b\n" - "sub z8.b, z8.b, z12.b\n" - "tbl z2.b, { z16.b }, z7.b\n" - "sub z7.b, z7.b, z12.b\n" - "tbl z1.b, { z16.b }, z6.b\n" - "sub z6.b, z6.b, z12.b\n" - "tbl z0.b, { z16.b }, z5.b\n" - "sub z5.b, z5.b, z12.b\n" - ".inst 0x052b2e29 // tbx z9.b, z17.b, z11.b\n" - "sub z11.b, z11.b, z12.b\n" - ".inst 0x052a2e24 // tbx z4.b, z17.b, z10.b\n" - "sub z10.b, z10.b, z12.b\n" - ".inst 0x05282e23 // tbx z3.b, z17.b, z8.b\n" - "sub z8.b, z8.b, z12.b\n" - ".inst 0x05272e22 // tbx z2.b, z17.b, z7.b\n" - "sub z7.b, z7.b, z12.b\n" - ".inst 0x05262e21 // tbx z1.b, z17.b, z6.b\n" - "sub z6.b, z6.b, z12.b\n" - ".inst 0x05252e20 // tbx z0.b, z17.b, z5.b\n" - "sub z5.b, z5.b, z12.b\n" - ".inst 0x052b2e49 // tbx z9.b, z18.b, z11.b\n" - "sub z11.b, z11.b, z12.b\n" - ".inst 0x052a2e44 // tbx z4.b, z18.b, z10.b\n" - "sub z10.b, z10.b, z12.b\n" - ".inst 0x05282e43 // tbx z3.b, z18.b, z8.b\n" - "sub z8.b, z8.b, z12.b\n" - ".inst 0x05272e42 // tbx z2.b, z18.b, z7.b\n" - "sub z7.b, z7.b, z12.b\n" - ".inst 0x05262e41 // tbx z1.b, z18.b, z6.b\n" - "sub z6.b, z6.b, z12.b\n" - ".inst 0x05252e40 // tbx z0.b, z18.b, z5.b\n" - "sub z5.b, z5.b, z12.b\n" - ".inst 0x052b2e69 // tbx z9.b, z19.b, z11.b\n" - "sub z11.b, z11.b, z12.b\n" - ".inst 0x052a2e64 // tbx z4.b, z19.b, z10.b\n" - "sub z10.b, z10.b, z12.b\n" - ".inst 0x05282e63 // tbx z3.b, z19.b, z8.b\n" - "sub z8.b, z8.b, z12.b\n" - ".inst 0x05272e62 // tbx z2.b, z19.b, z7.b\n" - "sub z7.b, z7.b, z12.b\n" - ".inst 0x05262e61 // tbx z1.b, z19.b, z6.b\n" - "sub z6.b, z6.b, z12.b\n" - ".inst 0x05252e60 // tbx z0.b, z19.b, z5.b\n" - "sub z5.b, z5.b, z12.b\n" - ".inst 0x052b2e89 // tbx z9.b, z20.b, z11.b\n" - "sub z11.b, z11.b, z12.b\n" - ".inst 0x052a2e84 // tbx z4.b, z20.b, z10.b\n" - "sub z10.b, z10.b, z12.b\n" - ".inst 0x05282e83 // tbx z3.b, z20.b, z8.b\n" - "sub z8.b, z8.b, z12.b\n" - ".inst 0x05272e82 // tbx z2.b, z20.b, z7.b\n" - "sub z7.b, z7.b, z12.b\n" - ".inst 0x05262e81 // tbx z1.b, z20.b, z6.b\n" - "sub z6.b, z6.b, z12.b\n" - ".inst 0x05252e80 // tbx z0.b, z20.b, z5.b\n" - "sub z5.b, z5.b, z12.b\n" - ".inst 0x052b2ea9 // tbx z9.b, z21.b, z11.b\n" - "sub z11.b, z11.b, z12.b\n" - ".inst 0x052a2ea4 // tbx z4.b, z21.b, z10.b\n" - "sub z10.b, z10.b, z12.b\n" - ".inst 0x05282ea3 // tbx z3.b, z21.b, z8.b\n" - "sub z8.b, z8.b, z12.b\n" - ".inst 0x05272ea2 // tbx z2.b, z21.b, z7.b\n" - "sub z7.b, z7.b, z12.b\n" - ".inst 0x05262ea1 // tbx z1.b, z21.b, z6.b\n" - "sub z6.b, z6.b, z12.b\n" - ".inst 0x05252ea0 // tbx z0.b, z21.b, z5.b\n" - "sub z5.b, z5.b, z12.b\n" - "addvl x21, x21, #-6\n" - ".inst 0x052b2ec9 // tbx z9.b, z22.b, z11.b\n" - "sub z11.b, z11.b, z12.b\n" - ".inst 0x052a2ec4 // tbx z4.b, z22.b, z10.b\n" - "sub z10.b, z10.b, z12.b\n" - ".inst 0x05282ec3 // tbx z3.b, z22.b, z8.b\n" - "sub z8.b, z8.b, z12.b\n" - ".inst 0x05272ec2 // tbx z2.b, z22.b, z7.b\n" - "sub z7.b, z7.b, z12.b\n" - ".inst 0x05262ec1 // tbx z1.b, z22.b, z6.b\n" - "sub z6.b, z6.b, z12.b\n" - ".inst 0x05252ec0 // tbx z0.b, z22.b, z5.b\n" - "sub z5.b, z5.b, z12.b\n" - "cmp x21, XZR\n" - ".inst 0x052b2ee9 // tbx z9.b, z23.b, z11.b\n" - ".inst 0x052a2ee4 // tbx z4.b, z23.b, z10.b\n" - ".inst 0x05282ee3 // tbx z3.b, z23.b, z8.b\n" - "st1b { z9.b }, p5, [x22]\n" - ".inst 0x05272ee2 // tbx z2.b, z23.b, z7.b\n" - ".inst 0x05262ee1 // tbx z1.b, z23.b, z6.b\n" - "st1b { z4.b }, p4, [x22, #1, MUL VL]\n" - ".inst 0x05252ee0 // tbx z0.b, z23.b, z5.b\n" - "st1b { z3.b }, p3, [x22, #2, MUL VL]\n" - "addvl x23, x23, #6\n" - "st1b { z2.b }, p2, [x22, #3, MUL VL]\n" - "st1b { z1.b }, p1, [x22, #4, MUL VL]\n" - "st1b { z0.b }, p0, [x22, #5, MUL VL]\n" - "addvl x22, x22, #6\n" - "bgt 6b\n" - "b 17f\n" - "8:" // 512 bits - "mov z12.b, #0x40\n" - "mov x21, %x[string_length]\n" - "ptrue p5.b\n" - "ptrue p4.b\n" - "ptrue p3.b\n" - "ptrue p2.b\n" - "ptrue p1.b\n" - "ptrue p0.b\n" - "9:" // 4 rounds: width loop - "addvl x20, x21, #-6\n" - "cmp x20, XZR\n" - "bge 10f\n" - "mov x20, #0x0\n" - "addvl x20, x20, #1\n" - "whilelt p5.b, XZR, x21\n" - "whilelt p4.b, x20, x21\n" - "addvl x20, x20, #1\n" - "whilelt p3.b, x20, x21\n" - "addvl x20, x20, #1\n" - "whilelt p2.b, x20, x21\n" - "addvl x20, x20, #1\n" - "whilelt p1.b, x20, x21\n" - "addvl x20, x20, #1\n" - "whilelt p0.b, x20, x21\n" - "10:" // 4 rounds: predicate OK - "ld1b { z11.b }, p5/Z, [x23]\n" - "ld1b { z10.b }, p4/Z, [x23, #1, MUL VL]\n" - "tbl z9.b, { z16.b }, z11.b\n" - "ld1b { z8.b }, p3/Z, [x23, #2, MUL VL]\n" - "ld1b { z7.b }, p2/Z, [x23, #3, MUL VL]\n" - "sub z11.b, z11.b, z12.b\n" - "ld1b { z6.b }, p1/Z, [x23, #4, MUL VL]\n" - "ld1b { z5.b }, p0/Z, [x23, #5, MUL VL]\n" - "tbl z4.b, { z16.b }, z10.b\n" - "sub z10.b, z10.b, z12.b\n" - "tbl z3.b, { z16.b }, z8.b\n" - "sub z8.b, z8.b, z12.b\n" - "tbl z2.b, { z16.b }, z7.b\n" - "sub z7.b, z7.b, z12.b\n" - "tbl z1.b, { z16.b }, z6.b\n" - "sub z6.b, z6.b, z12.b\n" - "tbl z0.b, { z16.b }, z5.b\n" - "sub z5.b, z5.b, z12.b\n" - ".inst 0x052b2e29 // tbx z9.b, z17.b, z11.b\n" - "sub z11.b, z11.b, z12.b\n" - ".inst 0x052a2e24 // tbx z4.b, z17.b, z10.b\n" - "sub z10.b, z10.b, z12.b\n" - ".inst 0x05282e23 // tbx z3.b, z17.b, z8.b\n" - "sub z8.b, z8.b, z12.b\n" - ".inst 0x05272e22 // tbx z2.b, z17.b, z7.b\n" - "sub z7.b, z7.b, z12.b\n" - ".inst 0x05262e21 // tbx z1.b, z17.b, z6.b\n" - "sub z6.b, z6.b, z12.b\n" - ".inst 0x05252e20 // tbx z0.b, z17.b, z5.b\n" - "sub z5.b, z5.b, z12.b\n" - "addvl x21, x21, #-6\n" - ".inst 0x052b2e49 // tbx z9.b, z18.b, z11.b\n" - "sub z11.b, z11.b, z12.b\n" - ".inst 0x052a2e44 // tbx z4.b, z18.b, z10.b\n" - "sub z10.b, z10.b, z12.b\n" - ".inst 0x05282e43 // tbx z3.b, z18.b, z8.b\n" - "sub z8.b, z8.b, z12.b\n" - ".inst 0x05272e42 // tbx z2.b, z18.b, z7.b\n" - "sub z7.b, z7.b, z12.b\n" - ".inst 0x05262e41 // tbx z1.b, z18.b, z6.b\n" - "sub z6.b, z6.b, z12.b\n" - ".inst 0x05252e40 // tbx z0.b, z18.b, z5.b\n" - "sub z5.b, z5.b, z12.b\n" - "cmp x21, XZR\n" - ".inst 0x052b2e69 // tbx z9.b, z19.b, z11.b\n" - ".inst 0x052a2e64 // tbx z4.b, z19.b, z10.b\n" - ".inst 0x05282e63 // tbx z3.b, z19.b, z8.b\n" - "st1b { z9.b }, p5, [x22]\n" - ".inst 0x05272e62 // tbx z2.b, z19.b, z7.b\n" - ".inst 0x05262e61 // tbx z1.b, z19.b, z6.b\n" - "st1b { z4.b }, p4, [x22, #1, MUL VL]\n" - ".inst 0x05252e60 // tbx z0.b, z19.b, z5.b\n" - "st1b { z3.b }, p3, [x22, #2, MUL VL]\n" - "addvl x23, x23, #6\n" - "st1b { z2.b }, p2, [x22, #3, MUL VL]\n" - "st1b { z1.b }, p1, [x22, #4, MUL VL]\n" - "st1b { z0.b }, p0, [x22, #5, MUL VL]\n" - "addvl x22, x22, #6\n" - "bgt 9b\n" - "b 17f\n" - "11:" // 1024 bits - "mov z12.b, #0x80\n" - "mov x21, %x[string_length]\n" - "ptrue p5.b\n" - "ptrue p4.b\n" - "ptrue p3.b\n" - "ptrue p2.b\n" - "ptrue p1.b\n" - "ptrue p0.b\n" - "12:" // 2 rounds: width loop - "addvl x20, x21, #-6\n" - "cmp x20, XZR\n" - "bge 13f\n" - "mov x20, #0x0\n" - "addvl x20, x20, #1\n" - "whilelt p5.b, XZR, x21\n" - "whilelt p4.b, x20, x21\n" - "addvl x20, x20, #1\n" - "whilelt p3.b, x20, x21\n" - "addvl x20, x20, #1\n" - "whilelt p2.b, x20, x21\n" - "addvl x20, x20, #1\n" - "whilelt p1.b, x20, x21\n" - "addvl x20, x20, #1\n" - "whilelt p0.b, x20, x21\n" - "13:" // 2 rounds: predicate OK - "ld1b { z11.b }, p5/Z, [x23]\n" - "ld1b { z10.b }, p4/Z, [x23, #1, MUL VL]\n" - "addvl x21, x21, #-6\n" - "ld1b { z8.b }, p3/Z, [x23, #2, MUL VL]\n" - "ld1b { z7.b }, p2/Z, [x23, #3, MUL VL]\n" - "tbl z9.b, { z16.b }, z11.b\n" - "ld1b { z6.b }, p1/Z, [x23, #4, MUL VL]\n" - "ld1b { z5.b }, p0/Z, [x23, #5, MUL VL]\n" - "sub z11.b, z11.b, z12.b\n" - "tbl z4.b, { z16.b }, z10.b\n" - "sub z10.b, z10.b, z12.b\n" - "tbl z3.b, { z16.b }, z8.b\n" - "sub z8.b, z8.b, z12.b\n" - "tbl z2.b, { z16.b }, z7.b\n" - "sub z7.b, z7.b, z12.b\n" - "tbl z1.b, { z16.b }, z6.b\n" - "sub z6.b, z6.b, z12.b\n" - "tbl z0.b, { z16.b }, z5.b\n" - "sub z5.b, z5.b, z12.b\n" - "cmp x21, XZR\n" - ".inst 0x052b2e29 // tbx z9.b, z17.b, z11.b\n" - ".inst 0x052a2e24 // tbx z4.b, z17.b, z10.b\n" - ".inst 0x05282e23 // tbx z3.b, z17.b, z8.b\n" - "st1b { z9.b }, p5, [x22]\n" - ".inst 0x05272e22 // tbx z2.b, z17.b, z7.b\n" - ".inst 0x05262e21 // tbx z1.b, z17.b, z6.b\n" - "st1b { z4.b }, p4, [x22, #1, MUL VL]\n" - ".inst 0x05252e20 // tbx z0.b, z17.b, z5.b\n" - "st1b { z3.b }, p3, [x22, #2, MUL VL]\n" - "addvl x23, x23, #6\n" - "st1b { z2.b }, p2, [x22, #3, MUL VL]\n" - "st1b { z1.b }, p1, [x22, #4, MUL VL]\n" - "st1b { z0.b }, p0, [x22, #5, MUL VL]\n" - "addvl x22, x22, #6\n" - "bgt 12b\n" - "b 17f\n" - "14:" // 2048 bits - "mov x21, %x[string_length]\n" - "ptrue p5.b\n" - "ptrue p4.b\n" - "ptrue p3.b\n" - "ptrue p2.b\n" - "ptrue p1.b\n" - "ptrue p0.b\n" - "15:" // 1 rounds: width loop - "addvl x20, x21, #-6\n" - "cmp x20, XZR\n" - "bge 16f\n" - "mov x20, #0x0\n" - "addvl x20, x20, #1\n" - "whilelt p5.b, XZR, x21\n" - "whilelt p4.b, x20, x21\n" - "addvl x20, x20, #1\n" - "whilelt p3.b, x20, x21\n" - "addvl x20, x20, #1\n" - "whilelt p2.b, x20, x21\n" - "addvl x20, x20, #1\n" - "whilelt p1.b, x20, x21\n" - "addvl x20, x20, #1\n" - "whilelt p0.b, x20, x21\n" - "16:" // 1 rounds: predicate OK - "addvl x21, x21, #-6\n" - "ld1b { z11.b }, p5/Z, [x23]\n" - "ld1b { z10.b }, p4/Z, [x23, #1, MUL VL]\n" - "ld1b { z8.b }, p3/Z, [x23, #2, MUL VL]\n" - "ld1b { z7.b }, p2/Z, [x23, #3, MUL VL]\n" - "cmp x21, XZR\n" - "ld1b { z6.b }, p1/Z, [x23, #4, MUL VL]\n" - "ld1b { z5.b }, p0/Z, [x23, #5, MUL VL]\n" - "tbl z9.b, { z16.b }, z11.b\n" - "tbl z4.b, { z16.b }, z10.b\n" - "tbl z3.b, { z16.b }, z8.b\n" - "st1b { z9.b }, p5, [x22]\n" - "tbl z2.b, { z16.b }, z7.b\n" - "tbl z1.b, { z16.b }, z6.b\n" - "st1b { z4.b }, p4, [x22, #1, MUL VL]\n" - "tbl z0.b, { z16.b }, z5.b\n" - "st1b { z3.b }, p3, [x22, #2, MUL VL]\n" - "addvl x23, x23, #6\n" - "st1b { z2.b }, p2, [x22, #3, MUL VL]\n" - "st1b { z1.b }, p1, [x22, #4, MUL VL]\n" - "st1b { z0.b }, p0, [x22, #5, MUL VL]\n" - "addvl x22, x22, #6\n" - "bgt 15b\n" - "17:" // SVE body done - "add x24, x24, #0x1\n" - "cmp x24, %x[num_strings]\n" - "bne 2b\n" - : [table] "+&r"(table) - : [input] "r"(input), [num_strings] "r"(num_strings), [output] "r"(output), [string_length] "r"(string_length) - : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "x20", "x21", "x22", "x23", "x24", "x25", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31"); -} - -} // namespace cpu -} // namespace arm_compute - -#endif // ARM_COMPUTE_ENABLE_SVE -#endif // __aarch64__ diff --git a/src/cpu/kernels/lut/generic/sve2/u8.cpp b/src/cpu/kernels/lut/generic/sve2/u8.cpp new file mode 100644 index 0000000000..b80d75326e --- /dev/null +++ b/src/cpu/kernels/lut/generic/sve2/u8.cpp @@ -0,0 +1,646 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "src/cpu/kernels/lut/list.h" + +#ifdef __aarch64__ +#ifdef ARM_COMPUTE_ENABLE_SVE + +namespace arm_compute +{ +namespace cpu +{ +void lut_u8_sve2( + const uint8_t *table, + size_t num_strings, + size_t string_length, + const uint8_t *const *input, + uint8_t *const *output) +{ + __asm__ __volatile__( + "ptrue p0.b\n" + "cntd x25\n" + "addvl %x[table], %x[table], #8\n" + "ld1b { z16.b }, p0/Z, [%x[table], #-8, MUL VL]\n" + "tbnz x25, #5, 1f\n" + "ld1b { z17.b }, p0/Z, [%x[table], #-7, MUL VL]\n" + "tbnz x25, #4, 1f\n" + "ld1b { z18.b }, p0/Z, [%x[table], #-6, MUL VL]\n" + "ld1b { z19.b }, p0/Z, [%x[table], #-5, MUL VL]\n" + "tbnz x25, #3, 1f\n" + "ld1b { z20.b }, p0/Z, [%x[table], #-4, MUL VL]\n" + "ld1b { z21.b }, p0/Z, [%x[table], #-3, MUL VL]\n" + "ld1b { z22.b }, p0/Z, [%x[table], #-2, MUL VL]\n" + "ld1b { z23.b }, p0/Z, [%x[table], #-1, MUL VL]\n" + "tbnz x25, #2, 1f\n" + "ld1b { z24.b }, p0/Z, [%x[table]]\n" + "ld1b { z25.b }, p0/Z, [%x[table], #1, MUL VL]\n" + "ld1b { z26.b }, p0/Z, [%x[table], #2, MUL VL]\n" + "ld1b { z27.b }, p0/Z, [%x[table], #3, MUL VL]\n" + "ld1b { z28.b }, p0/Z, [%x[table], #4, MUL VL]\n" + "ld1b { z29.b }, p0/Z, [%x[table], #5, MUL VL]\n" + "ld1b { z30.b }, p0/Z, [%x[table], #6, MUL VL]\n" + "ld1b { z31.b }, p0/Z, [%x[table], #7, MUL VL]\n" + "1:" // Table load done + "mov x24, #0x0\n" + "2:" // string loop + "ldr x23, [%x[input], x24, LSL #0x3]\n" + "ldr x22, [%x[output], x24, LSL #0x3]\n" + "tbnz x25, #5, 14f\n" + "tbnz x25, #4, 11f\n" + "tbnz x25, #3, 8f\n" + "tbnz x25, #2, 5f\n" + "mov z12.b, #0x10\n" + "mov x21, %x[string_length]\n" + "ptrue p5.b\n" + "ptrue p4.b\n" + "ptrue p3.b\n" + "ptrue p2.b\n" + "ptrue p1.b\n" + "ptrue p0.b\n" + "3:" // 16 rounds: width loop + "addvl x20, x21, #-6\n" + "cmp x20, XZR\n" + "bge 4f\n" + "mov x20, #0x0\n" + "addvl x20, x20, #1\n" + "whilelt p5.b, XZR, x21\n" + "whilelt p4.b, x20, x21\n" + "addvl x20, x20, #1\n" + "whilelt p3.b, x20, x21\n" + "addvl x20, x20, #1\n" + "whilelt p2.b, x20, x21\n" + "addvl x20, x20, #1\n" + "whilelt p1.b, x20, x21\n" + "addvl x20, x20, #1\n" + "whilelt p0.b, x20, x21\n" + "4:" // 16 rounds: predicate OK + "ld1b { z11.b }, p5/Z, [x23]\n" + "ld1b { z10.b }, p4/Z, [x23, #1, MUL VL]\n" + "tbl z9.b, { z16.b }, z11.b\n" + "ld1b { z8.b }, p3/Z, [x23, #2, MUL VL]\n" + "ld1b { z7.b }, p2/Z, [x23, #3, MUL VL]\n" + "sub z11.b, z11.b, z12.b\n" + "ld1b { z6.b }, p1/Z, [x23, #4, MUL VL]\n" + "ld1b { z5.b }, p0/Z, [x23, #5, MUL VL]\n" + "tbl z4.b, { z16.b }, z10.b\n" + "sub z10.b, z10.b, z12.b\n" + "tbl z3.b, { z16.b }, z8.b\n" + "sub z8.b, z8.b, z12.b\n" + "tbl z2.b, { z16.b }, z7.b\n" + "sub z7.b, z7.b, z12.b\n" + "tbl z1.b, { z16.b }, z6.b\n" + "sub z6.b, z6.b, z12.b\n" + "tbl z0.b, { z16.b }, z5.b\n" + "sub z5.b, z5.b, z12.b\n" + ".inst 0x052b2e29 // tbx z9.b, z17.b, z11.b\n" + "sub z11.b, z11.b, z12.b\n" + ".inst 0x052a2e24 // tbx z4.b, z17.b, z10.b\n" + "sub z10.b, z10.b, z12.b\n" + ".inst 0x05282e23 // tbx z3.b, z17.b, z8.b\n" + "sub z8.b, z8.b, z12.b\n" + ".inst 0x05272e22 // tbx z2.b, z17.b, z7.b\n" + "sub z7.b, z7.b, z12.b\n" + ".inst 0x05262e21 // tbx z1.b, z17.b, z6.b\n" + "sub z6.b, z6.b, z12.b\n" + ".inst 0x05252e20 // tbx z0.b, z17.b, z5.b\n" + "sub z5.b, z5.b, z12.b\n" + ".inst 0x052b2e49 // tbx z9.b, z18.b, z11.b\n" + "sub z11.b, z11.b, z12.b\n" + ".inst 0x052a2e44 // tbx z4.b, z18.b, z10.b\n" + "sub z10.b, z10.b, z12.b\n" + ".inst 0x05282e43 // tbx z3.b, z18.b, z8.b\n" + "sub z8.b, z8.b, z12.b\n" + ".inst 0x05272e42 // tbx z2.b, z18.b, z7.b\n" + "sub z7.b, z7.b, z12.b\n" + ".inst 0x05262e41 // tbx z1.b, z18.b, z6.b\n" + "sub z6.b, z6.b, z12.b\n" + ".inst 0x05252e40 // tbx z0.b, z18.b, z5.b\n" + "sub z5.b, z5.b, z12.b\n" + ".inst 0x052b2e69 // tbx z9.b, z19.b, z11.b\n" + "sub z11.b, z11.b, z12.b\n" + ".inst 0x052a2e64 // tbx z4.b, z19.b, z10.b\n" + "sub z10.b, z10.b, z12.b\n" + ".inst 0x05282e63 // tbx z3.b, z19.b, z8.b\n" + "sub z8.b, z8.b, z12.b\n" + ".inst 0x05272e62 // tbx z2.b, z19.b, z7.b\n" + "sub z7.b, z7.b, z12.b\n" + ".inst 0x05262e61 // tbx z1.b, z19.b, z6.b\n" + "sub z6.b, z6.b, z12.b\n" + ".inst 0x05252e60 // tbx z0.b, z19.b, z5.b\n" + "sub z5.b, z5.b, z12.b\n" + ".inst 0x052b2e89 // tbx z9.b, z20.b, z11.b\n" + "sub z11.b, z11.b, z12.b\n" + ".inst 0x052a2e84 // tbx z4.b, z20.b, z10.b\n" + "sub z10.b, z10.b, z12.b\n" + ".inst 0x05282e83 // tbx z3.b, z20.b, z8.b\n" + "sub z8.b, z8.b, z12.b\n" + ".inst 0x05272e82 // tbx z2.b, z20.b, z7.b\n" + "sub z7.b, z7.b, z12.b\n" + ".inst 0x05262e81 // tbx z1.b, z20.b, z6.b\n" + "sub z6.b, z6.b, z12.b\n" + ".inst 0x05252e80 // tbx z0.b, z20.b, z5.b\n" + "sub z5.b, z5.b, z12.b\n" + ".inst 0x052b2ea9 // tbx z9.b, z21.b, z11.b\n" + "sub z11.b, z11.b, z12.b\n" + ".inst 0x052a2ea4 // tbx z4.b, z21.b, z10.b\n" + "sub z10.b, z10.b, z12.b\n" + ".inst 0x05282ea3 // tbx z3.b, z21.b, z8.b\n" + "sub z8.b, z8.b, z12.b\n" + ".inst 0x05272ea2 // tbx z2.b, z21.b, z7.b\n" + "sub z7.b, z7.b, z12.b\n" + ".inst 0x05262ea1 // tbx z1.b, z21.b, z6.b\n" + "sub z6.b, z6.b, z12.b\n" + ".inst 0x05252ea0 // tbx z0.b, z21.b, z5.b\n" + "sub z5.b, z5.b, z12.b\n" + ".inst 0x052b2ec9 // tbx z9.b, z22.b, z11.b\n" + "sub z11.b, z11.b, z12.b\n" + ".inst 0x052a2ec4 // tbx z4.b, z22.b, z10.b\n" + "sub z10.b, z10.b, z12.b\n" + ".inst 0x05282ec3 // tbx z3.b, z22.b, z8.b\n" + "sub z8.b, z8.b, z12.b\n" + ".inst 0x05272ec2 // tbx z2.b, z22.b, z7.b\n" + "sub z7.b, z7.b, z12.b\n" + ".inst 0x05262ec1 // tbx z1.b, z22.b, z6.b\n" + "sub z6.b, z6.b, z12.b\n" + ".inst 0x05252ec0 // tbx z0.b, z22.b, z5.b\n" + "sub z5.b, z5.b, z12.b\n" + ".inst 0x052b2ee9 // tbx z9.b, z23.b, z11.b\n" + "sub z11.b, z11.b, z12.b\n" + ".inst 0x052a2ee4 // tbx z4.b, z23.b, z10.b\n" + "sub z10.b, z10.b, z12.b\n" + ".inst 0x05282ee3 // tbx z3.b, z23.b, z8.b\n" + "sub z8.b, z8.b, z12.b\n" + ".inst 0x05272ee2 // tbx z2.b, z23.b, z7.b\n" + "sub z7.b, z7.b, z12.b\n" + ".inst 0x05262ee1 // tbx z1.b, z23.b, z6.b\n" + "sub z6.b, z6.b, z12.b\n" + ".inst 0x05252ee0 // tbx z0.b, z23.b, z5.b\n" + "sub z5.b, z5.b, z12.b\n" + ".inst 0x052b2f09 // tbx z9.b, z24.b, z11.b\n" + "sub z11.b, z11.b, z12.b\n" + ".inst 0x052a2f04 // tbx z4.b, z24.b, z10.b\n" + "sub z10.b, z10.b, z12.b\n" + ".inst 0x05282f03 // tbx z3.b, z24.b, z8.b\n" + "sub z8.b, z8.b, z12.b\n" + ".inst 0x05272f02 // tbx z2.b, z24.b, z7.b\n" + "sub z7.b, z7.b, z12.b\n" + ".inst 0x05262f01 // tbx z1.b, z24.b, z6.b\n" + "sub z6.b, z6.b, z12.b\n" + ".inst 0x05252f00 // tbx z0.b, z24.b, z5.b\n" + "sub z5.b, z5.b, z12.b\n" + ".inst 0x052b2f29 // tbx z9.b, z25.b, z11.b\n" + "sub z11.b, z11.b, z12.b\n" + ".inst 0x052a2f24 // tbx z4.b, z25.b, z10.b\n" + "sub z10.b, z10.b, z12.b\n" + ".inst 0x05282f23 // tbx z3.b, z25.b, z8.b\n" + "sub z8.b, z8.b, z12.b\n" + ".inst 0x05272f22 // tbx z2.b, z25.b, z7.b\n" + "sub z7.b, z7.b, z12.b\n" + ".inst 0x05262f21 // tbx z1.b, z25.b, z6.b\n" + "sub z6.b, z6.b, z12.b\n" + ".inst 0x05252f20 // tbx z0.b, z25.b, z5.b\n" + "sub z5.b, z5.b, z12.b\n" + ".inst 0x052b2f49 // tbx z9.b, z26.b, z11.b\n" + "sub z11.b, z11.b, z12.b\n" + ".inst 0x052a2f44 // tbx z4.b, z26.b, z10.b\n" + "sub z10.b, z10.b, z12.b\n" + ".inst 0x05282f43 // tbx z3.b, z26.b, z8.b\n" + "sub z8.b, z8.b, z12.b\n" + ".inst 0x05272f42 // tbx z2.b, z26.b, z7.b\n" + "sub z7.b, z7.b, z12.b\n" + ".inst 0x05262f41 // tbx z1.b, z26.b, z6.b\n" + "sub z6.b, z6.b, z12.b\n" + ".inst 0x05252f40 // tbx z0.b, z26.b, z5.b\n" + "sub z5.b, z5.b, z12.b\n" + ".inst 0x052b2f69 // tbx z9.b, z27.b, z11.b\n" + "sub z11.b, z11.b, z12.b\n" + ".inst 0x052a2f64 // tbx z4.b, z27.b, z10.b\n" + "sub z10.b, z10.b, z12.b\n" + ".inst 0x05282f63 // tbx z3.b, z27.b, z8.b\n" + "sub z8.b, z8.b, z12.b\n" + ".inst 0x05272f62 // tbx z2.b, z27.b, z7.b\n" + "sub z7.b, z7.b, z12.b\n" + ".inst 0x05262f61 // tbx z1.b, z27.b, z6.b\n" + "sub z6.b, z6.b, z12.b\n" + ".inst 0x05252f60 // tbx z0.b, z27.b, z5.b\n" + "sub z5.b, z5.b, z12.b\n" + ".inst 0x052b2f89 // tbx z9.b, z28.b, z11.b\n" + "sub z11.b, z11.b, z12.b\n" + ".inst 0x052a2f84 // tbx z4.b, z28.b, z10.b\n" + "sub z10.b, z10.b, z12.b\n" + ".inst 0x05282f83 // tbx z3.b, z28.b, z8.b\n" + "sub z8.b, z8.b, z12.b\n" + ".inst 0x05272f82 // tbx z2.b, z28.b, z7.b\n" + "sub z7.b, z7.b, z12.b\n" + ".inst 0x05262f81 // tbx z1.b, z28.b, z6.b\n" + "sub z6.b, z6.b, z12.b\n" + ".inst 0x05252f80 // tbx z0.b, z28.b, z5.b\n" + "sub z5.b, z5.b, z12.b\n" + ".inst 0x052b2fa9 // tbx z9.b, z29.b, z11.b\n" + "sub z11.b, z11.b, z12.b\n" + ".inst 0x052a2fa4 // tbx z4.b, z29.b, z10.b\n" + "sub z10.b, z10.b, z12.b\n" + ".inst 0x05282fa3 // tbx z3.b, z29.b, z8.b\n" + "sub z8.b, z8.b, z12.b\n" + ".inst 0x05272fa2 // tbx z2.b, z29.b, z7.b\n" + "sub z7.b, z7.b, z12.b\n" + ".inst 0x05262fa1 // tbx z1.b, z29.b, z6.b\n" + "sub z6.b, z6.b, z12.b\n" + ".inst 0x05252fa0 // tbx z0.b, z29.b, z5.b\n" + "sub z5.b, z5.b, z12.b\n" + "addvl x21, x21, #-6\n" + ".inst 0x052b2fc9 // tbx z9.b, z30.b, z11.b\n" + "sub z11.b, z11.b, z12.b\n" + ".inst 0x052a2fc4 // tbx z4.b, z30.b, z10.b\n" + "sub z10.b, z10.b, z12.b\n" + ".inst 0x05282fc3 // tbx z3.b, z30.b, z8.b\n" + "sub z8.b, z8.b, z12.b\n" + ".inst 0x05272fc2 // tbx z2.b, z30.b, z7.b\n" + "sub z7.b, z7.b, z12.b\n" + ".inst 0x05262fc1 // tbx z1.b, z30.b, z6.b\n" + "sub z6.b, z6.b, z12.b\n" + ".inst 0x05252fc0 // tbx z0.b, z30.b, z5.b\n" + "sub z5.b, z5.b, z12.b\n" + "cmp x21, XZR\n" + ".inst 0x052b2fe9 // tbx z9.b, z31.b, z11.b\n" + ".inst 0x052a2fe4 // tbx z4.b, z31.b, z10.b\n" + ".inst 0x05282fe3 // tbx z3.b, z31.b, z8.b\n" + "st1b { z9.b }, p5, [x22]\n" + ".inst 0x05272fe2 // tbx z2.b, z31.b, z7.b\n" + ".inst 0x05262fe1 // tbx z1.b, z31.b, z6.b\n" + "st1b { z4.b }, p4, [x22, #1, MUL VL]\n" + ".inst 0x05252fe0 // tbx z0.b, z31.b, z5.b\n" + "st1b { z3.b }, p3, [x22, #2, MUL VL]\n" + "addvl x23, x23, #6\n" + "st1b { z2.b }, p2, [x22, #3, MUL VL]\n" + "st1b { z1.b }, p1, [x22, #4, MUL VL]\n" + "st1b { z0.b }, p0, [x22, #5, MUL VL]\n" + "addvl x22, x22, #6\n" + "bgt 3b\n" + "b 17f\n" + "5:" // 256 bits + "mov z12.b, #0x20\n" + "mov x21, %x[string_length]\n" + "ptrue p5.b\n" + "ptrue p4.b\n" + "ptrue p3.b\n" + "ptrue p2.b\n" + "ptrue p1.b\n" + "ptrue p0.b\n" + "6:" // 8 rounds: width loop + "addvl x20, x21, #-6\n" + "cmp x20, XZR\n" + "bge 7f\n" + "mov x20, #0x0\n" + "addvl x20, x20, #1\n" + "whilelt p5.b, XZR, x21\n" + "whilelt p4.b, x20, x21\n" + "addvl x20, x20, #1\n" + "whilelt p3.b, x20, x21\n" + "addvl x20, x20, #1\n" + "whilelt p2.b, x20, x21\n" + "addvl x20, x20, #1\n" + "whilelt p1.b, x20, x21\n" + "addvl x20, x20, #1\n" + "whilelt p0.b, x20, x21\n" + "7:" // 8 rounds: predicate OK + "ld1b { z11.b }, p5/Z, [x23]\n" + "ld1b { z10.b }, p4/Z, [x23, #1, MUL VL]\n" + "tbl z9.b, { z16.b }, z11.b\n" + "ld1b { z8.b }, p3/Z, [x23, #2, MUL VL]\n" + "ld1b { z7.b }, p2/Z, [x23, #3, MUL VL]\n" + "sub z11.b, z11.b, z12.b\n" + "ld1b { z6.b }, p1/Z, [x23, #4, MUL VL]\n" + "ld1b { z5.b }, p0/Z, [x23, #5, MUL VL]\n" + "tbl z4.b, { z16.b }, z10.b\n" + "sub z10.b, z10.b, z12.b\n" + "tbl z3.b, { z16.b }, z8.b\n" + "sub z8.b, z8.b, z12.b\n" + "tbl z2.b, { z16.b }, z7.b\n" + "sub z7.b, z7.b, z12.b\n" + "tbl z1.b, { z16.b }, z6.b\n" + "sub z6.b, z6.b, z12.b\n" + "tbl z0.b, { z16.b }, z5.b\n" + "sub z5.b, z5.b, z12.b\n" + ".inst 0x052b2e29 // tbx z9.b, z17.b, z11.b\n" + "sub z11.b, z11.b, z12.b\n" + ".inst 0x052a2e24 // tbx z4.b, z17.b, z10.b\n" + "sub z10.b, z10.b, z12.b\n" + ".inst 0x05282e23 // tbx z3.b, z17.b, z8.b\n" + "sub z8.b, z8.b, z12.b\n" + ".inst 0x05272e22 // tbx z2.b, z17.b, z7.b\n" + "sub z7.b, z7.b, z12.b\n" + ".inst 0x05262e21 // tbx z1.b, z17.b, z6.b\n" + "sub z6.b, z6.b, z12.b\n" + ".inst 0x05252e20 // tbx z0.b, z17.b, z5.b\n" + "sub z5.b, z5.b, z12.b\n" + ".inst 0x052b2e49 // tbx z9.b, z18.b, z11.b\n" + "sub z11.b, z11.b, z12.b\n" + ".inst 0x052a2e44 // tbx z4.b, z18.b, z10.b\n" + "sub z10.b, z10.b, z12.b\n" + ".inst 0x05282e43 // tbx z3.b, z18.b, z8.b\n" + "sub z8.b, z8.b, z12.b\n" + ".inst 0x05272e42 // tbx z2.b, z18.b, z7.b\n" + "sub z7.b, z7.b, z12.b\n" + ".inst 0x05262e41 // tbx z1.b, z18.b, z6.b\n" + "sub z6.b, z6.b, z12.b\n" + ".inst 0x05252e40 // tbx z0.b, z18.b, z5.b\n" + "sub z5.b, z5.b, z12.b\n" + ".inst 0x052b2e69 // tbx z9.b, z19.b, z11.b\n" + "sub z11.b, z11.b, z12.b\n" + ".inst 0x052a2e64 // tbx z4.b, z19.b, z10.b\n" + "sub z10.b, z10.b, z12.b\n" + ".inst 0x05282e63 // tbx z3.b, z19.b, z8.b\n" + "sub z8.b, z8.b, z12.b\n" + ".inst 0x05272e62 // tbx z2.b, z19.b, z7.b\n" + "sub z7.b, z7.b, z12.b\n" + ".inst 0x05262e61 // tbx z1.b, z19.b, z6.b\n" + "sub z6.b, z6.b, z12.b\n" + ".inst 0x05252e60 // tbx z0.b, z19.b, z5.b\n" + "sub z5.b, z5.b, z12.b\n" + ".inst 0x052b2e89 // tbx z9.b, z20.b, z11.b\n" + "sub z11.b, z11.b, z12.b\n" + ".inst 0x052a2e84 // tbx z4.b, z20.b, z10.b\n" + "sub z10.b, z10.b, z12.b\n" + ".inst 0x05282e83 // tbx z3.b, z20.b, z8.b\n" + "sub z8.b, z8.b, z12.b\n" + ".inst 0x05272e82 // tbx z2.b, z20.b, z7.b\n" + "sub z7.b, z7.b, z12.b\n" + ".inst 0x05262e81 // tbx z1.b, z20.b, z6.b\n" + "sub z6.b, z6.b, z12.b\n" + ".inst 0x05252e80 // tbx z0.b, z20.b, z5.b\n" + "sub z5.b, z5.b, z12.b\n" + ".inst 0x052b2ea9 // tbx z9.b, z21.b, z11.b\n" + "sub z11.b, z11.b, z12.b\n" + ".inst 0x052a2ea4 // tbx z4.b, z21.b, z10.b\n" + "sub z10.b, z10.b, z12.b\n" + ".inst 0x05282ea3 // tbx z3.b, z21.b, z8.b\n" + "sub z8.b, z8.b, z12.b\n" + ".inst 0x05272ea2 // tbx z2.b, z21.b, z7.b\n" + "sub z7.b, z7.b, z12.b\n" + ".inst 0x05262ea1 // tbx z1.b, z21.b, z6.b\n" + "sub z6.b, z6.b, z12.b\n" + ".inst 0x05252ea0 // tbx z0.b, z21.b, z5.b\n" + "sub z5.b, z5.b, z12.b\n" + "addvl x21, x21, #-6\n" + ".inst 0x052b2ec9 // tbx z9.b, z22.b, z11.b\n" + "sub z11.b, z11.b, z12.b\n" + ".inst 0x052a2ec4 // tbx z4.b, z22.b, z10.b\n" + "sub z10.b, z10.b, z12.b\n" + ".inst 0x05282ec3 // tbx z3.b, z22.b, z8.b\n" + "sub z8.b, z8.b, z12.b\n" + ".inst 0x05272ec2 // tbx z2.b, z22.b, z7.b\n" + "sub z7.b, z7.b, z12.b\n" + ".inst 0x05262ec1 // tbx z1.b, z22.b, z6.b\n" + "sub z6.b, z6.b, z12.b\n" + ".inst 0x05252ec0 // tbx z0.b, z22.b, z5.b\n" + "sub z5.b, z5.b, z12.b\n" + "cmp x21, XZR\n" + ".inst 0x052b2ee9 // tbx z9.b, z23.b, z11.b\n" + ".inst 0x052a2ee4 // tbx z4.b, z23.b, z10.b\n" + ".inst 0x05282ee3 // tbx z3.b, z23.b, z8.b\n" + "st1b { z9.b }, p5, [x22]\n" + ".inst 0x05272ee2 // tbx z2.b, z23.b, z7.b\n" + ".inst 0x05262ee1 // tbx z1.b, z23.b, z6.b\n" + "st1b { z4.b }, p4, [x22, #1, MUL VL]\n" + ".inst 0x05252ee0 // tbx z0.b, z23.b, z5.b\n" + "st1b { z3.b }, p3, [x22, #2, MUL VL]\n" + "addvl x23, x23, #6\n" + "st1b { z2.b }, p2, [x22, #3, MUL VL]\n" + "st1b { z1.b }, p1, [x22, #4, MUL VL]\n" + "st1b { z0.b }, p0, [x22, #5, MUL VL]\n" + "addvl x22, x22, #6\n" + "bgt 6b\n" + "b 17f\n" + "8:" // 512 bits + "mov z12.b, #0x40\n" + "mov x21, %x[string_length]\n" + "ptrue p5.b\n" + "ptrue p4.b\n" + "ptrue p3.b\n" + "ptrue p2.b\n" + "ptrue p1.b\n" + "ptrue p0.b\n" + "9:" // 4 rounds: width loop + "addvl x20, x21, #-6\n" + "cmp x20, XZR\n" + "bge 10f\n" + "mov x20, #0x0\n" + "addvl x20, x20, #1\n" + "whilelt p5.b, XZR, x21\n" + "whilelt p4.b, x20, x21\n" + "addvl x20, x20, #1\n" + "whilelt p3.b, x20, x21\n" + "addvl x20, x20, #1\n" + "whilelt p2.b, x20, x21\n" + "addvl x20, x20, #1\n" + "whilelt p1.b, x20, x21\n" + "addvl x20, x20, #1\n" + "whilelt p0.b, x20, x21\n" + "10:" // 4 rounds: predicate OK + "ld1b { z11.b }, p5/Z, [x23]\n" + "ld1b { z10.b }, p4/Z, [x23, #1, MUL VL]\n" + "tbl z9.b, { z16.b }, z11.b\n" + "ld1b { z8.b }, p3/Z, [x23, #2, MUL VL]\n" + "ld1b { z7.b }, p2/Z, [x23, #3, MUL VL]\n" + "sub z11.b, z11.b, z12.b\n" + "ld1b { z6.b }, p1/Z, [x23, #4, MUL VL]\n" + "ld1b { z5.b }, p0/Z, [x23, #5, MUL VL]\n" + "tbl z4.b, { z16.b }, z10.b\n" + "sub z10.b, z10.b, z12.b\n" + "tbl z3.b, { z16.b }, z8.b\n" + "sub z8.b, z8.b, z12.b\n" + "tbl z2.b, { z16.b }, z7.b\n" + "sub z7.b, z7.b, z12.b\n" + "tbl z1.b, { z16.b }, z6.b\n" + "sub z6.b, z6.b, z12.b\n" + "tbl z0.b, { z16.b }, z5.b\n" + "sub z5.b, z5.b, z12.b\n" + ".inst 0x052b2e29 // tbx z9.b, z17.b, z11.b\n" + "sub z11.b, z11.b, z12.b\n" + ".inst 0x052a2e24 // tbx z4.b, z17.b, z10.b\n" + "sub z10.b, z10.b, z12.b\n" + ".inst 0x05282e23 // tbx z3.b, z17.b, z8.b\n" + "sub z8.b, z8.b, z12.b\n" + ".inst 0x05272e22 // tbx z2.b, z17.b, z7.b\n" + "sub z7.b, z7.b, z12.b\n" + ".inst 0x05262e21 // tbx z1.b, z17.b, z6.b\n" + "sub z6.b, z6.b, z12.b\n" + ".inst 0x05252e20 // tbx z0.b, z17.b, z5.b\n" + "sub z5.b, z5.b, z12.b\n" + "addvl x21, x21, #-6\n" + ".inst 0x052b2e49 // tbx z9.b, z18.b, z11.b\n" + "sub z11.b, z11.b, z12.b\n" + ".inst 0x052a2e44 // tbx z4.b, z18.b, z10.b\n" + "sub z10.b, z10.b, z12.b\n" + ".inst 0x05282e43 // tbx z3.b, z18.b, z8.b\n" + "sub z8.b, z8.b, z12.b\n" + ".inst 0x05272e42 // tbx z2.b, z18.b, z7.b\n" + "sub z7.b, z7.b, z12.b\n" + ".inst 0x05262e41 // tbx z1.b, z18.b, z6.b\n" + "sub z6.b, z6.b, z12.b\n" + ".inst 0x05252e40 // tbx z0.b, z18.b, z5.b\n" + "sub z5.b, z5.b, z12.b\n" + "cmp x21, XZR\n" + ".inst 0x052b2e69 // tbx z9.b, z19.b, z11.b\n" + ".inst 0x052a2e64 // tbx z4.b, z19.b, z10.b\n" + ".inst 0x05282e63 // tbx z3.b, z19.b, z8.b\n" + "st1b { z9.b }, p5, [x22]\n" + ".inst 0x05272e62 // tbx z2.b, z19.b, z7.b\n" + ".inst 0x05262e61 // tbx z1.b, z19.b, z6.b\n" + "st1b { z4.b }, p4, [x22, #1, MUL VL]\n" + ".inst 0x05252e60 // tbx z0.b, z19.b, z5.b\n" + "st1b { z3.b }, p3, [x22, #2, MUL VL]\n" + "addvl x23, x23, #6\n" + "st1b { z2.b }, p2, [x22, #3, MUL VL]\n" + "st1b { z1.b }, p1, [x22, #4, MUL VL]\n" + "st1b { z0.b }, p0, [x22, #5, MUL VL]\n" + "addvl x22, x22, #6\n" + "bgt 9b\n" + "b 17f\n" + "11:" // 1024 bits + "mov z12.b, #0x80\n" + "mov x21, %x[string_length]\n" + "ptrue p5.b\n" + "ptrue p4.b\n" + "ptrue p3.b\n" + "ptrue p2.b\n" + "ptrue p1.b\n" + "ptrue p0.b\n" + "12:" // 2 rounds: width loop + "addvl x20, x21, #-6\n" + "cmp x20, XZR\n" + "bge 13f\n" + "mov x20, #0x0\n" + "addvl x20, x20, #1\n" + "whilelt p5.b, XZR, x21\n" + "whilelt p4.b, x20, x21\n" + "addvl x20, x20, #1\n" + "whilelt p3.b, x20, x21\n" + "addvl x20, x20, #1\n" + "whilelt p2.b, x20, x21\n" + "addvl x20, x20, #1\n" + "whilelt p1.b, x20, x21\n" + "addvl x20, x20, #1\n" + "whilelt p0.b, x20, x21\n" + "13:" // 2 rounds: predicate OK + "ld1b { z11.b }, p5/Z, [x23]\n" + "ld1b { z10.b }, p4/Z, [x23, #1, MUL VL]\n" + "addvl x21, x21, #-6\n" + "ld1b { z8.b }, p3/Z, [x23, #2, MUL VL]\n" + "ld1b { z7.b }, p2/Z, [x23, #3, MUL VL]\n" + "tbl z9.b, { z16.b }, z11.b\n" + "ld1b { z6.b }, p1/Z, [x23, #4, MUL VL]\n" + "ld1b { z5.b }, p0/Z, [x23, #5, MUL VL]\n" + "sub z11.b, z11.b, z12.b\n" + "tbl z4.b, { z16.b }, z10.b\n" + "sub z10.b, z10.b, z12.b\n" + "tbl z3.b, { z16.b }, z8.b\n" + "sub z8.b, z8.b, z12.b\n" + "tbl z2.b, { z16.b }, z7.b\n" + "sub z7.b, z7.b, z12.b\n" + "tbl z1.b, { z16.b }, z6.b\n" + "sub z6.b, z6.b, z12.b\n" + "tbl z0.b, { z16.b }, z5.b\n" + "sub z5.b, z5.b, z12.b\n" + "cmp x21, XZR\n" + ".inst 0x052b2e29 // tbx z9.b, z17.b, z11.b\n" + ".inst 0x052a2e24 // tbx z4.b, z17.b, z10.b\n" + ".inst 0x05282e23 // tbx z3.b, z17.b, z8.b\n" + "st1b { z9.b }, p5, [x22]\n" + ".inst 0x05272e22 // tbx z2.b, z17.b, z7.b\n" + ".inst 0x05262e21 // tbx z1.b, z17.b, z6.b\n" + "st1b { z4.b }, p4, [x22, #1, MUL VL]\n" + ".inst 0x05252e20 // tbx z0.b, z17.b, z5.b\n" + "st1b { z3.b }, p3, [x22, #2, MUL VL]\n" + "addvl x23, x23, #6\n" + "st1b { z2.b }, p2, [x22, #3, MUL VL]\n" + "st1b { z1.b }, p1, [x22, #4, MUL VL]\n" + "st1b { z0.b }, p0, [x22, #5, MUL VL]\n" + "addvl x22, x22, #6\n" + "bgt 12b\n" + "b 17f\n" + "14:" // 2048 bits + "mov x21, %x[string_length]\n" + "ptrue p5.b\n" + "ptrue p4.b\n" + "ptrue p3.b\n" + "ptrue p2.b\n" + "ptrue p1.b\n" + "ptrue p0.b\n" + "15:" // 1 rounds: width loop + "addvl x20, x21, #-6\n" + "cmp x20, XZR\n" + "bge 16f\n" + "mov x20, #0x0\n" + "addvl x20, x20, #1\n" + "whilelt p5.b, XZR, x21\n" + "whilelt p4.b, x20, x21\n" + "addvl x20, x20, #1\n" + "whilelt p3.b, x20, x21\n" + "addvl x20, x20, #1\n" + "whilelt p2.b, x20, x21\n" + "addvl x20, x20, #1\n" + "whilelt p1.b, x20, x21\n" + "addvl x20, x20, #1\n" + "whilelt p0.b, x20, x21\n" + "16:" // 1 rounds: predicate OK + "addvl x21, x21, #-6\n" + "ld1b { z11.b }, p5/Z, [x23]\n" + "ld1b { z10.b }, p4/Z, [x23, #1, MUL VL]\n" + "ld1b { z8.b }, p3/Z, [x23, #2, MUL VL]\n" + "ld1b { z7.b }, p2/Z, [x23, #3, MUL VL]\n" + "cmp x21, XZR\n" + "ld1b { z6.b }, p1/Z, [x23, #4, MUL VL]\n" + "ld1b { z5.b }, p0/Z, [x23, #5, MUL VL]\n" + "tbl z9.b, { z16.b }, z11.b\n" + "tbl z4.b, { z16.b }, z10.b\n" + "tbl z3.b, { z16.b }, z8.b\n" + "st1b { z9.b }, p5, [x22]\n" + "tbl z2.b, { z16.b }, z7.b\n" + "tbl z1.b, { z16.b }, z6.b\n" + "st1b { z4.b }, p4, [x22, #1, MUL VL]\n" + "tbl z0.b, { z16.b }, z5.b\n" + "st1b { z3.b }, p3, [x22, #2, MUL VL]\n" + "addvl x23, x23, #6\n" + "st1b { z2.b }, p2, [x22, #3, MUL VL]\n" + "st1b { z1.b }, p1, [x22, #4, MUL VL]\n" + "st1b { z0.b }, p0, [x22, #5, MUL VL]\n" + "addvl x22, x22, #6\n" + "bgt 15b\n" + "17:" // SVE body done + "add x24, x24, #0x1\n" + "cmp x24, %x[num_strings]\n" + "bne 2b\n" + : [table] "+&r"(table) + : [input] "r"(input), [num_strings] "r"(num_strings), [output] "r"(output), [string_length] "r"(string_length) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "x20", "x21", "x22", "x23", "x24", "x25", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31"); +} + +} // namespace cpu +} // namespace arm_compute + +#endif // ARM_COMPUTE_ENABLE_SVE +#endif // __aarch64__ diff --git a/src/cpu/kernels/lut/list.h b/src/cpu/kernels/lut/list.h index 9749b91cfe..7a2afc6927 100644 --- a/src/cpu/kernels/lut/list.h +++ b/src/cpu/kernels/lut/list.h @@ -43,7 +43,7 @@ namespace cpu uint8_t *const *output) DECLARE_LUT_KERNEL(lut_u8_neon); -DECLARE_LUT_KERNEL(lut_u8_sve); +DECLARE_LUT_KERNEL(lut_u8_sve2); #undef DECLARE_LUT_KERNEL #endif // __aarch64__ -- cgit v1.2.1