Age | Commit message (Collapse) | Author |
|
-Removes shift from depth conversion tests.
-Changes Cast tolerance between float conversions to zero
Change-Id: I6c456f7d910eb3c02069f1e4d5df7b257d6d784e
Reviewed-on: https://review.mlplatform.org/341
Reviewed-by: Anthony Barbier <Anthony.barbier@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
|
|
Change-Id: Ice653e48211053bd3cd20a693bd76de6b4efc370
Reviewed-on: https://review.mlplatform.org/270
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
|
|
Change-Id: I7eae2e55cc0b0b7bbebb7617299daaca6f75f40c
Reviewed-on: https://review.mlplatform.org/292
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
|
|
Adds support for Equal,NotEqual,Less,LessEqual,Greater,GreaterEqual
Change-Id: If0cdf4aae7f95c94709b195eee485f6663f45909
|
|
Change-Id: I2a18f0acea382960a8bc71a8f56928a5998f0dd6
|
|
Change-Id: Id74cc7ba8e5cabee6acd3798d4779f88b1f00a9b
|
|
Change-Id: I49b2e8b4200c9ed654736d9451e4ab9c073b4b10
|
|
Change-Id: I29e35024e29781a6b943b568abec9c73649215e6
|
|
Change-Id: I6ee2c0b670727fc808fa636c53ddfaec3a0036c9
|
|
Change-Id: I49f1d865f5e7562f1d80db849353a89ef77e6a9e
|
|
Output of Priorbox should be independent of the input
data layout and should always be in NCHW format
Change-Id: Ie80cd4e51c78945b158c0db1af1923bdf8d7ea7b
|
|
Fixes for:
- ReduceMean, reduction on the X axis for FP16 with 8 elements was
performed only up to a certain point. The fix now takes into account the
number of elements of the vector and does as many reductions as
necessary.
- YOLOLayer, activation for FP16 has to be performed on 32 bits until
the FP16 approximations is fixed.
Change-Id: I75373f4edd37de476e6fe1a56de3ef386b65c619
|
|
NHWC reduction on 0 axis requires a lot of memory. Testing only
axis 1 and 2 for now.
Change-Id: I82e16a27b6dfc6b426e6294cde63c3d88cb41a09
|
|
-Simplifies import memory interface
-Changes the used of void** handles with appropriate interfaces.
Change-Id: I5918c855c11f46352058864623336b352162a4b7
|
|
-Adds NHWC support for FP16
Change-Id: I61addf8efecf511ac8cd5f8aa9afc3e09c476aaf
|
|
Changed random distribution to [1, 2] as values close to
zero generate mismatches.
Change-Id: I4a00fc4f445b123dea624dd8459efce945f06126
|
|
Change-Id: I770b044b67d93510ef65e556905135b34be7ea0a
|
|
Change-Id: I6e7dee8bd615a5eff01c523f208a218574ee5eab
|
|
kernels
Change-Id: I98183f95814442b6f3dbb67a1bdae99df05b9b01
|
|
- Fixing a bug for which we did not scale the boxes before transforming them
- Adding the correct_transform_coords option to BoundingBoxTransformInfo
Change-Id: I40281254bcf87e7c8583c119e99562414fe59822
|
|
BoxWithNMSLimitKernel
COMPMID-1792: Accuracy issue in CLGenerateProposals
This patch does the following:
- Some fixes for GenerateProposals function and tests
- Adapting BoxWithNMSLimitKernel to only accept U32 tensors as keeps_size
- Update 3rdparty
- Adds a small tolerance for a GenerateProposals test
Change-Id: Ia8ec1cdfe941fe05003645e86deb9ea6a6044d74
|
|
Introduced F32 accumulation for F16 winograd gemm and output transform
WinogradConvolution will be available for F16 only if fast math flag is enabled
Change-Id: I215593c205236a0f9669218437bb40b184ec6a4f
|
|
Increase tolerance for FP16
Change-Id: I88f95da5471bbceb7449f453e2e33cf0bc4da23e
|
|
Change-Id: I99e1c3939cfea4b9cb0ddfa313706f31b213ca89
|
|
Change-Id: I69e995973597ba3927d29e4f6ed5438560e53d77
|
|
In case of CIFG optimisation scratch buffer should have a size of
[batch_size, num_units * 3] else [batch_size, num_units * 4].
Change-Id: I43e46f7b52e791472f1196f36e9142240ba76c5c
|
|
Added test cases to exercise the code path where the reshaping of B is performed on the fly.
Change-Id: Ifa4348e1054dc0019be3927f482adf64b18fd554
|
|
Change-Id: Ib0798cc17496b7817f5b5769b25d98913a33a69d
|
|
Change-Id: I5bf5d751ec7c02d96c26a769f49d03ea23a248b7
|
|
Change-Id: Ibab049f09413258c99335b7da6b151530a1bd136
|
|
and 8 tensors (Part 1)
Creating special cases for concatening 2 and 4 tensors.
Change-Id: I6a739a494ae45011acb65369e353f9ef96970b90
|
|
The issue was related to CLIm2Col when the number of input channels was less than
the number of elements processed by each thread.
The bug has been fixed in the validate_and_configure_window() function setting the correct number of elements accessed
in the output tensor.
Also fixed an issue GEMM3D when we have a single output channel
Change-Id: I094292d0c7662599c4a4c3916ec5f5821df5faef
|
|
Change-Id: I6d5f91579850906e1eb973ff6c5612195255e631
|
|
Change-Id: I807ef84dbf893bd401dcac5c0fa3a4ee49aabc66
|
|
ArmNN reported an issue with padding in CLLSTMLayer. This was due to the fact
that some tensors were allocated before they were passed to some configure
functions which attempted to change the padding requirement on already allocated
memory.
Also, increase tolerance on number of mismatches for CLBBoxTransform FP16.
Change-Id: Iad75b012be895693d0e553f3ab85f1ca7144e882
|
|
The tab characters were corrupting the output JSON file of arm_compute_validation
Change-Id: I8792fd0e02393aef60341552b428111e969a3927
|
|
Reduce the amount of precommit tests run in DirectConvolution,
Deconvolution and Pooling. Proper investigation scheduled for later.
Change-Id: Idc2510cf6877e7a605cead84f384852b609e3216
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/156466
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Vidhya Sudhan Loganathan <vidhyasudhan.loganathan@arm.com>
|
|
Also added the test case reported by ArmNN.
Change-Id: I9fe9a1b4f74267a3346529f3a597b37486593c4a
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/155914
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Gian Marco Iodice <gianmarco.iodice@arm.com>
|
|
Change-Id: Iac6a95ba7f388e65b7f1c8865c3e9bf289b233ea
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/155490
Reviewed-by: Anthony Barbier <anthony.barbier@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
|
|
OpenCL
COMPMID-1424 - Add dot product support for CLDepthwise QASYMM8 3x3 NHWC non-unit stride
With this patch we are able to improve the performance of MobileNet v1-qasymm8 by 37 %
Tried to use the dot product instruction in CLDepthwise QASYMM8 3x3 NHWC non-unit stride
but I have not seen any benefit (maybe because we have few arithemtic operation and we
do not have more load instructions). However Depthwise convolution has been improved by
30%
Change-Id: Id768a99c2e53a04276707e427af5d0ec93419ada
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/155082
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
|
|
Increases relative tolerance slightly as error was quite small.
Change-Id: I4789c5e3eeb4f2d3aaf2b4c76966474f045af4c1
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/155418
Reviewed-by: Michalis Spyrou <michalis.spyrou@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
|
|
COMPMID-1690: Add tests for NEPermute with PermutationVector dimension > 3
Change-Id: I4bfc6ff88cd46863c2e39975b5663c624db1a63d
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/155316
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
|
|
Set input range to [-1, 1] in order to avoid inf values
when calculating sqrt.
Change-Id: I18f1e427baa7830fdc587bedf27a92d78c72f49b
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/155397
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
|
|
Instead of changing the tolerances I increased the sizes of the input. In this way, for a single mismatch, as it was the case, we are below the 1% tolerance set.
Change-Id: I787261a1d1adb559c1687b7bd1e0317a72594130
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/155168
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
|
|
Increase tolerance for fp32 and added absolute tolerance
Change-Id: Iff828457b514d6301ed2c8e04b66ce86867f72b6
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/155086
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Isabella Gottardi <isabella.gottardi@arm.com>
|
|
NEWidthConcatenateLayerKernel works with 4D tensors too, hence the check has
been removed and tests have been added.
Change-Id: I73814cabe5fae975a44cc1a03b092c552497e57d
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/155070
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Isabella Gottardi <isabella.gottardi@arm.com>
|
|
Change-Id: I7bd4a8ce81483ba56686b765ca3caabebe42882d
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/155000
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Michele DiGiorgio <michele.digiorgio@arm.com>
|
|
vector
When one of the operands is a vector, the kernel does a broadcast addition and
the window is not collapsed. This represent an issue because it leads to a lot
of enqueues that increases the time taken by the OpenCL driver. This patch
allows to collapse the window when one of the two operands is a vector.
Furthermore, it adds LWS tuner to the kernel.
It also changes the number of elements processed per iteration to 8 to make
better usage of the cache.
Change-Id: I5f09ab0ddcffb3b7f9326a987c79a997b2d7fa8c
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/155003
Reviewed-by: Giuseppe Rossini <giuseppe.rossini@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
|
|
Change-Id: Ic8312a5b6790aa7cd4468d42f08d557ad40e9441
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/154570
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Gian Marco Iodice <gianmarco.iodice@arm.com>
|
|
Change-Id: I91865506166951b3bf7f06a0b2d4cde925cfefb6
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/153447
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Pablo Tello <pablo.tello@arm.com>
|