Age | Commit message (Collapse) | Author |
|
- Currently regresses on A73 devices (tested on android hikey, inceptionv3), this patch solves this
- Changed mws for all cores to use default values
- Existing mws value for A73 tuned for hikey-linux, caused regression on hikey-android
Resolves [COMPMID-5044]
Change-Id: Ifd6faaa34a0b405d0c390015566f2c75436dfb07
Signed-off-by: Mohammed Suhail Munshi <MohammedSuhail.Munshi@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6973
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: SiCong Li <sicong.li@arm.com>
|
|
1- reorganize the folders struct according the new definition
2- separate between unary and binary implementations
3- decuple kernels - unary , binary op and binary comparision
Resolves COMPMID-4634
Change-Id: I0195846cc372e74a63c659069a4508de53a22110
Signed-off-by: Dana Zlotnik <dana.zlotnik@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6860
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
|
|
Resolves COMPMID-4633
Change-Id: I9f93b28fbc3b18ccaeb453596dc8e0eddfe06b6a
Signed-off-by: Dana Zlotnik <dana.zlotnik@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6861
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Pablo Marquez Tello <pablo.tello@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
|
|
Resolves COMPMID-4617
Change-Id: Ic8793aaf64c6137f848f39c62e33b44ae79ad21d
Signed-off-by: Dana Zlotnik <dana.zlotnik@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6870
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
|
|
Resolves COMPMID-4620
Signed-off-by: Dana Zlotnik <dana.zlotnik@arm.com>
Change-Id: I22c285339840493c9cfd4c1abfbc3768ad4db824
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6871
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
|
|
Change-Id: I1d65fb9d3a7583cf8d4163ca7c0fbee27dc52633
Signed-off-by: Yair Schwarzbaum <yair.schwarzbaum@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6767
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
|
|
Resolves COMPMID-4622
Signed-off-by: Dana Zlotnik <dana.zlotnik@arm.com>
Change-Id: I18acd03e323f7734635284a763442d2cb4ded177
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6872
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
|
|
Resolves COMPMID-4624
Change-Id: Ib8d24c44ae62c4f8272310c9305d863d8447eafa
Signed-off-by: Dana Zlotnik <dana.zlotnik@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6873
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
|
|
Resolves COMPMID-4621
Change-Id: I3d89fa6d8273cc5f61a5cc0470fd730919bcd432
Signed-off-by: Dana Zlotnik <dana.zlotnik@arm.com>
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/c/VisualCompute/ComputeLibrary/+/385363
Tested-by: bsgcomp <bsgcomp@arm.com>
Comments-Addressed: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6867
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
|
|
Resolves COMPMID-4619
Change-Id: I9c43dcd3fb3a688e1c0ccc858a02376741381ba7
Signed-off-by: Dana Zlotnik <dana.zlotnik@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6874
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
|
|
* Add floating point validation tests for this configuration
* Fix reference implementation to return -inf for this configuration
* Prohibit this config in Cl, as well as non-float cases in Cpu
* Direct this config to non-asm path
Resolves COMPMID-4998
Change-Id: If88025c51b14ea337aea2441c548f858e95e5819
Signed-off-by: SiCongLi <sicong.li@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6857
Reviewed-by: Gunes Bayir <gunes.bayir@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
|
|
Change-Id: I1f39ba6a255847f4d21837a3dce4f867322203e6
Signed-off-by: alerah01 <alex.rahlis@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6799
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
|
|
1- Data types were already decoupled. This commit arrange the folder struct of the activation kernel.
2- Refactor NEON CpuActivationKernel for floating-point cases.
Resolves COMPMID-4636
Change-Id: Ia4527244c84260dce1dd1d4bd4a9e3cfe2486d85
Signed-off-by: Dana Zlotnik <dana.zlotnik@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6739
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
|
|
* Allows NEDeconvLayer to reduce memory usage when workload has
filter size 8x8 and NCHW
* Resolves MLCE-696
Change-Id: Iaaf40c813376360f813d5babfb988d3e04e4bbc0
Signed-off-by: Pablo Marquez Tello <pablo.tello@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6806
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
|
|
Unsupported case: Any of the convolution padding > pool size
Resolve COMPMID-4999
Signed-off-by: Giorgio Arena <giorgio.arena@arm.com>
Change-Id: I4279f3f14d865e0faf53e04847b52ef328970cf2
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6817
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Michele Di Giorgio <michele.digiorgio@arm.com>
|
|
Resolves: COMPMID-4998
Signed-off-by: SiCongLi <sicong.li@arm.com>
Change-Id: Ia34c4b063ebcdb193db0a3d6c22f6769a8a902d5
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6822
Reviewed-by: Gian Marco Iodice <gianmarco.iodice@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
|
|
- Enhance the SCons build system to support V8
SVE/SVE2 achitecture in a single binary
- Add additional filedefs.json to include build definitions
Resolves: COMPMID-4921
Signed-off-by: Motti Gondabi <motti.gondabi@arm.com>
Change-Id: Ie3c0ef444303270ba560ca3f43c6e22d50b86679
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6689
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
|
|
Resolves: COMPMID-5001
Change-Id: I13fbe859d2557be0459ba76da0136d0efb15f311
Signed-off-by: Mohammed Suhail Munshi <MohammedSuhail.Munshi@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6809
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Sheri Zhang <sheri.zhang@arm.com>
|
|
1- NEON supported data types are : fp32, fp16, u8, s16, s32 , q8, q_s8 , q16
2- SVE supported data types are: fp32, fp16, u8, s16, s32
3- SVE2 supported data types are : q8, q_s8 , q16
4- Re-arange SVE folder sturct
** Need to remove gaurds and add testing after Multi ISA build system and validation tests will be avalible
Resolves COMPMID-4635
Change-Id: I90e4f6a219478aa9ad5c4a6b9858496afa8af42d
Signed-off-by: Dana Zlotnik <dana.zlotnik@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6711
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
|
|
Resolves: COMPMID-4986
Signed-off-by: Freddie Liardet <frederick.liardet@arm.com>
Change-Id: I54b682d377f3bcfc57fec54113debc5e8a1d75df
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6745
Reviewed-by: Gunes Bayir <gunes.bayir@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
|
|
* Resolves problem in macOS Monterey + Clang 13 where there is no memalloc and
memalign must be used
* Resolves builld error when passing an empty list of files to the AR
tool
* Resolves MLCE-685
Change-Id: I862ff1dc7f74b2ba32479f6e8abaa32a88d47995
Signed-off-by: Pablo Marquez Tello <pablo.tello@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6706
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Gunes Bayir <gunes.bayir@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
|
|
- Decouple data type for CPU implementation,
supported data types are: fp32, fp16, u8, u16, u32, s8, s16, s32
Resolves COMPMID-4612
Signed-off-by: Yair Schwarzbaum <yair.schwarzbaum@arm.com>
Change-Id: Iec9aab9f59c5a344950c788281fc500290a19bbc
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6686
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
|
|
Resolves COMPMID-4649
Change-Id: I941d2f8a40737ff05c49f6695a42884731ef2dc9
Signed-off-by: Dana Zlotnik <dana.zlotnik@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6656
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: SiCong Li <sicong.li@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
|
|
ONCPUML-529
* Add support for passing fast_math for fullyconnected layers via fc_info.
* Add support for passing fast_math to run ACL benchmark graphs.
* Add validation test and accuracy tests (updated fixtures).
Note: abs and rel. tolerance for fast math mode are set based on experimental data.
Signed-off-by: cfRod <crefeda.rodrigues@arm.com>
change-Id: Ib107d6264d3ae5e36555334f39a13e678f8618df
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6521
Reviewed-by: SiCong Li <sicong.li@arm.com>
Reviewed-by: Gian Marco Iodice <gianmarco.iodice@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
|
|
Resolves: COMPMID-4927
Signed-off-by: Freddie Liardet <frederick.liardet@arm.com>
Change-Id: I265bf2b08598c6dec6303e3427bb9ba3f818cf03
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6578
Reviewed-by: Gunes Bayir <gunes.bayir@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
|
|
Improve validation of cpu conv3d and add validation test.
Align Size3D to Size3D comparison with how Size2D implements it.
Remove print statement in MaxUnpooling validation tests.
Signed-off-by: Freddie Liardet <frederick.liardet@arm.com>
Change-Id: I17048d56b08704cdbf1ad978af02009e57f3aa83
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6512
Reviewed-by: Gunes Bayir <gunes.bayir@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
|
|
Add support for qasymm8/qasymm8_signed in cpu conv3d.
Resolves: COMPMID-4665
Signed-off-by: Freddie Liardet <frederick.liardet@arm.com>
Change-Id: I2450bb6f24969745c8b936f4b657bd406b788c57
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6478
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
|
|
- Decouple data support of CpuDirectConv3dKernel
- Update documentation for Conv3d
Signed-off-by: Sheri Zhang <sheri.zhang@arm.com>
Change-Id: I1d94aa28f821f45a1a3d39cc3335c8faeee89f0d
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6453
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
|
|
* create get_mws method in ICPPKernel class that retuns default value for all kernels
* overwrite the default value for all the kernels used by small networks (according to banchmark case)
Resolves COMPMID-4648
Change-Id: I46d7cae61217213279d2ee740edc73f600b6d576
Signed-off-by: Dana Zlotnik <dana.zlotnik@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6412
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: SiCong Li <sicong.li@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
|
|
* Add CpuDirectConv3d support for fp32 and fp16
* Dilation is not supported
* Need decouple
Partially resolve: COMPMID-4661
Signed-off-by: Sheri Zhang <sheri.zhang@arm.com>
Change-Id: Ib1865b9ff328b684d131512b1baf77bc2f10318f
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6430
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
|
|
* Resolves COMPMID-4845
Change-Id: If286584c74d747e76fc12e3cb5c75d4411d0878d
Signed-off-by: Pablo Tello <pablo.tello@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6426
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Freddie Liardet <frederick.liardet@arm.com>
|
|
Remove padding from all cpuPool2d NCHW kernels (FP16,FP32 & Quantized)
Resolves: COMPMID-4728, COMPMID-4823
Signed-off-by: Freddie Liardet <frederick.liardet@arm.com>
Change-Id: Ida619f67cd6606b33828f2d9dee925aeb794cc50
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6358
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Pablo Marquez Tello <pablo.tello@arm.com>
Reviewed-by: Gian Marco Iodice <gianmarco.iodice@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
|
|
- Fixes identification heuristics for SVE2 based kernels in CpuAdd
- Adds identification heuristics for SVE to CpuElementwise
Signed-off-by: Georgios Pinitas <georgios.pinitas@arm.com>
Change-Id: Id287dbd72fba81afc415d7aec74e06aae11984e3
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6369
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
|
|
- Rework CpuScaleKernel F32/F16 NHWC - bilinear
- Rework CpuScaleKernel F32/F16 NHWC - nearest
- Add test to validate the vector computation path
Resolves COMPMID-4801, COMPMID-4802
Change-Id: Ie6e4f262a8cce509edd7b8f564c940758625c58a
Signed-off-by: Gian Marco Iodice <gianmarco.iodice@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6361
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Pablo Marquez Tello <pablo.tello@arm.com>
|
|
Changing the approach for specifying that weights and biases tensors are
non-constant by making it a member of TensorInfo rather than an option
of the functions.
Resolves: COMPMID-4222, COMPMID-4811
Signed-off-by: Giorgio Arena <giorgio.arena@arm.com>
Change-Id: I9b0081ccbcf8271ce029ba6755563d64c59e1d32
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6313
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Pablo Marquez Tello <pablo.tello@arm.com>
Reviewed-by: Michele Di Giorgio <michele.digiorgio@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
|
|
Partially Resolves: COMPMID-4718
Signed-off-by: Ramy Elgammal <ramy.elgammal@arm.com>
Change-Id: I02eabdd6bce8cd561ab2fdfd644a686a3762b817
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6253
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
|
|
This reverts commit aed63ee175e0d64c934389e9d1b2edd0cb1a5cdd.
* Resolves COMPMID-4812
Change-Id: I16919e2f3b22c868ae146d0d10dae97a80e1ba46
Signed-off-by: Pablo Marquez Tello <pablo.tello@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6266
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Sheri Zhang <sheri.zhang@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
|
|
Resolve COMPMID-4788
Signed-off-by: Giorgio Arena <giorgio.arena@arm.com>
Change-Id: I415f331b6b689128857be2b7f1dddfae41bb3b61
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6234
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
Reviewed-by: Gunes Bayir <gunes.bayir@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
|
|
Changing the approach for specifying that weights and biases tensors are
non-constant by making it a member of TensorInfo rather than an option
of the functions.
Resolves: COMPMID-4222
Change-Id: I96e6f3868f51785c9700a3ef6a1fe7b05747862c
Signed-off-by: Michele Di Giorgio <michele.digiorgio@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6162
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
|
|
Resolves: COMPMID-4718
Change-Id: Id4dd762cd1b759bb814b9d0b1ea0c9ba4dfbae6f
Signed-off-by: Ramy Elgammal <ramy.elgammal@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6139
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
|
|
Resolves COMPMID-2138
Change-Id: I5587fe53ec99d164413cde1809d1791bf909b8df
Signed-off-by: Michalis Spyrou <michalis.spyrou@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6171
Reviewed-by: Michele Di Giorgio <michele.digiorgio@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
|
|
Legacy structure contained two libraries core/runtime with two backends
in each.
We reduce the core/runtime libraries to a single library thus merging
the backend files
Signed-off-by: Georgios Pinitas <georgios.pinitas@arm.com>
Change-Id: I69545765fe7a730368105cdbd067d3135ec7a174
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6155
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Michele Di Giorgio <michele.digiorgio@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
|
|
Resolves: COMPMID-4512
Signed-off-by: Georgios Pinitas <georgios.pinitas@arm.com>
Change-Id: Id12130365fa3fe2261160931dcc7affb6b467186
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6031
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Michele Di Giorgio <michele.digiorgio@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
|
|
Refactors the CpuInfo extraction code and cleans the usage of it in the
CpuContext class
Signed-off-by: Georgios Pinitas <georgios.pinitas@arm.com>
Change-Id: Iea47dfdaad431fb49285da92778d6b42cf318f60
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/5848
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
|
|
A smaller core library is created using a subset of the operators.
Changed the structure of filelist.json in order to include more
information about the kernels and make the selection easier.
Resolves: COMPMID-4514
Change-Id: I079ca7d8e64346174eebdd13b834e1dd4dc36ca2
Signed-off-by: Michalis Spyrou <michalis.spyrou@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/5786
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
|
|
Resolves: COMPMID-4500
Signed-off-by: Georgios Pinitas <georgios.pinitas@arm.com>
Change-Id: I008c51934ef813fb1f489b531288c4419e701955
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/5799
Reviewed-by: Michele Di Giorgio <michele.digiorgio@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
|
|
Queues are responsible for scheduling operators and performing other
runtime related activities like for example tuning.
Signed-off-by: Georgios Pinitas <georgios.pinitas@arm.com>
Change-Id: I0366d9048470d277b8cbf59fa42f95c0ae57c5c9
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/5487
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Michele Di Giorgio <michele.digiorgio@arm.com>
Reviewed-by: Michalis Spyrou <michalis.spyrou@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
|
|
A couple of utility functions to get the information
about tensors are added. Those functions are placed
at an additional header file for better grouping.
Related test cases are also added.
Resolves: COMPMID-4376
Change-Id: I6bd09cbf60fddcf4fe651906982397afb0451392
Signed-off-by: Sang-Hoon Park <sang-hoon.park@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/5405
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
Reviewed-by: Michele Di Giorgio <michele.digiorgio@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
|
|
Adds the following:
- TensorDescriptor: which is responsible for holding the information
needed to represent a tensor (e.g. shape, dimensions, etc)
- Tensor: an aggreate object of a descriptor and a backing memory
- TensorPack: A map of tensor that can be passed to operators as
inputs/outputs
Signed-off-by: Georgios Pinitas <georgios.pinitas@arm.com>
Change-Id: I02734ac6ad85700d91d6e73217b4637adbf5d177
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/5260
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
|
|
Some compilers don't support aligned_alloc as they fallback on
posix_memalign.
Change-Id: Ifa2ca9fa4684a7ffbe3674328060c0603ec0c6b4
Signed-off-by: Michalis Spyrou <michalis.spyrou@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/5244
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Michele Di Giorgio <michele.digiorgio@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
|