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- Rename NEFloorKernel to CpuFloorKernel to accomodate new ISA
implementations
- Remove state and instead pass tensors to operate during run
- Add member function to generate an execution window given an input and
output tensor description
Signed-off-by: Georgios Pinitas <georgios.pinitas@arm.com>
Change-Id: I9240b8ec534589c0f15c354f771f1ac5d7010c3b
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/4773
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Michalis Spyrou <michalis.spyrou@arm.com>
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Change-Id: I4ec7561a7f6a42a22b8187968ae302dbe75023bc
Signed-off-by: Michalis Spyrou <michalis.spyrou@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/4753
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Sang-Hoon Park <sang-hoon.park@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
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- Few bit-width dependent intrinsics are added.
- Few math functions are added.
Partially implements: COMPMID-3872
Change-Id: Ia6ab46bd170fec9c7c8d4410b7ef4d84710b68ed
Signed-off-by: Sang-Hoon Park <sang-hoon.park@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/4718
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Michalis Spyrou <michalis.spyrou@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
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Adds support for ActivationLayer for SVE and SVE2.
Datatypes supported:
*FP32
*FP16
*QASYMM8
*QASYMM8_SIGNED
*QSYMM16
Change-Id: Ia3583891795cda4ca2f9fa27c440731a5c27710d
Signed-off-by: Michalis Spyrou <michalis.spyrou@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/4566
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
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