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Change-Id: I6b7f7a406fcb8d64adb221a24d7983e11bcb391e
Signed-off-by: Gian Marco Iodice <gianmarco.iodice@arm.com>
Reviewed-on: https://review.mlplatform.org/c/846
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Michele Di Giorgio <michele.digiorgio@arm.com>
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CLDepthwiseConvolution
Change-Id: I97788d9e349f37fcd818d588d668e2d5e22fd568
Signed-off-by: giuros01 <giuseppe.rossini@arm.com>
Reviewed-on: https://review.mlplatform.org/c/818
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Gian Marco Iodice <gianmarco.iodice@arm.com>
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Change-Id: I364c7ec5a43ad391a73429489802b0e679ee0c6e
Signed-off-by: Gian Marco Iodice <gianmarco.iodice@arm.com>
Reviewed-on: https://review.mlplatform.org/c/732
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
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Change-Id: Ie08a6874347085f96b00f25bdb605eee7d683c25
Signed-off-by: giuros01 <giuseppe.rossini@arm.com>
Reviewed-on: https://review.mlplatform.org/719
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
Reviewed-by: Michalis Spyrou <michalis.spyrou@arm.com>
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Logistic activation in QASYMM8 is performed in floating point and then
converting back to QASYMM8. However, if input and output have different
quantization information, a double conversion is done leading to loss in
accuracy.
This patch creates a special case kernel for logistic activation.
Change-Id: Ia18ee0b2f84701674f88785bcd13753b50d64a08
Signed-off-by: Michele Di Giorgio <michele.digiorgio@arm.com>
Reviewed-on: https://review.mlplatform.org/696
Reviewed-by: Gian Marco Iodice <gianmarco.iodice@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
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This reverts commit cd96a26f67bfbb9b0efe6e0e2b229d0b46b4e3e6.
Change-Id: I1d46f37095c94968ad4f3b781269adaa03e2e410
Signed-off-by: giuros01 <giuseppe.rossini@arm.com>
Reviewed-on: https://review.mlplatform.org/706
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
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kernels (stride=1 and stride=2)
Change-Id: I7d0d2dc350feeb40d253d17f9ffd5051a8fb42ef
Reviewed-on: https://review.mlplatform.org/511
Reviewed-by: Gian Marco Iodice <gianmarco.iodice@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
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Change-Id: Ia4db21b394a0b9235393202ce3c00b11cceb94ea
Reviewed-on: https://review.mlplatform.org/568
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Michele Di Giorgio <michele.digiorgio@arm.com>
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This patch will add a generic permute cl-kernel to handle
all permutations available for tensors having rank upto 4.
Change-Id: I50eb555d9d45d5ad5f7fa9b0a3862dd17551d458
Signed-off-by: shubham <shub98.gupta@samsung.com>
Reviewed-on: https://review.mlplatform.org/449
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Manuel Bottini <manuel.bottini@arm.com>
Reviewed-by: Michalis Spyrou <michalis.spyrou@arm.com>
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Change-Id: I3d859da09a4de1019bb8c2046725eab942247927
Reviewed-on: https://review.mlplatform.org/386
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
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Change-Id: I913a7297a0c34a05b1d37eab1489b430423700e8
Reviewed-on: https://review.mlplatform.org/417
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Michele Di Giorgio <michele.digiorgio@arm.com>
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Change-Id: I88da6eb5289c303b1dc91606c1560ce629746058
Reviewed-on: https://review.mlplatform.org/381
Reviewed-by: Gian Marco Iodice <gianmarco.iodice@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
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The current implementation is limited just to FP32
Change-Id: I185ab57e483e879d7c301e9cc3033efc8b41e244
Reviewed-on: https://review.mlplatform.org/389
Reviewed-by: Anthony Barbier <Anthony.barbier@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Michele Di Giorgio <michele.digiorgio@arm.com>
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matrix of GEMM/GEMMLowp
Change-Id: I77f2bfcc5d170bcc2428a2f27104942c1ec877d7
Reviewed-on: https://review.mlplatform.org/375
Reviewed-by: Michele Di Giorgio <michele.digiorgio@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
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matrix of GEMM/GEMMLowp
Change-Id: I8c5fd4c8bcdffda1522c83158981ed92baa045f4
Reviewed-on: https://review.mlplatform.org/364
Reviewed-by: Michele Di Giorgio <michele.digiorgio@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
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Change-Id: I827b26239043a9e90d26c2583122648d2a45303a
Reviewed-on: https://review.mlplatform.org/317
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
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Change-Id: Id0d4a07af24e2331161996083b0c1bab072bd405
Reviewed-on: https://review.mlplatform.org/322
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
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Change-Id: I13f6e4c600f39355f69e015409bf30dafdc5e3aa
Reviewed-on: https://review.mlplatform.org/332
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Michele Di Giorgio <michele.digiorgio@arm.com>
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Change-Id: Ice653e48211053bd3cd20a693bd76de6b4efc370
Reviewed-on: https://review.mlplatform.org/270
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
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Change-Id: I7eae2e55cc0b0b7bbebb7617299daaca6f75f40c
Reviewed-on: https://review.mlplatform.org/292
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
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Adds support for Equal,NotEqual,Less,LessEqual,Greater,GreaterEqual
Change-Id: If0cdf4aae7f95c94709b195eee485f6663f45909
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Change-Id: I2a18f0acea382960a8bc71a8f56928a5998f0dd6
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Change-Id: I49b2e8b4200c9ed654736d9451e4ab9c073b4b10
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Change-Id: I49f1d865f5e7562f1d80db849353a89ef77e6a9e
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Output of Priorbox should be independent of the input
data layout and should always be in NCHW format
Change-Id: Ie80cd4e51c78945b158c0db1af1923bdf8d7ea7b
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FP mixed precision support added to GEMM kernel used for fp16 winograd conv on Midgard GPUs
Change-Id: I1619beb025fc484a1ac9d3e528d785edabbc7ee6
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Introduced F32 accumulation for F16 winograd gemm and output transform
WinogradConvolution will be available for F16 only if fast math flag is enabled
Change-Id: I215593c205236a0f9669218437bb40b184ec6a4f
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Change-Id: Ib0798cc17496b7817f5b5769b25d98913a33a69d
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Change-Id: I5bf5d751ec7c02d96c26a769f49d03ea23a248b7
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Change-Id: Ibab049f09413258c99335b7da6b151530a1bd136
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and 8 tensors (Part 1)
Creating special cases for concatening 2 and 4 tensors.
Change-Id: I6a739a494ae45011acb65369e353f9ef96970b90
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OpenCL
COMPMID-1424 - Add dot product support for CLDepthwise QASYMM8 3x3 NHWC non-unit stride
With this patch we are able to improve the performance of MobileNet v1-qasymm8 by 37 %
Tried to use the dot product instruction in CLDepthwise QASYMM8 3x3 NHWC non-unit stride
but I have not seen any benefit (maybe because we have few arithemtic operation and we
do not have more load instructions). However Depthwise convolution has been improved by
30%
Change-Id: Id768a99c2e53a04276707e427af5d0ec93419ada
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/155082
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
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Change-Id: Ic8312a5b6790aa7cd4468d42f08d557ad40e9441
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/154570
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Gian Marco Iodice <gianmarco.iodice@arm.com>
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Change-Id: I91865506166951b3bf7f06a0b2d4cde925cfefb6
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/153447
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Pablo Tello <pablo.tello@arm.com>
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Change-Id: Iae22554d5fe893fd22a000eab5bfd8275ea06eb3
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/154102
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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Change-Id: I146936c9e98b343496a4b61cdbadf0eaa38e885a
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/154008
Reviewed-by: Michele DiGiorgio <michele.digiorgio@arm.com>
Reviewed-by: Giuseppe Rossini <giuseppe.rossini@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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Change-Id: Id331199f569f52a37280a9ada5bf84694580b93c
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/152843
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Michele DiGiorgio <michele.digiorgio@arm.com>
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Change-Id: Ie215daacd10477309dbf8af1bb2b05b7a0a8f203
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/150773
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Isabella Gottardi <isabella.gottardi@arm.com>
Reviewed-by: Pablo Tello <pablo.tello@arm.com>
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Change-Id: I62bbf510cc106a90ed2884be3c9c0c127da25898
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/150681
Reviewed-by: Giuseppe Rossini <giuseppe.rossini@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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Change-Id: Ic1f9e85306a0a0b1459c9f9aa35bd629deea1710
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/148797
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Anthony Barbier <anthony.barbier@arm.com>
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
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Change-Id: I5f719f5b2915c18cd0ca6271db401152112863a6
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/148982
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Isabella Gottardi <isabella.gottardi@arm.com>
Reviewed-by: Anthony Barbier <anthony.barbier@arm.com>
Reviewed-by: Giuseppe Rossini <giuseppe.rossini@arm.com>
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Change-Id: Ifa37a6758f79d0a6ca771dcfb4c55a5d96b452d0
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/148892
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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Change-Id: Id7ea6e7f57179478e5ba0e9231274e98fa089590
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/148028
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
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Change-Id: I05d21f9a92013ecfd1128d12cf1561cfd6e5c5e9
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/147983
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Anthony Barbier <anthony.barbier@arm.com>
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Change-Id: Ideead99410e5e0bda1035030af1bbcd0a65ea15e
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/144792
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
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Change-Id: I4a32e47e6d9152633668cf0e14db88fc8c26f7ea
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/148167
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Michele DiGiorgio <michele.digiorgio@arm.com>
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Change-Id: If7ae0a8b6255a10711365068d9fb153c71f09818
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/147751
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
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COMPMID-1589 - Add support for NHWC to CLChannelShuffleLayerKernel
Change-Id: I13936a5cd1659d01fdb10b346e90f0d72d79f1f1
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/148475
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Michele DiGiorgio <michele.digiorgio@arm.com>
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Change-Id: I6fd83d6584c56a4fd2470948f1987e23237c16d3
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/145577
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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Change-Id: I332c0703e1399fca0c5b724529b54a28f49c88da
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/146842
Tested-by: Jenkins <bsgcomp@arm.com>
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
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