diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/kernels/add/generic/sve/fp16.cpp | 2 | ||||
| -rw-r--r-- | src/cpu/kernels/add/generic/sve/fp32.cpp | 4 | ||||
| -rw-r--r-- | src/cpu/kernels/add/generic/sve/impl.cpp | 4 | ||||
| -rw-r--r-- | src/cpu/kernels/add/generic/sve/impl.h | 4 | ||||
| -rw-r--r-- | src/cpu/kernels/add/generic/sve/integer.cpp | 4 | ||||
| -rw-r--r-- | src/cpu/kernels/add/generic/sve2/qasymm8.cpp | 5 | ||||
| -rw-r--r-- | src/cpu/kernels/add/generic/sve2/qasymm8_signed.cpp | 4 | ||||
| -rw-r--r-- | src/cpu/kernels/add/generic/sve2/qsymm16.cpp | 4 |
8 files changed, 15 insertions, 16 deletions
diff --git a/src/cpu/kernels/add/generic/sve/fp16.cpp b/src/cpu/kernels/add/generic/sve/fp16.cpp index 28f4d2ba8e..7dc3142d3d 100644 --- a/src/cpu/kernels/add/generic/sve/fp16.cpp +++ b/src/cpu/kernels/add/generic/sve/fp16.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * diff --git a/src/cpu/kernels/add/generic/sve/fp32.cpp b/src/cpu/kernels/add/generic/sve/fp32.cpp index 8f651b3ed2..5383b887ba 100644 --- a/src/cpu/kernels/add/generic/sve/fp32.cpp +++ b/src/cpu/kernels/add/generic/sve/fp32.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -36,4 +36,4 @@ void add_fp32_sve(const ITensor *src0, const ITensor *src1, ITensor *dst, const } } } // namespace arm_compute -#endif //ARM_COMPUTE_ENABLE_SVE +#endif //ARM_COMPUTE_ENABLE_SVE
\ No newline at end of file diff --git a/src/cpu/kernels/add/generic/sve/impl.cpp b/src/cpu/kernels/add/generic/sve/impl.cpp index 52429bbe1e..615f346dff 100644 --- a/src/cpu/kernels/add/generic/sve/impl.cpp +++ b/src/cpu/kernels/add/generic/sve/impl.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -133,4 +133,4 @@ template void add_same_sve<float16_t>(const ITensor *src0, const ITensor *src1, #endif /* (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(ENABLE_FP16_KERNELS) */ } // namespace cpu } // namespace arm_compute -#endif // ARM_COMPUTE_ENABLE_SVE +#endif // ARM_COMPUTE_ENABLE_SVE
\ No newline at end of file diff --git a/src/cpu/kernels/add/generic/sve/impl.h b/src/cpu/kernels/add/generic/sve/impl.h index 59f39e90c9..219dbc9b2e 100644 --- a/src/cpu/kernels/add/generic/sve/impl.h +++ b/src/cpu/kernels/add/generic/sve/impl.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -37,4 +37,4 @@ void add_same_sve(const ITensor *src0, const ITensor *src1, ITensor *dst, const } // namespace cpu } // namespace arm_compute #endif // SRC_CORE_SVE_KERNELS_ADD_IMPL_H -#endif // ARM_COMPUTE_ENABLE_SVE +#endif // ARM_COMPUTE_ENABLE_SVE
\ No newline at end of file diff --git a/src/cpu/kernels/add/generic/sve/integer.cpp b/src/cpu/kernels/add/generic/sve/integer.cpp index d197717cf0..1d25d3463a 100644 --- a/src/cpu/kernels/add/generic/sve/integer.cpp +++ b/src/cpu/kernels/add/generic/sve/integer.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -46,4 +46,4 @@ void add_s32_sve(const ITensor *src0, const ITensor *src1, ITensor *dst, const C } } } // namespace arm_compute -#endif //(ARM_COMPUTE_ENABLE_SVE) +#endif //(ARM_COMPUTE_ENABLE_SVE)
\ No newline at end of file diff --git a/src/cpu/kernels/add/generic/sve2/qasymm8.cpp b/src/cpu/kernels/add/generic/sve2/qasymm8.cpp index c61089e937..5fe9b95a48 100644 --- a/src/cpu/kernels/add/generic/sve2/qasymm8.cpp +++ b/src/cpu/kernels/add/generic/sve2/qasymm8.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021 Arm Limited. + * Copyright (c) 2020-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -22,7 +22,6 @@ * SOFTWARE. */ #if defined(ARM_COMPUTE_ENABLE_SVE2) - #include "arm_compute/core/Helpers.h" #include "arm_compute/core/ITensor.h" #include "arm_compute/core/Types.h" @@ -180,4 +179,4 @@ void add_qasymm8_sve2(const ITensor *src0, const ITensor *src1, ITensor *dst, co } } // namespace cpu } // namespace arm_compute -#endif //ARM_COMPUTE_ENABLE_SVE2 +#endif //ARM_COMPUTE_ENABLE_SVE2
\ No newline at end of file diff --git a/src/cpu/kernels/add/generic/sve2/qasymm8_signed.cpp b/src/cpu/kernels/add/generic/sve2/qasymm8_signed.cpp index 9ac138aaef..9135dfdcf6 100644 --- a/src/cpu/kernels/add/generic/sve2/qasymm8_signed.cpp +++ b/src/cpu/kernels/add/generic/sve2/qasymm8_signed.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021 Arm Limited. + * Copyright (c) 2020-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -178,4 +178,4 @@ void add_qasymm8_signed_sve2(const ITensor *src0, const ITensor *src1, ITensor * } } // namespace cpu } // namespace arm_compute -#endif //ARM_COMPUTE_ENABLE_SVE2 +#endif //(ARM_COMPUTE_ENABLE_SVE2)
\ No newline at end of file diff --git a/src/cpu/kernels/add/generic/sve2/qsymm16.cpp b/src/cpu/kernels/add/generic/sve2/qsymm16.cpp index f148872c17..723d2a6c98 100644 --- a/src/cpu/kernels/add/generic/sve2/qsymm16.cpp +++ b/src/cpu/kernels/add/generic/sve2/qsymm16.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021 Arm Limited. + * Copyright (c) 2020-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -153,4 +153,4 @@ void add_qsymm16_sve2(const ITensor *src0, const ITensor *src1, ITensor *dst, co } } // namespace cpu } // namespace arm_compute -#endif //ARM_COMPUTE_ENABLE_SVE2 +#endif //ARM_COMPUTE_ENABLE_SVE2
\ No newline at end of file |