diff options
Diffstat (limited to 'src/cpu/kernels/range/generic')
-rw-r--r-- | src/cpu/kernels/range/generic/neon/fp16.cpp | 41 | ||||
-rw-r--r-- | src/cpu/kernels/range/generic/neon/fp32.cpp | 39 | ||||
-rw-r--r-- | src/cpu/kernels/range/generic/neon/impl.cpp | 93 | ||||
-rw-r--r-- | src/cpu/kernels/range/generic/neon/impl.h | 38 | ||||
-rw-r--r-- | src/cpu/kernels/range/generic/neon/integer.cpp | 64 |
5 files changed, 275 insertions, 0 deletions
diff --git a/src/cpu/kernels/range/generic/neon/fp16.cpp b/src/cpu/kernels/range/generic/neon/fp16.cpp new file mode 100644 index 0000000000..5d50dce907 --- /dev/null +++ b/src/cpu/kernels/range/generic/neon/fp16.cpp @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2021 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#if defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(ENABLE_FP16_KERNELS) + +#include "src/cpu/kernels/range/generic/neon/impl.h" + +#include "arm_compute/core/Helpers.h" +#include "src/core/NEON/wrapper/wrapper.h" + +namespace arm_compute +{ +namespace cpu +{ +void fp16_neon_range_function(ITensor *output, float start, float step, const Window &window) +{ + return neon_range_function<float16_t>(output, start, step, window); +} +} // namespace cpu +} // namespace arm_compute +#endif /* defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(ENABLE_FP16_KERNELS) */ diff --git a/src/cpu/kernels/range/generic/neon/fp32.cpp b/src/cpu/kernels/range/generic/neon/fp32.cpp new file mode 100644 index 0000000000..6044f0f886 --- /dev/null +++ b/src/cpu/kernels/range/generic/neon/fp32.cpp @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2021 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "src/cpu/kernels/range/generic/neon/impl.h" + +#include "arm_compute/core/Helpers.h" +#include "src/core/NEON/wrapper/wrapper.h" + +namespace arm_compute +{ +namespace cpu +{ +void fp32_neon_range_function(ITensor *output, float start, float step, const Window &window) +{ + return neon_range_function<float32_t>(output, start, step, window); +} +} // namespace cpu +} // namespace arm_compute diff --git a/src/cpu/kernels/range/generic/neon/impl.cpp b/src/cpu/kernels/range/generic/neon/impl.cpp new file mode 100644 index 0000000000..f91251c914 --- /dev/null +++ b/src/cpu/kernels/range/generic/neon/impl.cpp @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2021 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#include "src/cpu/kernels/range/generic/neon/impl.h" + +#include "arm_compute/core/Helpers.h" +#include "arm_compute/core/TensorInfo.h" +#include "src/core/NEON/wrapper/wrapper.h" +#include "src/core/common/Registrars.h" + +namespace arm_compute +{ +namespace cpu +{ +template <typename T> +void neon_range_function(ITensor *output, float start, float step, const Window &window) +{ + /** SIMD vector tag type. */ + using ExactTagType = typename wrapper::traits::neon_bitvector<T, wrapper::traits::BitWidth::W128>::tag_type; + + const auto step_vec = wrapper::vdup_n(static_cast<T>(step), ExactTagType{}); + const auto start_vec = wrapper::vdup_n(static_cast<T>(start), ExactTagType{}); + auto id_vec = wrapper::vdup_n(static_cast<T>(0.f), ExactTagType{}); + + const auto window_start_x = static_cast<int>(window.x().start()); + const auto window_end_x = static_cast<int>(window.x().end()); + const int window_step_x = 16 / sizeof(T); + + Window win{ window }; + win.set(Window::DimX, Window::Dimension(0, 1, 1)); + Iterator output_it(output, win); + + execute_window_loop(win, [&](const Coordinates &) + { + int x = window_start_x; + const auto out_ptr = reinterpret_cast<T *>(output_it.ptr()); + for(; x <= (window_end_x - window_step_x); x += window_step_x) + { + for(int count = 0; count < window_step_x; ++count) + { + id_vec = wrapper::vsetlane(static_cast<T>(x + count), id_vec, count); + } + + // start + step * id + const auto res_vec = wrapper::vmla(start_vec, id_vec, step_vec); + wrapper::vstore(out_ptr + x, res_vec); + } + + // Compute left-over elements + for(; x < window_end_x; ++x) + { + const auto res = start + x * step; + *(out_ptr + x) = res; + } + + }, + output_it); +} + +template void neon_range_function<uint8_t>(ITensor *output, float start, float step, const Window &window); +template void neon_range_function<uint16_t>(ITensor *output, float start, float step, const Window &window); +template void neon_range_function<uint32_t>(ITensor *output, float start, float step, const Window &window); +template void neon_range_function<int8_t>(ITensor *output, float start, float step, const Window &window); +template void neon_range_function<int16_t>(ITensor *output, float start, float step, const Window &window); +template void neon_range_function<int32_t>(ITensor *output, float start, float step, const Window &window); +template void neon_range_function<float32_t>(ITensor *output, float start, float step, const Window &window); + +#if defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(ENABLE_FP16_KERNELS) +template void neon_range_function<float16_t>(ITensor *output, float start, float step, const Window &window); +#endif /* defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(ENABLE_FP16_KERNELS) */ + +} // namespace cpu +} // namespace arm_compute diff --git a/src/cpu/kernels/range/generic/neon/impl.h b/src/cpu/kernels/range/generic/neon/impl.h new file mode 100644 index 0000000000..7ac2fc9c11 --- /dev/null +++ b/src/cpu/kernels/range/generic/neon/impl.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2021 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef SRC_CORE_NEON_KERNELS_RANGE_IMPL_H +#define SRC_CORE_NEON_KERNELS_RANGE_IMPL_H + +namespace arm_compute +{ +class ITensor; +class Window; + +namespace cpu +{ +template <typename T> +void neon_range_function(ITensor *output, float start, float step, const Window &window); +} // namespace cpu +} // namespace arm_compute +#endif //SRC_CORE_NEON_KERNELS_RANGE_IMPL_H diff --git a/src/cpu/kernels/range/generic/neon/integer.cpp b/src/cpu/kernels/range/generic/neon/integer.cpp new file mode 100644 index 0000000000..0f3ff89b71 --- /dev/null +++ b/src/cpu/kernels/range/generic/neon/integer.cpp @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2021 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "src/cpu/kernels/range/generic/neon/impl.h" + +#include <cstdint> + +namespace arm_compute +{ +namespace cpu +{ +void u8_neon_range_function(ITensor *output, float start, float step, const Window &window) +{ + return neon_range_function<uint8_t>(output, start, step, window); +} + +void u16_neon_range_function(ITensor *output, float start, float step, const Window &window) +{ + return neon_range_function<uint16_t>(output, start, step, window); +} + +void u32_neon_range_function(ITensor *output, float start, float step, const Window &window) +{ + return neon_range_function<uint32_t>(output, start, step, window); +} + +void s8_neon_range_function(ITensor *output, float start, float step, const Window &window) +{ + return neon_range_function<int8_t>(output, start, step, window); +} + +void s16_neon_range_function(ITensor *output, float start, float step, const Window &window) +{ + return neon_range_function<int16_t>(output, start, step, window); +} + +void s32_neon_range_function(ITensor *output, float start, float step, const Window &window) +{ + return neon_range_function<int32_t>(output, start, step, window); +} + +} // namespace cpu +} // namespace arm_compute |