diff options
Diffstat (limited to 'src/cpu/kernels/add/generic/sve2')
-rw-r--r-- | src/cpu/kernels/add/generic/sve2/qasymm8.cpp | 5 | ||||
-rw-r--r-- | src/cpu/kernels/add/generic/sve2/qasymm8_signed.cpp | 4 | ||||
-rw-r--r-- | src/cpu/kernels/add/generic/sve2/qsymm16.cpp | 4 |
3 files changed, 6 insertions, 7 deletions
diff --git a/src/cpu/kernels/add/generic/sve2/qasymm8.cpp b/src/cpu/kernels/add/generic/sve2/qasymm8.cpp index c61089e937..5fe9b95a48 100644 --- a/src/cpu/kernels/add/generic/sve2/qasymm8.cpp +++ b/src/cpu/kernels/add/generic/sve2/qasymm8.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021 Arm Limited. + * Copyright (c) 2020-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -22,7 +22,6 @@ * SOFTWARE. */ #if defined(ARM_COMPUTE_ENABLE_SVE2) - #include "arm_compute/core/Helpers.h" #include "arm_compute/core/ITensor.h" #include "arm_compute/core/Types.h" @@ -180,4 +179,4 @@ void add_qasymm8_sve2(const ITensor *src0, const ITensor *src1, ITensor *dst, co } } // namespace cpu } // namespace arm_compute -#endif //ARM_COMPUTE_ENABLE_SVE2 +#endif //ARM_COMPUTE_ENABLE_SVE2
\ No newline at end of file diff --git a/src/cpu/kernels/add/generic/sve2/qasymm8_signed.cpp b/src/cpu/kernels/add/generic/sve2/qasymm8_signed.cpp index 9ac138aaef..9135dfdcf6 100644 --- a/src/cpu/kernels/add/generic/sve2/qasymm8_signed.cpp +++ b/src/cpu/kernels/add/generic/sve2/qasymm8_signed.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021 Arm Limited. + * Copyright (c) 2020-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -178,4 +178,4 @@ void add_qasymm8_signed_sve2(const ITensor *src0, const ITensor *src1, ITensor * } } // namespace cpu } // namespace arm_compute -#endif //ARM_COMPUTE_ENABLE_SVE2 +#endif //(ARM_COMPUTE_ENABLE_SVE2)
\ No newline at end of file diff --git a/src/cpu/kernels/add/generic/sve2/qsymm16.cpp b/src/cpu/kernels/add/generic/sve2/qsymm16.cpp index f148872c17..723d2a6c98 100644 --- a/src/cpu/kernels/add/generic/sve2/qsymm16.cpp +++ b/src/cpu/kernels/add/generic/sve2/qsymm16.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021 Arm Limited. + * Copyright (c) 2020-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -153,4 +153,4 @@ void add_qsymm16_sve2(const ITensor *src0, const ITensor *src1, ITensor *dst, co } } // namespace cpu } // namespace arm_compute -#endif //ARM_COMPUTE_ENABLE_SVE2 +#endif //ARM_COMPUTE_ENABLE_SVE2
\ No newline at end of file |