diff options
Diffstat (limited to 'src/core/NEON/kernels/arm_gemm/kernels')
8 files changed, 1864 insertions, 0 deletions
diff --git a/src/core/NEON/kernels/arm_gemm/kernels/a64_interleaved_s8s32_mmla_12x8.hpp b/src/core/NEON/kernels/arm_gemm/kernels/a64_interleaved_s8s32_mmla_12x8.hpp new file mode 100644 index 0000000000..f669b870c6 --- /dev/null +++ b/src/core/NEON/kernels/arm_gemm/kernels/a64_interleaved_s8s32_mmla_12x8.hpp @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2019 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#pragma once + +#ifdef __aarch64__ + +#include <cstdint> +#include "../std_transforms_fixed.hpp" + +namespace arm_gemm { + +// Actual kernel implementations +void a64_interleaved_s8s32_mmla_12x8(const int8_t *, const int8_t *, int32_t *, int, int, int); + +class interleaved_s8s32_mmla_12x8 { +public: + typedef int8_t operand_type; + typedef int32_t result_type; + + typedef void (*kern_type)(const int8_t *, const int8_t *, int32_t *, int, int, int); + + /* Kernel blocking parameters */ + static unsigned int out_width() + { + return 12; + } + + static unsigned int out_height() + { + return 8; + } + + static unsigned int k_unroll() + { + return 8; + } + + // Use the standard fixed size transforms. + StdTransformsFixed<operand_type, result_type, 8, 12, 8> transforms = {}; + + kern_type kernel=a64_interleaved_s8s32_mmla_12x8; + + interleaved_s8s32_mmla_12x8(const CPUInfo *ci) + { + UNUSED(ci); + } +}; + +} // namespace arm_gemm + +#endif // __aarch64__ diff --git a/src/core/NEON/kernels/arm_gemm/kernels/a64_interleaved_s8s32_mmla_12x8/generic.cpp b/src/core/NEON/kernels/arm_gemm/kernels/a64_interleaved_s8s32_mmla_12x8/generic.cpp new file mode 100644 index 0000000000..49dbdb866e --- /dev/null +++ b/src/core/NEON/kernels/arm_gemm/kernels/a64_interleaved_s8s32_mmla_12x8/generic.cpp @@ -0,0 +1,393 @@ +/* + * Copyright (c) 2019 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifdef __aarch64__ + +#include <cstdint> +#include "../../asmlib.hpp" + +namespace arm_gemm { + +void a64_interleaved_s8s32_mmla_12x8(const int8_t *Apanel, const int8_t *Bpanel, int32_t *Cpanel, int ablocks, int bblocks, int K) { + const int8_t *a_ptr = Apanel; + int32_t *c_ptr = Cpanel; + + K /= 8; + const long loops_count = (K / 2) - 1; + const long tails_count = K % 2; + + for (int yb=0; yb<ablocks; yb++) { + const int8_t *a_ptr0 = a_ptr; + const int8_t *b_ptr = Bpanel; + + for (int xb=0; xb<bblocks; xb++) { + a_ptr = a_ptr0; + long loops = loops_count; + long tails = tails_count; + + __asm __volatile ( + "movi v8.4s, #0\n" + "ldr q0, [%[a_ptr]]\n" + "movi v9.4s, #0\n" + "ldr q4, [%[b_ptr]]\n" + "movi v10.4s, #0\n" + "ldr q1, [%[a_ptr], #0x10]\n" + "movi v11.4s, #0\n" + "ldr q5, [%[b_ptr], #0x10]\n" + "movi v12.4s, #0\n" + "ldr q2, [%[a_ptr], #0x20]\n" + "movi v13.4s, #0\n" + "ldr q6, [%[b_ptr], #0x20]\n" + "movi v14.4s, #0\n" + "ldr q3, [%[a_ptr], #0x30]\n" + "movi v15.4s, #0\n" + "ldr q7, [%[b_ptr], #0x30]\n" + "movi v16.4s, #0\n" + "add %[a_ptr], %[a_ptr], #0x40\n" + "movi v17.4s, #0\n" + "add %[b_ptr], %[b_ptr], #0x40\n" + "movi v18.4s, #0\n" + "movi v19.4s, #0\n" + "movi v20.4s, #0\n" + "movi v21.4s, #0\n" + "movi v22.4s, #0\n" + "movi v23.4s, #0\n" + "movi v24.4s, #0\n" + "movi v25.4s, #0\n" + "movi v26.4s, #0\n" + "movi v27.4s, #0\n" + "movi v28.4s, #0\n" + "movi v29.4s, #0\n" + "movi v30.4s, #0\n" + "movi v31.4s, #0\n" + "cbz %[loops], 1f\n" + "2:\n" + ".inst 0x4e84a408 // smmla v8.4s, v0.16b, v4.16b\n" + "subs %[loops], %[loops], #0x1\n" + ".inst 0x4e84a42e // smmla v14.4s, v1.16b, v4.16b\n" + ".inst 0x4e84a454 // smmla v20.4s, v2.16b, v4.16b\n" + ".inst 0x4e84a47a // smmla v26.4s, v3.16b, v4.16b\n" + "ldr q4, [%[b_ptr]]\n" + ".inst 0x4e85a409 // smmla v9.4s, v0.16b, v5.16b\n" + ".inst 0x4e85a42f // smmla v15.4s, v1.16b, v5.16b\n" + ".inst 0x4e85a455 // smmla v21.4s, v2.16b, v5.16b\n" + ".inst 0x4e85a47b // smmla v27.4s, v3.16b, v5.16b\n" + "ldr q5, [%[b_ptr], #0x10]\n" + ".inst 0x4e86a40a // smmla v10.4s, v0.16b, v6.16b\n" + ".inst 0x4e86a430 // smmla v16.4s, v1.16b, v6.16b\n" + ".inst 0x4e86a456 // smmla v22.4s, v2.16b, v6.16b\n" + ".inst 0x4e86a47c // smmla v28.4s, v3.16b, v6.16b\n" + "ldr q6, [%[b_ptr], #0x20]\n" + ".inst 0x4e87a40b // smmla v11.4s, v0.16b, v7.16b\n" + ".inst 0x4e87a431 // smmla v17.4s, v1.16b, v7.16b\n" + ".inst 0x4e87a457 // smmla v23.4s, v2.16b, v7.16b\n" + ".inst 0x4e87a47d // smmla v29.4s, v3.16b, v7.16b\n" + "ldr q7, [%[b_ptr], #0x30]\n" + ".inst 0x4e84a40c // smmla v12.4s, v0.16b, v4.16b\n" + ".inst 0x4e84a432 // smmla v18.4s, v1.16b, v4.16b\n" + ".inst 0x4e84a458 // smmla v24.4s, v2.16b, v4.16b\n" + ".inst 0x4e84a47e // smmla v30.4s, v3.16b, v4.16b\n" + "ldr q4, [%[b_ptr], #0x40]\n" + ".inst 0x4e85a40d // smmla v13.4s, v0.16b, v5.16b\n" + "ldr q0, [%[a_ptr]]\n" + ".inst 0x4e85a433 // smmla v19.4s, v1.16b, v5.16b\n" + "ldr q1, [%[a_ptr], #0x10]\n" + ".inst 0x4e85a459 // smmla v25.4s, v2.16b, v5.16b\n" + "ldr q2, [%[a_ptr], #0x20]\n" + ".inst 0x4e85a47f // smmla v31.4s, v3.16b, v5.16b\n" + "ldr q5, [%[b_ptr], #0x50]\n" + ".inst 0x4e86a408 // smmla v8.4s, v0.16b, v6.16b\n" + "ldr q3, [%[a_ptr], #0x30]\n" + ".inst 0x4e86a42e // smmla v14.4s, v1.16b, v6.16b\n" + "add %[a_ptr], %[a_ptr], #0x80\n" + ".inst 0x4e86a454 // smmla v20.4s, v2.16b, v6.16b\n" + "add %[b_ptr], %[b_ptr], #0xc0\n" + ".inst 0x4e86a47a // smmla v26.4s, v3.16b, v6.16b\n" + "ldr q6, [%[b_ptr], #-0x60]\n" + ".inst 0x4e87a409 // smmla v9.4s, v0.16b, v7.16b\n" + ".inst 0x4e87a42f // smmla v15.4s, v1.16b, v7.16b\n" + ".inst 0x4e87a455 // smmla v21.4s, v2.16b, v7.16b\n" + ".inst 0x4e87a47b // smmla v27.4s, v3.16b, v7.16b\n" + "ldr q7, [%[b_ptr], #-0x50]\n" + ".inst 0x4e84a40a // smmla v10.4s, v0.16b, v4.16b\n" + ".inst 0x4e84a430 // smmla v16.4s, v1.16b, v4.16b\n" + ".inst 0x4e84a456 // smmla v22.4s, v2.16b, v4.16b\n" + ".inst 0x4e84a47c // smmla v28.4s, v3.16b, v4.16b\n" + "ldr q4, [%[b_ptr], #-0x40]\n" + ".inst 0x4e85a40b // smmla v11.4s, v0.16b, v5.16b\n" + ".inst 0x4e85a431 // smmla v17.4s, v1.16b, v5.16b\n" + ".inst 0x4e85a457 // smmla v23.4s, v2.16b, v5.16b\n" + ".inst 0x4e85a47d // smmla v29.4s, v3.16b, v5.16b\n" + "ldr q5, [%[b_ptr], #-0x30]\n" + ".inst 0x4e86a40c // smmla v12.4s, v0.16b, v6.16b\n" + ".inst 0x4e86a432 // smmla v18.4s, v1.16b, v6.16b\n" + ".inst 0x4e86a458 // smmla v24.4s, v2.16b, v6.16b\n" + ".inst 0x4e86a47e // smmla v30.4s, v3.16b, v6.16b\n" + "ldr q6, [%[b_ptr], #-0x20]\n" + ".inst 0x4e87a40d // smmla v13.4s, v0.16b, v7.16b\n" + "ldr q0, [%[a_ptr], #-0x40]\n" + ".inst 0x4e87a433 // smmla v19.4s, v1.16b, v7.16b\n" + "ldr q1, [%[a_ptr], #-0x30]\n" + ".inst 0x4e87a459 // smmla v25.4s, v2.16b, v7.16b\n" + "ldr q2, [%[a_ptr], #-0x20]\n" + ".inst 0x4e87a47f // smmla v31.4s, v3.16b, v7.16b\n" + "ldr q7, [%[b_ptr], #-0x10]\n" + "ldr q3, [%[a_ptr], #-0x10]\n" + "b.ne 2b\n" + "1:\n" + "cbz %[tails], 3f\n" + ".inst 0x4e84a408 // smmla v8.4s, v0.16b, v4.16b\n" + ".inst 0x4e84a42e // smmla v14.4s, v1.16b, v4.16b\n" + ".inst 0x4e84a454 // smmla v20.4s, v2.16b, v4.16b\n" + ".inst 0x4e84a47a // smmla v26.4s, v3.16b, v4.16b\n" + "ldr q4, [%[b_ptr]]\n" + ".inst 0x4e85a409 // smmla v9.4s, v0.16b, v5.16b\n" + ".inst 0x4e85a42f // smmla v15.4s, v1.16b, v5.16b\n" + ".inst 0x4e85a455 // smmla v21.4s, v2.16b, v5.16b\n" + ".inst 0x4e85a47b // smmla v27.4s, v3.16b, v5.16b\n" + "ldr q5, [%[b_ptr], #0x10]\n" + ".inst 0x4e86a40a // smmla v10.4s, v0.16b, v6.16b\n" + ".inst 0x4e86a430 // smmla v16.4s, v1.16b, v6.16b\n" + ".inst 0x4e86a456 // smmla v22.4s, v2.16b, v6.16b\n" + ".inst 0x4e86a47c // smmla v28.4s, v3.16b, v6.16b\n" + "ldr q6, [%[b_ptr], #0x20]\n" + ".inst 0x4e87a40b // smmla v11.4s, v0.16b, v7.16b\n" + ".inst 0x4e87a431 // smmla v17.4s, v1.16b, v7.16b\n" + ".inst 0x4e87a457 // smmla v23.4s, v2.16b, v7.16b\n" + ".inst 0x4e87a47d // smmla v29.4s, v3.16b, v7.16b\n" + "ldr q7, [%[b_ptr], #0x30]\n" + ".inst 0x4e84a40c // smmla v12.4s, v0.16b, v4.16b\n" + ".inst 0x4e84a432 // smmla v18.4s, v1.16b, v4.16b\n" + ".inst 0x4e84a458 // smmla v24.4s, v2.16b, v4.16b\n" + ".inst 0x4e84a47e // smmla v30.4s, v3.16b, v4.16b\n" + "ldr q4, [%[b_ptr], #0x40]\n" + ".inst 0x4e85a40d // smmla v13.4s, v0.16b, v5.16b\n" + "ldr q0, [%[a_ptr]]\n" + ".inst 0x4e85a433 // smmla v19.4s, v1.16b, v5.16b\n" + "ldr q1, [%[a_ptr], #0x10]\n" + ".inst 0x4e85a459 // smmla v25.4s, v2.16b, v5.16b\n" + "ldr q2, [%[a_ptr], #0x20]\n" + ".inst 0x4e85a47f // smmla v31.4s, v3.16b, v5.16b\n" + "ldr q5, [%[b_ptr], #0x50]\n" + ".inst 0x4e86a408 // smmla v8.4s, v0.16b, v6.16b\n" + "ldr q3, [%[a_ptr], #0x30]\n" + ".inst 0x4e86a42e // smmla v14.4s, v1.16b, v6.16b\n" + "add %[a_ptr], %[a_ptr], #0x80\n" + ".inst 0x4e86a454 // smmla v20.4s, v2.16b, v6.16b\n" + "add %[b_ptr], %[b_ptr], #0xe0\n" + ".inst 0x4e86a47a // smmla v26.4s, v3.16b, v6.16b\n" + "ldr q6, [%[b_ptr], #-0x80]\n" + ".inst 0x4e87a409 // smmla v9.4s, v0.16b, v7.16b\n" + ".inst 0x4e87a42f // smmla v15.4s, v1.16b, v7.16b\n" + ".inst 0x4e87a455 // smmla v21.4s, v2.16b, v7.16b\n" + ".inst 0x4e87a47b // smmla v27.4s, v3.16b, v7.16b\n" + "ldr q7, [%[b_ptr], #-0x70]\n" + ".inst 0x4e84a40a // smmla v10.4s, v0.16b, v4.16b\n" + ".inst 0x4e84a430 // smmla v16.4s, v1.16b, v4.16b\n" + ".inst 0x4e84a456 // smmla v22.4s, v2.16b, v4.16b\n" + ".inst 0x4e84a47c // smmla v28.4s, v3.16b, v4.16b\n" + "ldr q4, [%[b_ptr], #-0x60]\n" + ".inst 0x4e85a40b // smmla v11.4s, v0.16b, v5.16b\n" + ".inst 0x4e85a431 // smmla v17.4s, v1.16b, v5.16b\n" + ".inst 0x4e85a457 // smmla v23.4s, v2.16b, v5.16b\n" + ".inst 0x4e85a47d // smmla v29.4s, v3.16b, v5.16b\n" + "ldr q5, [%[b_ptr], #-0x50]\n" + ".inst 0x4e86a40c // smmla v12.4s, v0.16b, v6.16b\n" + ".inst 0x4e86a432 // smmla v18.4s, v1.16b, v6.16b\n" + ".inst 0x4e86a458 // smmla v24.4s, v2.16b, v6.16b\n" + ".inst 0x4e86a47e // smmla v30.4s, v3.16b, v6.16b\n" + "ldr q6, [%[b_ptr], #-0x40]\n" + ".inst 0x4e87a40d // smmla v13.4s, v0.16b, v7.16b\n" + "ldr q0, [%[a_ptr], #-0x40]\n" + ".inst 0x4e87a433 // smmla v19.4s, v1.16b, v7.16b\n" + "ldr q1, [%[a_ptr], #-0x30]\n" + ".inst 0x4e87a459 // smmla v25.4s, v2.16b, v7.16b\n" + "ldr q2, [%[a_ptr], #-0x20]\n" + ".inst 0x4e87a47f // smmla v31.4s, v3.16b, v7.16b\n" + "ldr q7, [%[b_ptr], #-0x30]\n" + ".inst 0x4e84a408 // smmla v8.4s, v0.16b, v4.16b\n" + "ldr q3, [%[a_ptr], #-0x10]\n" + ".inst 0x4e84a42e // smmla v14.4s, v1.16b, v4.16b\n" + ".inst 0x4e84a454 // smmla v20.4s, v2.16b, v4.16b\n" + ".inst 0x4e85a409 // smmla v9.4s, v0.16b, v5.16b\n" + ".inst 0x4e84a47a // smmla v26.4s, v3.16b, v4.16b\n" + "ldr q4, [%[b_ptr], #-0x20]\n" + ".inst 0x4e85a42f // smmla v15.4s, v1.16b, v5.16b\n" + ".inst 0x4e85a455 // smmla v21.4s, v2.16b, v5.16b\n" + ".inst 0x4e85a47b // smmla v27.4s, v3.16b, v5.16b\n" + "ldr q5, [%[b_ptr], #-0x10]\n" + ".inst 0x4e86a40a // smmla v10.4s, v0.16b, v6.16b\n" + ".inst 0x4e86a430 // smmla v16.4s, v1.16b, v6.16b\n" + ".inst 0x4e86a456 // smmla v22.4s, v2.16b, v6.16b\n" + ".inst 0x4e86a47c // smmla v28.4s, v3.16b, v6.16b\n" + "uzp1 v6.2d, v14.2d, v15.2d\n" + ".inst 0x4e87a40b // smmla v11.4s, v0.16b, v7.16b\n" + ".inst 0x4e87a431 // smmla v17.4s, v1.16b, v7.16b\n" + ".inst 0x4e87a457 // smmla v23.4s, v2.16b, v7.16b\n" + ".inst 0x4e87a47d // smmla v29.4s, v3.16b, v7.16b\n" + ".inst 0x4e84a40c // smmla v12.4s, v0.16b, v4.16b\n" + "uzp1 v7.2d, v16.2d, v17.2d\n" + ".inst 0x4e84a432 // smmla v18.4s, v1.16b, v4.16b\n" + ".inst 0x4e84a458 // smmla v24.4s, v2.16b, v4.16b\n" + ".inst 0x4e84a47e // smmla v30.4s, v3.16b, v4.16b\n" + "uzp2 v4.2d, v10.2d, v11.2d\n" + ".inst 0x4e85a40d // smmla v13.4s, v0.16b, v5.16b\n" + "uzp1 v0.2d, v8.2d, v9.2d\n" + ".inst 0x4e85a433 // smmla v19.4s, v1.16b, v5.16b\n" + "uzp1 v1.2d, v10.2d, v11.2d\n" + ".inst 0x4e85a459 // smmla v25.4s, v2.16b, v5.16b\n" + "str q0, [%[c_ptr]]\n" + "uzp1 v2.2d, v12.2d, v13.2d\n" + "uzp1 v0.2d, v18.2d, v19.2d\n" + ".inst 0x4e85a47f // smmla v31.4s, v3.16b, v5.16b\n" + "str q1, [%[c_ptr], #0x10]\n" + "uzp2 v3.2d, v8.2d, v9.2d\n" + "uzp2 v5.2d, v12.2d, v13.2d\n" + "uzp2 v1.2d, v14.2d, v15.2d\n" + "str q2, [%[c_ptr], #0x20]\n" + "b 4f\n" + "3:\n" + ".inst 0x4e84a408 // smmla v8.4s, v0.16b, v4.16b\n" + "add %[a_ptr], %[a_ptr], #0x40\n" + ".inst 0x4e84a42e // smmla v14.4s, v1.16b, v4.16b\n" + "add %[b_ptr], %[b_ptr], #0x80\n" + ".inst 0x4e84a454 // smmla v20.4s, v2.16b, v4.16b\n" + ".inst 0x4e84a47a // smmla v26.4s, v3.16b, v4.16b\n" + "ldr q4, [%[b_ptr], #-0x80]\n" + ".inst 0x4e85a409 // smmla v9.4s, v0.16b, v5.16b\n" + ".inst 0x4e85a42f // smmla v15.4s, v1.16b, v5.16b\n" + ".inst 0x4e85a455 // smmla v21.4s, v2.16b, v5.16b\n" + ".inst 0x4e85a47b // smmla v27.4s, v3.16b, v5.16b\n" + "ldr q5, [%[b_ptr], #-0x70]\n" + ".inst 0x4e86a40a // smmla v10.4s, v0.16b, v6.16b\n" + ".inst 0x4e86a430 // smmla v16.4s, v1.16b, v6.16b\n" + ".inst 0x4e86a456 // smmla v22.4s, v2.16b, v6.16b\n" + ".inst 0x4e86a47c // smmla v28.4s, v3.16b, v6.16b\n" + "ldr q6, [%[b_ptr], #-0x60]\n" + ".inst 0x4e87a40b // smmla v11.4s, v0.16b, v7.16b\n" + ".inst 0x4e87a431 // smmla v17.4s, v1.16b, v7.16b\n" + ".inst 0x4e87a457 // smmla v23.4s, v2.16b, v7.16b\n" + ".inst 0x4e87a47d // smmla v29.4s, v3.16b, v7.16b\n" + "ldr q7, [%[b_ptr], #-0x50]\n" + ".inst 0x4e84a40c // smmla v12.4s, v0.16b, v4.16b\n" + ".inst 0x4e84a432 // smmla v18.4s, v1.16b, v4.16b\n" + ".inst 0x4e84a458 // smmla v24.4s, v2.16b, v4.16b\n" + ".inst 0x4e84a47e // smmla v30.4s, v3.16b, v4.16b\n" + "ldr q4, [%[b_ptr], #-0x40]\n" + ".inst 0x4e85a40d // smmla v13.4s, v0.16b, v5.16b\n" + "ldr q0, [%[a_ptr], #-0x40]\n" + ".inst 0x4e85a433 // smmla v19.4s, v1.16b, v5.16b\n" + "ldr q1, [%[a_ptr], #-0x30]\n" + ".inst 0x4e85a459 // smmla v25.4s, v2.16b, v5.16b\n" + "ldr q2, [%[a_ptr], #-0x20]\n" + ".inst 0x4e85a47f // smmla v31.4s, v3.16b, v5.16b\n" + "ldr q5, [%[b_ptr], #-0x30]\n" + ".inst 0x4e86a408 // smmla v8.4s, v0.16b, v6.16b\n" + "ldr q3, [%[a_ptr], #-0x10]\n" + ".inst 0x4e86a42e // smmla v14.4s, v1.16b, v6.16b\n" + ".inst 0x4e86a454 // smmla v20.4s, v2.16b, v6.16b\n" + ".inst 0x4e87a409 // smmla v9.4s, v0.16b, v7.16b\n" + ".inst 0x4e86a47a // smmla v26.4s, v3.16b, v6.16b\n" + "ldr q6, [%[b_ptr], #-0x20]\n" + ".inst 0x4e87a42f // smmla v15.4s, v1.16b, v7.16b\n" + ".inst 0x4e87a455 // smmla v21.4s, v2.16b, v7.16b\n" + ".inst 0x4e87a47b // smmla v27.4s, v3.16b, v7.16b\n" + "ldr q7, [%[b_ptr], #-0x10]\n" + ".inst 0x4e84a40a // smmla v10.4s, v0.16b, v4.16b\n" + ".inst 0x4e84a430 // smmla v16.4s, v1.16b, v4.16b\n" + ".inst 0x4e84a456 // smmla v22.4s, v2.16b, v4.16b\n" + ".inst 0x4e84a47c // smmla v28.4s, v3.16b, v4.16b\n" + ".inst 0x4e85a40b // smmla v11.4s, v0.16b, v5.16b\n" + ".inst 0x4e85a431 // smmla v17.4s, v1.16b, v5.16b\n" + ".inst 0x4e85a457 // smmla v23.4s, v2.16b, v5.16b\n" + ".inst 0x4e85a47d // smmla v29.4s, v3.16b, v5.16b\n" + "uzp2 v4.2d, v10.2d, v11.2d\n" + ".inst 0x4e86a40c // smmla v12.4s, v0.16b, v6.16b\n" + ".inst 0x4e86a432 // smmla v18.4s, v1.16b, v6.16b\n" + ".inst 0x4e86a458 // smmla v24.4s, v2.16b, v6.16b\n" + ".inst 0x4e86a47e // smmla v30.4s, v3.16b, v6.16b\n" + "uzp1 v6.2d, v14.2d, v15.2d\n" + ".inst 0x4e87a40d // smmla v13.4s, v0.16b, v7.16b\n" + "uzp1 v0.2d, v8.2d, v9.2d\n" + ".inst 0x4e87a433 // smmla v19.4s, v1.16b, v7.16b\n" + "uzp1 v1.2d, v10.2d, v11.2d\n" + "uzp2 v5.2d, v12.2d, v13.2d\n" + "str q0, [%[c_ptr]]\n" + ".inst 0x4e87a459 // smmla v25.4s, v2.16b, v7.16b\n" + "uzp1 v2.2d, v12.2d, v13.2d\n" + "uzp1 v0.2d, v18.2d, v19.2d\n" + "str q1, [%[c_ptr], #0x10]\n" + "uzp2 v1.2d, v14.2d, v15.2d\n" + ".inst 0x4e87a47f // smmla v31.4s, v3.16b, v7.16b\n" + "uzp2 v3.2d, v8.2d, v9.2d\n" + "str q2, [%[c_ptr], #0x20]\n" + "uzp1 v7.2d, v16.2d, v17.2d\n" + "4:\n" + "uzp2 v2.2d, v16.2d, v17.2d\n" + "str q3, [%[c_ptr], #0x30]\n" + "uzp2 v3.2d, v18.2d, v19.2d\n" + "str q4, [%[c_ptr], #0x40]\n" + "uzp1 v4.2d, v20.2d, v21.2d\n" + "str q5, [%[c_ptr], #0x50]\n" + "uzp1 v5.2d, v22.2d, v23.2d\n" + "str q6, [%[c_ptr], #0x60]\n" + "uzp1 v6.2d, v24.2d, v25.2d\n" + "str q7, [%[c_ptr], #0x70]\n" + "uzp2 v7.2d, v20.2d, v21.2d\n" + "str q0, [%[c_ptr], #0x80]\n" + "uzp2 v0.2d, v22.2d, v23.2d\n" + "str q1, [%[c_ptr], #0x90]\n" + "uzp2 v1.2d, v24.2d, v25.2d\n" + "str q2, [%[c_ptr], #0xa0]\n" + "uzp1 v2.2d, v26.2d, v27.2d\n" + "str q3, [%[c_ptr], #0xb0]\n" + "uzp1 v3.2d, v28.2d, v29.2d\n" + "str q4, [%[c_ptr], #0xc0]\n" + "uzp1 v4.2d, v30.2d, v31.2d\n" + "str q5, [%[c_ptr], #0xd0]\n" + "uzp2 v5.2d, v26.2d, v27.2d\n" + "str q6, [%[c_ptr], #0xe0]\n" + "uzp2 v6.2d, v28.2d, v29.2d\n" + "str q7, [%[c_ptr], #0xf0]\n" + "uzp2 v7.2d, v30.2d, v31.2d\n" + "str q0, [%[c_ptr], #0x100]\n" + "str q1, [%[c_ptr], #0x110]\n" + "str q2, [%[c_ptr], #0x120]\n" + "str q3, [%[c_ptr], #0x130]\n" + "str q4, [%[c_ptr], #0x140]\n" + "str q5, [%[c_ptr], #0x150]\n" + "str q6, [%[c_ptr], #0x160]\n" + "str q7, [%[c_ptr], #0x170]\n" + "add %[c_ptr], %[c_ptr], #0x180\n" + : [a_ptr] "+r" (a_ptr), [b_ptr] "+r" (b_ptr), [c_ptr] "+r" (c_ptr), + [loops] "+r" (loops), [tails] "+r" (tails) + : + : "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "cc", "memory" + ); + } + } +} + +} // namespace arm_gemm + +#endif // __aarch64__ diff --git a/src/core/NEON/kernels/arm_gemm/kernels/a64_interleaved_u8u32_mmla_12x8.hpp b/src/core/NEON/kernels/arm_gemm/kernels/a64_interleaved_u8u32_mmla_12x8.hpp new file mode 100644 index 0000000000..d66edd832a --- /dev/null +++ b/src/core/NEON/kernels/arm_gemm/kernels/a64_interleaved_u8u32_mmla_12x8.hpp @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2019 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#pragma once + +#ifdef __aarch64__ + +#include <cstdint> +#include "../std_transforms_fixed.hpp" + +namespace arm_gemm { + +// Actual kernel implementations +void a64_interleaved_u8u32_mmla_12x8(const uint8_t *, const uint8_t *, uint32_t *, int, int, int); + +class interleaved_u8u32_mmla_12x8 { +public: + typedef uint8_t operand_type; + typedef uint32_t result_type; + + typedef void (*kern_type)(const uint8_t *, const uint8_t *, uint32_t *, int, int, int); + + /* Kernel blocking parameters */ + static unsigned int out_width() + { + return 12; + } + + static unsigned int out_height() + { + return 8; + } + + static unsigned int k_unroll() + { + return 8; + } + + // Use the standard fixed size transforms. + StdTransformsFixed<operand_type, result_type, 8, 12, 8> transforms = {}; + + kern_type kernel=a64_interleaved_u8u32_mmla_12x8; + + interleaved_u8u32_mmla_12x8(const CPUInfo *ci) + { + UNUSED(ci); + } +}; + +} // namespace arm_gemm + +#endif // __aarch64__ diff --git a/src/core/NEON/kernels/arm_gemm/kernels/a64_interleaved_u8u32_mmla_12x8/generic.cpp b/src/core/NEON/kernels/arm_gemm/kernels/a64_interleaved_u8u32_mmla_12x8/generic.cpp new file mode 100644 index 0000000000..e182a425f4 --- /dev/null +++ b/src/core/NEON/kernels/arm_gemm/kernels/a64_interleaved_u8u32_mmla_12x8/generic.cpp @@ -0,0 +1,393 @@ +/* + * Copyright (c) 2019 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifdef __aarch64__ + +#include <cstdint> +#include "../../asmlib.hpp" + +namespace arm_gemm { + +void a64_interleaved_u8u32_mmla_12x8(const uint8_t *Apanel, const uint8_t *Bpanel, uint32_t *Cpanel, int ablocks, int bblocks, int K) { + const uint8_t *a_ptr = Apanel; + uint32_t *c_ptr = Cpanel; + + K /= 8; + const long loops_count = (K / 2) - 1; + const long tails_count = K % 2; + + for (int yb=0; yb<ablocks; yb++) { + const uint8_t *a_ptr0 = a_ptr; + const uint8_t *b_ptr = Bpanel; + + for (int xb=0; xb<bblocks; xb++) { + a_ptr = a_ptr0; + long loops = loops_count; + long tails = tails_count; + + __asm __volatile ( + "movi v8.4s, #0\n" + "ldr q0, [%[a_ptr]]\n" + "movi v9.4s, #0\n" + "ldr q4, [%[b_ptr]]\n" + "movi v10.4s, #0\n" + "ldr q1, [%[a_ptr], #0x10]\n" + "movi v11.4s, #0\n" + "ldr q5, [%[b_ptr], #0x10]\n" + "movi v12.4s, #0\n" + "ldr q2, [%[a_ptr], #0x20]\n" + "movi v13.4s, #0\n" + "ldr q6, [%[b_ptr], #0x20]\n" + "movi v14.4s, #0\n" + "ldr q3, [%[a_ptr], #0x30]\n" + "movi v15.4s, #0\n" + "ldr q7, [%[b_ptr], #0x30]\n" + "movi v16.4s, #0\n" + "add %[a_ptr], %[a_ptr], #0x40\n" + "movi v17.4s, #0\n" + "add %[b_ptr], %[b_ptr], #0x40\n" + "movi v18.4s, #0\n" + "movi v19.4s, #0\n" + "movi v20.4s, #0\n" + "movi v21.4s, #0\n" + "movi v22.4s, #0\n" + "movi v23.4s, #0\n" + "movi v24.4s, #0\n" + "movi v25.4s, #0\n" + "movi v26.4s, #0\n" + "movi v27.4s, #0\n" + "movi v28.4s, #0\n" + "movi v29.4s, #0\n" + "movi v30.4s, #0\n" + "movi v31.4s, #0\n" + "cbz %[loops], 1f\n" + "2:\n" + ".inst 0x6e84a408 // ummla v8.4s, v0.16b, v4.16b\n" + "subs %[loops], %[loops], #0x1\n" + ".inst 0x6e84a42e // ummla v14.4s, v1.16b, v4.16b\n" + ".inst 0x6e84a454 // ummla v20.4s, v2.16b, v4.16b\n" + ".inst 0x6e84a47a // ummla v26.4s, v3.16b, v4.16b\n" + "ldr q4, [%[b_ptr]]\n" + ".inst 0x6e85a409 // ummla v9.4s, v0.16b, v5.16b\n" + ".inst 0x6e85a42f // ummla v15.4s, v1.16b, v5.16b\n" + ".inst 0x6e85a455 // ummla v21.4s, v2.16b, v5.16b\n" + ".inst 0x6e85a47b // ummla v27.4s, v3.16b, v5.16b\n" + "ldr q5, [%[b_ptr], #0x10]\n" + ".inst 0x6e86a40a // ummla v10.4s, v0.16b, v6.16b\n" + ".inst 0x6e86a430 // ummla v16.4s, v1.16b, v6.16b\n" + ".inst 0x6e86a456 // ummla v22.4s, v2.16b, v6.16b\n" + ".inst 0x6e86a47c // ummla v28.4s, v3.16b, v6.16b\n" + "ldr q6, [%[b_ptr], #0x20]\n" + ".inst 0x6e87a40b // ummla v11.4s, v0.16b, v7.16b\n" + ".inst 0x6e87a431 // ummla v17.4s, v1.16b, v7.16b\n" + ".inst 0x6e87a457 // ummla v23.4s, v2.16b, v7.16b\n" + ".inst 0x6e87a47d // ummla v29.4s, v3.16b, v7.16b\n" + "ldr q7, [%[b_ptr], #0x30]\n" + ".inst 0x6e84a40c // ummla v12.4s, v0.16b, v4.16b\n" + ".inst 0x6e84a432 // ummla v18.4s, v1.16b, v4.16b\n" + ".inst 0x6e84a458 // ummla v24.4s, v2.16b, v4.16b\n" + ".inst 0x6e84a47e // ummla v30.4s, v3.16b, v4.16b\n" + "ldr q4, [%[b_ptr], #0x40]\n" + ".inst 0x6e85a40d // ummla v13.4s, v0.16b, v5.16b\n" + "ldr q0, [%[a_ptr]]\n" + ".inst 0x6e85a433 // ummla v19.4s, v1.16b, v5.16b\n" + "ldr q1, [%[a_ptr], #0x10]\n" + ".inst 0x6e85a459 // ummla v25.4s, v2.16b, v5.16b\n" + "ldr q2, [%[a_ptr], #0x20]\n" + ".inst 0x6e85a47f // ummla v31.4s, v3.16b, v5.16b\n" + "ldr q5, [%[b_ptr], #0x50]\n" + ".inst 0x6e86a408 // ummla v8.4s, v0.16b, v6.16b\n" + "ldr q3, [%[a_ptr], #0x30]\n" + ".inst 0x6e86a42e // ummla v14.4s, v1.16b, v6.16b\n" + "add %[a_ptr], %[a_ptr], #0x80\n" + ".inst 0x6e86a454 // ummla v20.4s, v2.16b, v6.16b\n" + "add %[b_ptr], %[b_ptr], #0xc0\n" + ".inst 0x6e86a47a // ummla v26.4s, v3.16b, v6.16b\n" + "ldr q6, [%[b_ptr], #-0x60]\n" + ".inst 0x6e87a409 // ummla v9.4s, v0.16b, v7.16b\n" + ".inst 0x6e87a42f // ummla v15.4s, v1.16b, v7.16b\n" + ".inst 0x6e87a455 // ummla v21.4s, v2.16b, v7.16b\n" + ".inst 0x6e87a47b // ummla v27.4s, v3.16b, v7.16b\n" + "ldr q7, [%[b_ptr], #-0x50]\n" + ".inst 0x6e84a40a // ummla v10.4s, v0.16b, v4.16b\n" + ".inst 0x6e84a430 // ummla v16.4s, v1.16b, v4.16b\n" + ".inst 0x6e84a456 // ummla v22.4s, v2.16b, v4.16b\n" + ".inst 0x6e84a47c // ummla v28.4s, v3.16b, v4.16b\n" + "ldr q4, [%[b_ptr], #-0x40]\n" + ".inst 0x6e85a40b // ummla v11.4s, v0.16b, v5.16b\n" + ".inst 0x6e85a431 // ummla v17.4s, v1.16b, v5.16b\n" + ".inst 0x6e85a457 // ummla v23.4s, v2.16b, v5.16b\n" + ".inst 0x6e85a47d // ummla v29.4s, v3.16b, v5.16b\n" + "ldr q5, [%[b_ptr], #-0x30]\n" + ".inst 0x6e86a40c // ummla v12.4s, v0.16b, v6.16b\n" + ".inst 0x6e86a432 // ummla v18.4s, v1.16b, v6.16b\n" + ".inst 0x6e86a458 // ummla v24.4s, v2.16b, v6.16b\n" + ".inst 0x6e86a47e // ummla v30.4s, v3.16b, v6.16b\n" + "ldr q6, [%[b_ptr], #-0x20]\n" + ".inst 0x6e87a40d // ummla v13.4s, v0.16b, v7.16b\n" + "ldr q0, [%[a_ptr], #-0x40]\n" + ".inst 0x6e87a433 // ummla v19.4s, v1.16b, v7.16b\n" + "ldr q1, [%[a_ptr], #-0x30]\n" + ".inst 0x6e87a459 // ummla v25.4s, v2.16b, v7.16b\n" + "ldr q2, [%[a_ptr], #-0x20]\n" + ".inst 0x6e87a47f // ummla v31.4s, v3.16b, v7.16b\n" + "ldr q7, [%[b_ptr], #-0x10]\n" + "ldr q3, [%[a_ptr], #-0x10]\n" + "b.ne 2b\n" + "1:\n" + "cbz %[tails], 3f\n" + ".inst 0x6e84a408 // ummla v8.4s, v0.16b, v4.16b\n" + ".inst 0x6e84a42e // ummla v14.4s, v1.16b, v4.16b\n" + ".inst 0x6e84a454 // ummla v20.4s, v2.16b, v4.16b\n" + ".inst 0x6e84a47a // ummla v26.4s, v3.16b, v4.16b\n" + "ldr q4, [%[b_ptr]]\n" + ".inst 0x6e85a409 // ummla v9.4s, v0.16b, v5.16b\n" + ".inst 0x6e85a42f // ummla v15.4s, v1.16b, v5.16b\n" + ".inst 0x6e85a455 // ummla v21.4s, v2.16b, v5.16b\n" + ".inst 0x6e85a47b // ummla v27.4s, v3.16b, v5.16b\n" + "ldr q5, [%[b_ptr], #0x10]\n" + ".inst 0x6e86a40a // ummla v10.4s, v0.16b, v6.16b\n" + ".inst 0x6e86a430 // ummla v16.4s, v1.16b, v6.16b\n" + ".inst 0x6e86a456 // ummla v22.4s, v2.16b, v6.16b\n" + ".inst 0x6e86a47c // ummla v28.4s, v3.16b, v6.16b\n" + "ldr q6, [%[b_ptr], #0x20]\n" + ".inst 0x6e87a40b // ummla v11.4s, v0.16b, v7.16b\n" + ".inst 0x6e87a431 // ummla v17.4s, v1.16b, v7.16b\n" + ".inst 0x6e87a457 // ummla v23.4s, v2.16b, v7.16b\n" + ".inst 0x6e87a47d // ummla v29.4s, v3.16b, v7.16b\n" + "ldr q7, [%[b_ptr], #0x30]\n" + ".inst 0x6e84a40c // ummla v12.4s, v0.16b, v4.16b\n" + ".inst 0x6e84a432 // ummla v18.4s, v1.16b, v4.16b\n" + ".inst 0x6e84a458 // ummla v24.4s, v2.16b, v4.16b\n" + ".inst 0x6e84a47e // ummla v30.4s, v3.16b, v4.16b\n" + "ldr q4, [%[b_ptr], #0x40]\n" + ".inst 0x6e85a40d // ummla v13.4s, v0.16b, v5.16b\n" + "ldr q0, [%[a_ptr]]\n" + ".inst 0x6e85a433 // ummla v19.4s, v1.16b, v5.16b\n" + "ldr q1, [%[a_ptr], #0x10]\n" + ".inst 0x6e85a459 // ummla v25.4s, v2.16b, v5.16b\n" + "ldr q2, [%[a_ptr], #0x20]\n" + ".inst 0x6e85a47f // ummla v31.4s, v3.16b, v5.16b\n" + "ldr q5, [%[b_ptr], #0x50]\n" + ".inst 0x6e86a408 // ummla v8.4s, v0.16b, v6.16b\n" + "ldr q3, [%[a_ptr], #0x30]\n" + ".inst 0x6e86a42e // ummla v14.4s, v1.16b, v6.16b\n" + "add %[a_ptr], %[a_ptr], #0x80\n" + ".inst 0x6e86a454 // ummla v20.4s, v2.16b, v6.16b\n" + "add %[b_ptr], %[b_ptr], #0xe0\n" + ".inst 0x6e86a47a // ummla v26.4s, v3.16b, v6.16b\n" + "ldr q6, [%[b_ptr], #-0x80]\n" + ".inst 0x6e87a409 // ummla v9.4s, v0.16b, v7.16b\n" + ".inst 0x6e87a42f // ummla v15.4s, v1.16b, v7.16b\n" + ".inst 0x6e87a455 // ummla v21.4s, v2.16b, v7.16b\n" + ".inst 0x6e87a47b // ummla v27.4s, v3.16b, v7.16b\n" + "ldr q7, [%[b_ptr], #-0x70]\n" + ".inst 0x6e84a40a // ummla v10.4s, v0.16b, v4.16b\n" + ".inst 0x6e84a430 // ummla v16.4s, v1.16b, v4.16b\n" + ".inst 0x6e84a456 // ummla v22.4s, v2.16b, v4.16b\n" + ".inst 0x6e84a47c // ummla v28.4s, v3.16b, v4.16b\n" + "ldr q4, [%[b_ptr], #-0x60]\n" + ".inst 0x6e85a40b // ummla v11.4s, v0.16b, v5.16b\n" + ".inst 0x6e85a431 // ummla v17.4s, v1.16b, v5.16b\n" + ".inst 0x6e85a457 // ummla v23.4s, v2.16b, v5.16b\n" + ".inst 0x6e85a47d // ummla v29.4s, v3.16b, v5.16b\n" + "ldr q5, [%[b_ptr], #-0x50]\n" + ".inst 0x6e86a40c // ummla v12.4s, v0.16b, v6.16b\n" + ".inst 0x6e86a432 // ummla v18.4s, v1.16b, v6.16b\n" + ".inst 0x6e86a458 // ummla v24.4s, v2.16b, v6.16b\n" + ".inst 0x6e86a47e // ummla v30.4s, v3.16b, v6.16b\n" + "ldr q6, [%[b_ptr], #-0x40]\n" + ".inst 0x6e87a40d // ummla v13.4s, v0.16b, v7.16b\n" + "ldr q0, [%[a_ptr], #-0x40]\n" + ".inst 0x6e87a433 // ummla v19.4s, v1.16b, v7.16b\n" + "ldr q1, [%[a_ptr], #-0x30]\n" + ".inst 0x6e87a459 // ummla v25.4s, v2.16b, v7.16b\n" + "ldr q2, [%[a_ptr], #-0x20]\n" + ".inst 0x6e87a47f // ummla v31.4s, v3.16b, v7.16b\n" + "ldr q7, [%[b_ptr], #-0x30]\n" + ".inst 0x6e84a408 // ummla v8.4s, v0.16b, v4.16b\n" + "ldr q3, [%[a_ptr], #-0x10]\n" + ".inst 0x6e84a42e // ummla v14.4s, v1.16b, v4.16b\n" + ".inst 0x6e84a454 // ummla v20.4s, v2.16b, v4.16b\n" + ".inst 0x6e85a409 // ummla v9.4s, v0.16b, v5.16b\n" + ".inst 0x6e84a47a // ummla v26.4s, v3.16b, v4.16b\n" + "ldr q4, [%[b_ptr], #-0x20]\n" + ".inst 0x6e85a42f // ummla v15.4s, v1.16b, v5.16b\n" + ".inst 0x6e85a455 // ummla v21.4s, v2.16b, v5.16b\n" + ".inst 0x6e85a47b // ummla v27.4s, v3.16b, v5.16b\n" + "ldr q5, [%[b_ptr], #-0x10]\n" + ".inst 0x6e86a40a // ummla v10.4s, v0.16b, v6.16b\n" + ".inst 0x6e86a430 // ummla v16.4s, v1.16b, v6.16b\n" + ".inst 0x6e86a456 // ummla v22.4s, v2.16b, v6.16b\n" + ".inst 0x6e86a47c // ummla v28.4s, v3.16b, v6.16b\n" + "uzp1 v6.2d, v14.2d, v15.2d\n" + ".inst 0x6e87a40b // ummla v11.4s, v0.16b, v7.16b\n" + ".inst 0x6e87a431 // ummla v17.4s, v1.16b, v7.16b\n" + ".inst 0x6e87a457 // ummla v23.4s, v2.16b, v7.16b\n" + ".inst 0x6e87a47d // ummla v29.4s, v3.16b, v7.16b\n" + ".inst 0x6e84a40c // ummla v12.4s, v0.16b, v4.16b\n" + "uzp1 v7.2d, v16.2d, v17.2d\n" + ".inst 0x6e84a432 // ummla v18.4s, v1.16b, v4.16b\n" + ".inst 0x6e84a458 // ummla v24.4s, v2.16b, v4.16b\n" + ".inst 0x6e84a47e // ummla v30.4s, v3.16b, v4.16b\n" + "uzp2 v4.2d, v10.2d, v11.2d\n" + ".inst 0x6e85a40d // ummla v13.4s, v0.16b, v5.16b\n" + "uzp1 v0.2d, v8.2d, v9.2d\n" + ".inst 0x6e85a433 // ummla v19.4s, v1.16b, v5.16b\n" + "uzp1 v1.2d, v10.2d, v11.2d\n" + ".inst 0x6e85a459 // ummla v25.4s, v2.16b, v5.16b\n" + "str q0, [%[c_ptr]]\n" + "uzp1 v2.2d, v12.2d, v13.2d\n" + "uzp1 v0.2d, v18.2d, v19.2d\n" + ".inst 0x6e85a47f // ummla v31.4s, v3.16b, v5.16b\n" + "str q1, [%[c_ptr], #0x10]\n" + "uzp2 v3.2d, v8.2d, v9.2d\n" + "uzp2 v5.2d, v12.2d, v13.2d\n" + "uzp2 v1.2d, v14.2d, v15.2d\n" + "str q2, [%[c_ptr], #0x20]\n" + "b 4f\n" + "3:\n" + ".inst 0x6e84a408 // ummla v8.4s, v0.16b, v4.16b\n" + "add %[a_ptr], %[a_ptr], #0x40\n" + ".inst 0x6e84a42e // ummla v14.4s, v1.16b, v4.16b\n" + "add %[b_ptr], %[b_ptr], #0x80\n" + ".inst 0x6e84a454 // ummla v20.4s, v2.16b, v4.16b\n" + ".inst 0x6e84a47a // ummla v26.4s, v3.16b, v4.16b\n" + "ldr q4, [%[b_ptr], #-0x80]\n" + ".inst 0x6e85a409 // ummla v9.4s, v0.16b, v5.16b\n" + ".inst 0x6e85a42f // ummla v15.4s, v1.16b, v5.16b\n" + ".inst 0x6e85a455 // ummla v21.4s, v2.16b, v5.16b\n" + ".inst 0x6e85a47b // ummla v27.4s, v3.16b, v5.16b\n" + "ldr q5, [%[b_ptr], #-0x70]\n" + ".inst 0x6e86a40a // ummla v10.4s, v0.16b, v6.16b\n" + ".inst 0x6e86a430 // ummla v16.4s, v1.16b, v6.16b\n" + ".inst 0x6e86a456 // ummla v22.4s, v2.16b, v6.16b\n" + ".inst 0x6e86a47c // ummla v28.4s, v3.16b, v6.16b\n" + "ldr q6, [%[b_ptr], #-0x60]\n" + ".inst 0x6e87a40b // ummla v11.4s, v0.16b, v7.16b\n" + ".inst 0x6e87a431 // ummla v17.4s, v1.16b, v7.16b\n" + ".inst 0x6e87a457 // ummla v23.4s, v2.16b, v7.16b\n" + ".inst 0x6e87a47d // ummla v29.4s, v3.16b, v7.16b\n" + "ldr q7, [%[b_ptr], #-0x50]\n" + ".inst 0x6e84a40c // ummla v12.4s, v0.16b, v4.16b\n" + ".inst 0x6e84a432 // ummla v18.4s, v1.16b, v4.16b\n" + ".inst 0x6e84a458 // ummla v24.4s, v2.16b, v4.16b\n" + ".inst 0x6e84a47e // ummla v30.4s, v3.16b, v4.16b\n" + "ldr q4, [%[b_ptr], #-0x40]\n" + ".inst 0x6e85a40d // ummla v13.4s, v0.16b, v5.16b\n" + "ldr q0, [%[a_ptr], #-0x40]\n" + ".inst 0x6e85a433 // ummla v19.4s, v1.16b, v5.16b\n" + "ldr q1, [%[a_ptr], #-0x30]\n" + ".inst 0x6e85a459 // ummla v25.4s, v2.16b, v5.16b\n" + "ldr q2, [%[a_ptr], #-0x20]\n" + ".inst 0x6e85a47f // ummla v31.4s, v3.16b, v5.16b\n" + "ldr q5, [%[b_ptr], #-0x30]\n" + ".inst 0x6e86a408 // ummla v8.4s, v0.16b, v6.16b\n" + "ldr q3, [%[a_ptr], #-0x10]\n" + ".inst 0x6e86a42e // ummla v14.4s, v1.16b, v6.16b\n" + ".inst 0x6e86a454 // ummla v20.4s, v2.16b, v6.16b\n" + ".inst 0x6e87a409 // ummla v9.4s, v0.16b, v7.16b\n" + ".inst 0x6e86a47a // ummla v26.4s, v3.16b, v6.16b\n" + "ldr q6, [%[b_ptr], #-0x20]\n" + ".inst 0x6e87a42f // ummla v15.4s, v1.16b, v7.16b\n" + ".inst 0x6e87a455 // ummla v21.4s, v2.16b, v7.16b\n" + ".inst 0x6e87a47b // ummla v27.4s, v3.16b, v7.16b\n" + "ldr q7, [%[b_ptr], #-0x10]\n" + ".inst 0x6e84a40a // ummla v10.4s, v0.16b, v4.16b\n" + ".inst 0x6e84a430 // ummla v16.4s, v1.16b, v4.16b\n" + ".inst 0x6e84a456 // ummla v22.4s, v2.16b, v4.16b\n" + ".inst 0x6e84a47c // ummla v28.4s, v3.16b, v4.16b\n" + ".inst 0x6e85a40b // ummla v11.4s, v0.16b, v5.16b\n" + ".inst 0x6e85a431 // ummla v17.4s, v1.16b, v5.16b\n" + ".inst 0x6e85a457 // ummla v23.4s, v2.16b, v5.16b\n" + ".inst 0x6e85a47d // ummla v29.4s, v3.16b, v5.16b\n" + "uzp2 v4.2d, v10.2d, v11.2d\n" + ".inst 0x6e86a40c // ummla v12.4s, v0.16b, v6.16b\n" + ".inst 0x6e86a432 // ummla v18.4s, v1.16b, v6.16b\n" + ".inst 0x6e86a458 // ummla v24.4s, v2.16b, v6.16b\n" + ".inst 0x6e86a47e // ummla v30.4s, v3.16b, v6.16b\n" + "uzp1 v6.2d, v14.2d, v15.2d\n" + ".inst 0x6e87a40d // ummla v13.4s, v0.16b, v7.16b\n" + "uzp1 v0.2d, v8.2d, v9.2d\n" + ".inst 0x6e87a433 // ummla v19.4s, v1.16b, v7.16b\n" + "uzp1 v1.2d, v10.2d, v11.2d\n" + "uzp2 v5.2d, v12.2d, v13.2d\n" + "str q0, [%[c_ptr]]\n" + ".inst 0x6e87a459 // ummla v25.4s, v2.16b, v7.16b\n" + "uzp1 v2.2d, v12.2d, v13.2d\n" + "uzp1 v0.2d, v18.2d, v19.2d\n" + "str q1, [%[c_ptr], #0x10]\n" + "uzp2 v1.2d, v14.2d, v15.2d\n" + ".inst 0x6e87a47f // ummla v31.4s, v3.16b, v7.16b\n" + "uzp2 v3.2d, v8.2d, v9.2d\n" + "str q2, [%[c_ptr], #0x20]\n" + "uzp1 v7.2d, v16.2d, v17.2d\n" + "4:\n" + "uzp2 v2.2d, v16.2d, v17.2d\n" + "str q3, [%[c_ptr], #0x30]\n" + "uzp2 v3.2d, v18.2d, v19.2d\n" + "str q4, [%[c_ptr], #0x40]\n" + "uzp1 v4.2d, v20.2d, v21.2d\n" + "str q5, [%[c_ptr], #0x50]\n" + "uzp1 v5.2d, v22.2d, v23.2d\n" + "str q6, [%[c_ptr], #0x60]\n" + "uzp1 v6.2d, v24.2d, v25.2d\n" + "str q7, [%[c_ptr], #0x70]\n" + "uzp2 v7.2d, v20.2d, v21.2d\n" + "str q0, [%[c_ptr], #0x80]\n" + "uzp2 v0.2d, v22.2d, v23.2d\n" + "str q1, [%[c_ptr], #0x90]\n" + "uzp2 v1.2d, v24.2d, v25.2d\n" + "str q2, [%[c_ptr], #0xa0]\n" + "uzp1 v2.2d, v26.2d, v27.2d\n" + "str q3, [%[c_ptr], #0xb0]\n" + "uzp1 v3.2d, v28.2d, v29.2d\n" + "str q4, [%[c_ptr], #0xc0]\n" + "uzp1 v4.2d, v30.2d, v31.2d\n" + "str q5, [%[c_ptr], #0xd0]\n" + "uzp2 v5.2d, v26.2d, v27.2d\n" + "str q6, [%[c_ptr], #0xe0]\n" + "uzp2 v6.2d, v28.2d, v29.2d\n" + "str q7, [%[c_ptr], #0xf0]\n" + "uzp2 v7.2d, v30.2d, v31.2d\n" + "str q0, [%[c_ptr], #0x100]\n" + "str q1, [%[c_ptr], #0x110]\n" + "str q2, [%[c_ptr], #0x120]\n" + "str q3, [%[c_ptr], #0x130]\n" + "str q4, [%[c_ptr], #0x140]\n" + "str q5, [%[c_ptr], #0x150]\n" + "str q6, [%[c_ptr], #0x160]\n" + "str q7, [%[c_ptr], #0x170]\n" + "add %[c_ptr], %[c_ptr], #0x180\n" + : [a_ptr] "+r" (a_ptr), [b_ptr] "+r" (b_ptr), [c_ptr] "+r" (c_ptr), + [loops] "+r" (loops), [tails] "+r" (tails) + : + : "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "cc", "memory" + ); + } + } +} + +} // namespace arm_gemm + +#endif // __aarch64__ diff --git a/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_s8s32_mmla_3VLx8.hpp b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_s8s32_mmla_3VLx8.hpp new file mode 100644 index 0000000000..cd50d0ded3 --- /dev/null +++ b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_s8s32_mmla_3VLx8.hpp @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2019 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#pragma once + +#ifdef __ARM_FEATURE_SVE + +#include <cstdint> +#include "../std_transforms_sve.hpp" + +namespace arm_gemm { + +// Actual kernel implementations +void sve_interleaved_s8s32_mmla_3VLx8(const int8_t *, const int8_t *, int32_t *, int, int, int); + +class interleaved_s8s32_mmla_3VLx8 { +public: + typedef int8_t operand_type; + typedef int32_t result_type; + + typedef void (*kern_type)(const int8_t *, const int8_t *, int32_t *, int, int, int); + + /* Kernel blocking parameters */ + static unsigned int out_width() + { + return get_vector_length<int32_t>() * 3; + } + + static unsigned int out_height() + { + return 8; + } + + static unsigned int k_unroll() + { + return 8; + } + + // Use the standard fixed size transforms. + StdTransformsSVE<operand_type, result_type, 8, 6, 8, 2> transforms = {}; + + kern_type kernel=sve_interleaved_s8s32_mmla_3VLx8; + + interleaved_s8s32_mmla_3VLx8(const CPUInfo *ci) + { + UNUSED(ci); + } +}; + +} // namespace arm_gemm + +#endif // __ARM_FEATURE_SVE diff --git a/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_s8s32_mmla_3VLx8/generic.cpp b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_s8s32_mmla_3VLx8/generic.cpp new file mode 100644 index 0000000000..d636c9d2a4 --- /dev/null +++ b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_s8s32_mmla_3VLx8/generic.cpp @@ -0,0 +1,395 @@ +/* + * Copyright (c) 2019 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifdef __ARM_FEATURE_SVE + +#include <cstdint> +#include "../../asmlib.hpp" + +namespace arm_gemm { + +void sve_interleaved_s8s32_mmla_3VLx8(const int8_t *Apanel, const int8_t *Bpanel, int32_t *Cpanel, int ablocks, int bblocks, int K) { + const int8_t *a_ptr = Apanel; + int32_t *c_ptr = Cpanel; + + K /= 8; + const long loops_count = (K / 2) - 1; + const long tails_count = K % 2; + + for (int yb=0; yb<ablocks; yb++) { + const int8_t *a_ptr0 = a_ptr; + const int8_t *b_ptr = Bpanel; + + for (int xb=0; xb<bblocks; xb++) { + a_ptr = a_ptr0; + long loops = loops_count; + long tails = tails_count; + + __asm __volatile ( + "mov z8.s, #0\n" + "ptrue p0.b\n" + "mov z9.s, #0\n" + "mov z10.s, #0\n" + "mov z11.s, #0\n" + "ld1rqb z0.b, p0/z, [%[a_ptr]]\n" + "mov z12.s, #0\n" + "ld1b z4.b, p0/z, [%[b_ptr]]\n" + "mov z13.s, #0\n" + "ld1rqb z1.b, p0/z, [%[a_ptr], #0x10]\n" + "mov z14.s, #0\n" + "ld1b z5.b, p0/z, [%[b_ptr], #1, MUL VL]\n" + "mov z15.s, #0\n" + "ld1rqb z2.b, p0/z, [%[a_ptr], #0x20]\n" + "mov z16.s, #0\n" + "ld1b z6.b, p0/z, [%[b_ptr], #2, MUL VL]\n" + "mov z17.s, #0\n" + "ld1rqb z3.b, p0/z, [%[a_ptr], #0x30]\n" + "mov z18.s, #0\n" + "ld1b z7.b, p0/z, [%[b_ptr], #3, MUL VL]\n" + "mov z19.s, #0\n" + "add %[a_ptr], %[a_ptr], #0x40\n" + "mov z20.s, #0\n" + "addvl %[b_ptr], %[b_ptr], #4\n" + "mov z21.s, #0\n" + "mov z22.s, #0\n" + "mov z23.s, #0\n" + "mov z24.s, #0\n" + "mov z25.s, #0\n" + "mov z26.s, #0\n" + "mov z27.s, #0\n" + "mov z28.s, #0\n" + "mov z29.s, #0\n" + "mov z30.s, #0\n" + "mov z31.s, #0\n" + "cbz %[loops], 1f\n" + "2:\n" + ".inst 0x45049808 // smmla z8.s, z0.b, z4.b\n" + "subs %[loops], %[loops], #0x1\n" + ".inst 0x4504982e // smmla z14.s, z1.b, z4.b\n" + ".inst 0x45049854 // smmla z20.s, z2.b, z4.b\n" + ".inst 0x4504987a // smmla z26.s, z3.b, z4.b\n" + "ld1b z4.b, p0/z, [%[b_ptr]]\n" + ".inst 0x45059809 // smmla z9.s, z0.b, z5.b\n" + ".inst 0x4505982f // smmla z15.s, z1.b, z5.b\n" + ".inst 0x45059855 // smmla z21.s, z2.b, z5.b\n" + ".inst 0x4505987b // smmla z27.s, z3.b, z5.b\n" + "ld1b z5.b, p0/z, [%[b_ptr], #1, MUL VL]\n" + ".inst 0x4506980a // smmla z10.s, z0.b, z6.b\n" + ".inst 0x45069830 // smmla z16.s, z1.b, z6.b\n" + ".inst 0x45069856 // smmla z22.s, z2.b, z6.b\n" + ".inst 0x4506987c // smmla z28.s, z3.b, z6.b\n" + "ld1b z6.b, p0/z, [%[b_ptr], #2, MUL VL]\n" + ".inst 0x4507980b // smmla z11.s, z0.b, z7.b\n" + ".inst 0x45079831 // smmla z17.s, z1.b, z7.b\n" + ".inst 0x45079857 // smmla z23.s, z2.b, z7.b\n" + ".inst 0x4507987d // smmla z29.s, z3.b, z7.b\n" + "ld1b z7.b, p0/z, [%[b_ptr], #3, MUL VL]\n" + ".inst 0x4504980c // smmla z12.s, z0.b, z4.b\n" + ".inst 0x45049832 // smmla z18.s, z1.b, z4.b\n" + ".inst 0x45049858 // smmla z24.s, z2.b, z4.b\n" + ".inst 0x4504987e // smmla z30.s, z3.b, z4.b\n" + "ld1b z4.b, p0/z, [%[b_ptr], #4, MUL VL]\n" + ".inst 0x4505980d // smmla z13.s, z0.b, z5.b\n" + "ld1rqb z0.b, p0/z, [%[a_ptr]]\n" + ".inst 0x45059833 // smmla z19.s, z1.b, z5.b\n" + "ld1rqb z1.b, p0/z, [%[a_ptr], #0x10]\n" + ".inst 0x45059859 // smmla z25.s, z2.b, z5.b\n" + "ld1rqb z2.b, p0/z, [%[a_ptr], #0x20]\n" + ".inst 0x4505987f // smmla z31.s, z3.b, z5.b\n" + "ld1b z5.b, p0/z, [%[b_ptr], #5, MUL VL]\n" + ".inst 0x45069808 // smmla z8.s, z0.b, z6.b\n" + "ld1rqb z3.b, p0/z, [%[a_ptr], #0x30]\n" + ".inst 0x4506982e // smmla z14.s, z1.b, z6.b\n" + "add %[a_ptr], %[a_ptr], #0x80\n" + ".inst 0x45069854 // smmla z20.s, z2.b, z6.b\n" + "addvl %[b_ptr], %[b_ptr], #12\n" + ".inst 0x4506987a // smmla z26.s, z3.b, z6.b\n" + ".inst 0x45079809 // smmla z9.s, z0.b, z7.b\n" + ".inst 0x4507982f // smmla z15.s, z1.b, z7.b\n" + "ld1b z6.b, p0/z, [%[b_ptr], #-6, MUL VL]\n" + ".inst 0x45079855 // smmla z21.s, z2.b, z7.b\n" + ".inst 0x4507987b // smmla z27.s, z3.b, z7.b\n" + "ld1b z7.b, p0/z, [%[b_ptr], #-5, MUL VL]\n" + ".inst 0x4504980a // smmla z10.s, z0.b, z4.b\n" + ".inst 0x45049830 // smmla z16.s, z1.b, z4.b\n" + ".inst 0x45049856 // smmla z22.s, z2.b, z4.b\n" + ".inst 0x4504987c // smmla z28.s, z3.b, z4.b\n" + "ld1b z4.b, p0/z, [%[b_ptr], #-4, MUL VL]\n" + ".inst 0x4505980b // smmla z11.s, z0.b, z5.b\n" + ".inst 0x45059831 // smmla z17.s, z1.b, z5.b\n" + ".inst 0x45059857 // smmla z23.s, z2.b, z5.b\n" + ".inst 0x4505987d // smmla z29.s, z3.b, z5.b\n" + "ld1b z5.b, p0/z, [%[b_ptr], #-3, MUL VL]\n" + ".inst 0x4506980c // smmla z12.s, z0.b, z6.b\n" + ".inst 0x45069832 // smmla z18.s, z1.b, z6.b\n" + ".inst 0x45069858 // smmla z24.s, z2.b, z6.b\n" + ".inst 0x4506987e // smmla z30.s, z3.b, z6.b\n" + "ld1b z6.b, p0/z, [%[b_ptr], #-2, MUL VL]\n" + ".inst 0x4507980d // smmla z13.s, z0.b, z7.b\n" + "ld1rqb z0.b, p0/z, [%[a_ptr], #-0x40]\n" + ".inst 0x45079833 // smmla z19.s, z1.b, z7.b\n" + "ld1rqb z1.b, p0/z, [%[a_ptr], #-0x30]\n" + ".inst 0x45079859 // smmla z25.s, z2.b, z7.b\n" + "ld1rqb z2.b, p0/z, [%[a_ptr], #-0x20]\n" + ".inst 0x4507987f // smmla z31.s, z3.b, z7.b\n" + "ld1b z7.b, p0/z, [%[b_ptr], #-1, MUL VL]\n" + "ld1rqb z3.b, p0/z, [%[a_ptr], #-0x10]\n" + "b.ne 2b\n" + "1:\n" + "cbz %[tails], 3f\n" + ".inst 0x45049808 // smmla z8.s, z0.b, z4.b\n" + ".inst 0x4504982e // smmla z14.s, z1.b, z4.b\n" + ".inst 0x45049854 // smmla z20.s, z2.b, z4.b\n" + ".inst 0x4504987a // smmla z26.s, z3.b, z4.b\n" + "ld1b z4.b, p0/z, [%[b_ptr]]\n" + ".inst 0x45059809 // smmla z9.s, z0.b, z5.b\n" + ".inst 0x4505982f // smmla z15.s, z1.b, z5.b\n" + ".inst 0x45059855 // smmla z21.s, z2.b, z5.b\n" + ".inst 0x4505987b // smmla z27.s, z3.b, z5.b\n" + "ld1b z5.b, p0/z, [%[b_ptr], #1, MUL VL]\n" + ".inst 0x4506980a // smmla z10.s, z0.b, z6.b\n" + ".inst 0x45069830 // smmla z16.s, z1.b, z6.b\n" + ".inst 0x45069856 // smmla z22.s, z2.b, z6.b\n" + ".inst 0x4506987c // smmla z28.s, z3.b, z6.b\n" + "ld1b z6.b, p0/z, [%[b_ptr], #2, MUL VL]\n" + ".inst 0x4507980b // smmla z11.s, z0.b, z7.b\n" + ".inst 0x45079831 // smmla z17.s, z1.b, z7.b\n" + ".inst 0x45079857 // smmla z23.s, z2.b, z7.b\n" + ".inst 0x4507987d // smmla z29.s, z3.b, z7.b\n" + "ld1b z7.b, p0/z, [%[b_ptr], #3, MUL VL]\n" + ".inst 0x4504980c // smmla z12.s, z0.b, z4.b\n" + ".inst 0x45049832 // smmla z18.s, z1.b, z4.b\n" + ".inst 0x45049858 // smmla z24.s, z2.b, z4.b\n" + ".inst 0x4504987e // smmla z30.s, z3.b, z4.b\n" + "ld1b z4.b, p0/z, [%[b_ptr], #4, MUL VL]\n" + ".inst 0x4505980d // smmla z13.s, z0.b, z5.b\n" + "ld1rqb z0.b, p0/z, [%[a_ptr]]\n" + ".inst 0x45059833 // smmla z19.s, z1.b, z5.b\n" + "ld1rqb z1.b, p0/z, [%[a_ptr], #0x10]\n" + ".inst 0x45059859 // smmla z25.s, z2.b, z5.b\n" + "ld1rqb z2.b, p0/z, [%[a_ptr], #0x20]\n" + ".inst 0x4505987f // smmla z31.s, z3.b, z5.b\n" + "ld1b z5.b, p0/z, [%[b_ptr], #5, MUL VL]\n" + ".inst 0x45069808 // smmla z8.s, z0.b, z6.b\n" + "ld1rqb z3.b, p0/z, [%[a_ptr], #0x30]\n" + ".inst 0x4506982e // smmla z14.s, z1.b, z6.b\n" + "add %[a_ptr], %[a_ptr], #0x80\n" + ".inst 0x45069854 // smmla z20.s, z2.b, z6.b\n" + "addvl %[b_ptr], %[b_ptr], #14\n" + ".inst 0x4506987a // smmla z26.s, z3.b, z6.b\n" + ".inst 0x45079809 // smmla z9.s, z0.b, z7.b\n" + ".inst 0x4507982f // smmla z15.s, z1.b, z7.b\n" + "ld1b z6.b, p0/z, [%[b_ptr], #-8, MUL VL]\n" + ".inst 0x45079855 // smmla z21.s, z2.b, z7.b\n" + ".inst 0x4507987b // smmla z27.s, z3.b, z7.b\n" + "ld1b z7.b, p0/z, [%[b_ptr], #-7, MUL VL]\n" + ".inst 0x4504980a // smmla z10.s, z0.b, z4.b\n" + ".inst 0x45049830 // smmla z16.s, z1.b, z4.b\n" + ".inst 0x45049856 // smmla z22.s, z2.b, z4.b\n" + ".inst 0x4504987c // smmla z28.s, z3.b, z4.b\n" + "ld1b z4.b, p0/z, [%[b_ptr], #-6, MUL VL]\n" + ".inst 0x4505980b // smmla z11.s, z0.b, z5.b\n" + ".inst 0x45059831 // smmla z17.s, z1.b, z5.b\n" + ".inst 0x45059857 // smmla z23.s, z2.b, z5.b\n" + ".inst 0x4505987d // smmla z29.s, z3.b, z5.b\n" + "ld1b z5.b, p0/z, [%[b_ptr], #-5, MUL VL]\n" + ".inst 0x4506980c // smmla z12.s, z0.b, z6.b\n" + ".inst 0x45069832 // smmla z18.s, z1.b, z6.b\n" + ".inst 0x45069858 // smmla z24.s, z2.b, z6.b\n" + ".inst 0x4506987e // smmla z30.s, z3.b, z6.b\n" + "ld1b z6.b, p0/z, [%[b_ptr], #-4, MUL VL]\n" + ".inst 0x4507980d // smmla z13.s, z0.b, z7.b\n" + "ld1rqb z0.b, p0/z, [%[a_ptr], #-0x40]\n" + ".inst 0x45079833 // smmla z19.s, z1.b, z7.b\n" + "ld1rqb z1.b, p0/z, [%[a_ptr], #-0x30]\n" + ".inst 0x45079859 // smmla z25.s, z2.b, z7.b\n" + "ld1rqb z2.b, p0/z, [%[a_ptr], #-0x20]\n" + ".inst 0x4507987f // smmla z31.s, z3.b, z7.b\n" + "ld1b z7.b, p0/z, [%[b_ptr], #-3, MUL VL]\n" + ".inst 0x45049808 // smmla z8.s, z0.b, z4.b\n" + "ld1rqb z3.b, p0/z, [%[a_ptr], #-0x10]\n" + ".inst 0x4504982e // smmla z14.s, z1.b, z4.b\n" + ".inst 0x45049854 // smmla z20.s, z2.b, z4.b\n" + ".inst 0x45059809 // smmla z9.s, z0.b, z5.b\n" + ".inst 0x4504987a // smmla z26.s, z3.b, z4.b\n" + "ld1b z4.b, p0/z, [%[b_ptr], #-2, MUL VL]\n" + ".inst 0x4505982f // smmla z15.s, z1.b, z5.b\n" + ".inst 0x45059855 // smmla z21.s, z2.b, z5.b\n" + ".inst 0x4505987b // smmla z27.s, z3.b, z5.b\n" + "ld1b z5.b, p0/z, [%[b_ptr], #-1, MUL VL]\n" + ".inst 0x4506980a // smmla z10.s, z0.b, z6.b\n" + ".inst 0x45069830 // smmla z16.s, z1.b, z6.b\n" + ".inst 0x45069856 // smmla z22.s, z2.b, z6.b\n" + ".inst 0x4506987c // smmla z28.s, z3.b, z6.b\n" + "uzp1 z6.d, z14.d, z15.d\n" + ".inst 0x4507980b // smmla z11.s, z0.b, z7.b\n" + ".inst 0x45079831 // smmla z17.s, z1.b, z7.b\n" + ".inst 0x45079857 // smmla z23.s, z2.b, z7.b\n" + ".inst 0x4507987d // smmla z29.s, z3.b, z7.b\n" + ".inst 0x4504980c // smmla z12.s, z0.b, z4.b\n" + "uzp1 z7.d, z16.d, z17.d\n" + ".inst 0x45049832 // smmla z18.s, z1.b, z4.b\n" + ".inst 0x45049858 // smmla z24.s, z2.b, z4.b\n" + ".inst 0x4504987e // smmla z30.s, z3.b, z4.b\n" + "uzp2 z4.d, z10.d, z11.d\n" + ".inst 0x4505980d // smmla z13.s, z0.b, z5.b\n" + "uzp1 z0.d, z8.d, z9.d\n" + ".inst 0x45059833 // smmla z19.s, z1.b, z5.b\n" + "uzp1 z1.d, z10.d, z11.d\n" + ".inst 0x45059859 // smmla z25.s, z2.b, z5.b\n" + "st1w z0.s, p0, [%[c_ptr]]\n" + "uzp1 z2.d, z12.d, z13.d\n" + "uzp1 z0.d, z18.d, z19.d\n" + ".inst 0x4505987f // smmla z31.s, z3.b, z5.b\n" + "st1w z1.s, p0, [%[c_ptr], #1, MUL VL]\n" + "uzp2 z3.d, z8.d, z9.d\n" + "uzp2 z5.d, z12.d, z13.d\n" + "uzp2 z1.d, z14.d, z15.d\n" + "st1w z2.s, p0, [%[c_ptr], #2, MUL VL]\n" + "b 4f\n" + "3:\n" + ".inst 0x45049808 // smmla z8.s, z0.b, z4.b\n" + "add %[a_ptr], %[a_ptr], #0x40\n" + ".inst 0x4504982e // smmla z14.s, z1.b, z4.b\n" + "addvl %[b_ptr], %[b_ptr], #8\n" + ".inst 0x45049854 // smmla z20.s, z2.b, z4.b\n" + ".inst 0x4504987a // smmla z26.s, z3.b, z4.b\n" + ".inst 0x45059809 // smmla z9.s, z0.b, z5.b\n" + "ld1b z4.b, p0/z, [%[b_ptr], #-8, MUL VL]\n" + ".inst 0x4505982f // smmla z15.s, z1.b, z5.b\n" + ".inst 0x45059855 // smmla z21.s, z2.b, z5.b\n" + ".inst 0x4505987b // smmla z27.s, z3.b, z5.b\n" + "ld1b z5.b, p0/z, [%[b_ptr], #-7, MUL VL]\n" + ".inst 0x4506980a // smmla z10.s, z0.b, z6.b\n" + ".inst 0x45069830 // smmla z16.s, z1.b, z6.b\n" + ".inst 0x45069856 // smmla z22.s, z2.b, z6.b\n" + ".inst 0x4506987c // smmla z28.s, z3.b, z6.b\n" + "ld1b z6.b, p0/z, [%[b_ptr], #-6, MUL VL]\n" + ".inst 0x4507980b // smmla z11.s, z0.b, z7.b\n" + ".inst 0x45079831 // smmla z17.s, z1.b, z7.b\n" + ".inst 0x45079857 // smmla z23.s, z2.b, z7.b\n" + ".inst 0x4507987d // smmla z29.s, z3.b, z7.b\n" + "ld1b z7.b, p0/z, [%[b_ptr], #-5, MUL VL]\n" + ".inst 0x4504980c // smmla z12.s, z0.b, z4.b\n" + ".inst 0x45049832 // smmla z18.s, z1.b, z4.b\n" + ".inst 0x45049858 // smmla z24.s, z2.b, z4.b\n" + ".inst 0x4504987e // smmla z30.s, z3.b, z4.b\n" + "ld1b z4.b, p0/z, [%[b_ptr], #-4, MUL VL]\n" + ".inst 0x4505980d // smmla z13.s, z0.b, z5.b\n" + "ld1rqb z0.b, p0/z, [%[a_ptr], #-0x40]\n" + ".inst 0x45059833 // smmla z19.s, z1.b, z5.b\n" + "ld1rqb z1.b, p0/z, [%[a_ptr], #-0x30]\n" + ".inst 0x45059859 // smmla z25.s, z2.b, z5.b\n" + "ld1rqb z2.b, p0/z, [%[a_ptr], #-0x20]\n" + ".inst 0x4505987f // smmla z31.s, z3.b, z5.b\n" + "ld1b z5.b, p0/z, [%[b_ptr], #-3, MUL VL]\n" + ".inst 0x45069808 // smmla z8.s, z0.b, z6.b\n" + "ld1rqb z3.b, p0/z, [%[a_ptr], #-0x10]\n" + ".inst 0x4506982e // smmla z14.s, z1.b, z6.b\n" + ".inst 0x45069854 // smmla z20.s, z2.b, z6.b\n" + ".inst 0x45079809 // smmla z9.s, z0.b, z7.b\n" + ".inst 0x4506987a // smmla z26.s, z3.b, z6.b\n" + "ld1b z6.b, p0/z, [%[b_ptr], #-2, MUL VL]\n" + ".inst 0x4507982f // smmla z15.s, z1.b, z7.b\n" + ".inst 0x45079855 // smmla z21.s, z2.b, z7.b\n" + ".inst 0x4507987b // smmla z27.s, z3.b, z7.b\n" + "ld1b z7.b, p0/z, [%[b_ptr], #-1, MUL VL]\n" + ".inst 0x4504980a // smmla z10.s, z0.b, z4.b\n" + ".inst 0x45049830 // smmla z16.s, z1.b, z4.b\n" + ".inst 0x45049856 // smmla z22.s, z2.b, z4.b\n" + ".inst 0x4504987c // smmla z28.s, z3.b, z4.b\n" + ".inst 0x4505980b // smmla z11.s, z0.b, z5.b\n" + ".inst 0x45059831 // smmla z17.s, z1.b, z5.b\n" + ".inst 0x45059857 // smmla z23.s, z2.b, z5.b\n" + ".inst 0x4505987d // smmla z29.s, z3.b, z5.b\n" + "uzp2 z4.d, z10.d, z11.d\n" + ".inst 0x4506980c // smmla z12.s, z0.b, z6.b\n" + ".inst 0x45069832 // smmla z18.s, z1.b, z6.b\n" + ".inst 0x45069858 // smmla z24.s, z2.b, z6.b\n" + ".inst 0x4506987e // smmla z30.s, z3.b, z6.b\n" + "uzp1 z6.d, z14.d, z15.d\n" + ".inst 0x4507980d // smmla z13.s, z0.b, z7.b\n" + "uzp1 z0.d, z8.d, z9.d\n" + ".inst 0x45079833 // smmla z19.s, z1.b, z7.b\n" + "uzp1 z1.d, z10.d, z11.d\n" + "uzp2 z5.d, z12.d, z13.d\n" + "st1w z0.s, p0, [%[c_ptr]]\n" + ".inst 0x45079859 // smmla z25.s, z2.b, z7.b\n" + "uzp1 z2.d, z12.d, z13.d\n" + "uzp1 z0.d, z18.d, z19.d\n" + "st1w z1.s, p0, [%[c_ptr], #1, MUL VL]\n" + "uzp2 z1.d, z14.d, z15.d\n" + ".inst 0x4507987f // smmla z31.s, z3.b, z7.b\n" + "uzp2 z3.d, z8.d, z9.d\n" + "st1w z2.s, p0, [%[c_ptr], #2, MUL VL]\n" + "uzp1 z7.d, z16.d, z17.d\n" + "4:\n" + "uzp2 z2.d, z16.d, z17.d\n" + "st1w z3.s, p0, [%[c_ptr], #3, MUL VL]\n" + "uzp2 z3.d, z18.d, z19.d\n" + "st1w z4.s, p0, [%[c_ptr], #4, MUL VL]\n" + "uzp1 z4.d, z20.d, z21.d\n" + "st1w z5.s, p0, [%[c_ptr], #5, MUL VL]\n" + "uzp1 z5.d, z22.d, z23.d\n" + "st1w z6.s, p0, [%[c_ptr], #6, MUL VL]\n" + "uzp1 z6.d, z24.d, z25.d\n" + "st1w z7.s, p0, [%[c_ptr], #7, MUL VL]\n" + "addvl %[c_ptr], %[c_ptr], #16\n" + "uzp2 z7.d, z20.d, z21.d\n" + "st1w z0.s, p0, [%[c_ptr], #-8, MUL VL]\n" + "uzp2 z0.d, z22.d, z23.d\n" + "st1w z1.s, p0, [%[c_ptr], #-7, MUL VL]\n" + "uzp2 z1.d, z24.d, z25.d\n" + "st1w z2.s, p0, [%[c_ptr], #-6, MUL VL]\n" + "uzp1 z2.d, z26.d, z27.d\n" + "st1w z3.s, p0, [%[c_ptr], #-5, MUL VL]\n" + "uzp1 z3.d, z28.d, z29.d\n" + "st1w z4.s, p0, [%[c_ptr], #-4, MUL VL]\n" + "uzp1 z4.d, z30.d, z31.d\n" + "st1w z5.s, p0, [%[c_ptr], #-3, MUL VL]\n" + "uzp2 z5.d, z26.d, z27.d\n" + "st1w z6.s, p0, [%[c_ptr], #-2, MUL VL]\n" + "uzp2 z6.d, z28.d, z29.d\n" + "st1w z7.s, p0, [%[c_ptr], #-1, MUL VL]\n" + "uzp2 z7.d, z30.d, z31.d\n" + "st1w z0.s, p0, [%[c_ptr]]\n" + "st1w z1.s, p0, [%[c_ptr], #1, MUL VL]\n" + "st1w z2.s, p0, [%[c_ptr], #2, MUL VL]\n" + "st1w z3.s, p0, [%[c_ptr], #3, MUL VL]\n" + "st1w z4.s, p0, [%[c_ptr], #4, MUL VL]\n" + "st1w z5.s, p0, [%[c_ptr], #5, MUL VL]\n" + "st1w z6.s, p0, [%[c_ptr], #6, MUL VL]\n" + "st1w z7.s, p0, [%[c_ptr], #7, MUL VL]\n" + "addvl %[c_ptr], %[c_ptr], #8\n" + : [a_ptr] "+r" (a_ptr), [b_ptr] "+r" (b_ptr), [c_ptr] "+r" (c_ptr), + [loops] "+r" (loops), [tails] "+r" (tails) + : + : "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31", "cc", "memory" + ); + } + } +} + +} // namespace arm_gemm + +#endif // __ARM_FEATURE_SVE diff --git a/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_u8u32_mmla_3VLx8.hpp b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_u8u32_mmla_3VLx8.hpp new file mode 100644 index 0000000000..9b5ca1049e --- /dev/null +++ b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_u8u32_mmla_3VLx8.hpp @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2019 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#pragma once + +#ifdef __ARM_FEATURE_SVE + +#include <cstdint> +#include "../std_transforms_sve.hpp" + +namespace arm_gemm { + +// Actual kernel implementations +void sve_interleaved_u8u32_mmla_3VLx8(const uint8_t *, const uint8_t *, uint32_t *, int, int, int); + +class interleaved_u8u32_mmla_3VLx8 { +public: + typedef uint8_t operand_type; + typedef uint32_t result_type; + + typedef void (*kern_type)(const uint8_t *, const uint8_t *, uint32_t *, int, int, int); + + /* Kernel blocking parameters */ + static unsigned int out_width() + { + return get_vector_length<uint32_t>() * 3; + } + + static unsigned int out_height() + { + return 8; + } + + static unsigned int k_unroll() + { + return 8; + } + + // Use the standard fixed size transforms. + StdTransformsSVE<operand_type, result_type, 8, 6, 8, 2> transforms = {}; + + kern_type kernel=sve_interleaved_u8u32_mmla_3VLx8; + + interleaved_u8u32_mmla_3VLx8(const CPUInfo *ci) + { + UNUSED(ci); + } +}; + +} // namespace arm_gemm + +#endif // __ARM_FEATURE_SVE diff --git a/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_u8u32_mmla_3VLx8/generic.cpp b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_u8u32_mmla_3VLx8/generic.cpp new file mode 100644 index 0000000000..15cc8fb897 --- /dev/null +++ b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_u8u32_mmla_3VLx8/generic.cpp @@ -0,0 +1,395 @@ +/* + * Copyright (c) 2019 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifdef __ARM_FEATURE_SVE + +#include <cstdint> +#include "../../asmlib.hpp" + +namespace arm_gemm { + +void sve_interleaved_u8u32_mmla_3VLx8(const uint8_t *Apanel, const uint8_t *Bpanel, uint32_t *Cpanel, int ablocks, int bblocks, int K) { + const uint8_t *a_ptr = Apanel; + uint32_t *c_ptr = Cpanel; + + K /= 8; + const long loops_count = (K / 2) - 1; + const long tails_count = K % 2; + + for (int yb=0; yb<ablocks; yb++) { + const uint8_t *a_ptr0 = a_ptr; + const uint8_t *b_ptr = Bpanel; + + for (int xb=0; xb<bblocks; xb++) { + a_ptr = a_ptr0; + long loops = loops_count; + long tails = tails_count; + + __asm __volatile ( + "mov z8.s, #0\n" + "ptrue p0.b\n" + "mov z9.s, #0\n" + "mov z10.s, #0\n" + "mov z11.s, #0\n" + "ld1rqb z0.b, p0/z, [%[a_ptr]]\n" + "mov z12.s, #0\n" + "ld1b z4.b, p0/z, [%[b_ptr]]\n" + "mov z13.s, #0\n" + "ld1rqb z1.b, p0/z, [%[a_ptr], #0x10]\n" + "mov z14.s, #0\n" + "ld1b z5.b, p0/z, [%[b_ptr], #1, MUL VL]\n" + "mov z15.s, #0\n" + "ld1rqb z2.b, p0/z, [%[a_ptr], #0x20]\n" + "mov z16.s, #0\n" + "ld1b z6.b, p0/z, [%[b_ptr], #2, MUL VL]\n" + "mov z17.s, #0\n" + "ld1rqb z3.b, p0/z, [%[a_ptr], #0x30]\n" + "mov z18.s, #0\n" + "ld1b z7.b, p0/z, [%[b_ptr], #3, MUL VL]\n" + "mov z19.s, #0\n" + "add %[a_ptr], %[a_ptr], #0x40\n" + "mov z20.s, #0\n" + "addvl %[b_ptr], %[b_ptr], #4\n" + "mov z21.s, #0\n" + "mov z22.s, #0\n" + "mov z23.s, #0\n" + "mov z24.s, #0\n" + "mov z25.s, #0\n" + "mov z26.s, #0\n" + "mov z27.s, #0\n" + "mov z28.s, #0\n" + "mov z29.s, #0\n" + "mov z30.s, #0\n" + "mov z31.s, #0\n" + "cbz %[loops], 1f\n" + "2:\n" + ".inst 0x45c49808 // ummla z8.s, z0.b, z4.b\n" + "subs %[loops], %[loops], #0x1\n" + ".inst 0x45c4982e // ummla z14.s, z1.b, z4.b\n" + ".inst 0x45c49854 // ummla z20.s, z2.b, z4.b\n" + ".inst 0x45c4987a // ummla z26.s, z3.b, z4.b\n" + "ld1b z4.b, p0/z, [%[b_ptr]]\n" + ".inst 0x45c59809 // ummla z9.s, z0.b, z5.b\n" + ".inst 0x45c5982f // ummla z15.s, z1.b, z5.b\n" + ".inst 0x45c59855 // ummla z21.s, z2.b, z5.b\n" + ".inst 0x45c5987b // ummla z27.s, z3.b, z5.b\n" + "ld1b z5.b, p0/z, [%[b_ptr], #1, MUL VL]\n" + ".inst 0x45c6980a // ummla z10.s, z0.b, z6.b\n" + ".inst 0x45c69830 // ummla z16.s, z1.b, z6.b\n" + ".inst 0x45c69856 // ummla z22.s, z2.b, z6.b\n" + ".inst 0x45c6987c // ummla z28.s, z3.b, z6.b\n" + "ld1b z6.b, p0/z, [%[b_ptr], #2, MUL VL]\n" + ".inst 0x45c7980b // ummla z11.s, z0.b, z7.b\n" + ".inst 0x45c79831 // ummla z17.s, z1.b, z7.b\n" + ".inst 0x45c79857 // ummla z23.s, z2.b, z7.b\n" + ".inst 0x45c7987d // ummla z29.s, z3.b, z7.b\n" + "ld1b z7.b, p0/z, [%[b_ptr], #3, MUL VL]\n" + ".inst 0x45c4980c // ummla z12.s, z0.b, z4.b\n" + ".inst 0x45c49832 // ummla z18.s, z1.b, z4.b\n" + ".inst 0x45c49858 // ummla z24.s, z2.b, z4.b\n" + ".inst 0x45c4987e // ummla z30.s, z3.b, z4.b\n" + "ld1b z4.b, p0/z, [%[b_ptr], #4, MUL VL]\n" + ".inst 0x45c5980d // ummla z13.s, z0.b, z5.b\n" + "ld1rqb z0.b, p0/z, [%[a_ptr]]\n" + ".inst 0x45c59833 // ummla z19.s, z1.b, z5.b\n" + "ld1rqb z1.b, p0/z, [%[a_ptr], #0x10]\n" + ".inst 0x45c59859 // ummla z25.s, z2.b, z5.b\n" + "ld1rqb z2.b, p0/z, [%[a_ptr], #0x20]\n" + ".inst 0x45c5987f // ummla z31.s, z3.b, z5.b\n" + "ld1b z5.b, p0/z, [%[b_ptr], #5, MUL VL]\n" + ".inst 0x45c69808 // ummla z8.s, z0.b, z6.b\n" + "ld1rqb z3.b, p0/z, [%[a_ptr], #0x30]\n" + ".inst 0x45c6982e // ummla z14.s, z1.b, z6.b\n" + "add %[a_ptr], %[a_ptr], #0x80\n" + ".inst 0x45c69854 // ummla z20.s, z2.b, z6.b\n" + "addvl %[b_ptr], %[b_ptr], #12\n" + ".inst 0x45c6987a // ummla z26.s, z3.b, z6.b\n" + ".inst 0x45c79809 // ummla z9.s, z0.b, z7.b\n" + ".inst 0x45c7982f // ummla z15.s, z1.b, z7.b\n" + "ld1b z6.b, p0/z, [%[b_ptr], #-6, MUL VL]\n" + ".inst 0x45c79855 // ummla z21.s, z2.b, z7.b\n" + ".inst 0x45c7987b // ummla z27.s, z3.b, z7.b\n" + "ld1b z7.b, p0/z, [%[b_ptr], #-5, MUL VL]\n" + ".inst 0x45c4980a // ummla z10.s, z0.b, z4.b\n" + ".inst 0x45c49830 // ummla z16.s, z1.b, z4.b\n" + ".inst 0x45c49856 // ummla z22.s, z2.b, z4.b\n" + ".inst 0x45c4987c // ummla z28.s, z3.b, z4.b\n" + "ld1b z4.b, p0/z, [%[b_ptr], #-4, MUL VL]\n" + ".inst 0x45c5980b // ummla z11.s, z0.b, z5.b\n" + ".inst 0x45c59831 // ummla z17.s, z1.b, z5.b\n" + ".inst 0x45c59857 // ummla z23.s, z2.b, z5.b\n" + ".inst 0x45c5987d // ummla z29.s, z3.b, z5.b\n" + "ld1b z5.b, p0/z, [%[b_ptr], #-3, MUL VL]\n" + ".inst 0x45c6980c // ummla z12.s, z0.b, z6.b\n" + ".inst 0x45c69832 // ummla z18.s, z1.b, z6.b\n" + ".inst 0x45c69858 // ummla z24.s, z2.b, z6.b\n" + ".inst 0x45c6987e // ummla z30.s, z3.b, z6.b\n" + "ld1b z6.b, p0/z, [%[b_ptr], #-2, MUL VL]\n" + ".inst 0x45c7980d // ummla z13.s, z0.b, z7.b\n" + "ld1rqb z0.b, p0/z, [%[a_ptr], #-0x40]\n" + ".inst 0x45c79833 // ummla z19.s, z1.b, z7.b\n" + "ld1rqb z1.b, p0/z, [%[a_ptr], #-0x30]\n" + ".inst 0x45c79859 // ummla z25.s, z2.b, z7.b\n" + "ld1rqb z2.b, p0/z, [%[a_ptr], #-0x20]\n" + ".inst 0x45c7987f // ummla z31.s, z3.b, z7.b\n" + "ld1b z7.b, p0/z, [%[b_ptr], #-1, MUL VL]\n" + "ld1rqb z3.b, p0/z, [%[a_ptr], #-0x10]\n" + "b.ne 2b\n" + "1:\n" + "cbz %[tails], 3f\n" + ".inst 0x45c49808 // ummla z8.s, z0.b, z4.b\n" + ".inst 0x45c4982e // ummla z14.s, z1.b, z4.b\n" + ".inst 0x45c49854 // ummla z20.s, z2.b, z4.b\n" + ".inst 0x45c4987a // ummla z26.s, z3.b, z4.b\n" + "ld1b z4.b, p0/z, [%[b_ptr]]\n" + ".inst 0x45c59809 // ummla z9.s, z0.b, z5.b\n" + ".inst 0x45c5982f // ummla z15.s, z1.b, z5.b\n" + ".inst 0x45c59855 // ummla z21.s, z2.b, z5.b\n" + ".inst 0x45c5987b // ummla z27.s, z3.b, z5.b\n" + "ld1b z5.b, p0/z, [%[b_ptr], #1, MUL VL]\n" + ".inst 0x45c6980a // ummla z10.s, z0.b, z6.b\n" + ".inst 0x45c69830 // ummla z16.s, z1.b, z6.b\n" + ".inst 0x45c69856 // ummla z22.s, z2.b, z6.b\n" + ".inst 0x45c6987c // ummla z28.s, z3.b, z6.b\n" + "ld1b z6.b, p0/z, [%[b_ptr], #2, MUL VL]\n" + ".inst 0x45c7980b // ummla z11.s, z0.b, z7.b\n" + ".inst 0x45c79831 // ummla z17.s, z1.b, z7.b\n" + ".inst 0x45c79857 // ummla z23.s, z2.b, z7.b\n" + ".inst 0x45c7987d // ummla z29.s, z3.b, z7.b\n" + "ld1b z7.b, p0/z, [%[b_ptr], #3, MUL VL]\n" + ".inst 0x45c4980c // ummla z12.s, z0.b, z4.b\n" + ".inst 0x45c49832 // ummla z18.s, z1.b, z4.b\n" + ".inst 0x45c49858 // ummla z24.s, z2.b, z4.b\n" + ".inst 0x45c4987e // ummla z30.s, z3.b, z4.b\n" + "ld1b z4.b, p0/z, [%[b_ptr], #4, MUL VL]\n" + ".inst 0x45c5980d // ummla z13.s, z0.b, z5.b\n" + "ld1rqb z0.b, p0/z, [%[a_ptr]]\n" + ".inst 0x45c59833 // ummla z19.s, z1.b, z5.b\n" + "ld1rqb z1.b, p0/z, [%[a_ptr], #0x10]\n" + ".inst 0x45c59859 // ummla z25.s, z2.b, z5.b\n" + "ld1rqb z2.b, p0/z, [%[a_ptr], #0x20]\n" + ".inst 0x45c5987f // ummla z31.s, z3.b, z5.b\n" + "ld1b z5.b, p0/z, [%[b_ptr], #5, MUL VL]\n" + ".inst 0x45c69808 // ummla z8.s, z0.b, z6.b\n" + "ld1rqb z3.b, p0/z, [%[a_ptr], #0x30]\n" + ".inst 0x45c6982e // ummla z14.s, z1.b, z6.b\n" + "add %[a_ptr], %[a_ptr], #0x80\n" + ".inst 0x45c69854 // ummla z20.s, z2.b, z6.b\n" + "addvl %[b_ptr], %[b_ptr], #14\n" + ".inst 0x45c6987a // ummla z26.s, z3.b, z6.b\n" + ".inst 0x45c79809 // ummla z9.s, z0.b, z7.b\n" + ".inst 0x45c7982f // ummla z15.s, z1.b, z7.b\n" + "ld1b z6.b, p0/z, [%[b_ptr], #-8, MUL VL]\n" + ".inst 0x45c79855 // ummla z21.s, z2.b, z7.b\n" + ".inst 0x45c7987b // ummla z27.s, z3.b, z7.b\n" + "ld1b z7.b, p0/z, [%[b_ptr], #-7, MUL VL]\n" + ".inst 0x45c4980a // ummla z10.s, z0.b, z4.b\n" + ".inst 0x45c49830 // ummla z16.s, z1.b, z4.b\n" + ".inst 0x45c49856 // ummla z22.s, z2.b, z4.b\n" + ".inst 0x45c4987c // ummla z28.s, z3.b, z4.b\n" + "ld1b z4.b, p0/z, [%[b_ptr], #-6, MUL VL]\n" + ".inst 0x45c5980b // ummla z11.s, z0.b, z5.b\n" + ".inst 0x45c59831 // ummla z17.s, z1.b, z5.b\n" + ".inst 0x45c59857 // ummla z23.s, z2.b, z5.b\n" + ".inst 0x45c5987d // ummla z29.s, z3.b, z5.b\n" + "ld1b z5.b, p0/z, [%[b_ptr], #-5, MUL VL]\n" + ".inst 0x45c6980c // ummla z12.s, z0.b, z6.b\n" + ".inst 0x45c69832 // ummla z18.s, z1.b, z6.b\n" + ".inst 0x45c69858 // ummla z24.s, z2.b, z6.b\n" + ".inst 0x45c6987e // ummla z30.s, z3.b, z6.b\n" + "ld1b z6.b, p0/z, [%[b_ptr], #-4, MUL VL]\n" + ".inst 0x45c7980d // ummla z13.s, z0.b, z7.b\n" + "ld1rqb z0.b, p0/z, [%[a_ptr], #-0x40]\n" + ".inst 0x45c79833 // ummla z19.s, z1.b, z7.b\n" + "ld1rqb z1.b, p0/z, [%[a_ptr], #-0x30]\n" + ".inst 0x45c79859 // ummla z25.s, z2.b, z7.b\n" + "ld1rqb z2.b, p0/z, [%[a_ptr], #-0x20]\n" + ".inst 0x45c7987f // ummla z31.s, z3.b, z7.b\n" + "ld1b z7.b, p0/z, [%[b_ptr], #-3, MUL VL]\n" + ".inst 0x45c49808 // ummla z8.s, z0.b, z4.b\n" + "ld1rqb z3.b, p0/z, [%[a_ptr], #-0x10]\n" + ".inst 0x45c4982e // ummla z14.s, z1.b, z4.b\n" + ".inst 0x45c49854 // ummla z20.s, z2.b, z4.b\n" + ".inst 0x45c59809 // ummla z9.s, z0.b, z5.b\n" + ".inst 0x45c4987a // ummla z26.s, z3.b, z4.b\n" + "ld1b z4.b, p0/z, [%[b_ptr], #-2, MUL VL]\n" + ".inst 0x45c5982f // ummla z15.s, z1.b, z5.b\n" + ".inst 0x45c59855 // ummla z21.s, z2.b, z5.b\n" + ".inst 0x45c5987b // ummla z27.s, z3.b, z5.b\n" + "ld1b z5.b, p0/z, [%[b_ptr], #-1, MUL VL]\n" + ".inst 0x45c6980a // ummla z10.s, z0.b, z6.b\n" + ".inst 0x45c69830 // ummla z16.s, z1.b, z6.b\n" + ".inst 0x45c69856 // ummla z22.s, z2.b, z6.b\n" + ".inst 0x45c6987c // ummla z28.s, z3.b, z6.b\n" + "uzp1 z6.d, z14.d, z15.d\n" + ".inst 0x45c7980b // ummla z11.s, z0.b, z7.b\n" + ".inst 0x45c79831 // ummla z17.s, z1.b, z7.b\n" + ".inst 0x45c79857 // ummla z23.s, z2.b, z7.b\n" + ".inst 0x45c7987d // ummla z29.s, z3.b, z7.b\n" + ".inst 0x45c4980c // ummla z12.s, z0.b, z4.b\n" + "uzp1 z7.d, z16.d, z17.d\n" + ".inst 0x45c49832 // ummla z18.s, z1.b, z4.b\n" + ".inst 0x45c49858 // ummla z24.s, z2.b, z4.b\n" + ".inst 0x45c4987e // ummla z30.s, z3.b, z4.b\n" + "uzp2 z4.d, z10.d, z11.d\n" + ".inst 0x45c5980d // ummla z13.s, z0.b, z5.b\n" + "uzp1 z0.d, z8.d, z9.d\n" + ".inst 0x45c59833 // ummla z19.s, z1.b, z5.b\n" + "uzp1 z1.d, z10.d, z11.d\n" + ".inst 0x45c59859 // ummla z25.s, z2.b, z5.b\n" + "st1w z0.s, p0, [%[c_ptr]]\n" + "uzp1 z2.d, z12.d, z13.d\n" + "uzp1 z0.d, z18.d, z19.d\n" + ".inst 0x45c5987f // ummla z31.s, z3.b, z5.b\n" + "st1w z1.s, p0, [%[c_ptr], #1, MUL VL]\n" + "uzp2 z3.d, z8.d, z9.d\n" + "uzp2 z5.d, z12.d, z13.d\n" + "uzp2 z1.d, z14.d, z15.d\n" + "st1w z2.s, p0, [%[c_ptr], #2, MUL VL]\n" + "b 4f\n" + "3:\n" + ".inst 0x45c49808 // ummla z8.s, z0.b, z4.b\n" + "add %[a_ptr], %[a_ptr], #0x40\n" + ".inst 0x45c4982e // ummla z14.s, z1.b, z4.b\n" + "addvl %[b_ptr], %[b_ptr], #8\n" + ".inst 0x45c49854 // ummla z20.s, z2.b, z4.b\n" + ".inst 0x45c4987a // ummla z26.s, z3.b, z4.b\n" + ".inst 0x45c59809 // ummla z9.s, z0.b, z5.b\n" + "ld1b z4.b, p0/z, [%[b_ptr], #-8, MUL VL]\n" + ".inst 0x45c5982f // ummla z15.s, z1.b, z5.b\n" + ".inst 0x45c59855 // ummla z21.s, z2.b, z5.b\n" + ".inst 0x45c5987b // ummla z27.s, z3.b, z5.b\n" + "ld1b z5.b, p0/z, [%[b_ptr], #-7, MUL VL]\n" + ".inst 0x45c6980a // ummla z10.s, z0.b, z6.b\n" + ".inst 0x45c69830 // ummla z16.s, z1.b, z6.b\n" + ".inst 0x45c69856 // ummla z22.s, z2.b, z6.b\n" + ".inst 0x45c6987c // ummla z28.s, z3.b, z6.b\n" + "ld1b z6.b, p0/z, [%[b_ptr], #-6, MUL VL]\n" + ".inst 0x45c7980b // ummla z11.s, z0.b, z7.b\n" + ".inst 0x45c79831 // ummla z17.s, z1.b, z7.b\n" + ".inst 0x45c79857 // ummla z23.s, z2.b, z7.b\n" + ".inst 0x45c7987d // ummla z29.s, z3.b, z7.b\n" + "ld1b z7.b, p0/z, [%[b_ptr], #-5, MUL VL]\n" + ".inst 0x45c4980c // ummla z12.s, z0.b, z4.b\n" + ".inst 0x45c49832 // ummla z18.s, z1.b, z4.b\n" + ".inst 0x45c49858 // ummla z24.s, z2.b, z4.b\n" + ".inst 0x45c4987e // ummla z30.s, z3.b, z4.b\n" + "ld1b z4.b, p0/z, [%[b_ptr], #-4, MUL VL]\n" + ".inst 0x45c5980d // ummla z13.s, z0.b, z5.b\n" + "ld1rqb z0.b, p0/z, [%[a_ptr], #-0x40]\n" + ".inst 0x45c59833 // ummla z19.s, z1.b, z5.b\n" + "ld1rqb z1.b, p0/z, [%[a_ptr], #-0x30]\n" + ".inst 0x45c59859 // ummla z25.s, z2.b, z5.b\n" + "ld1rqb z2.b, p0/z, [%[a_ptr], #-0x20]\n" + ".inst 0x45c5987f // ummla z31.s, z3.b, z5.b\n" + "ld1b z5.b, p0/z, [%[b_ptr], #-3, MUL VL]\n" + ".inst 0x45c69808 // ummla z8.s, z0.b, z6.b\n" + "ld1rqb z3.b, p0/z, [%[a_ptr], #-0x10]\n" + ".inst 0x45c6982e // ummla z14.s, z1.b, z6.b\n" + ".inst 0x45c69854 // ummla z20.s, z2.b, z6.b\n" + ".inst 0x45c79809 // ummla z9.s, z0.b, z7.b\n" + ".inst 0x45c6987a // ummla z26.s, z3.b, z6.b\n" + "ld1b z6.b, p0/z, [%[b_ptr], #-2, MUL VL]\n" + ".inst 0x45c7982f // ummla z15.s, z1.b, z7.b\n" + ".inst 0x45c79855 // ummla z21.s, z2.b, z7.b\n" + ".inst 0x45c7987b // ummla z27.s, z3.b, z7.b\n" + "ld1b z7.b, p0/z, [%[b_ptr], #-1, MUL VL]\n" + ".inst 0x45c4980a // ummla z10.s, z0.b, z4.b\n" + ".inst 0x45c49830 // ummla z16.s, z1.b, z4.b\n" + ".inst 0x45c49856 // ummla z22.s, z2.b, z4.b\n" + ".inst 0x45c4987c // ummla z28.s, z3.b, z4.b\n" + ".inst 0x45c5980b // ummla z11.s, z0.b, z5.b\n" + ".inst 0x45c59831 // ummla z17.s, z1.b, z5.b\n" + ".inst 0x45c59857 // ummla z23.s, z2.b, z5.b\n" + ".inst 0x45c5987d // ummla z29.s, z3.b, z5.b\n" + "uzp2 z4.d, z10.d, z11.d\n" + ".inst 0x45c6980c // ummla z12.s, z0.b, z6.b\n" + ".inst 0x45c69832 // ummla z18.s, z1.b, z6.b\n" + ".inst 0x45c69858 // ummla z24.s, z2.b, z6.b\n" + ".inst 0x45c6987e // ummla z30.s, z3.b, z6.b\n" + "uzp1 z6.d, z14.d, z15.d\n" + ".inst 0x45c7980d // ummla z13.s, z0.b, z7.b\n" + "uzp1 z0.d, z8.d, z9.d\n" + ".inst 0x45c79833 // ummla z19.s, z1.b, z7.b\n" + "uzp1 z1.d, z10.d, z11.d\n" + "uzp2 z5.d, z12.d, z13.d\n" + "st1w z0.s, p0, [%[c_ptr]]\n" + ".inst 0x45c79859 // ummla z25.s, z2.b, z7.b\n" + "uzp1 z2.d, z12.d, z13.d\n" + "uzp1 z0.d, z18.d, z19.d\n" + "st1w z1.s, p0, [%[c_ptr], #1, MUL VL]\n" + "uzp2 z1.d, z14.d, z15.d\n" + ".inst 0x45c7987f // ummla z31.s, z3.b, z7.b\n" + "uzp2 z3.d, z8.d, z9.d\n" + "st1w z2.s, p0, [%[c_ptr], #2, MUL VL]\n" + "uzp1 z7.d, z16.d, z17.d\n" + "4:\n" + "uzp2 z2.d, z16.d, z17.d\n" + "st1w z3.s, p0, [%[c_ptr], #3, MUL VL]\n" + "uzp2 z3.d, z18.d, z19.d\n" + "st1w z4.s, p0, [%[c_ptr], #4, MUL VL]\n" + "uzp1 z4.d, z20.d, z21.d\n" + "st1w z5.s, p0, [%[c_ptr], #5, MUL VL]\n" + "uzp1 z5.d, z22.d, z23.d\n" + "st1w z6.s, p0, [%[c_ptr], #6, MUL VL]\n" + "uzp1 z6.d, z24.d, z25.d\n" + "st1w z7.s, p0, [%[c_ptr], #7, MUL VL]\n" + "addvl %[c_ptr], %[c_ptr], #16\n" + "uzp2 z7.d, z20.d, z21.d\n" + "st1w z0.s, p0, [%[c_ptr], #-8, MUL VL]\n" + "uzp2 z0.d, z22.d, z23.d\n" + "st1w z1.s, p0, [%[c_ptr], #-7, MUL VL]\n" + "uzp2 z1.d, z24.d, z25.d\n" + "st1w z2.s, p0, [%[c_ptr], #-6, MUL VL]\n" + "uzp1 z2.d, z26.d, z27.d\n" + "st1w z3.s, p0, [%[c_ptr], #-5, MUL VL]\n" + "uzp1 z3.d, z28.d, z29.d\n" + "st1w z4.s, p0, [%[c_ptr], #-4, MUL VL]\n" + "uzp1 z4.d, z30.d, z31.d\n" + "st1w z5.s, p0, [%[c_ptr], #-3, MUL VL]\n" + "uzp2 z5.d, z26.d, z27.d\n" + "st1w z6.s, p0, [%[c_ptr], #-2, MUL VL]\n" + "uzp2 z6.d, z28.d, z29.d\n" + "st1w z7.s, p0, [%[c_ptr], #-1, MUL VL]\n" + "uzp2 z7.d, z30.d, z31.d\n" + "st1w z0.s, p0, [%[c_ptr]]\n" + "st1w z1.s, p0, [%[c_ptr], #1, MUL VL]\n" + "st1w z2.s, p0, [%[c_ptr], #2, MUL VL]\n" + "st1w z3.s, p0, [%[c_ptr], #3, MUL VL]\n" + "st1w z4.s, p0, [%[c_ptr], #4, MUL VL]\n" + "st1w z5.s, p0, [%[c_ptr], #5, MUL VL]\n" + "st1w z6.s, p0, [%[c_ptr], #6, MUL VL]\n" + "st1w z7.s, p0, [%[c_ptr], #7, MUL VL]\n" + "addvl %[c_ptr], %[c_ptr], #8\n" + : [a_ptr] "+r" (a_ptr), [b_ptr] "+r" (b_ptr), [c_ptr] "+r" (c_ptr), + [loops] "+r" (loops), [tails] "+r" (tails) + : + : "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31", "cc", "memory" + ); + } + } +} + +} // namespace arm_gemm + +#endif // __ARM_FEATURE_SVE |