diff options
Diffstat (limited to 'src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_u8u32_mmla_3VLx8/generic.cpp')
| -rw-r--r-- | src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_u8u32_mmla_3VLx8/generic.cpp | 32 |
1 files changed, 17 insertions, 15 deletions
diff --git a/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_u8u32_mmla_3VLx8/generic.cpp b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_u8u32_mmla_3VLx8/generic.cpp index 15cc8fb897..81a1dbcf51 100644 --- a/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_u8u32_mmla_3VLx8/generic.cpp +++ b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_u8u32_mmla_3VLx8/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 Arm Limited. + * Copyright (c) 2019-2020 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -63,13 +63,11 @@ void sve_interleaved_u8u32_mmla_3VLx8(const uint8_t *Apanel, const uint8_t *Bpan "mov z16.s, #0\n" "ld1b z6.b, p0/z, [%[b_ptr], #2, MUL VL]\n" "mov z17.s, #0\n" - "ld1rqb z3.b, p0/z, [%[a_ptr], #0x30]\n" + "add %[a_ptr], %[a_ptr], #0x40\n" "mov z18.s, #0\n" - "ld1b z7.b, p0/z, [%[b_ptr], #3, MUL VL]\n" + "addvl %[b_ptr], %[b_ptr], #4\n" "mov z19.s, #0\n" - "add %[a_ptr], %[a_ptr], #0x40\n" "mov z20.s, #0\n" - "addvl %[b_ptr], %[b_ptr], #4\n" "mov z21.s, #0\n" "mov z22.s, #0\n" "mov z23.s, #0\n" @@ -84,12 +82,14 @@ void sve_interleaved_u8u32_mmla_3VLx8(const uint8_t *Apanel, const uint8_t *Bpan "cbz %[loops], 1f\n" "2:\n" ".inst 0x45c49808 // ummla z8.s, z0.b, z4.b\n" - "subs %[loops], %[loops], #0x1\n" + "ld1b z7.b, p0/z, [%[b_ptr], #-1, MUL VL]\n" ".inst 0x45c4982e // ummla z14.s, z1.b, z4.b\n" + "ld1rqb z3.b, p0/z, [%[a_ptr], #-0x10]\n" ".inst 0x45c49854 // ummla z20.s, z2.b, z4.b\n" + "subs %[loops], %[loops], #0x1\n" + ".inst 0x45c59809 // ummla z9.s, z0.b, z5.b\n" ".inst 0x45c4987a // ummla z26.s, z3.b, z4.b\n" "ld1b z4.b, p0/z, [%[b_ptr]]\n" - ".inst 0x45c59809 // ummla z9.s, z0.b, z5.b\n" ".inst 0x45c5982f // ummla z15.s, z1.b, z5.b\n" ".inst 0x45c59855 // ummla z21.s, z2.b, z5.b\n" ".inst 0x45c5987b // ummla z27.s, z3.b, z5.b\n" @@ -152,18 +152,18 @@ void sve_interleaved_u8u32_mmla_3VLx8(const uint8_t *Apanel, const uint8_t *Bpan ".inst 0x45c79859 // ummla z25.s, z2.b, z7.b\n" "ld1rqb z2.b, p0/z, [%[a_ptr], #-0x20]\n" ".inst 0x45c7987f // ummla z31.s, z3.b, z7.b\n" - "ld1b z7.b, p0/z, [%[b_ptr], #-1, MUL VL]\n" - "ld1rqb z3.b, p0/z, [%[a_ptr], #-0x10]\n" "b.ne 2b\n" "1:\n" "cbz %[tails], 3f\n" ".inst 0x45c49808 // ummla z8.s, z0.b, z4.b\n" + "ld1b z7.b, p0/z, [%[b_ptr], #-1, MUL VL]\n" ".inst 0x45c4982e // ummla z14.s, z1.b, z4.b\n" + "ld1rqb z3.b, p0/z, [%[a_ptr], #-0x10]\n" ".inst 0x45c49854 // ummla z20.s, z2.b, z4.b\n" - ".inst 0x45c4987a // ummla z26.s, z3.b, z4.b\n" - "ld1b z4.b, p0/z, [%[b_ptr]]\n" ".inst 0x45c59809 // ummla z9.s, z0.b, z5.b\n" ".inst 0x45c5982f // ummla z15.s, z1.b, z5.b\n" + ".inst 0x45c4987a // ummla z26.s, z3.b, z4.b\n" + "ld1b z4.b, p0/z, [%[b_ptr]]\n" ".inst 0x45c59855 // ummla z21.s, z2.b, z5.b\n" ".inst 0x45c5987b // ummla z27.s, z3.b, z5.b\n" "ld1b z5.b, p0/z, [%[b_ptr], #1, MUL VL]\n" @@ -269,15 +269,17 @@ void sve_interleaved_u8u32_mmla_3VLx8(const uint8_t *Apanel, const uint8_t *Bpan "b 4f\n" "3:\n" ".inst 0x45c49808 // ummla z8.s, z0.b, z4.b\n" - "add %[a_ptr], %[a_ptr], #0x40\n" + "ld1b z7.b, p0/z, [%[b_ptr], #-1, MUL VL]\n" ".inst 0x45c4982e // ummla z14.s, z1.b, z4.b\n" - "addvl %[b_ptr], %[b_ptr], #8\n" + "ld1rqb z3.b, p0/z, [%[a_ptr], #-0x10]\n" ".inst 0x45c49854 // ummla z20.s, z2.b, z4.b\n" - ".inst 0x45c4987a // ummla z26.s, z3.b, z4.b\n" + "add %[a_ptr], %[a_ptr], #0x40\n" ".inst 0x45c59809 // ummla z9.s, z0.b, z5.b\n" - "ld1b z4.b, p0/z, [%[b_ptr], #-8, MUL VL]\n" + "addvl %[b_ptr], %[b_ptr], #8\n" + ".inst 0x45c4987a // ummla z26.s, z3.b, z4.b\n" ".inst 0x45c5982f // ummla z15.s, z1.b, z5.b\n" ".inst 0x45c59855 // ummla z21.s, z2.b, z5.b\n" + "ld1b z4.b, p0/z, [%[b_ptr], #-8, MUL VL]\n" ".inst 0x45c5987b // ummla z27.s, z3.b, z5.b\n" "ld1b z5.b, p0/z, [%[b_ptr], #-7, MUL VL]\n" ".inst 0x45c6980a // ummla z10.s, z0.b, z6.b\n" |