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Diffstat (limited to 'src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_u8u32_dot_8x3VL/a64fx.cpp')
-rw-r--r--src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_u8u32_dot_8x3VL/a64fx.cpp70
1 files changed, 35 insertions, 35 deletions
diff --git a/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_u8u32_dot_8x3VL/a64fx.cpp b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_u8u32_dot_8x3VL/a64fx.cpp
index 1e2fb138fd..2bfec8f350 100644
--- a/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_u8u32_dot_8x3VL/a64fx.cpp
+++ b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_u8u32_dot_8x3VL/a64fx.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021 Arm Limited.
+ * Copyright (c) 2021, 2023 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -10,16 +10,16 @@
* sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
*/
#ifdef ARM_COMPUTE_ENABLE_SVE
@@ -33,34 +33,34 @@ void sve_interleaved_u8u32_dot_8x3VL_a64fx(
uint32_t *Cpanel, int ablocks, int bblocks, int K) {
struct KernelArgs {
- size_t bblocks = {};
size_t K = {};
const uint8_t *Bpanel = {};
+ size_t bblocks = {};
} ka;
- ka.bblocks = bblocks;
ka.K = (K/4) - 1;
ka.Bpanel = Bpanel;
+ ka.bblocks = bblocks;
__asm__ __volatile__(
"ptrue p0.b\n"
"1:" // Height loop
- "ldr x22, [%x[args_ptr], %[offsetof_bblocks]]\n"
+ "ldr x23, [%x[args_ptr], %[offsetof_bblocks]]\n"
+ "ldr x22, [%x[args_ptr], %[offsetof_Bpanel]]\n"
"mov x21, %x[Apanel]\n"
- "ldr x20, [%x[args_ptr], %[offsetof_Bpanel]]\n"
"2:" // Width loop
- "ldr x19, [%x[args_ptr], %[offsetof_K]]\n"
+ "ldr x20, [%x[args_ptr], %[offsetof_K]]\n"
"mov %x[Apanel], x21\n"
- "cmp x19, #0x2\n"
+ "cmp x20, #0x2\n"
"mov z8.s, #0x0\n"
"mov z9.s, #0x0\n"
- "ld1b { z0.b }, p0/Z, [x20]\n"
+ "ld1b { z0.b }, p0/Z, [x22]\n"
"mov z10.s, #0x0\n"
"mov z11.s, #0x0\n"
- "ld1b { z1.b }, p0/Z, [x20, #1, MUL VL]\n"
+ "ld1b { z1.b }, p0/Z, [x22, #1, MUL VL]\n"
"mov z12.s, #0x0\n"
"mov z13.s, #0x0\n"
- "ld1b { z2.b }, p0/Z, [x20, #2, MUL VL]\n"
+ "ld1b { z2.b }, p0/Z, [x22, #2, MUL VL]\n"
"mov z14.s, #0x0\n"
"mov z15.s, #0x0\n"
"ld1rw { z3.s }, p0/Z, [%x[Apanel]]\n"
@@ -87,7 +87,7 @@ void sve_interleaved_u8u32_dot_8x3VL_a64fx(
"3:" // main loop head
"udot z8.s, z0.b, z3.b\n"
"udot z9.s, z1.b, z3.b\n"
- "sub x19, x19, #0x2\n"
+ "sub x20, x20, #0x2\n"
"udot z10.s, z2.b, z3.b\n"
"ld1rw { z3.s }, p0/Z, [%x[Apanel], #16]\n"
"udot z11.s, z0.b, z4.b\n"
@@ -96,7 +96,7 @@ void sve_interleaved_u8u32_dot_8x3VL_a64fx(
"ld1rw { z4.s }, p0/Z, [%x[Apanel], #20]\n"
"udot z14.s, z0.b, z5.b\n"
"udot z15.s, z1.b, z5.b\n"
- "cmp x19, #0x2\n"
+ "cmp x20, #0x2\n"
"udot z16.s, z2.b, z5.b\n"
"ld1rw { z5.s }, p0/Z, [%x[Apanel], #24]\n"
"udot z17.s, z0.b, z6.b\n"
@@ -116,11 +116,11 @@ void sve_interleaved_u8u32_dot_8x3VL_a64fx(
"udot z28.s, z2.b, z5.b\n"
"ld1rw { z5.s }, p0/Z, [%x[Apanel], #40]\n"
"udot z29.s, z0.b, z6.b\n"
- "ld1b { z0.b }, p0/Z, [x20, #3, MUL VL]\n"
+ "ld1b { z0.b }, p0/Z, [x22, #3, MUL VL]\n"
"udot z30.s, z1.b, z6.b\n"
"udot z31.s, z2.b, z6.b\n"
- "ld1b { z1.b }, p0/Z, [x20, #4, MUL VL]\n"
- "ld1b { z2.b }, p0/Z, [x20, #5, MUL VL]\n"
+ "ld1b { z1.b }, p0/Z, [x22, #4, MUL VL]\n"
+ "ld1b { z2.b }, p0/Z, [x22, #5, MUL VL]\n"
"udot z8.s, z0.b, z3.b\n"
"ld1rw { z6.s }, p0/Z, [%x[Apanel], #44]\n"
"udot z9.s, z1.b, z3.b\n"
@@ -132,7 +132,7 @@ void sve_interleaved_u8u32_dot_8x3VL_a64fx(
"ld1rw { z4.s }, p0/Z, [%x[Apanel], #52]\n"
"udot z14.s, z0.b, z5.b\n"
"udot z15.s, z1.b, z5.b\n"
- "addvl x20, x20, #6\n"
+ "addvl x22, x22, #6\n"
"udot z16.s, z2.b, z5.b\n"
"ld1rw { z5.s }, p0/Z, [%x[Apanel], #56]\n"
"udot z17.s, z0.b, z6.b\n"
@@ -152,18 +152,18 @@ void sve_interleaved_u8u32_dot_8x3VL_a64fx(
"udot z27.s, z1.b, z5.b\n"
"udot z28.s, z2.b, z5.b\n"
"udot z29.s, z0.b, z6.b\n"
- "ld1b { z0.b }, p0/Z, [x20]\n"
+ "ld1b { z0.b }, p0/Z, [x22]\n"
"udot z30.s, z1.b, z6.b\n"
"udot z31.s, z2.b, z6.b\n"
- "ld1b { z1.b }, p0/Z, [x20, #1, MUL VL]\n"
- "ld1b { z2.b }, p0/Z, [x20, #2, MUL VL]\n"
+ "ld1b { z1.b }, p0/Z, [x22, #1, MUL VL]\n"
+ "ld1b { z2.b }, p0/Z, [x22, #2, MUL VL]\n"
"ld1rw { z5.s }, p0/Z, [%x[Apanel], #8]\n"
"ld1rw { z6.s }, p0/Z, [%x[Apanel], #12]\n"
"bge 3b\n"
"4:" // main loop skip
"udot z8.s, z0.b, z3.b\n"
"udot z9.s, z1.b, z3.b\n"
- "addvl x20, x20, #3\n"
+ "addvl x22, x22, #3\n"
"udot z10.s, z2.b, z3.b\n"
"ld1rw { z3.s }, p0/Z, [%x[Apanel], #16]\n"
"udot z11.s, z0.b, z4.b\n"
@@ -191,10 +191,10 @@ void sve_interleaved_u8u32_dot_8x3VL_a64fx(
"udot z29.s, z0.b, z6.b\n"
"udot z30.s, z1.b, z6.b\n"
"udot z31.s, z2.b, z6.b\n"
- "cbz x19, 5f\n"
- "ld1b { z0.b }, p0/Z, [x20]\n"
- "ld1b { z1.b }, p0/Z, [x20, #1, MUL VL]\n"
- "ld1b { z2.b }, p0/Z, [x20, #2, MUL VL]\n"
+ "cbz x20, 5f\n"
+ "ld1b { z0.b }, p0/Z, [x22]\n"
+ "ld1b { z1.b }, p0/Z, [x22, #1, MUL VL]\n"
+ "ld1b { z2.b }, p0/Z, [x22, #2, MUL VL]\n"
"ld1rw { z3.s }, p0/Z, [%x[Apanel]]\n"
"udot z8.s, z0.b, z3.b\n"
"ld1rw { z4.s }, p0/Z, [%x[Apanel], #4]\n"
@@ -203,24 +203,24 @@ void sve_interleaved_u8u32_dot_8x3VL_a64fx(
"ld1rw { z6.s }, p0/Z, [%x[Apanel], #12]\n"
"udot z10.s, z2.b, z3.b\n"
"udot z11.s, z0.b, z4.b\n"
- "ld1rw { z3.s }, p0/Z, [%x[Apanel], #16]\n"
"udot z12.s, z1.b, z4.b\n"
"udot z13.s, z2.b, z4.b\n"
- "ld1rw { z4.s }, p0/Z, [%x[Apanel], #20]\n"
+ "ld1rw { z3.s }, p0/Z, [%x[Apanel], #16]\n"
"udot z14.s, z0.b, z5.b\n"
"udot z15.s, z1.b, z5.b\n"
+ "ld1rw { z4.s }, p0/Z, [%x[Apanel], #20]\n"
"udot z16.s, z2.b, z5.b\n"
"udot z17.s, z0.b, z6.b\n"
"ld1rw { z5.s }, p0/Z, [%x[Apanel], #24]\n"
"udot z18.s, z1.b, z6.b\n"
"udot z19.s, z2.b, z6.b\n"
"ld1rw { z6.s }, p0/Z, [%x[Apanel], #28]\n"
- "addvl x20, x20, #3\n"
"udot z20.s, z0.b, z3.b\n"
"udot z21.s, z1.b, z3.b\n"
- "add %x[Apanel], %x[Apanel], #0x20\n"
+ "addvl x22, x22, #3\n"
"udot z22.s, z2.b, z3.b\n"
"udot z23.s, z0.b, z4.b\n"
+ "add %x[Apanel], %x[Apanel], #0x20\n"
"udot z24.s, z1.b, z4.b\n"
"udot z25.s, z2.b, z4.b\n"
"udot z26.s, z0.b, z5.b\n"
@@ -231,7 +231,7 @@ void sve_interleaved_u8u32_dot_8x3VL_a64fx(
"udot z31.s, z2.b, z6.b\n"
"5:" // multiply loop done
"st1w { z8.s }, p0, [%x[Cpanel]]\n"
- "subs x22, x22, #0x1\n"
+ "subs x23, x23, #0x1\n"
"st1w { z9.s }, p0, [%x[Cpanel], #1, MUL VL]\n"
"st1w { z10.s }, p0, [%x[Cpanel], #2, MUL VL]\n"
"st1w { z11.s }, p0, [%x[Cpanel], #3, MUL VL]\n"
@@ -262,7 +262,7 @@ void sve_interleaved_u8u32_dot_8x3VL_a64fx(
"bne 1b\n"
: [Apanel] "+&r" (Apanel), [Cpanel] "+&r" (Cpanel), [ablocks] "+&r" (ablocks)
: [args_ptr] "r" (&ka), [offsetof_Bpanel] "I" (offsetof(KernelArgs, Bpanel)), [offsetof_K] "I" (offsetof(KernelArgs, K)), [offsetof_bblocks] "I" (offsetof(KernelArgs, bblocks))
- : "cc", "memory", "p0", "x19", "x20", "x21", "x22", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31"
+ : "cc", "memory", "p0", "x20", "x21", "x22", "x23", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31"
);
}
generated by cgit v1.2.1 (git 2.23.0) at 2024-05-20 11:06:23 +0000