diff options
Diffstat (limited to 'src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_u8u32_dot_8x3VL.hpp')
-rw-r--r-- | src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_u8u32_dot_8x3VL.hpp | 118 |
1 files changed, 118 insertions, 0 deletions
diff --git a/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_u8u32_dot_8x3VL.hpp b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_u8u32_dot_8x3VL.hpp new file mode 100644 index 0000000000..c0b215ccb4 --- /dev/null +++ b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_u8u32_dot_8x3VL.hpp @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2019-2021, 2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#pragma once +#ifdef ARM_COMPUTE_ENABLE_SVE + +#include "../std_transforms_sve.hpp" +#include "../performance_parameters.hpp" + +#define ARGLIST \ + const uint8_t *, const uint8_t *, \ + uint32_t *, int, int, int + +namespace arm_gemm +{ +// Actual kernel implementations +void sve_interleaved_u8u32_dot_8x3VL( ARGLIST ); +void sve_interleaved_u8u32_dot_8x3VL_a64fx( ARGLIST ); + +class cls_sve_interleaved_u8u32_dot_8x3VL +{ +public: + typedef uint8_t operand_type; + typedef uint32_t result_type; + + typedef void (*kern_type)( ARGLIST ); + + /* Kernel blocking parameters */ + static constexpr unsigned int out_height() + { + return 8; + } + + static unsigned int out_width() + { + return get_vector_length<uint32_t>() * 3; + } + + static constexpr unsigned int k_unroll() + { + return 4; + } + + + StdTransformsSVE<operand_type, result_type, 8, 3, 4, 1> transforms = {}; + StdTransformsSVE<operand_type, result_type, 8, 3, 4, 1, true> transforms_quantized = {}; + template<typename T> + static inline PerformanceParameters get_performance_parameters(const CPUInfo *ci) + { + + if (std::is_same<T, uint32_t>::value) { + switch (ci->get_cpu_model()) { + default: + return { 31.66, 4.11, 7.94 }; + case CPUModel::A510: + return { 27.44, 3.41, 2.90 }; + case CPUModel::V1: + return { 63.30, 4.97, 11.52 }; + case CPUModel::A64FX: + return { 109.76, 3.88, 6.76 }; + } + } + + + if (std::is_same<T, uint8_t>::value) { + switch (ci->get_cpu_model()) { + default: + return { 31.67, 4.04, 0.50 }; + case CPUModel::A510: + return { 27.45, 1.65, 0.28 }; + case CPUModel::V1: + return { 52.24, 7.49, 0.80 }; + case CPUModel::A64FX: + return { 110.18, 2.34, 0.40 }; + } + } + + return { 1.0 }; + } + + // Default to the generic kernel + kern_type kernel=sve_interleaved_u8u32_dot_8x3VL; + cls_sve_interleaved_u8u32_dot_8x3VL(const CPUInfo *ci) + { + switch(ci->get_cpu_model()) { + default: + break; + case CPUModel::A64FX: + kernel=sve_interleaved_u8u32_dot_8x3VL_a64fx; + break; + } + } +}; + +} // namespace arm_gemm + +#undef ARGLIST +#endif // ARM_COMPUTE_ENABLE_SVE |