diff options
Diffstat (limited to 'src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp32_mla_8x3VL/generic.cpp')
| -rw-r--r-- | src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp32_mla_8x3VL/generic.cpp | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp32_mla_8x3VL/generic.cpp b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp32_mla_8x3VL/generic.cpp index c7f32ff7a9..43591e9201 100644 --- a/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp32_mla_8x3VL/generic.cpp +++ b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp32_mla_8x3VL/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2021, 2023 Arm Limited. + * Copyright (c) 2019-2021, 2023-2024 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -54,25 +54,25 @@ void sve_interleaved_fp32_mla_8x3VL( "2:" // Width loop "ldr x20, [%x[args_ptr], %[offsetof_K]]\n" "mov %x[Apanel], x21\n" - "cmp x20, #0x2\n" "mov z8.b, #0x0\n" "mov z9.b, #0x0\n" - "ld1rqw { z0.s }, p0/Z, [%x[Apanel]]\n" "mov z10.b, #0x0\n" + "ld1w { z4.s }, p0/Z, [x22]\n" "mov z11.b, #0x0\n" - "ld1rqw { z1.s }, p0/Z, [%x[Apanel], #16]\n" "mov z12.b, #0x0\n" + "ld1w { z5.s }, p0/Z, [x22, #1, MUL VL]\n" + "cmp x20, #0x2\n" "mov z13.b, #0x0\n" - "ld1w { z4.s }, p0/Z, [x22]\n" "mov z14.b, #0x0\n" "mov z15.b, #0x0\n" - "ld1w { z5.s }, p0/Z, [x22, #1, MUL VL]\n" "mov z16.b, #0x0\n" + "ld1rqw { z0.s }, p0/Z, [%x[Apanel]]\n" "mov z17.b, #0x0\n" - "ld1w { z6.s }, p0/Z, [x22, #2, MUL VL]\n" "mov z18.b, #0x0\n" + "ld1rqw { z1.s }, p0/Z, [%x[Apanel], #16]\n" "mov z19.b, #0x0\n" "mov z20.b, #0x0\n" + "ld1w { z6.s }, p0/Z, [x22, #2, MUL VL]\n" "mov z21.b, #0x0\n" "mov z22.b, #0x0\n" "mov z23.b, #0x0\n" @@ -150,12 +150,12 @@ void sve_interleaved_fp32_mla_8x3VL( "ld1w { z6.s }, p0/Z, [x22, #2, MUL VL]\n" "bge 3b\n" "4:" // main loop skip + "add %x[Apanel], %x[Apanel], #0x20\n" + "addvl x22, x22, #3\n" "fmla z8.s, z4.s, z0.s[0]\n" "fmla z11.s, z4.s, z0.s[1]\n" - "add %x[Apanel], %x[Apanel], #0x20\n" "fmla z14.s, z4.s, z0.s[2]\n" "fmla z17.s, z4.s, z0.s[3]\n" - "addvl x22, x22, #3\n" "fmla z20.s, z4.s, z1.s[0]\n" "fmla z23.s, z4.s, z1.s[1]\n" "fmla z26.s, z4.s, z1.s[2]\n" @@ -182,13 +182,13 @@ void sve_interleaved_fp32_mla_8x3VL( "add %x[Apanel], %x[Apanel], #0x20\n" "ld1w { z2.s }, p0/Z, [x22]\n" "ld1w { z1.s }, p0/Z, [x22, #1, MUL VL]\n" - "fmla z8.s, z2.s, z4.s[0]\n" "ld1w { z0.s }, p0/Z, [x22, #2, MUL VL]\n" + "addvl x22, x22, #3\n" + "fmla z8.s, z2.s, z4.s[0]\n" "fmla z11.s, z2.s, z4.s[1]\n" "fmla z14.s, z2.s, z4.s[2]\n" "fmla z17.s, z2.s, z4.s[3]\n" "fmla z20.s, z2.s, z3.s[0]\n" - "addvl x22, x22, #3\n" "fmla z23.s, z2.s, z3.s[1]\n" "fmla z26.s, z2.s, z3.s[2]\n" "fmla z29.s, z2.s, z3.s[3]\n" |