diff options
Diffstat (limited to 'src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp32_mla_8x3VL/a64fx.cpp')
| -rw-r--r-- | src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp32_mla_8x3VL/a64fx.cpp | 182 |
1 files changed, 93 insertions, 89 deletions
diff --git a/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp32_mla_8x3VL/a64fx.cpp b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp32_mla_8x3VL/a64fx.cpp index 3141a258a8..0b13913717 100644 --- a/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp32_mla_8x3VL/a64fx.cpp +++ b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp32_mla_8x3VL/a64fx.cpp @@ -28,8 +28,12 @@ namespace arm_gemm { void sve_interleaved_fp32_mla_8x3VL_a64fx( - const float *Apanel, const float *Bpanel, - float *Cpanel, int ablocks, int bblocks, int K) { + const float *Apanel, + const float *Bpanel, + float *Cpanel, + int ablocks, + int bblocks, + int K) { struct KernelArgs { size_t K = {}; @@ -88,7 +92,7 @@ void sve_interleaved_fp32_mla_8x3VL_a64fx( "fmla z9.s, p0/M, z1.s, z3.s\n" "sub x20, x20, #0x2\n" "fmla z10.s, p0/M, z2.s, z3.s\n" - "ld1rw { z3.s }, p0/Z, [%x[Apanel], #16]\n" + "ld1rw { z7.s }, p0/Z, [%x[Apanel], #16]\n" "fmla z11.s, p0/M, z0.s, z4.s\n" "fmla z12.s, p0/M, z1.s, z4.s\n" "fmla z13.s, p0/M, z2.s, z4.s\n" @@ -97,63 +101,63 @@ void sve_interleaved_fp32_mla_8x3VL_a64fx( "fmla z15.s, p0/M, z1.s, z5.s\n" "cmp x20, #0x2\n" "fmla z16.s, p0/M, z2.s, z5.s\n" - "ld1rw { z5.s }, p0/Z, [%x[Apanel], #24]\n" + "ld1rw { z3.s }, p0/Z, [%x[Apanel], #24]\n" "fmla z17.s, p0/M, z0.s, z6.s\n" "fmla z18.s, p0/M, z1.s, z6.s\n" "fmla z19.s, p0/M, z2.s, z6.s\n" - "ld1rw { z6.s }, p0/Z, [%x[Apanel], #28]\n" - "fmla z20.s, p0/M, z0.s, z3.s\n" - "fmla z21.s, p0/M, z1.s, z3.s\n" - "fmla z22.s, p0/M, z2.s, z3.s\n" - "ld1rw { z3.s }, p0/Z, [%x[Apanel], #32]\n" + "ld1rw { z5.s }, p0/Z, [%x[Apanel], #28]\n" + "fmla z20.s, p0/M, z0.s, z7.s\n" + "fmla z21.s, p0/M, z1.s, z7.s\n" + "fmla z22.s, p0/M, z2.s, z7.s\n" + "ld1rw { z7.s }, p0/Z, [%x[Apanel], #32]\n" "fmla z23.s, p0/M, z0.s, z4.s\n" "fmla z24.s, p0/M, z1.s, z4.s\n" "fmla z25.s, p0/M, z2.s, z4.s\n" "ld1rw { z4.s }, p0/Z, [%x[Apanel], #36]\n" - "fmla z26.s, p0/M, z0.s, z5.s\n" - "fmla z27.s, p0/M, z1.s, z5.s\n" - "fmla z28.s, p0/M, z2.s, z5.s\n" - "ld1rw { z5.s }, p0/Z, [%x[Apanel], #40]\n" - "fmla z29.s, p0/M, z0.s, z6.s\n" - "ld1w { z0.s }, p0/Z, [x22, #3, MUL VL]\n" - "fmla z30.s, p0/M, z1.s, z6.s\n" - "fmla z31.s, p0/M, z2.s, z6.s\n" - "ld1w { z1.s }, p0/Z, [x22, #4, MUL VL]\n" - "ld1w { z2.s }, p0/Z, [x22, #5, MUL VL]\n" - "fmla z8.s, p0/M, z0.s, z3.s\n" - "ld1rw { z6.s }, p0/Z, [%x[Apanel], #44]\n" - "fmla z9.s, p0/M, z1.s, z3.s\n" - "fmla z10.s, p0/M, z2.s, z3.s\n" - "fmla z11.s, p0/M, z0.s, z4.s\n" - "ld1rw { z3.s }, p0/Z, [%x[Apanel], #48]\n" - "fmla z12.s, p0/M, z1.s, z4.s\n" - "fmla z13.s, p0/M, z2.s, z4.s\n" + "fmla z26.s, p0/M, z0.s, z3.s\n" + "fmla z27.s, p0/M, z1.s, z3.s\n" + "fmla z28.s, p0/M, z2.s, z3.s\n" + "ld1rw { z3.s }, p0/Z, [%x[Apanel], #40]\n" + "fmla z29.s, p0/M, z0.s, z5.s\n" + "ld1w { z6.s }, p0/Z, [x22, #3, MUL VL]\n" + "fmla z30.s, p0/M, z1.s, z5.s\n" + "fmla z31.s, p0/M, z2.s, z5.s\n" + "ld1w { z2.s }, p0/Z, [x22, #4, MUL VL]\n" + "ld1w { z5.s }, p0/Z, [x22, #5, MUL VL]\n" + "fmla z8.s, p0/M, z6.s, z7.s\n" + "ld1rw { z1.s }, p0/Z, [%x[Apanel], #44]\n" + "fmla z9.s, p0/M, z2.s, z7.s\n" + "fmla z10.s, p0/M, z5.s, z7.s\n" + "fmla z11.s, p0/M, z6.s, z4.s\n" + "ld1rw { z7.s }, p0/Z, [%x[Apanel], #48]\n" + "fmla z12.s, p0/M, z2.s, z4.s\n" + "fmla z13.s, p0/M, z5.s, z4.s\n" "ld1rw { z4.s }, p0/Z, [%x[Apanel], #52]\n" - "fmla z14.s, p0/M, z0.s, z5.s\n" - "fmla z15.s, p0/M, z1.s, z5.s\n" + "fmla z14.s, p0/M, z6.s, z3.s\n" + "fmla z15.s, p0/M, z2.s, z3.s\n" "addvl x22, x22, #6\n" - "fmla z16.s, p0/M, z2.s, z5.s\n" - "ld1rw { z5.s }, p0/Z, [%x[Apanel], #56]\n" - "fmla z17.s, p0/M, z0.s, z6.s\n" - "fmla z18.s, p0/M, z1.s, z6.s\n" - "fmla z19.s, p0/M, z2.s, z6.s\n" - "ld1rw { z6.s }, p0/Z, [%x[Apanel], #60]\n" + "fmla z16.s, p0/M, z5.s, z3.s\n" + "ld1rw { z0.s }, p0/Z, [%x[Apanel], #56]\n" + "fmla z17.s, p0/M, z6.s, z1.s\n" + "fmla z18.s, p0/M, z2.s, z1.s\n" + "fmla z19.s, p0/M, z5.s, z1.s\n" + "ld1rw { z1.s }, p0/Z, [%x[Apanel], #60]\n" "add %x[Apanel], %x[Apanel], #0x40\n" - "fmla z20.s, p0/M, z0.s, z3.s\n" - "fmla z21.s, p0/M, z1.s, z3.s\n" - "fmla z22.s, p0/M, z2.s, z3.s\n" - "fmla z23.s, p0/M, z0.s, z4.s\n" + "fmla z20.s, p0/M, z6.s, z7.s\n" + "fmla z21.s, p0/M, z2.s, z7.s\n" + "fmla z22.s, p0/M, z5.s, z7.s\n" + "fmla z23.s, p0/M, z6.s, z4.s\n" "ld1rw { z3.s }, p0/Z, [%x[Apanel]]\n" - "fmla z24.s, p0/M, z1.s, z4.s\n" - "fmla z25.s, p0/M, z2.s, z4.s\n" + "fmla z24.s, p0/M, z2.s, z4.s\n" + "fmla z25.s, p0/M, z5.s, z4.s\n" "ld1rw { z4.s }, p0/Z, [%x[Apanel], #4]\n" - "fmla z26.s, p0/M, z0.s, z5.s\n" - "fmla z27.s, p0/M, z1.s, z5.s\n" - "fmla z28.s, p0/M, z2.s, z5.s\n" - "fmla z29.s, p0/M, z0.s, z6.s\n" + "fmla z26.s, p0/M, z6.s, z0.s\n" + "fmla z27.s, p0/M, z2.s, z0.s\n" + "fmla z28.s, p0/M, z5.s, z0.s\n" + "fmla z29.s, p0/M, z6.s, z1.s\n" "ld1w { z0.s }, p0/Z, [x22]\n" - "fmla z30.s, p0/M, z1.s, z6.s\n" - "fmla z31.s, p0/M, z2.s, z6.s\n" + "fmla z30.s, p0/M, z2.s, z1.s\n" + "fmla z31.s, p0/M, z5.s, z1.s\n" "ld1w { z1.s }, p0/Z, [x22, #1, MUL VL]\n" "ld1w { z2.s }, p0/Z, [x22, #2, MUL VL]\n" "ld1rw { z5.s }, p0/Z, [%x[Apanel], #8]\n" @@ -164,7 +168,7 @@ void sve_interleaved_fp32_mla_8x3VL_a64fx( "fmla z9.s, p0/M, z1.s, z3.s\n" "addvl x22, x22, #3\n" "fmla z10.s, p0/M, z2.s, z3.s\n" - "ld1rw { z3.s }, p0/Z, [%x[Apanel], #16]\n" + "ld1rw { z7.s }, p0/Z, [%x[Apanel], #16]\n" "fmla z11.s, p0/M, z0.s, z4.s\n" "fmla z12.s, p0/M, z1.s, z4.s\n" "fmla z13.s, p0/M, z2.s, z4.s\n" @@ -176,58 +180,58 @@ void sve_interleaved_fp32_mla_8x3VL_a64fx( "fmla z17.s, p0/M, z0.s, z6.s\n" "fmla z18.s, p0/M, z1.s, z6.s\n" "fmla z19.s, p0/M, z2.s, z6.s\n" - "ld1rw { z6.s }, p0/Z, [%x[Apanel], #28]\n" - "fmla z20.s, p0/M, z0.s, z3.s\n" - "fmla z21.s, p0/M, z1.s, z3.s\n" + "ld1rw { z3.s }, p0/Z, [%x[Apanel], #28]\n" + "fmla z20.s, p0/M, z0.s, z7.s\n" + "fmla z21.s, p0/M, z1.s, z7.s\n" "add %x[Apanel], %x[Apanel], #0x20\n" - "fmla z22.s, p0/M, z2.s, z3.s\n" + "fmla z22.s, p0/M, z2.s, z7.s\n" "fmla z23.s, p0/M, z0.s, z4.s\n" "fmla z24.s, p0/M, z1.s, z4.s\n" "fmla z25.s, p0/M, z2.s, z4.s\n" "fmla z26.s, p0/M, z0.s, z5.s\n" "fmla z27.s, p0/M, z1.s, z5.s\n" "fmla z28.s, p0/M, z2.s, z5.s\n" - "fmla z29.s, p0/M, z0.s, z6.s\n" - "fmla z30.s, p0/M, z1.s, z6.s\n" - "fmla z31.s, p0/M, z2.s, z6.s\n" + "fmla z29.s, p0/M, z0.s, z3.s\n" + "fmla z30.s, p0/M, z1.s, z3.s\n" + "fmla z31.s, p0/M, z2.s, z3.s\n" "cbz x20, 5f\n" - "ld1w { z0.s }, p0/Z, [x22]\n" - "ld1w { z1.s }, p0/Z, [x22, #1, MUL VL]\n" - "ld1w { z2.s }, p0/Z, [x22, #2, MUL VL]\n" + "ld1w { z6.s }, p0/Z, [x22]\n" + "ld1w { z5.s }, p0/Z, [x22, #1, MUL VL]\n" + "ld1w { z4.s }, p0/Z, [x22, #2, MUL VL]\n" "ld1rw { z3.s }, p0/Z, [%x[Apanel]]\n" - "fmla z8.s, p0/M, z0.s, z3.s\n" - "ld1rw { z4.s }, p0/Z, [%x[Apanel], #4]\n" - "ld1rw { z5.s }, p0/Z, [%x[Apanel], #8]\n" - "fmla z9.s, p0/M, z1.s, z3.s\n" - "ld1rw { z6.s }, p0/Z, [%x[Apanel], #12]\n" - "fmla z10.s, p0/M, z2.s, z3.s\n" - "fmla z11.s, p0/M, z0.s, z4.s\n" - "fmla z12.s, p0/M, z1.s, z4.s\n" - "fmla z13.s, p0/M, z2.s, z4.s\n" + "fmla z8.s, p0/M, z6.s, z3.s\n" + "ld1rw { z2.s }, p0/Z, [%x[Apanel], #4]\n" + "ld1rw { z1.s }, p0/Z, [%x[Apanel], #8]\n" + "fmla z9.s, p0/M, z5.s, z3.s\n" + "ld1rw { z0.s }, p0/Z, [%x[Apanel], #12]\n" + "fmla z10.s, p0/M, z4.s, z3.s\n" + "fmla z11.s, p0/M, z6.s, z2.s\n" + "fmla z12.s, p0/M, z5.s, z2.s\n" + "fmla z13.s, p0/M, z4.s, z2.s\n" "ld1rw { z3.s }, p0/Z, [%x[Apanel], #16]\n" - "fmla z14.s, p0/M, z0.s, z5.s\n" - "fmla z15.s, p0/M, z1.s, z5.s\n" - "ld1rw { z4.s }, p0/Z, [%x[Apanel], #20]\n" - "fmla z16.s, p0/M, z2.s, z5.s\n" - "fmla z17.s, p0/M, z0.s, z6.s\n" - "ld1rw { z5.s }, p0/Z, [%x[Apanel], #24]\n" - "fmla z18.s, p0/M, z1.s, z6.s\n" - "fmla z19.s, p0/M, z2.s, z6.s\n" - "ld1rw { z6.s }, p0/Z, [%x[Apanel], #28]\n" - "fmla z20.s, p0/M, z0.s, z3.s\n" - "fmla z21.s, p0/M, z1.s, z3.s\n" + "fmla z14.s, p0/M, z6.s, z1.s\n" + "fmla z15.s, p0/M, z5.s, z1.s\n" + "ld1rw { z2.s }, p0/Z, [%x[Apanel], #20]\n" + "fmla z16.s, p0/M, z4.s, z1.s\n" + "fmla z17.s, p0/M, z6.s, z0.s\n" + "ld1rw { z1.s }, p0/Z, [%x[Apanel], #24]\n" + "fmla z18.s, p0/M, z5.s, z0.s\n" + "fmla z19.s, p0/M, z4.s, z0.s\n" + "ld1rw { z0.s }, p0/Z, [%x[Apanel], #28]\n" + "fmla z20.s, p0/M, z6.s, z3.s\n" + "fmla z21.s, p0/M, z5.s, z3.s\n" "addvl x22, x22, #3\n" - "fmla z22.s, p0/M, z2.s, z3.s\n" - "fmla z23.s, p0/M, z0.s, z4.s\n" + "fmla z22.s, p0/M, z4.s, z3.s\n" + "fmla z23.s, p0/M, z6.s, z2.s\n" "add %x[Apanel], %x[Apanel], #0x20\n" - "fmla z24.s, p0/M, z1.s, z4.s\n" - "fmla z25.s, p0/M, z2.s, z4.s\n" - "fmla z26.s, p0/M, z0.s, z5.s\n" - "fmla z27.s, p0/M, z1.s, z5.s\n" - "fmla z28.s, p0/M, z2.s, z5.s\n" - "fmla z29.s, p0/M, z0.s, z6.s\n" - "fmla z30.s, p0/M, z1.s, z6.s\n" - "fmla z31.s, p0/M, z2.s, z6.s\n" + "fmla z24.s, p0/M, z5.s, z2.s\n" + "fmla z25.s, p0/M, z4.s, z2.s\n" + "fmla z26.s, p0/M, z6.s, z1.s\n" + "fmla z27.s, p0/M, z5.s, z1.s\n" + "fmla z28.s, p0/M, z4.s, z1.s\n" + "fmla z29.s, p0/M, z6.s, z0.s\n" + "fmla z30.s, p0/M, z5.s, z0.s\n" + "fmla z31.s, p0/M, z4.s, z0.s\n" "5:" // multiply loop done "st1w { z8.s }, p0, [%x[Cpanel]]\n" "subs x23, x23, #0x1\n" @@ -261,7 +265,7 @@ void sve_interleaved_fp32_mla_8x3VL_a64fx( "bne 1b\n" : [Apanel] "+&r" (Apanel), [Cpanel] "+&r" (Cpanel), [ablocks] "+&r" (ablocks) : [args_ptr] "r" (&ka), [offsetof_Bpanel] "I" (offsetof(KernelArgs, Bpanel)), [offsetof_K] "I" (offsetof(KernelArgs, K)), [offsetof_bblocks] "I" (offsetof(KernelArgs, bblocks)) - : "cc", "memory", "p0", "x20", "x21", "x22", "x23", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + : "cc", "memory", "p0", "x20", "x21", "x22", "x23", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" ); } |