diff options
Diffstat (limited to 'src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_bf16fp32_dot_8x3VL/generic.cpp')
| -rw-r--r-- | src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_bf16fp32_dot_8x3VL/generic.cpp | 78 |
1 files changed, 39 insertions, 39 deletions
diff --git a/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_bf16fp32_dot_8x3VL/generic.cpp b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_bf16fp32_dot_8x3VL/generic.cpp index e604dcc4bc..94452929c6 100644 --- a/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_bf16fp32_dot_8x3VL/generic.cpp +++ b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_bf16fp32_dot_8x3VL/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2021 Arm Limited. + * Copyright (c) 2019-2021, 2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -10,16 +10,16 @@ * sell copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. */ #ifdef ARM_COMPUTE_ENABLE_SVE @@ -33,42 +33,44 @@ void sve_interleaved_bf16fp32_dot_8x3VL( float *Cpanel, int ablocks, int bblocks, int K) { struct KernelArgs { - size_t bblocks = {}; size_t K = {}; const bfloat16 *Bpanel = {}; + size_t bblocks = {}; } ka; - ka.bblocks = bblocks; ka.K = (K/2) - 1; ka.Bpanel = Bpanel; + ka.bblocks = bblocks; __asm__ __volatile__( "ptrue p0.b\n" "1:" // Height loop - "ldr x22, [%x[args_ptr], %[offsetof_bblocks]]\n" + "ldr x23, [%x[args_ptr], %[offsetof_bblocks]]\n" + "ldr x22, [%x[args_ptr], %[offsetof_Bpanel]]\n" "mov x21, %x[Apanel]\n" - "ldr x20, [%x[args_ptr], %[offsetof_Bpanel]]\n" "2:" // Width loop + "ldr x20, [%x[args_ptr], %[offsetof_K]]\n" + "mov %x[Apanel], x21\n" + "cmp x20, #0x2\n" "mov z8.b, #0x0\n" "mov z9.b, #0x0\n" - "ldr x19, [%x[args_ptr], %[offsetof_K]]\n" + "ld1rqh { z0.h }, p0/Z, [%x[Apanel]]\n" "mov z10.b, #0x0\n" "mov z11.b, #0x0\n" - "ld1h { z4.h }, p0/Z, [x20]\n" + "ld1rqh { z1.h }, p0/Z, [%x[Apanel], #16]\n" "mov z12.b, #0x0\n" "mov z13.b, #0x0\n" - "mov %x[Apanel], x21\n" + "ld1h { z4.h }, p0/Z, [x22]\n" "mov z14.b, #0x0\n" "mov z15.b, #0x0\n" - "cmp x19, #0x2\n" + "ld1h { z5.h }, p0/Z, [x22, #1, MUL VL]\n" "mov z16.b, #0x0\n" "mov z17.b, #0x0\n" + "ld1h { z6.h }, p0/Z, [x22, #2, MUL VL]\n" "mov z18.b, #0x0\n" "mov z19.b, #0x0\n" - "ld1rqh { z0.h }, p0/Z, [%x[Apanel]]\n" "mov z20.b, #0x0\n" "mov z21.b, #0x0\n" - "ld1rqh { z1.h }, p0/Z, [%x[Apanel], #16]\n" "mov z22.b, #0x0\n" "mov z23.b, #0x0\n" "mov z24.b, #0x0\n" @@ -83,31 +85,29 @@ void sve_interleaved_bf16fp32_dot_8x3VL( "3:" // main loop head ".inst 0x64604088 // bfdot z8.s, z4.h, z0.h[0]\n" ".inst 0x6468408b // bfdot z11.s, z4.h, z0.h[1]\n" - "ld1h { z5.h }, p0/Z, [x20, #1, MUL VL]\n" + "ld1rqh { z2.h }, p0/Z, [%x[Apanel], #32]\n" ".inst 0x6470408e // bfdot z14.s, z4.h, z0.h[2]\n" ".inst 0x64784091 // bfdot z17.s, z4.h, z0.h[3]\n" - "ld1h { z6.h }, p0/Z, [x20, #2, MUL VL]\n" + "ld1rqh { z3.h }, p0/Z, [%x[Apanel], #48]\n" ".inst 0x64614094 // bfdot z20.s, z4.h, z1.h[0]\n" ".inst 0x64694097 // bfdot z23.s, z4.h, z1.h[1]\n" - "ld1rqh { z2.h }, p0/Z, [%x[Apanel], #32]\n" + "sub x20, x20, #0x2\n" ".inst 0x6471409a // bfdot z26.s, z4.h, z1.h[2]\n" ".inst 0x6479409d // bfdot z29.s, z4.h, z1.h[3]\n" - "ld1rqh { z3.h }, p0/Z, [%x[Apanel], #48]\n" + "ld1h { z4.h }, p0/Z, [x22, #3, MUL VL]\n" ".inst 0x646040a9 // bfdot z9.s, z5.h, z0.h[0]\n" ".inst 0x646840ac // bfdot z12.s, z5.h, z0.h[1]\n" - "ld1h { z4.h }, p0/Z, [x20, #3, MUL VL]\n" + "cmp x20, #0x2\n" ".inst 0x647040af // bfdot z15.s, z5.h, z0.h[2]\n" ".inst 0x647840b2 // bfdot z18.s, z5.h, z0.h[3]\n" - "sub x19, x19, #0x2\n" + "add %x[Apanel], %x[Apanel], #0x40\n" ".inst 0x646140b5 // bfdot z21.s, z5.h, z1.h[0]\n" ".inst 0x646940b8 // bfdot z24.s, z5.h, z1.h[1]\n" - "cmp x19, #0x2\n" ".inst 0x647140bb // bfdot z27.s, z5.h, z1.h[2]\n" ".inst 0x647940be // bfdot z30.s, z5.h, z1.h[3]\n" - "ld1h { z5.h }, p0/Z, [x20, #4, MUL VL]\n" + "ld1h { z5.h }, p0/Z, [x22, #4, MUL VL]\n" ".inst 0x646040ca // bfdot z10.s, z6.h, z0.h[0]\n" ".inst 0x646840cd // bfdot z13.s, z6.h, z0.h[1]\n" - "add %x[Apanel], %x[Apanel], #0x40\n" ".inst 0x647040d0 // bfdot z16.s, z6.h, z0.h[2]\n" ".inst 0x647840d3 // bfdot z19.s, z6.h, z0.h[3]\n" "ld1rqh { z0.h }, p0/Z, [%x[Apanel]]\n" @@ -115,26 +115,27 @@ void sve_interleaved_bf16fp32_dot_8x3VL( ".inst 0x646940d9 // bfdot z25.s, z6.h, z1.h[1]\n" ".inst 0x647140dc // bfdot z28.s, z6.h, z1.h[2]\n" ".inst 0x647940df // bfdot z31.s, z6.h, z1.h[3]\n" - "ld1h { z6.h }, p0/Z, [x20, #5, MUL VL]\n" + "ld1h { z6.h }, p0/Z, [x22, #5, MUL VL]\n" + "addvl x22, x22, #6\n" ".inst 0x64624088 // bfdot z8.s, z4.h, z2.h[0]\n" ".inst 0x646a408b // bfdot z11.s, z4.h, z2.h[1]\n" "ld1rqh { z1.h }, p0/Z, [%x[Apanel], #16]\n" ".inst 0x6472408e // bfdot z14.s, z4.h, z2.h[2]\n" ".inst 0x647a4091 // bfdot z17.s, z4.h, z2.h[3]\n" - "addvl x20, x20, #6\n" ".inst 0x64634094 // bfdot z20.s, z4.h, z3.h[0]\n" ".inst 0x646b4097 // bfdot z23.s, z4.h, z3.h[1]\n" ".inst 0x6473409a // bfdot z26.s, z4.h, z3.h[2]\n" ".inst 0x647b409d // bfdot z29.s, z4.h, z3.h[3]\n" + "ld1h { z4.h }, p0/Z, [x22]\n" ".inst 0x646240a9 // bfdot z9.s, z5.h, z2.h[0]\n" ".inst 0x646a40ac // bfdot z12.s, z5.h, z2.h[1]\n" - "ld1h { z4.h }, p0/Z, [x20]\n" ".inst 0x647240af // bfdot z15.s, z5.h, z2.h[2]\n" ".inst 0x647a40b2 // bfdot z18.s, z5.h, z2.h[3]\n" ".inst 0x646340b5 // bfdot z21.s, z5.h, z3.h[0]\n" ".inst 0x646b40b8 // bfdot z24.s, z5.h, z3.h[1]\n" ".inst 0x647340bb // bfdot z27.s, z5.h, z3.h[2]\n" ".inst 0x647b40be // bfdot z30.s, z5.h, z3.h[3]\n" + "ld1h { z5.h }, p0/Z, [x22, #1, MUL VL]\n" ".inst 0x646240ca // bfdot z10.s, z6.h, z2.h[0]\n" ".inst 0x646a40cd // bfdot z13.s, z6.h, z2.h[1]\n" ".inst 0x647240d0 // bfdot z16.s, z6.h, z2.h[2]\n" @@ -143,20 +144,19 @@ void sve_interleaved_bf16fp32_dot_8x3VL( ".inst 0x646b40d9 // bfdot z25.s, z6.h, z3.h[1]\n" ".inst 0x647340dc // bfdot z28.s, z6.h, z3.h[2]\n" ".inst 0x647b40df // bfdot z31.s, z6.h, z3.h[3]\n" + "ld1h { z6.h }, p0/Z, [x22, #2, MUL VL]\n" "bge 3b\n" "4:" // main loop skip ".inst 0x64604088 // bfdot z8.s, z4.h, z0.h[0]\n" ".inst 0x6468408b // bfdot z11.s, z4.h, z0.h[1]\n" - "ld1h { z5.h }, p0/Z, [x20, #1, MUL VL]\n" + "add %x[Apanel], %x[Apanel], #0x20\n" ".inst 0x6470408e // bfdot z14.s, z4.h, z0.h[2]\n" ".inst 0x64784091 // bfdot z17.s, z4.h, z0.h[3]\n" - "ld1h { z6.h }, p0/Z, [x20, #2, MUL VL]\n" + "addvl x22, x22, #3\n" ".inst 0x64614094 // bfdot z20.s, z4.h, z1.h[0]\n" ".inst 0x64694097 // bfdot z23.s, z4.h, z1.h[1]\n" - "add %x[Apanel], %x[Apanel], #0x20\n" ".inst 0x6471409a // bfdot z26.s, z4.h, z1.h[2]\n" ".inst 0x6479409d // bfdot z29.s, z4.h, z1.h[3]\n" - "addvl x20, x20, #3\n" ".inst 0x646040a9 // bfdot z9.s, z5.h, z0.h[0]\n" ".inst 0x646840ac // bfdot z12.s, z5.h, z0.h[1]\n" ".inst 0x647040af // bfdot z15.s, z5.h, z0.h[2]\n" @@ -173,19 +173,19 @@ void sve_interleaved_bf16fp32_dot_8x3VL( ".inst 0x646940d9 // bfdot z25.s, z6.h, z1.h[1]\n" ".inst 0x647140dc // bfdot z28.s, z6.h, z1.h[2]\n" ".inst 0x647940df // bfdot z31.s, z6.h, z1.h[3]\n" - "cbz x19, 5f\n" + "cbz x20, 5f\n" "ld1rqh { z0.h }, p0/Z, [%x[Apanel]]\n" "ld1rqh { z1.h }, p0/Z, [%x[Apanel], #16]\n" "add %x[Apanel], %x[Apanel], #0x20\n" - "ld1h { z7.h }, p0/Z, [x20]\n" - "ld1h { z4.h }, p0/Z, [x20, #1, MUL VL]\n" - "ld1h { z5.h }, p0/Z, [x20, #2, MUL VL]\n" - "addvl x20, x20, #3\n" + "ld1h { z7.h }, p0/Z, [x22]\n" + "ld1h { z4.h }, p0/Z, [x22, #1, MUL VL]\n" ".inst 0x646040e8 // bfdot z8.s, z7.h, z0.h[0]\n" + "ld1h { z5.h }, p0/Z, [x22, #2, MUL VL]\n" ".inst 0x646840eb // bfdot z11.s, z7.h, z0.h[1]\n" ".inst 0x647040ee // bfdot z14.s, z7.h, z0.h[2]\n" ".inst 0x647840f1 // bfdot z17.s, z7.h, z0.h[3]\n" ".inst 0x646140f4 // bfdot z20.s, z7.h, z1.h[0]\n" + "addvl x22, x22, #3\n" ".inst 0x646940f7 // bfdot z23.s, z7.h, z1.h[1]\n" ".inst 0x647140fa // bfdot z26.s, z7.h, z1.h[2]\n" ".inst 0x647940fd // bfdot z29.s, z7.h, z1.h[3]\n" @@ -207,7 +207,7 @@ void sve_interleaved_bf16fp32_dot_8x3VL( ".inst 0x647940bf // bfdot z31.s, z5.h, z1.h[3]\n" "5:" // multiply loop done "st1w { z8.s }, p0, [%x[Cpanel]]\n" - "subs x22, x22, #0x1\n" + "subs x23, x23, #0x1\n" "st1w { z9.s }, p0, [%x[Cpanel], #1, MUL VL]\n" "st1w { z10.s }, p0, [%x[Cpanel], #2, MUL VL]\n" "st1w { z11.s }, p0, [%x[Cpanel], #3, MUL VL]\n" @@ -238,7 +238,7 @@ void sve_interleaved_bf16fp32_dot_8x3VL( "bne 1b\n" : [Apanel] "+&r" (Apanel), [Cpanel] "+&r" (Cpanel), [ablocks] "+&r" (ablocks) : [args_ptr] "r" (&ka), [offsetof_Bpanel] "I" (offsetof(KernelArgs, Bpanel)), [offsetof_K] "I" (offsetof(KernelArgs, K)), [offsetof_bblocks] "I" (offsetof(KernelArgs, bblocks)) - : "cc", "memory", "p0", "x19", "x20", "x21", "x22", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + : "cc", "memory", "p0", "x20", "x21", "x22", "x23", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" ); } |