diff options
Diffstat (limited to 'src/core/NEON/kernels/arm_gemm/indirect-interleaves')
24 files changed, 1926 insertions, 1929 deletions
diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a32_interleave6_block1_fp32_fp32.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a32_interleave6_block1_fp32_fp32.hpp index 074299997d..807511f0d2 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a32_interleave6_block1_fp32_fp32.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a32_interleave6_block1_fp32_fp32.hpp @@ -22,9 +22,6 @@ * SOFTWARE. */ #pragma once -#if (defined(__GNUC__) && (__GNUC__ >= 7)) -#pragma GCC diagnostic ignored "-Wimplicit-fallthrough" -#endif #ifdef __arm__ diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave4_block16_s8_s8.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave4_block16_s8_s8.hpp index 8054c2b96b..6a8caf6ce6 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave4_block16_s8_s8.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave4_block16_s8_s8.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020 Arm Limited. + * Copyright (c) 2019-2021 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -58,19 +58,19 @@ void interleave_block<4, 16, VLType::None, false>( "blt 3f\n" "2:" // Main loop head "ldr q19, [x22], #0x10\n" - "prfm pldl1keep, [x22, #0x70]\n" + "subs %x[width], %x[width], #0x10\n" "ldr q18, [x21], #0x10\n" + "cmp %x[width], #0x10\n" "ldr q17, [x20], #0x10\n" - "prfm pldl1keep, [x21, #0x70]\n" "ldr q16, [x19], #0x10\n" + "prfm pldl1keep, [x22, #0x70]\n" + "prfm pldl1keep, [x21, #0x70]\n" "prfm pldl1keep, [x20, #0x70]\n" + "prfm pldl1keep, [x19, #0x70]\n" "str q19, [%x[out_ptr], #0x0]\n" "str q18, [%x[out_ptr], #0x10]\n" - "prfm pldl1keep, [x19, #0x70]\n" "str q17, [%x[out_ptr], #0x20]\n" "str q16, [%x[out_ptr], #0x30]\n" - "subs %x[width], %x[width], #0x10\n" - "cmp %x[width], #0x10\n" "add %x[out_ptr], %x[out_ptr], #0x40\n" "bge 2b\n" "3:" // Main loop skip @@ -171,7 +171,7 @@ void interleave_block<4, 16, VLType::None, false>( "add %x[out_ptr], %x[out_ptr], #0x40\n" "12:" // Odds skip - : [out_ptr] "+r" (out_ptr), [width] "+r" (width) + : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) : "cc", "memory", "v16", "v17", "v18", "v19", "x19", "x20", "x21", "x22" ); diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave4_block16_s8_s8_summing.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave4_block16_s8_s8_summing.hpp index 1650916f9f..954a86656e 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave4_block16_s8_s8_summing.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave4_block16_s8_s8_summing.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020 Arm Limited. + * Copyright (c) 2019-2021 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -84,24 +84,24 @@ void interleave_block<4, 16, VLType::None, true>( "mov x22, #0x0\n" "4:" // no_accumulate_16 "ldr q19, [x23], #0x10\n" - "prfm pldl1keep, [x23, #0x70]\n" + "add x22, x22, #0x1\n" "ldr q18, [x21], #0x10\n" + "subs %x[width], %x[width], #0x10\n" "ldr q17, [x20], #0x10\n" - "prfm pldl1keep, [x21, #0x70]\n" + "cmp %x[width], #0x10\n" "ldr q16, [x19], #0x10\n" - "prfm pldl1keep, [x20, #0x70]\n" - "str q19, [%x[out_ptr], #0x0]\n" "sadalp v28.8h, v19.16b\n" + "prfm pldl1keep, [x23, #0x70]\n" + "prfm pldl1keep, [x21, #0x70]\n" + "sadalp v27.8h, v18.16b\n" + "prfm pldl1keep, [x20, #0x70]\n" + "sadalp v26.8h, v17.16b\n" "prfm pldl1keep, [x19, #0x70]\n" + "sadalp v25.8h, v16.16b\n" + "str q19, [%x[out_ptr], #0x0]\n" "str q18, [%x[out_ptr], #0x10]\n" - "sadalp v27.8h, v18.16b\n" "str q17, [%x[out_ptr], #0x20]\n" - "sadalp v26.8h, v17.16b\n" "str q16, [%x[out_ptr], #0x30]\n" - "sadalp v25.8h, v16.16b\n" - "add x22, x22, #0x1\n" - "subs %x[width], %x[width], #0x10\n" - "cmp %x[width], #0x10\n" "add %x[out_ptr], %x[out_ptr], #0x40\n" "bge 3b\n" "5:" // Main loop skip @@ -215,7 +215,7 @@ void interleave_block<4, 16, VLType::None, true>( "add v24.4s, v24.4s, v20.4s\n" "str q24, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" - : [out_ptr] "+r" (out_ptr), [width] "+r" (width) + : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [first] "r" (first), [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "x19", "x20", "x21", "x22", "x23" ); diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave4_block16_u8_u8_summing.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave4_block16_u8_u8_summing.hpp index af3efb25b2..c81146212c 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave4_block16_u8_u8_summing.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave4_block16_u8_u8_summing.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020 Arm Limited. + * Copyright (c) 2019-2021 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -84,24 +84,24 @@ void interleave_block<4, 16, VLType::None, true>( "mov x22, #0x0\n" "4:" // no_accumulate_16 "ldr q19, [x23], #0x10\n" - "prfm pldl1keep, [x23, #0x70]\n" + "add x22, x22, #0x1\n" "ldr q18, [x21], #0x10\n" + "subs %x[width], %x[width], #0x10\n" "ldr q17, [x20], #0x10\n" - "prfm pldl1keep, [x21, #0x70]\n" + "cmp %x[width], #0x10\n" "ldr q16, [x19], #0x10\n" - "prfm pldl1keep, [x20, #0x70]\n" - "str q19, [%x[out_ptr], #0x0]\n" "uadalp v28.8h, v19.16b\n" + "prfm pldl1keep, [x23, #0x70]\n" + "prfm pldl1keep, [x21, #0x70]\n" + "uadalp v27.8h, v18.16b\n" + "prfm pldl1keep, [x20, #0x70]\n" + "uadalp v26.8h, v17.16b\n" "prfm pldl1keep, [x19, #0x70]\n" + "uadalp v25.8h, v16.16b\n" + "str q19, [%x[out_ptr], #0x0]\n" "str q18, [%x[out_ptr], #0x10]\n" - "uadalp v27.8h, v18.16b\n" "str q17, [%x[out_ptr], #0x20]\n" - "uadalp v26.8h, v17.16b\n" "str q16, [%x[out_ptr], #0x30]\n" - "uadalp v25.8h, v16.16b\n" - "add x22, x22, #0x1\n" - "subs %x[width], %x[width], #0x10\n" - "cmp %x[width], #0x10\n" "add %x[out_ptr], %x[out_ptr], #0x40\n" "bge 3b\n" "5:" // Main loop skip @@ -215,7 +215,7 @@ void interleave_block<4, 16, VLType::None, true>( "add v24.4s, v24.4s, v20.4s\n" "str q24, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" - : [out_ptr] "+r" (out_ptr), [width] "+r" (width) + : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [first] "r" (first), [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "x19", "x20", "x21", "x22", "x23" ); diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_bf16_fp32.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_bf16_fp32.hpp index 34d25f27b8..42574295f1 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_bf16_fp32.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_bf16_fp32.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020 Arm Limited. + * Copyright (c) 2019-2021 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -31,7 +31,7 @@ void interleave_block<8, 1, VLType::None, false>( ) { __asm__ __volatile__( - "movi v29.8h, #0x0\n" + "movi v30.8h, #0x0\n" "ldr x27, [%x[in], #0x0]\n" "cmp %x[height], #0x8\n" "ldr x26, [%x[in], #0x8]\n" @@ -80,53 +80,53 @@ void interleave_block<8, 1, VLType::None, false>( "prfm pldl1keep, [x20, #0x40]\n" "blt 3f\n" "2:" // Main loop head - "ldr d28, [x27], #0x8\n" - "zip1 v28.8h, v29.8h, v28.8h\n" + "ldr d29, [x27], #0x8\n" + "zip1 v29.8h, v30.8h, v29.8h\n" + "ldr d28, [x26], #0x8\n" + "subs %x[width], %x[width], #0x4\n" + "zip1 v28.8h, v30.8h, v28.8h\n" + "ldr d24, [x25], #0x8\n" + "cmp %x[width], #0x4\n" + "zip1 v24.8h, v30.8h, v24.8h\n" + "ldr d27, [x24], #0x8\n" + "ldr d26, [x23], #0x8\n" + "zip1 v25.4s, v29.4s, v24.4s\n" + "zip2 v24.4s, v29.4s, v24.4s\n" + "ldr d23, [x22], #0x8\n" + "ldr d22, [x21], #0x8\n" + "zip1 v27.8h, v30.8h, v27.8h\n" + "ldr d21, [x20], #0x8\n" + "zip1 v26.8h, v30.8h, v26.8h\n" "prfm pldl1keep, [x27, #0x70]\n" - "ldr d27, [x26], #0x8\n" - "zip1 v27.8h, v29.8h, v27.8h\n" + "zip1 v20.4s, v28.4s, v27.4s\n" "prfm pldl1keep, [x26, #0x70]\n" - "ldr d26, [x25], #0x8\n" - "zip1 v26.8h, v29.8h, v26.8h\n" + "zip1 v23.8h, v30.8h, v23.8h\n" "prfm pldl1keep, [x25, #0x70]\n" - "ldr d25, [x24], #0x8\n" - "zip1 v20.4s, v28.4s, v26.4s\n" + "zip1 v22.8h, v30.8h, v22.8h\n" "prfm pldl1keep, [x24, #0x70]\n" - "zip1 v25.8h, v29.8h, v25.8h\n" - "ldr d24, [x23], #0x8\n" - "zip1 v19.4s, v27.4s, v25.4s\n" + "zip1 v21.8h, v30.8h, v21.8h\n" "prfm pldl1keep, [x23, #0x70]\n" - "zip1 v24.8h, v29.8h, v24.8h\n" - "ldr d23, [x22], #0x8\n" - "zip1 v16.4s, v20.4s, v19.4s\n" + "zip1 v17.4s, v25.4s, v20.4s\n" "prfm pldl1keep, [x22, #0x70]\n" - "zip1 v23.8h, v29.8h, v23.8h\n" - "ldr d22, [x21], #0x8\n" - "zip2 v19.4s, v20.4s, v19.4s\n" + "zip1 v19.4s, v26.4s, v22.4s\n" "prfm pldl1keep, [x21, #0x70]\n" - "zip1 v22.8h, v29.8h, v22.8h\n" - "ldr d21, [x20], #0x8\n" - "zip1 v18.4s, v24.4s, v22.4s\n" + "zip1 v18.4s, v23.4s, v21.4s\n" "prfm pldl1keep, [x20, #0x70]\n" - "zip1 v21.8h, v29.8h, v21.8h\n" - "str q16, [%x[out_ptr], #0x0]\n" - "zip1 v17.4s, v23.4s, v21.4s\n" - "subs %x[width], %x[width], #0x4\n" - "zip2 v20.4s, v28.4s, v26.4s\n" - "cmp %x[width], #0x4\n" - "zip1 v16.4s, v18.4s, v17.4s\n" + "zip1 v16.4s, v19.4s, v18.4s\n" + "str q17, [%x[out_ptr], #0x0]\n" + "zip2 v17.4s, v25.4s, v20.4s\n" "str q16, [%x[out_ptr], #0x10]\n" - "zip2 v16.4s, v18.4s, v17.4s\n" - "str q19, [%x[out_ptr], #0x20]\n" - "zip2 v19.4s, v27.4s, v25.4s\n" + "zip2 v16.4s, v19.4s, v18.4s\n" + "str q17, [%x[out_ptr], #0x20]\n" + "zip2 v19.4s, v28.4s, v27.4s\n" "str q16, [%x[out_ptr], #0x30]\n" - "zip1 v16.4s, v20.4s, v19.4s\n" + "zip1 v16.4s, v24.4s, v19.4s\n" "str q16, [%x[out_ptr], #0x40]\n" - "zip2 v18.4s, v24.4s, v22.4s\n" + "zip2 v18.4s, v26.4s, v22.4s\n" "zip2 v17.4s, v23.4s, v21.4s\n" "zip1 v16.4s, v18.4s, v17.4s\n" "str q16, [%x[out_ptr], #0x50]\n" - "zip2 v16.4s, v20.4s, v19.4s\n" + "zip2 v16.4s, v24.4s, v19.4s\n" "str q16, [%x[out_ptr], #0x60]\n" "zip2 v16.4s, v18.4s, v17.4s\n" "str q16, [%x[out_ptr], #0x70]\n" @@ -135,77 +135,77 @@ void interleave_block<8, 1, VLType::None, false>( "3:" // Main loop skip "cbz %x[width], 6f\n" "tbz %x[width], #1, 4f\n" - "ldr s28, [x27], #0x4\n" - "ldr s27, [x26], #0x4\n" - "ldr s26, [x25], #0x4\n" - "ldr s25, [x24], #0x4\n" - "ldr s24, [x23], #0x4\n" + "ldr s29, [x27], #0x4\n" + "ldr s28, [x26], #0x4\n" + "mov x19, #0x2\n" + "ldr s24, [x25], #0x4\n" + "ldr s27, [x24], #0x4\n" + "ldr s26, [x23], #0x4\n" "ldr s23, [x22], #0x4\n" "ldr s22, [x21], #0x4\n" "ldr s21, [x20], #0x4\n" - "mov x19, #0x2\n" "tbz %x[width], #0, 5f\n" - "ld1 { v28.h }[2], [x27]\n" - "ld1 { v27.h }[2], [x26]\n" - "ld1 { v26.h }[2], [x25]\n" - "ld1 { v25.h }[2], [x24]\n" - "ld1 { v24.h }[2], [x23]\n" + "ld1 { v29.h }[2], [x27]\n" + "mov x19, #0x3\n" + "ld1 { v28.h }[2], [x26]\n" + "ld1 { v24.h }[2], [x25]\n" + "ld1 { v27.h }[2], [x24]\n" + "ld1 { v26.h }[2], [x23]\n" "ld1 { v23.h }[2], [x22]\n" "ld1 { v22.h }[2], [x21]\n" "ld1 { v21.h }[2], [x20]\n" - "mov x19, #0x3\n" "b 5f\n" "4:" // odd_loads_1_0 - "ldr h28, [x27, #0x0]\n" - "ldr h27, [x26, #0x0]\n" - "ldr h26, [x25, #0x0]\n" - "ldr h25, [x24, #0x0]\n" - "ldr h24, [x23, #0x0]\n" + "ldr h29, [x27, #0x0]\n" + "mov x19, #0x1\n" + "ldr h28, [x26, #0x0]\n" + "ldr h24, [x25, #0x0]\n" + "ldr h27, [x24, #0x0]\n" + "ldr h26, [x23, #0x0]\n" "ldr h23, [x22, #0x0]\n" "ldr h22, [x21, #0x0]\n" "ldr h21, [x20, #0x0]\n" - "mov x19, #0x1\n" "5:" // Odd load end - "zip1 v28.8h, v29.8h, v28.8h\n" + "zip1 v29.8h, v30.8h, v29.8h\n" "subs x19, x19, #0x1\n" - "zip1 v27.8h, v29.8h, v27.8h\n" - "zip1 v26.8h, v29.8h, v26.8h\n" - "zip1 v25.8h, v29.8h, v25.8h\n" - "zip1 v24.8h, v29.8h, v24.8h\n" - "zip1 v23.8h, v29.8h, v23.8h\n" - "zip1 v22.8h, v29.8h, v22.8h\n" - "zip1 v21.8h, v29.8h, v21.8h\n" - "zip1 v20.4s, v28.4s, v26.4s\n" - "zip1 v19.4s, v27.4s, v25.4s\n" - "zip1 v16.4s, v20.4s, v19.4s\n" - "str q16, [%x[out_ptr], #0x0]\n" - "zip1 v18.4s, v24.4s, v22.4s\n" - "zip1 v17.4s, v23.4s, v21.4s\n" - "zip1 v16.4s, v18.4s, v17.4s\n" + "zip1 v28.8h, v30.8h, v28.8h\n" + "zip1 v24.8h, v30.8h, v24.8h\n" + "zip1 v27.8h, v30.8h, v27.8h\n" + "zip1 v26.8h, v30.8h, v26.8h\n" + "zip1 v23.8h, v30.8h, v23.8h\n" + "zip1 v22.8h, v30.8h, v22.8h\n" + "zip1 v21.8h, v30.8h, v21.8h\n" + "zip1 v25.4s, v29.4s, v24.4s\n" + "zip1 v20.4s, v28.4s, v27.4s\n" + "zip1 v17.4s, v25.4s, v20.4s\n" + "str q17, [%x[out_ptr], #0x0]\n" + "zip1 v19.4s, v26.4s, v22.4s\n" + "zip1 v18.4s, v23.4s, v21.4s\n" + "zip1 v16.4s, v19.4s, v18.4s\n" "str q16, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "beq 6f\n" - "zip2 v19.4s, v20.4s, v19.4s\n" - "zip2 v16.4s, v18.4s, v17.4s\n" - "str q19, [%x[out_ptr], #0x0]\n" - "str q16, [%x[out_ptr], #0x10]\n" + "zip2 v17.4s, v25.4s, v20.4s\n" + "str q17, [%x[out_ptr], #0x0]\n" + "zip2 v16.4s, v19.4s, v18.4s\n" "subs x19, x19, #0x1\n" + "str q16, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "beq 6f\n" - "zip2 v20.4s, v28.4s, v26.4s\n" - "zip2 v19.4s, v27.4s, v25.4s\n" - "zip1 v16.4s, v20.4s, v19.4s\n" + "zip2 v24.4s, v29.4s, v24.4s\n" + "zip2 v19.4s, v28.4s, v27.4s\n" + "zip1 v16.4s, v24.4s, v19.4s\n" "str q16, [%x[out_ptr], #0x0]\n" - "zip2 v18.4s, v24.4s, v22.4s\n" + "zip2 v18.4s, v26.4s, v22.4s\n" "zip2 v17.4s, v23.4s, v21.4s\n" "zip1 v16.4s, v18.4s, v17.4s\n" "str q16, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "6:" // Odds skip - : [out_ptr] "+r" (out_ptr), [width] "+r" (width) + : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) - : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" + : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); } diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_fp16_fp16.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_fp16_fp16.hpp index d547957129..62d1657a9a 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_fp16_fp16.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_fp16_fp16.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020 Arm Limited. + * Copyright (c) 2019-2021 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -80,51 +80,51 @@ void interleave_block<8, 1, VLType::None, false>( "blt 3f\n" "2:" // Main loop head "ldr q30, [x27], #0x10\n" - "prfm pldl1keep, [x27, #0x70]\n" + "subs %x[width], %x[width], #0x8\n" "ldr q29, [x26], #0x10\n" + "cmp %x[width], #0x8\n" "ldr q28, [x25], #0x10\n" - "prfm pldl1keep, [x26, #0x70]\n" "ldr q27, [x24], #0x10\n" + "ldr q25, [x23], #0x10\n" + "zip1 v26.8h, v30.8h, v25.8h\n" + "ldr q21, [x22], #0x10\n" + "zip2 v25.8h, v30.8h, v25.8h\n" + "ldr q24, [x21], #0x10\n" + "ldr q23, [x20], #0x10\n" + "zip1 v22.8h, v29.8h, v21.8h\n" + "prfm pldl1keep, [x27, #0x70]\n" + "zip2 v21.8h, v29.8h, v21.8h\n" + "prfm pldl1keep, [x26, #0x70]\n" + "zip1 v20.8h, v28.8h, v24.8h\n" "prfm pldl1keep, [x25, #0x70]\n" - "ldr q24, [x23], #0x10\n" - "zip1 v26.8h, v30.8h, v24.8h\n" + "zip1 v18.8h, v26.8h, v20.8h\n" "prfm pldl1keep, [x24, #0x70]\n" - "ldr q25, [x22], #0x10\n" - "zip2 v24.8h, v30.8h, v24.8h\n" + "zip1 v19.8h, v27.8h, v23.8h\n" "prfm pldl1keep, [x23, #0x70]\n" - "ldr q23, [x21], #0x10\n" - "zip1 v21.8h, v29.8h, v25.8h\n" + "zip1 v16.8h, v22.8h, v19.8h\n" "prfm pldl1keep, [x22, #0x70]\n" - "ldr q22, [x20], #0x10\n" - "zip1 v18.8h, v28.8h, v23.8h\n" + "zip1 v17.8h, v18.8h, v16.8h\n" "prfm pldl1keep, [x21, #0x70]\n" - "subs %x[width], %x[width], #0x8\n" - "zip1 v20.8h, v26.8h, v18.8h\n" + "zip2 v16.8h, v18.8h, v16.8h\n" "prfm pldl1keep, [x20, #0x70]\n" - "zip1 v19.8h, v27.8h, v22.8h\n" - "cmp %x[width], #0x8\n" - "zip1 v17.8h, v21.8h, v19.8h\n" - "zip2 v18.8h, v26.8h, v18.8h\n" - "zip1 v16.8h, v20.8h, v17.8h\n" - "str q16, [%x[out_ptr], #0x0]\n" - "zip2 v16.8h, v20.8h, v17.8h\n" + "zip2 v18.8h, v26.8h, v20.8h\n" + "str q17, [%x[out_ptr], #0x0]\n" + "zip2 v17.8h, v22.8h, v19.8h\n" "str q16, [%x[out_ptr], #0x10]\n" - "zip2 v17.8h, v21.8h, v19.8h\n" "zip1 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x20]\n" "zip2 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x30]\n" - "zip2 v21.8h, v28.8h, v23.8h\n" - "zip1 v18.8h, v24.8h, v21.8h\n" - "zip2 v20.8h, v29.8h, v25.8h\n" - "zip2 v19.8h, v27.8h, v22.8h\n" - "zip1 v17.8h, v20.8h, v19.8h\n" + "zip2 v20.8h, v28.8h, v24.8h\n" + "zip1 v18.8h, v25.8h, v20.8h\n" + "zip2 v19.8h, v27.8h, v23.8h\n" + "zip1 v17.8h, v21.8h, v19.8h\n" "zip1 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x40]\n" "zip2 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x50]\n" - "zip2 v18.8h, v24.8h, v21.8h\n" - "zip2 v17.8h, v20.8h, v19.8h\n" + "zip2 v18.8h, v25.8h, v20.8h\n" + "zip2 v17.8h, v21.8h, v19.8h\n" "zip1 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x60]\n" "zip2 v16.8h, v18.8h, v17.8h\n" @@ -138,129 +138,129 @@ void interleave_block<8, 1, VLType::None, false>( "ldr d29, [x26], #0x8\n" "ldr d28, [x25], #0x8\n" "ldr d27, [x24], #0x8\n" - "ldr d24, [x23], #0x8\n" - "ldr d25, [x22], #0x8\n" - "ldr d23, [x21], #0x8\n" - "ldr d22, [x20], #0x8\n" + "ldr d25, [x23], #0x8\n" + "ldr d21, [x22], #0x8\n" + "ldr d24, [x21], #0x8\n" + "ldr d23, [x20], #0x8\n" "tbz %x[width], #1, 4f\n" "ld1 { v30.s }[2], [x27], #0x4\n" + "mov x19, #0x6\n" "ld1 { v29.s }[2], [x26], #0x4\n" "ld1 { v28.s }[2], [x25], #0x4\n" "ld1 { v27.s }[2], [x24], #0x4\n" - "ld1 { v24.s }[2], [x23], #0x4\n" - "ld1 { v25.s }[2], [x22], #0x4\n" - "ld1 { v23.s }[2], [x21], #0x4\n" - "ld1 { v22.s }[2], [x20], #0x4\n" - "mov x19, #0x6\n" + "ld1 { v25.s }[2], [x23], #0x4\n" + "ld1 { v21.s }[2], [x22], #0x4\n" + "ld1 { v24.s }[2], [x21], #0x4\n" + "ld1 { v23.s }[2], [x20], #0x4\n" "tbz %x[width], #0, 7f\n" "ld1 { v30.h }[6], [x27]\n" + "mov x19, #0x7\n" "ld1 { v29.h }[6], [x26]\n" "ld1 { v28.h }[6], [x25]\n" "ld1 { v27.h }[6], [x24]\n" - "ld1 { v24.h }[6], [x23]\n" - "ld1 { v25.h }[6], [x22]\n" - "ld1 { v23.h }[6], [x21]\n" - "ld1 { v22.h }[6], [x20]\n" - "mov x19, #0x7\n" + "ld1 { v25.h }[6], [x23]\n" + "ld1 { v21.h }[6], [x22]\n" + "ld1 { v24.h }[6], [x21]\n" + "ld1 { v23.h }[6], [x20]\n" "b 7f\n" "4:" // odd_loads_1_4 "mov x19, #0x4\n" "tbz %x[width], #0, 7f\n" "ld1 { v30.h }[4], [x27]\n" "ld1 { v29.h }[4], [x26]\n" + "mov x19, #0x5\n" "ld1 { v28.h }[4], [x25]\n" "ld1 { v27.h }[4], [x24]\n" - "ld1 { v24.h }[4], [x23]\n" - "ld1 { v25.h }[4], [x22]\n" - "ld1 { v23.h }[4], [x21]\n" - "ld1 { v22.h }[4], [x20]\n" - "mov x19, #0x5\n" + "ld1 { v25.h }[4], [x23]\n" + "ld1 { v21.h }[4], [x22]\n" + "ld1 { v24.h }[4], [x21]\n" + "ld1 { v23.h }[4], [x20]\n" "b 7f\n" "5:" // odd_loads_2_0 "tbz %x[width], #1, 6f\n" "ldr s30, [x27], #0x4\n" "ldr s29, [x26], #0x4\n" + "mov x19, #0x2\n" "ldr s28, [x25], #0x4\n" "ldr s27, [x24], #0x4\n" - "ldr s24, [x23], #0x4\n" - "ldr s25, [x22], #0x4\n" - "ldr s23, [x21], #0x4\n" - "ldr s22, [x20], #0x4\n" - "mov x19, #0x2\n" + "ldr s25, [x23], #0x4\n" + "ldr s21, [x22], #0x4\n" + "ldr s24, [x21], #0x4\n" + "ldr s23, [x20], #0x4\n" "tbz %x[width], #0, 7f\n" "ld1 { v30.h }[2], [x27]\n" + "mov x19, #0x3\n" "ld1 { v29.h }[2], [x26]\n" "ld1 { v28.h }[2], [x25]\n" "ld1 { v27.h }[2], [x24]\n" - "ld1 { v24.h }[2], [x23]\n" - "ld1 { v25.h }[2], [x22]\n" - "ld1 { v23.h }[2], [x21]\n" - "ld1 { v22.h }[2], [x20]\n" - "mov x19, #0x3\n" + "ld1 { v25.h }[2], [x23]\n" + "ld1 { v21.h }[2], [x22]\n" + "ld1 { v24.h }[2], [x21]\n" + "ld1 { v23.h }[2], [x20]\n" "b 7f\n" "6:" // odd_loads_1_0 "ldr h30, [x27, #0x0]\n" + "mov x19, #0x1\n" "ldr h29, [x26, #0x0]\n" "ldr h28, [x25, #0x0]\n" "ldr h27, [x24, #0x0]\n" - "ldr h24, [x23, #0x0]\n" - "ldr h25, [x22, #0x0]\n" - "ldr h23, [x21, #0x0]\n" - "ldr h22, [x20, #0x0]\n" - "mov x19, #0x1\n" + "ldr h25, [x23, #0x0]\n" + "ldr h21, [x22, #0x0]\n" + "ldr h24, [x21, #0x0]\n" + "ldr h23, [x20, #0x0]\n" "7:" // Odd load end - "zip1 v26.8h, v30.8h, v24.8h\n" + "zip1 v26.8h, v30.8h, v25.8h\n" "subs x19, x19, #0x1\n" - "zip1 v18.8h, v28.8h, v23.8h\n" - "zip1 v20.8h, v26.8h, v18.8h\n" - "zip1 v21.8h, v29.8h, v25.8h\n" - "zip1 v19.8h, v27.8h, v22.8h\n" - "zip1 v17.8h, v21.8h, v19.8h\n" - "zip1 v16.8h, v20.8h, v17.8h\n" - "str q16, [%x[out_ptr], #0x0]\n" + "zip1 v20.8h, v28.8h, v24.8h\n" + "zip1 v18.8h, v26.8h, v20.8h\n" + "zip1 v22.8h, v29.8h, v21.8h\n" + "zip1 v19.8h, v27.8h, v23.8h\n" + "zip1 v16.8h, v22.8h, v19.8h\n" + "zip1 v17.8h, v18.8h, v16.8h\n" + "str q17, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" - "zip2 v16.8h, v20.8h, v17.8h\n" - "subs x19, x19, #0x1\n" + "zip2 v16.8h, v18.8h, v16.8h\n" "str q16, [%x[out_ptr], #0x0]\n" + "subs x19, x19, #0x1\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" - "zip2 v18.8h, v26.8h, v18.8h\n" - "zip2 v17.8h, v21.8h, v19.8h\n" + "zip2 v18.8h, v26.8h, v20.8h\n" + "zip2 v17.8h, v22.8h, v19.8h\n" "subs x19, x19, #0x1\n" "zip1 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" "zip2 v16.8h, v18.8h, v17.8h\n" - "subs x19, x19, #0x1\n" "str q16, [%x[out_ptr], #0x0]\n" + "subs x19, x19, #0x1\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" - "zip2 v24.8h, v30.8h, v24.8h\n" - "zip2 v21.8h, v28.8h, v23.8h\n" + "zip2 v25.8h, v30.8h, v25.8h\n" + "zip2 v20.8h, v28.8h, v24.8h\n" "subs x19, x19, #0x1\n" - "zip1 v18.8h, v24.8h, v21.8h\n" - "zip2 v20.8h, v29.8h, v25.8h\n" - "zip2 v19.8h, v27.8h, v22.8h\n" - "zip1 v17.8h, v20.8h, v19.8h\n" + "zip1 v18.8h, v25.8h, v20.8h\n" + "zip2 v21.8h, v29.8h, v21.8h\n" + "zip2 v19.8h, v27.8h, v23.8h\n" + "zip1 v17.8h, v21.8h, v19.8h\n" "zip1 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" "zip2 v16.8h, v18.8h, v17.8h\n" - "subs x19, x19, #0x1\n" "str q16, [%x[out_ptr], #0x0]\n" + "subs x19, x19, #0x1\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" - "zip2 v18.8h, v24.8h, v21.8h\n" - "zip2 v17.8h, v20.8h, v19.8h\n" + "zip2 v18.8h, v25.8h, v20.8h\n" + "zip2 v17.8h, v21.8h, v19.8h\n" "zip1 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "8:" // Odds skip - : [out_ptr] "+r" (out_ptr), [width] "+r" (width) + : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_fp16_fp32.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_fp16_fp32.hpp index b45e622a47..b67840b280 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_fp16_fp32.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_fp16_fp32.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020 Arm Limited. + * Copyright (c) 2019-2021 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -79,132 +79,132 @@ void interleave_block<8, 1, VLType::None, false>( "prfm pldl1keep, [x20, #0x40]\n" "blt 3f\n" "2:" // Main loop head - "ldr d29, [x27], #0x8\n" + "ldr d30, [x27], #0x8\n" + "subs %x[width], %x[width], #0x4\n" + "ldr d29, [x26], #0x8\n" + "cmp %x[width], #0x4\n" + "ldr d28, [x25], #0x8\n" + "fcvtl v30.4s, v30.4h\n" + "ldr d21, [x24], #0x8\n" + "ldr d27, [x23], #0x8\n" + "fcvtl v29.4s, v29.4h\n" + "ldr d26, [x22], #0x8\n" + "fcvtl v28.4s, v28.4h\n" + "zip1 v20.4s, v30.4s, v28.4s\n" + "ldr d25, [x21], #0x8\n" + "fcvtl v21.4s, v21.4h\n" + "zip2 v17.4s, v30.4s, v28.4s\n" + "ldr d24, [x20], #0x8\n" + "fcvtl v27.4s, v27.4h\n" + "zip1 v18.4s, v29.4s, v21.4s\n" "prfm pldl1keep, [x27, #0x70]\n" - "ldr d28, [x26], #0x8\n" - "ldr d27, [x25], #0x8\n" + "fcvtl v26.4s, v26.4h\n" + "zip1 v23.4s, v20.4s, v18.4s\n" "prfm pldl1keep, [x26, #0x70]\n" - "ldr d26, [x24], #0x8\n" + "fcvtl v25.4s, v25.4h\n" + "zip2 v22.4s, v20.4s, v18.4s\n" "prfm pldl1keep, [x25, #0x70]\n" - "ldr d25, [x23], #0x8\n" - "ldr d24, [x22], #0x8\n" + "fcvtl v24.4s, v24.4h\n" + "zip2 v16.4s, v29.4s, v21.4s\n" "prfm pldl1keep, [x24, #0x70]\n" - "ldr d23, [x21], #0x8\n" - "ldr d22, [x20], #0x8\n" "prfm pldl1keep, [x23, #0x70]\n" + "zip1 v21.4s, v17.4s, v16.4s\n" + "zip2 v20.4s, v17.4s, v16.4s\n" "prfm pldl1keep, [x22, #0x70]\n" - "fcvtl v29.4s, v29.4h\n" - "fcvtl v28.4s, v28.4h\n" "prfm pldl1keep, [x21, #0x70]\n" - "fcvtl v27.4s, v27.4h\n" - "zip1 v20.4s, v29.4s, v27.4s\n" + "zip1 v19.4s, v27.4s, v25.4s\n" + "zip2 v18.4s, v27.4s, v25.4s\n" "prfm pldl1keep, [x20, #0x70]\n" - "fcvtl v26.4s, v26.4h\n" - "zip2 v18.4s, v29.4s, v27.4s\n" - "fcvtl v25.4s, v25.4h\n" - "fcvtl v24.4s, v24.4h\n" - "zip1 v19.4s, v28.4s, v26.4s\n" - "fcvtl v23.4s, v23.4h\n" - "zip2 v17.4s, v28.4s, v26.4s\n" - "fcvtl v22.4s, v22.4h\n" - "zip1 v16.4s, v20.4s, v19.4s\n" - "str q16, [%x[out_ptr], #0x0]\n" - "zip2 v21.4s, v20.4s, v19.4s\n" - "subs %x[width], %x[width], #0x4\n" - "zip1 v20.4s, v18.4s, v17.4s\n" - "cmp %x[width], #0x4\n" - "zip2 v19.4s, v18.4s, v17.4s\n" - "zip1 v18.4s, v25.4s, v23.4s\n" - "zip1 v17.4s, v24.4s, v22.4s\n" - "zip1 v16.4s, v18.4s, v17.4s\n" + "zip1 v17.4s, v26.4s, v24.4s\n" + "str q23, [%x[out_ptr], #0x0]\n" + "zip1 v16.4s, v19.4s, v17.4s\n" "str q16, [%x[out_ptr], #0x10]\n" - "zip2 v16.4s, v18.4s, v17.4s\n" - "str q21, [%x[out_ptr], #0x20]\n" - "zip2 v18.4s, v25.4s, v23.4s\n" - "str q16, [%x[out_ptr], #0x30]\n" - "zip2 v17.4s, v24.4s, v22.4s\n" - "str q20, [%x[out_ptr], #0x40]\n" - "zip1 v16.4s, v18.4s, v17.4s\n" - "str q16, [%x[out_ptr], #0x50]\n" - "zip2 v16.4s, v18.4s, v17.4s\n" - "str q19, [%x[out_ptr], #0x60]\n" + "zip2 v17.4s, v19.4s, v17.4s\n" + "str q22, [%x[out_ptr], #0x20]\n" + "zip2 v16.4s, v26.4s, v24.4s\n" + "str q17, [%x[out_ptr], #0x30]\n" + "zip1 v17.4s, v18.4s, v16.4s\n" + "str q21, [%x[out_ptr], #0x40]\n" + "zip2 v16.4s, v18.4s, v16.4s\n" + "str q17, [%x[out_ptr], #0x50]\n" + "str q20, [%x[out_ptr], #0x60]\n" "str q16, [%x[out_ptr], #0x70]\n" "add %x[out_ptr], %x[out_ptr], #0x80\n" "bge 2b\n" "3:" // Main loop skip "cbz %x[width], 6f\n" "tbz %x[width], #1, 4f\n" - "ldr s29, [x27], #0x4\n" - "ldr s28, [x26], #0x4\n" - "ldr s27, [x25], #0x4\n" - "ldr s26, [x24], #0x4\n" - "ldr s25, [x23], #0x4\n" - "ldr s24, [x22], #0x4\n" - "ldr s23, [x21], #0x4\n" - "ldr s22, [x20], #0x4\n" + "ldr s30, [x27], #0x4\n" + "ldr s29, [x26], #0x4\n" "mov x19, #0x2\n" + "ldr s28, [x25], #0x4\n" + "ldr s21, [x24], #0x4\n" + "ldr s27, [x23], #0x4\n" + "ldr s26, [x22], #0x4\n" + "ldr s25, [x21], #0x4\n" + "ldr s24, [x20], #0x4\n" "tbz %x[width], #0, 5f\n" - "ld1 { v29.h }[2], [x27]\n" - "ld1 { v28.h }[2], [x26]\n" - "ld1 { v27.h }[2], [x25]\n" - "ld1 { v26.h }[2], [x24]\n" - "ld1 { v25.h }[2], [x23]\n" - "ld1 { v24.h }[2], [x22]\n" - "ld1 { v23.h }[2], [x21]\n" - "ld1 { v22.h }[2], [x20]\n" + "ld1 { v30.h }[2], [x27]\n" "mov x19, #0x3\n" + "ld1 { v29.h }[2], [x26]\n" + "ld1 { v28.h }[2], [x25]\n" + "ld1 { v21.h }[2], [x24]\n" + "ld1 { v27.h }[2], [x23]\n" + "ld1 { v26.h }[2], [x22]\n" + "ld1 { v25.h }[2], [x21]\n" + "ld1 { v24.h }[2], [x20]\n" "b 5f\n" "4:" // odd_loads_1_0 - "ldr h29, [x27, #0x0]\n" - "ldr h28, [x26, #0x0]\n" - "ldr h27, [x25, #0x0]\n" - "ldr h26, [x24, #0x0]\n" - "ldr h25, [x23, #0x0]\n" - "ldr h24, [x22, #0x0]\n" - "ldr h23, [x21, #0x0]\n" - "ldr h22, [x20, #0x0]\n" + "ldr h30, [x27, #0x0]\n" "mov x19, #0x1\n" + "ldr h29, [x26, #0x0]\n" + "ldr h28, [x25, #0x0]\n" + "ldr h21, [x24, #0x0]\n" + "ldr h27, [x23, #0x0]\n" + "ldr h26, [x22, #0x0]\n" + "ldr h25, [x21, #0x0]\n" + "ldr h24, [x20, #0x0]\n" "5:" // Odd load end + "fcvtl v30.4s, v30.4h\n" "fcvtl v29.4s, v29.4h\n" "fcvtl v28.4s, v28.4h\n" + "zip1 v20.4s, v30.4s, v28.4s\n" + "fcvtl v21.4s, v21.4h\n" "fcvtl v27.4s, v27.4h\n" - "zip1 v20.4s, v29.4s, v27.4s\n" + "zip1 v18.4s, v29.4s, v21.4s\n" "fcvtl v26.4s, v26.4h\n" "fcvtl v25.4s, v25.4h\n" - "zip1 v19.4s, v28.4s, v26.4s\n" + "zip1 v23.4s, v20.4s, v18.4s\n" + "str q23, [%x[out_ptr], #0x0]\n" + "zip1 v19.4s, v27.4s, v25.4s\n" "fcvtl v24.4s, v24.4h\n" - "fcvtl v23.4s, v23.4h\n" - "zip1 v16.4s, v20.4s, v19.4s\n" - "fcvtl v22.4s, v22.4h\n" - "zip1 v18.4s, v25.4s, v23.4s\n" - "str q16, [%x[out_ptr], #0x0]\n" "subs x19, x19, #0x1\n" - "zip1 v17.4s, v24.4s, v22.4s\n" - "zip1 v16.4s, v18.4s, v17.4s\n" + "zip1 v17.4s, v26.4s, v24.4s\n" + "zip1 v16.4s, v19.4s, v17.4s\n" "str q16, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "beq 6f\n" - "zip2 v21.4s, v20.4s, v19.4s\n" - "zip2 v16.4s, v18.4s, v17.4s\n" - "str q21, [%x[out_ptr], #0x0]\n" - "str q16, [%x[out_ptr], #0x10]\n" + "zip2 v22.4s, v20.4s, v18.4s\n" + "str q22, [%x[out_ptr], #0x0]\n" + "zip2 v17.4s, v19.4s, v17.4s\n" "subs x19, x19, #0x1\n" + "str q17, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "beq 6f\n" - "zip2 v18.4s, v29.4s, v27.4s\n" - "zip2 v17.4s, v28.4s, v26.4s\n" - "zip1 v20.4s, v18.4s, v17.4s\n" - "str q20, [%x[out_ptr], #0x0]\n" - "zip2 v18.4s, v25.4s, v23.4s\n" - "zip2 v17.4s, v24.4s, v22.4s\n" - "zip1 v16.4s, v18.4s, v17.4s\n" - "str q16, [%x[out_ptr], #0x10]\n" + "zip2 v17.4s, v30.4s, v28.4s\n" + "zip2 v16.4s, v29.4s, v21.4s\n" + "zip1 v21.4s, v17.4s, v16.4s\n" + "str q21, [%x[out_ptr], #0x0]\n" + "zip2 v18.4s, v27.4s, v25.4s\n" + "zip2 v16.4s, v26.4s, v24.4s\n" + "zip1 v17.4s, v18.4s, v16.4s\n" + "str q17, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "6:" // Odds skip - : [out_ptr] "+r" (out_ptr), [width] "+r" (width) + : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) - : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" + : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); } diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_fp32_fp32.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_fp32_fp32.hpp index 3f38859c1c..eefb8549ea 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_fp32_fp32.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_fp32_fp32.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020 Arm Limited. + * Copyright (c) 2019-2021 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -80,45 +80,45 @@ void interleave_block<8, 1, VLType::None, false>( "blt 3f\n" "2:" // Main loop head "ldr q28, [x27], #0x10\n" + "subs %x[width], %x[width], #0x4\n" + "ldr q29, [x26], #0x10\n" + "cmp %x[width], #0x4\n" + "ldr q25, [x25], #0x10\n" + "zip1 v22.4s, v28.4s, v25.4s\n" + "ldr q21, [x24], #0x10\n" + "zip2 v28.4s, v28.4s, v25.4s\n" + "ldr q27, [x23], #0x10\n" + "ldr q26, [x22], #0x10\n" + "zip1 v20.4s, v29.4s, v21.4s\n" + "ldr q19, [x21], #0x10\n" + "zip2 v25.4s, v29.4s, v21.4s\n" + "ldr q24, [x20], #0x10\n" + "zip1 v23.4s, v22.4s, v20.4s\n" "prfm pldl1keep, [x27, #0x70]\n" - "ldr q27, [x26], #0x10\n" - "ldr q26, [x25], #0x10\n" - "zip1 v23.4s, v28.4s, v26.4s\n" + "zip2 v22.4s, v22.4s, v20.4s\n" "prfm pldl1keep, [x26, #0x70]\n" - "ldr q22, [x24], #0x10\n" - "zip2 v26.4s, v28.4s, v26.4s\n" + "zip1 v21.4s, v28.4s, v25.4s\n" "prfm pldl1keep, [x25, #0x70]\n" - "ldr q25, [x23], #0x10\n" - "zip1 v20.4s, v27.4s, v22.4s\n" + "zip1 v18.4s, v27.4s, v19.4s\n" "prfm pldl1keep, [x24, #0x70]\n" - "ldr q24, [x22], #0x10\n" - "zip1 v16.4s, v23.4s, v20.4s\n" + "zip1 v16.4s, v26.4s, v24.4s\n" "prfm pldl1keep, [x23, #0x70]\n" - "ldr q19, [x21], #0x10\n" - "zip2 v23.4s, v23.4s, v20.4s\n" + "zip1 v17.4s, v18.4s, v16.4s\n" "prfm pldl1keep, [x22, #0x70]\n" - "zip2 v22.4s, v27.4s, v22.4s\n" - "ldr q21, [x20], #0x10\n" - "zip1 v18.4s, v25.4s, v19.4s\n" + "zip2 v20.4s, v18.4s, v16.4s\n" "prfm pldl1keep, [x21, #0x70]\n" - "str q16, [%x[out_ptr], #0x0]\n" - "zip1 v20.4s, v26.4s, v22.4s\n" + "zip2 v19.4s, v27.4s, v19.4s\n" "prfm pldl1keep, [x20, #0x70]\n" - "zip1 v16.4s, v24.4s, v21.4s\n" - "subs %x[width], %x[width], #0x4\n" - "zip1 v17.4s, v18.4s, v16.4s\n" - "cmp %x[width], #0x4\n" - "zip2 v16.4s, v18.4s, v16.4s\n" + "zip2 v16.4s, v26.4s, v24.4s\n" + "str q23, [%x[out_ptr], #0x0]\n" + "zip1 v18.4s, v19.4s, v16.4s\n" "str q17, [%x[out_ptr], #0x10]\n" - "zip2 v19.4s, v25.4s, v19.4s\n" - "str q23, [%x[out_ptr], #0x20]\n" - "zip2 v18.4s, v24.4s, v21.4s\n" - "str q16, [%x[out_ptr], #0x30]\n" - "zip1 v16.4s, v19.4s, v18.4s\n" - "str q20, [%x[out_ptr], #0x40]\n" - "zip2 v17.4s, v26.4s, v22.4s\n" - "str q16, [%x[out_ptr], #0x50]\n" - "zip2 v16.4s, v19.4s, v18.4s\n" + "zip2 v17.4s, v28.4s, v25.4s\n" + "str q22, [%x[out_ptr], #0x20]\n" + "zip2 v16.4s, v19.4s, v16.4s\n" + "str q20, [%x[out_ptr], #0x30]\n" + "str q21, [%x[out_ptr], #0x40]\n" + "str q18, [%x[out_ptr], #0x50]\n" "str q17, [%x[out_ptr], #0x60]\n" "str q16, [%x[out_ptr], #0x70]\n" "add %x[out_ptr], %x[out_ptr], #0x80\n" @@ -127,68 +127,68 @@ void interleave_block<8, 1, VLType::None, false>( "cbz %x[width], 6f\n" "tbz %x[width], #1, 4f\n" "ldr d28, [x27], #0x8\n" - "ldr d27, [x26], #0x8\n" - "ldr d26, [x25], #0x8\n" - "ldr d22, [x24], #0x8\n" - "ldr d25, [x23], #0x8\n" - "ldr d24, [x22], #0x8\n" - "ldr d19, [x21], #0x8\n" - "ldr d21, [x20], #0x8\n" + "ldr d29, [x26], #0x8\n" "mov x19, #0x2\n" + "ldr d25, [x25], #0x8\n" + "ldr d21, [x24], #0x8\n" + "ldr d27, [x23], #0x8\n" + "ldr d26, [x22], #0x8\n" + "ldr d19, [x21], #0x8\n" + "ldr d24, [x20], #0x8\n" "tbz %x[width], #0, 5f\n" "ld1 { v28.s }[2], [x27]\n" - "ld1 { v27.s }[2], [x26]\n" - "ld1 { v26.s }[2], [x25]\n" - "ld1 { v22.s }[2], [x24]\n" - "ld1 { v25.s }[2], [x23]\n" - "ld1 { v24.s }[2], [x22]\n" - "ld1 { v19.s }[2], [x21]\n" - "ld1 { v21.s }[2], [x20]\n" "mov x19, #0x3\n" + "ld1 { v29.s }[2], [x26]\n" + "ld1 { v25.s }[2], [x25]\n" + "ld1 { v21.s }[2], [x24]\n" + "ld1 { v27.s }[2], [x23]\n" + "ld1 { v26.s }[2], [x22]\n" + "ld1 { v19.s }[2], [x21]\n" + "ld1 { v24.s }[2], [x20]\n" "b 5f\n" "4:" // odd_loads_1_0 "ldr s28, [x27, #0x0]\n" - "ldr s27, [x26, #0x0]\n" - "ldr s26, [x25, #0x0]\n" - "ldr s22, [x24, #0x0]\n" - "ldr s25, [x23, #0x0]\n" - "ldr s24, [x22, #0x0]\n" - "ldr s19, [x21, #0x0]\n" - "ldr s21, [x20, #0x0]\n" "mov x19, #0x1\n" + "ldr s29, [x26, #0x0]\n" + "ldr s25, [x25, #0x0]\n" + "ldr s21, [x24, #0x0]\n" + "ldr s27, [x23, #0x0]\n" + "ldr s26, [x22, #0x0]\n" + "ldr s19, [x21, #0x0]\n" + "ldr s24, [x20, #0x0]\n" "5:" // Odd load end - "zip1 v23.4s, v28.4s, v26.4s\n" + "zip1 v22.4s, v28.4s, v25.4s\n" "subs x19, x19, #0x1\n" - "zip1 v20.4s, v27.4s, v22.4s\n" - "zip1 v16.4s, v23.4s, v20.4s\n" - "str q16, [%x[out_ptr], #0x0]\n" - "zip1 v18.4s, v25.4s, v19.4s\n" - "zip1 v16.4s, v24.4s, v21.4s\n" + "zip1 v20.4s, v29.4s, v21.4s\n" + "zip1 v23.4s, v22.4s, v20.4s\n" + "str q23, [%x[out_ptr], #0x0]\n" + "zip1 v18.4s, v27.4s, v19.4s\n" + "zip1 v16.4s, v26.4s, v24.4s\n" "zip1 v17.4s, v18.4s, v16.4s\n" "str q17, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "beq 6f\n" - "zip2 v23.4s, v23.4s, v20.4s\n" - "zip2 v16.4s, v18.4s, v16.4s\n" - "str q23, [%x[out_ptr], #0x0]\n" - "str q16, [%x[out_ptr], #0x10]\n" + "zip2 v22.4s, v22.4s, v20.4s\n" + "str q22, [%x[out_ptr], #0x0]\n" + "zip2 v20.4s, v18.4s, v16.4s\n" "subs x19, x19, #0x1\n" + "str q20, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "beq 6f\n" - "zip2 v26.4s, v28.4s, v26.4s\n" - "zip2 v22.4s, v27.4s, v22.4s\n" - "zip1 v20.4s, v26.4s, v22.4s\n" - "str q20, [%x[out_ptr], #0x0]\n" - "zip2 v19.4s, v25.4s, v19.4s\n" - "zip2 v18.4s, v24.4s, v21.4s\n" - "zip1 v16.4s, v19.4s, v18.4s\n" - "str q16, [%x[out_ptr], #0x10]\n" + "zip2 v28.4s, v28.4s, v25.4s\n" + "zip2 v25.4s, v29.4s, v21.4s\n" + "zip1 v21.4s, v28.4s, v25.4s\n" + "str q21, [%x[out_ptr], #0x0]\n" + "zip2 v19.4s, v27.4s, v19.4s\n" + "zip2 v16.4s, v26.4s, v24.4s\n" + "zip1 v18.4s, v19.4s, v16.4s\n" + "str q18, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "6:" // Odds skip - : [out_ptr] "+r" (out_ptr), [width] "+r" (width) + : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) - : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" + : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); } diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_s16_s16.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_s16_s16.hpp index 03f552a575..b0523b96ce 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_s16_s16.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_s16_s16.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020 Arm Limited. + * Copyright (c) 2019-2021 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -80,51 +80,51 @@ void interleave_block<8, 1, VLType::None, false>( "blt 3f\n" "2:" // Main loop head "ldr q30, [x27], #0x10\n" - "prfm pldl1keep, [x27, #0x70]\n" + "subs %x[width], %x[width], #0x8\n" "ldr q29, [x26], #0x10\n" + "cmp %x[width], #0x8\n" "ldr q28, [x25], #0x10\n" - "prfm pldl1keep, [x26, #0x70]\n" "ldr q27, [x24], #0x10\n" + "ldr q25, [x23], #0x10\n" + "zip1 v26.8h, v30.8h, v25.8h\n" + "ldr q21, [x22], #0x10\n" + "zip2 v25.8h, v30.8h, v25.8h\n" + "ldr q24, [x21], #0x10\n" + "ldr q23, [x20], #0x10\n" + "zip1 v22.8h, v29.8h, v21.8h\n" + "prfm pldl1keep, [x27, #0x70]\n" + "zip2 v21.8h, v29.8h, v21.8h\n" + "prfm pldl1keep, [x26, #0x70]\n" + "zip1 v20.8h, v28.8h, v24.8h\n" "prfm pldl1keep, [x25, #0x70]\n" - "ldr q24, [x23], #0x10\n" - "zip1 v26.8h, v30.8h, v24.8h\n" + "zip1 v18.8h, v26.8h, v20.8h\n" "prfm pldl1keep, [x24, #0x70]\n" - "ldr q25, [x22], #0x10\n" - "zip2 v24.8h, v30.8h, v24.8h\n" + "zip1 v19.8h, v27.8h, v23.8h\n" "prfm pldl1keep, [x23, #0x70]\n" - "ldr q23, [x21], #0x10\n" - "zip1 v21.8h, v29.8h, v25.8h\n" + "zip1 v16.8h, v22.8h, v19.8h\n" "prfm pldl1keep, [x22, #0x70]\n" - "ldr q22, [x20], #0x10\n" - "zip1 v18.8h, v28.8h, v23.8h\n" + "zip1 v17.8h, v18.8h, v16.8h\n" "prfm pldl1keep, [x21, #0x70]\n" - "subs %x[width], %x[width], #0x8\n" - "zip1 v20.8h, v26.8h, v18.8h\n" + "zip2 v16.8h, v18.8h, v16.8h\n" "prfm pldl1keep, [x20, #0x70]\n" - "zip1 v19.8h, v27.8h, v22.8h\n" - "cmp %x[width], #0x8\n" - "zip1 v17.8h, v21.8h, v19.8h\n" - "zip2 v18.8h, v26.8h, v18.8h\n" - "zip1 v16.8h, v20.8h, v17.8h\n" - "str q16, [%x[out_ptr], #0x0]\n" - "zip2 v16.8h, v20.8h, v17.8h\n" + "zip2 v18.8h, v26.8h, v20.8h\n" + "str q17, [%x[out_ptr], #0x0]\n" + "zip2 v17.8h, v22.8h, v19.8h\n" "str q16, [%x[out_ptr], #0x10]\n" - "zip2 v17.8h, v21.8h, v19.8h\n" "zip1 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x20]\n" "zip2 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x30]\n" - "zip2 v21.8h, v28.8h, v23.8h\n" - "zip1 v18.8h, v24.8h, v21.8h\n" - "zip2 v20.8h, v29.8h, v25.8h\n" - "zip2 v19.8h, v27.8h, v22.8h\n" - "zip1 v17.8h, v20.8h, v19.8h\n" + "zip2 v20.8h, v28.8h, v24.8h\n" + "zip1 v18.8h, v25.8h, v20.8h\n" + "zip2 v19.8h, v27.8h, v23.8h\n" + "zip1 v17.8h, v21.8h, v19.8h\n" "zip1 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x40]\n" "zip2 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x50]\n" - "zip2 v18.8h, v24.8h, v21.8h\n" - "zip2 v17.8h, v20.8h, v19.8h\n" + "zip2 v18.8h, v25.8h, v20.8h\n" + "zip2 v17.8h, v21.8h, v19.8h\n" "zip1 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x60]\n" "zip2 v16.8h, v18.8h, v17.8h\n" @@ -138,129 +138,129 @@ void interleave_block<8, 1, VLType::None, false>( "ldr d29, [x26], #0x8\n" "ldr d28, [x25], #0x8\n" "ldr d27, [x24], #0x8\n" - "ldr d24, [x23], #0x8\n" - "ldr d25, [x22], #0x8\n" - "ldr d23, [x21], #0x8\n" - "ldr d22, [x20], #0x8\n" + "ldr d25, [x23], #0x8\n" + "ldr d21, [x22], #0x8\n" + "ldr d24, [x21], #0x8\n" + "ldr d23, [x20], #0x8\n" "tbz %x[width], #1, 4f\n" "ld1 { v30.s }[2], [x27], #0x4\n" + "mov x19, #0x6\n" "ld1 { v29.s }[2], [x26], #0x4\n" "ld1 { v28.s }[2], [x25], #0x4\n" "ld1 { v27.s }[2], [x24], #0x4\n" - "ld1 { v24.s }[2], [x23], #0x4\n" - "ld1 { v25.s }[2], [x22], #0x4\n" - "ld1 { v23.s }[2], [x21], #0x4\n" - "ld1 { v22.s }[2], [x20], #0x4\n" - "mov x19, #0x6\n" + "ld1 { v25.s }[2], [x23], #0x4\n" + "ld1 { v21.s }[2], [x22], #0x4\n" + "ld1 { v24.s }[2], [x21], #0x4\n" + "ld1 { v23.s }[2], [x20], #0x4\n" "tbz %x[width], #0, 7f\n" "ld1 { v30.h }[6], [x27]\n" + "mov x19, #0x7\n" "ld1 { v29.h }[6], [x26]\n" "ld1 { v28.h }[6], [x25]\n" "ld1 { v27.h }[6], [x24]\n" - "ld1 { v24.h }[6], [x23]\n" - "ld1 { v25.h }[6], [x22]\n" - "ld1 { v23.h }[6], [x21]\n" - "ld1 { v22.h }[6], [x20]\n" - "mov x19, #0x7\n" + "ld1 { v25.h }[6], [x23]\n" + "ld1 { v21.h }[6], [x22]\n" + "ld1 { v24.h }[6], [x21]\n" + "ld1 { v23.h }[6], [x20]\n" "b 7f\n" "4:" // odd_loads_1_4 "mov x19, #0x4\n" "tbz %x[width], #0, 7f\n" "ld1 { v30.h }[4], [x27]\n" "ld1 { v29.h }[4], [x26]\n" + "mov x19, #0x5\n" "ld1 { v28.h }[4], [x25]\n" "ld1 { v27.h }[4], [x24]\n" - "ld1 { v24.h }[4], [x23]\n" - "ld1 { v25.h }[4], [x22]\n" - "ld1 { v23.h }[4], [x21]\n" - "ld1 { v22.h }[4], [x20]\n" - "mov x19, #0x5\n" + "ld1 { v25.h }[4], [x23]\n" + "ld1 { v21.h }[4], [x22]\n" + "ld1 { v24.h }[4], [x21]\n" + "ld1 { v23.h }[4], [x20]\n" "b 7f\n" "5:" // odd_loads_2_0 "tbz %x[width], #1, 6f\n" "ldr s30, [x27], #0x4\n" "ldr s29, [x26], #0x4\n" + "mov x19, #0x2\n" "ldr s28, [x25], #0x4\n" "ldr s27, [x24], #0x4\n" - "ldr s24, [x23], #0x4\n" - "ldr s25, [x22], #0x4\n" - "ldr s23, [x21], #0x4\n" - "ldr s22, [x20], #0x4\n" - "mov x19, #0x2\n" + "ldr s25, [x23], #0x4\n" + "ldr s21, [x22], #0x4\n" + "ldr s24, [x21], #0x4\n" + "ldr s23, [x20], #0x4\n" "tbz %x[width], #0, 7f\n" "ld1 { v30.h }[2], [x27]\n" + "mov x19, #0x3\n" "ld1 { v29.h }[2], [x26]\n" "ld1 { v28.h }[2], [x25]\n" "ld1 { v27.h }[2], [x24]\n" - "ld1 { v24.h }[2], [x23]\n" - "ld1 { v25.h }[2], [x22]\n" - "ld1 { v23.h }[2], [x21]\n" - "ld1 { v22.h }[2], [x20]\n" - "mov x19, #0x3\n" + "ld1 { v25.h }[2], [x23]\n" + "ld1 { v21.h }[2], [x22]\n" + "ld1 { v24.h }[2], [x21]\n" + "ld1 { v23.h }[2], [x20]\n" "b 7f\n" "6:" // odd_loads_1_0 "ldr h30, [x27, #0x0]\n" + "mov x19, #0x1\n" "ldr h29, [x26, #0x0]\n" "ldr h28, [x25, #0x0]\n" "ldr h27, [x24, #0x0]\n" - "ldr h24, [x23, #0x0]\n" - "ldr h25, [x22, #0x0]\n" - "ldr h23, [x21, #0x0]\n" - "ldr h22, [x20, #0x0]\n" - "mov x19, #0x1\n" + "ldr h25, [x23, #0x0]\n" + "ldr h21, [x22, #0x0]\n" + "ldr h24, [x21, #0x0]\n" + "ldr h23, [x20, #0x0]\n" "7:" // Odd load end - "zip1 v26.8h, v30.8h, v24.8h\n" + "zip1 v26.8h, v30.8h, v25.8h\n" "subs x19, x19, #0x1\n" - "zip1 v18.8h, v28.8h, v23.8h\n" - "zip1 v20.8h, v26.8h, v18.8h\n" - "zip1 v21.8h, v29.8h, v25.8h\n" - "zip1 v19.8h, v27.8h, v22.8h\n" - "zip1 v17.8h, v21.8h, v19.8h\n" - "zip1 v16.8h, v20.8h, v17.8h\n" - "str q16, [%x[out_ptr], #0x0]\n" + "zip1 v20.8h, v28.8h, v24.8h\n" + "zip1 v18.8h, v26.8h, v20.8h\n" + "zip1 v22.8h, v29.8h, v21.8h\n" + "zip1 v19.8h, v27.8h, v23.8h\n" + "zip1 v16.8h, v22.8h, v19.8h\n" + "zip1 v17.8h, v18.8h, v16.8h\n" + "str q17, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" - "zip2 v16.8h, v20.8h, v17.8h\n" - "subs x19, x19, #0x1\n" + "zip2 v16.8h, v18.8h, v16.8h\n" "str q16, [%x[out_ptr], #0x0]\n" + "subs x19, x19, #0x1\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" - "zip2 v18.8h, v26.8h, v18.8h\n" - "zip2 v17.8h, v21.8h, v19.8h\n" + "zip2 v18.8h, v26.8h, v20.8h\n" + "zip2 v17.8h, v22.8h, v19.8h\n" "subs x19, x19, #0x1\n" "zip1 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" "zip2 v16.8h, v18.8h, v17.8h\n" - "subs x19, x19, #0x1\n" "str q16, [%x[out_ptr], #0x0]\n" + "subs x19, x19, #0x1\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" - "zip2 v24.8h, v30.8h, v24.8h\n" - "zip2 v21.8h, v28.8h, v23.8h\n" + "zip2 v25.8h, v30.8h, v25.8h\n" + "zip2 v20.8h, v28.8h, v24.8h\n" "subs x19, x19, #0x1\n" - "zip1 v18.8h, v24.8h, v21.8h\n" - "zip2 v20.8h, v29.8h, v25.8h\n" - "zip2 v19.8h, v27.8h, v22.8h\n" - "zip1 v17.8h, v20.8h, v19.8h\n" + "zip1 v18.8h, v25.8h, v20.8h\n" + "zip2 v21.8h, v29.8h, v21.8h\n" + "zip2 v19.8h, v27.8h, v23.8h\n" + "zip1 v17.8h, v21.8h, v19.8h\n" "zip1 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" "zip2 v16.8h, v18.8h, v17.8h\n" - "subs x19, x19, #0x1\n" "str q16, [%x[out_ptr], #0x0]\n" + "subs x19, x19, #0x1\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" - "zip2 v18.8h, v24.8h, v21.8h\n" - "zip2 v17.8h, v20.8h, v19.8h\n" + "zip2 v18.8h, v25.8h, v20.8h\n" + "zip2 v17.8h, v21.8h, v19.8h\n" "zip1 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "8:" // Odds skip - : [out_ptr] "+r" (out_ptr), [width] "+r" (width) + : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_s16_s16_summing.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_s16_s16_summing.hpp index 35c7719de7..292a38f401 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_s16_s16_summing.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_s16_s16_summing.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020 Arm Limited. + * Copyright (c) 2019-2021 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -96,58 +96,58 @@ void interleave_block<8, 1, VLType::None, true>( "movi v1.8h, #0x0\n" "4:" // no_accumulate_16 "ldr q30, [x27], #0x10\n" - "prfm pldl1keep, [x27, #0x70]\n" + "add x19, x19, #0x1\n" "ldr q29, [x26], #0x10\n" + "subs %x[width], %x[width], #0x8\n" "ldr q28, [x25], #0x10\n" - "prfm pldl1keep, [x26, #0x70]\n" + "cmp %x[width], #0x8\n" "ldr q27, [x24], #0x10\n" + "ldr q25, [x23], #0x10\n" + "zip1 v26.8h, v30.8h, v25.8h\n" + "ldr q21, [x22], #0x10\n" + "zip2 v25.8h, v30.8h, v25.8h\n" + "ldr q24, [x21], #0x10\n" + "ldr q23, [x20], #0x10\n" + "zip1 v22.8h, v29.8h, v21.8h\n" + "prfm pldl1keep, [x27, #0x70]\n" + "zip2 v21.8h, v29.8h, v21.8h\n" + "prfm pldl1keep, [x26, #0x70]\n" + "zip1 v20.8h, v28.8h, v24.8h\n" "prfm pldl1keep, [x25, #0x70]\n" - "ldr q24, [x23], #0x10\n" - "zip1 v26.8h, v30.8h, v24.8h\n" + "zip1 v18.8h, v26.8h, v20.8h\n" "prfm pldl1keep, [x24, #0x70]\n" - "ldr q25, [x22], #0x10\n" - "zip2 v24.8h, v30.8h, v24.8h\n" + "zip1 v19.8h, v27.8h, v23.8h\n" "prfm pldl1keep, [x23, #0x70]\n" - "ldr q23, [x21], #0x10\n" - "zip1 v21.8h, v29.8h, v25.8h\n" + "zip1 v16.8h, v22.8h, v19.8h\n" "prfm pldl1keep, [x22, #0x70]\n" - "ldr q22, [x20], #0x10\n" - "zip1 v18.8h, v28.8h, v23.8h\n" + "zip1 v17.8h, v18.8h, v16.8h\n" "prfm pldl1keep, [x21, #0x70]\n" - "add x19, x19, #0x1\n" - "zip1 v20.8h, v26.8h, v18.8h\n" - "prfm pldl1keep, [x20, #0x70]\n" - "zip1 v19.8h, v27.8h, v22.8h\n" - "subs %x[width], %x[width], #0x8\n" - "zip1 v17.8h, v21.8h, v19.8h\n" - "cmp %x[width], #0x8\n" - "zip2 v18.8h, v26.8h, v18.8h\n" - "zip1 v16.8h, v20.8h, v17.8h\n" - "str q16, [%x[out_ptr], #0x0]\n" - "add v1.8h, v1.8h, v16.8h\n" - "zip2 v17.8h, v20.8h, v17.8h\n" - "str q17, [%x[out_ptr], #0x10]\n" - "zip2 v16.8h, v21.8h, v19.8h\n" "add v1.8h, v1.8h, v17.8h\n" - "zip1 v17.8h, v18.8h, v16.8h\n" - "str q17, [%x[out_ptr], #0x20]\n" + "prfm pldl1keep, [x20, #0x70]\n" "zip2 v16.8h, v18.8h, v16.8h\n" + "str q17, [%x[out_ptr], #0x0]\n" + "zip2 v18.8h, v26.8h, v20.8h\n" + "str q16, [%x[out_ptr], #0x10]\n" + "add v1.8h, v1.8h, v16.8h\n" + "zip2 v17.8h, v22.8h, v19.8h\n" + "zip1 v16.8h, v18.8h, v17.8h\n" + "str q16, [%x[out_ptr], #0x20]\n" + "add v1.8h, v1.8h, v16.8h\n" + "zip2 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x30]\n" - "add v1.8h, v1.8h, v17.8h\n" - "zip2 v21.8h, v28.8h, v23.8h\n" - "zip1 v18.8h, v24.8h, v21.8h\n" + "zip2 v20.8h, v28.8h, v24.8h\n" "add v1.8h, v1.8h, v16.8h\n" - "zip2 v20.8h, v29.8h, v25.8h\n" - "zip2 v19.8h, v27.8h, v22.8h\n" - "zip1 v17.8h, v20.8h, v19.8h\n" + "zip1 v18.8h, v25.8h, v20.8h\n" + "zip2 v19.8h, v27.8h, v23.8h\n" + "zip1 v17.8h, v21.8h, v19.8h\n" "zip1 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x40]\n" "add v1.8h, v1.8h, v16.8h\n" "zip2 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x50]\n" - "zip2 v18.8h, v24.8h, v21.8h\n" + "zip2 v18.8h, v25.8h, v20.8h\n" "add v1.8h, v1.8h, v16.8h\n" - "zip2 v17.8h, v20.8h, v19.8h\n" + "zip2 v17.8h, v21.8h, v19.8h\n" "zip1 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x60]\n" "add v1.8h, v1.8h, v16.8h\n" @@ -163,140 +163,140 @@ void interleave_block<8, 1, VLType::None, true>( "ldr d29, [x26], #0x8\n" "ldr d28, [x25], #0x8\n" "ldr d27, [x24], #0x8\n" - "ldr d24, [x23], #0x8\n" - "ldr d25, [x22], #0x8\n" - "ldr d23, [x21], #0x8\n" - "ldr d22, [x20], #0x8\n" + "ldr d25, [x23], #0x8\n" + "ldr d21, [x22], #0x8\n" + "ldr d24, [x21], #0x8\n" + "ldr d23, [x20], #0x8\n" "tbz %x[width], #1, 6f\n" "ld1 { v30.s }[2], [x27], #0x4\n" + "mov x19, #0x6\n" "ld1 { v29.s }[2], [x26], #0x4\n" "ld1 { v28.s }[2], [x25], #0x4\n" "ld1 { v27.s }[2], [x24], #0x4\n" - "ld1 { v24.s }[2], [x23], #0x4\n" - "ld1 { v25.s }[2], [x22], #0x4\n" - "ld1 { v23.s }[2], [x21], #0x4\n" - "ld1 { v22.s }[2], [x20], #0x4\n" - "mov x19, #0x6\n" + "ld1 { v25.s }[2], [x23], #0x4\n" + "ld1 { v21.s }[2], [x22], #0x4\n" + "ld1 { v24.s }[2], [x21], #0x4\n" + "ld1 { v23.s }[2], [x20], #0x4\n" "tbz %x[width], #0, 9f\n" "ld1 { v30.h }[6], [x27]\n" + "mov x19, #0x7\n" "ld1 { v29.h }[6], [x26]\n" "ld1 { v28.h }[6], [x25]\n" "ld1 { v27.h }[6], [x24]\n" - "ld1 { v24.h }[6], [x23]\n" - "ld1 { v25.h }[6], [x22]\n" - "ld1 { v23.h }[6], [x21]\n" - "ld1 { v22.h }[6], [x20]\n" - "mov x19, #0x7\n" + "ld1 { v25.h }[6], [x23]\n" + "ld1 { v21.h }[6], [x22]\n" + "ld1 { v24.h }[6], [x21]\n" + "ld1 { v23.h }[6], [x20]\n" "b 9f\n" "6:" // odd_loads_1_4 "mov x19, #0x4\n" "tbz %x[width], #0, 9f\n" "ld1 { v30.h }[4], [x27]\n" "ld1 { v29.h }[4], [x26]\n" + "mov x19, #0x5\n" "ld1 { v28.h }[4], [x25]\n" "ld1 { v27.h }[4], [x24]\n" - "ld1 { v24.h }[4], [x23]\n" - "ld1 { v25.h }[4], [x22]\n" - "ld1 { v23.h }[4], [x21]\n" - "ld1 { v22.h }[4], [x20]\n" - "mov x19, #0x5\n" + "ld1 { v25.h }[4], [x23]\n" + "ld1 { v21.h }[4], [x22]\n" + "ld1 { v24.h }[4], [x21]\n" + "ld1 { v23.h }[4], [x20]\n" "b 9f\n" "7:" // odd_loads_2_0 "tbz %x[width], #1, 8f\n" "ldr s30, [x27], #0x4\n" "ldr s29, [x26], #0x4\n" + "mov x19, #0x2\n" "ldr s28, [x25], #0x4\n" "ldr s27, [x24], #0x4\n" - "ldr s24, [x23], #0x4\n" - "ldr s25, [x22], #0x4\n" - "ldr s23, [x21], #0x4\n" - "ldr s22, [x20], #0x4\n" - "mov x19, #0x2\n" + "ldr s25, [x23], #0x4\n" + "ldr s21, [x22], #0x4\n" + "ldr s24, [x21], #0x4\n" + "ldr s23, [x20], #0x4\n" "tbz %x[width], #0, 9f\n" "ld1 { v30.h }[2], [x27]\n" + "mov x19, #0x3\n" "ld1 { v29.h }[2], [x26]\n" "ld1 { v28.h }[2], [x25]\n" "ld1 { v27.h }[2], [x24]\n" - "ld1 { v24.h }[2], [x23]\n" - "ld1 { v25.h }[2], [x22]\n" - "ld1 { v23.h }[2], [x21]\n" - "ld1 { v22.h }[2], [x20]\n" - "mov x19, #0x3\n" + "ld1 { v25.h }[2], [x23]\n" + "ld1 { v21.h }[2], [x22]\n" + "ld1 { v24.h }[2], [x21]\n" + "ld1 { v23.h }[2], [x20]\n" "b 9f\n" "8:" // odd_loads_1_0 "ldr h30, [x27, #0x0]\n" + "mov x19, #0x1\n" "ldr h29, [x26, #0x0]\n" "ldr h28, [x25, #0x0]\n" "ldr h27, [x24, #0x0]\n" - "ldr h24, [x23, #0x0]\n" - "ldr h25, [x22, #0x0]\n" - "ldr h23, [x21, #0x0]\n" - "ldr h22, [x20, #0x0]\n" - "mov x19, #0x1\n" + "ldr h25, [x23, #0x0]\n" + "ldr h21, [x22, #0x0]\n" + "ldr h24, [x21, #0x0]\n" + "ldr h23, [x20, #0x0]\n" "9:" // Odd load end - "zip1 v26.8h, v30.8h, v24.8h\n" + "zip1 v26.8h, v30.8h, v25.8h\n" "subs x19, x19, #0x1\n" - "zip1 v18.8h, v28.8h, v23.8h\n" - "zip1 v20.8h, v26.8h, v18.8h\n" - "zip1 v21.8h, v29.8h, v25.8h\n" - "zip1 v19.8h, v27.8h, v22.8h\n" - "zip1 v17.8h, v21.8h, v19.8h\n" - "zip1 v16.8h, v20.8h, v17.8h\n" - "str q16, [%x[out_ptr], #0x0]\n" - "add v1.8h, v1.8h, v16.8h\n" + "zip1 v20.8h, v28.8h, v24.8h\n" + "zip1 v18.8h, v26.8h, v20.8h\n" + "zip1 v22.8h, v29.8h, v21.8h\n" + "zip1 v19.8h, v27.8h, v23.8h\n" + "zip1 v16.8h, v22.8h, v19.8h\n" + "zip1 v17.8h, v18.8h, v16.8h\n" + "str q17, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" + "add v1.8h, v1.8h, v17.8h\n" "beq 10f\n" - "zip2 v17.8h, v20.8h, v17.8h\n" + "zip2 v16.8h, v18.8h, v16.8h\n" + "str q16, [%x[out_ptr], #0x0]\n" "subs x19, x19, #0x1\n" - "add v1.8h, v1.8h, v17.8h\n" - "str q17, [%x[out_ptr], #0x0]\n" + "add v1.8h, v1.8h, v16.8h\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 10f\n" - "zip2 v18.8h, v26.8h, v18.8h\n" - "zip2 v16.8h, v21.8h, v19.8h\n" + "zip2 v18.8h, v26.8h, v20.8h\n" + "zip2 v17.8h, v22.8h, v19.8h\n" "subs x19, x19, #0x1\n" - "zip1 v17.8h, v18.8h, v16.8h\n" - "str q17, [%x[out_ptr], #0x0]\n" - "add v1.8h, v1.8h, v17.8h\n" + "zip1 v16.8h, v18.8h, v17.8h\n" + "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" + "add v1.8h, v1.8h, v16.8h\n" "beq 10f\n" - "zip2 v16.8h, v18.8h, v16.8h\n" + "zip2 v16.8h, v18.8h, v17.8h\n" + "str q16, [%x[out_ptr], #0x0]\n" "subs x19, x19, #0x1\n" "add v1.8h, v1.8h, v16.8h\n" - "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 10f\n" - "zip2 v24.8h, v30.8h, v24.8h\n" - "zip2 v21.8h, v28.8h, v23.8h\n" + "zip2 v25.8h, v30.8h, v25.8h\n" + "zip2 v20.8h, v28.8h, v24.8h\n" "subs x19, x19, #0x1\n" - "zip1 v18.8h, v24.8h, v21.8h\n" - "zip2 v20.8h, v29.8h, v25.8h\n" - "zip2 v19.8h, v27.8h, v22.8h\n" - "zip1 v17.8h, v20.8h, v19.8h\n" + "zip1 v18.8h, v25.8h, v20.8h\n" + "zip2 v21.8h, v29.8h, v21.8h\n" + "zip2 v19.8h, v27.8h, v23.8h\n" + "zip1 v17.8h, v21.8h, v19.8h\n" "zip1 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" - "add v1.8h, v1.8h, v16.8h\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" + "add v1.8h, v1.8h, v16.8h\n" "beq 10f\n" "zip2 v16.8h, v18.8h, v17.8h\n" + "str q16, [%x[out_ptr], #0x0]\n" "subs x19, x19, #0x1\n" "add v1.8h, v1.8h, v16.8h\n" - "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 10f\n" - "zip2 v18.8h, v24.8h, v21.8h\n" - "zip2 v17.8h, v20.8h, v19.8h\n" + "zip2 v18.8h, v25.8h, v20.8h\n" + "zip2 v17.8h, v21.8h, v19.8h\n" "zip1 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" - "add v1.8h, v1.8h, v16.8h\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" + "add v1.8h, v1.8h, v16.8h\n" "10:" // Odds skip "saddw v0.4s, v0.4s, v1.4h\n" "str q0, [%x[out_ptr], #0x0]\n" "saddw2 v31.4s, v31.4s, v1.8h\n" "str q31, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" - : [out_ptr] "+r" (out_ptr), [width] "+r" (width) + : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [first] "r" (first), [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) : "cc", "memory", "v0", "v1", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_s8_s16.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_s8_s16.hpp index 582836fe67..6cfed8f3a4 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_s8_s16.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_s8_s16.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020 Arm Limited. + * Copyright (c) 2019-2021 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -79,206 +79,206 @@ void interleave_block<8, 1, VLType::None, false>( "prfm pldl1keep, [x20, #0x40]\n" "blt 3f\n" "2:" // Main loop head - "ldr d30, [x27], #0x8\n" + "ldr d31, [x27], #0x8\n" + "sshll v31.8h, v31.8b, #0x0\n" + "ldr d30, [x26], #0x8\n" + "subs %x[width], %x[width], #0x8\n" + "sshll v30.8h, v30.8b, #0x0\n" + "ldr d29, [x25], #0x8\n" + "cmp %x[width], #0x8\n" + "sshll v29.8h, v29.8b, #0x0\n" + "ldr d28, [x24], #0x8\n" + "ldr d25, [x23], #0x8\n" + "sshll v28.8h, v28.8b, #0x0\n" + "ldr d23, [x22], #0x8\n" + "sshll v25.8h, v25.8b, #0x0\n" + "ldr d27, [x21], #0x8\n" + "zip1 v20.8h, v31.8h, v25.8h\n" + "ldr d26, [x20], #0x8\n" + "zip2 v25.8h, v31.8h, v25.8h\n" "prfm pldl1keep, [x27, #0x70]\n" - "ldr d29, [x26], #0x8\n" - "ldr d28, [x25], #0x8\n" "prfm pldl1keep, [x26, #0x70]\n" - "ldr d27, [x24], #0x8\n" + "sshll v23.8h, v23.8b, #0x0\n" "prfm pldl1keep, [x25, #0x70]\n" - "ldr d23, [x23], #0x8\n" - "ldr d21, [x22], #0x8\n" + "zip1 v24.8h, v30.8h, v23.8h\n" + "zip2 v23.8h, v30.8h, v23.8h\n" "prfm pldl1keep, [x24, #0x70]\n" - "ldr d26, [x21], #0x8\n" - "ldr d25, [x20], #0x8\n" + "sshll v27.8h, v27.8b, #0x0\n" "prfm pldl1keep, [x23, #0x70]\n" + "zip1 v19.8h, v29.8h, v27.8h\n" "prfm pldl1keep, [x22, #0x70]\n" - "sshll v30.8h, v30.8b, #0x0\n" - "sshll v29.8h, v29.8b, #0x0\n" + "zip1 v22.8h, v20.8h, v19.8h\n" "prfm pldl1keep, [x21, #0x70]\n" - "sshll v28.8h, v28.8b, #0x0\n" + "zip2 v21.8h, v20.8h, v19.8h\n" "prfm pldl1keep, [x20, #0x70]\n" - "sshll v27.8h, v27.8b, #0x0\n" - "sshll v23.8h, v23.8b, #0x0\n" - "zip1 v24.8h, v30.8h, v23.8h\n" - "sshll v21.8h, v21.8b, #0x0\n" - "zip2 v23.8h, v30.8h, v23.8h\n" + "zip2 v19.8h, v29.8h, v27.8h\n" + "zip1 v20.8h, v25.8h, v19.8h\n" + "zip2 v19.8h, v25.8h, v19.8h\n" "sshll v26.8h, v26.8b, #0x0\n" - "sshll v25.8h, v25.8b, #0x0\n" - "zip1 v22.8h, v29.8h, v21.8h\n" - "subs %x[width], %x[width], #0x8\n" - "zip2 v21.8h, v29.8h, v21.8h\n" - "cmp %x[width], #0x8\n" - "zip1 v20.8h, v28.8h, v26.8h\n" - "zip1 v18.8h, v24.8h, v20.8h\n" - "zip1 v19.8h, v27.8h, v25.8h\n" - "zip1 v17.8h, v22.8h, v19.8h\n" - "zip1 v16.8h, v18.8h, v17.8h\n" + "zip1 v18.8h, v28.8h, v26.8h\n" + "zip1 v17.8h, v24.8h, v18.8h\n" + "zip1 v16.8h, v22.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" - "zip2 v16.8h, v18.8h, v17.8h\n" + "zip2 v16.8h, v22.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x10]\n" - "zip2 v18.8h, v24.8h, v20.8h\n" - "zip2 v17.8h, v22.8h, v19.8h\n" - "zip1 v16.8h, v18.8h, v17.8h\n" + "zip2 v17.8h, v24.8h, v18.8h\n" + "zip1 v16.8h, v21.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x20]\n" - "zip2 v16.8h, v18.8h, v17.8h\n" + "zip2 v16.8h, v21.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x30]\n" - "zip2 v20.8h, v28.8h, v26.8h\n" - "zip1 v18.8h, v23.8h, v20.8h\n" - "zip2 v19.8h, v27.8h, v25.8h\n" - "zip1 v17.8h, v21.8h, v19.8h\n" - "zip1 v16.8h, v18.8h, v17.8h\n" + "zip2 v18.8h, v28.8h, v26.8h\n" + "zip1 v17.8h, v23.8h, v18.8h\n" + "zip1 v16.8h, v20.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x40]\n" - "zip2 v16.8h, v18.8h, v17.8h\n" + "zip2 v16.8h, v20.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x50]\n" - "zip2 v18.8h, v23.8h, v20.8h\n" - "zip2 v17.8h, v21.8h, v19.8h\n" - "zip1 v16.8h, v18.8h, v17.8h\n" + "zip2 v17.8h, v23.8h, v18.8h\n" + "zip1 v16.8h, v19.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x60]\n" - "zip2 v16.8h, v18.8h, v17.8h\n" + "zip2 v16.8h, v19.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x70]\n" "add %x[out_ptr], %x[out_ptr], #0x80\n" "bge 2b\n" "3:" // Main loop skip "cbz %x[width], 8f\n" "tbz %x[width], #2, 5f\n" - "ldr s30, [x27], #0x4\n" - "ldr s29, [x26], #0x4\n" - "ldr s28, [x25], #0x4\n" - "ldr s27, [x24], #0x4\n" - "ldr s23, [x23], #0x4\n" - "ldr s21, [x22], #0x4\n" - "ldr s26, [x21], #0x4\n" - "ldr s25, [x20], #0x4\n" + "ldr s31, [x27], #0x4\n" + "ldr s30, [x26], #0x4\n" + "ldr s29, [x25], #0x4\n" + "ldr s28, [x24], #0x4\n" + "ldr s25, [x23], #0x4\n" + "ldr s23, [x22], #0x4\n" + "ldr s27, [x21], #0x4\n" + "ldr s26, [x20], #0x4\n" "tbz %x[width], #1, 4f\n" - "ld1 { v30.h }[2], [x27], #0x2\n" - "ld1 { v29.h }[2], [x26], #0x2\n" - "ld1 { v28.h }[2], [x25], #0x2\n" - "ld1 { v27.h }[2], [x24], #0x2\n" - "ld1 { v23.h }[2], [x23], #0x2\n" - "ld1 { v21.h }[2], [x22], #0x2\n" - "ld1 { v26.h }[2], [x21], #0x2\n" - "ld1 { v25.h }[2], [x20], #0x2\n" + "ld1 { v31.h }[2], [x27], #0x2\n" "mov x19, #0x6\n" + "ld1 { v30.h }[2], [x26], #0x2\n" + "ld1 { v29.h }[2], [x25], #0x2\n" + "ld1 { v28.h }[2], [x24], #0x2\n" + "ld1 { v25.h }[2], [x23], #0x2\n" + "ld1 { v23.h }[2], [x22], #0x2\n" + "ld1 { v27.h }[2], [x21], #0x2\n" + "ld1 { v26.h }[2], [x20], #0x2\n" "tbz %x[width], #0, 7f\n" - "ld1 { v30.b }[6], [x27]\n" - "ld1 { v29.b }[6], [x26]\n" - "ld1 { v28.b }[6], [x25]\n" - "ld1 { v27.b }[6], [x24]\n" - "ld1 { v23.b }[6], [x23]\n" - "ld1 { v21.b }[6], [x22]\n" - "ld1 { v26.b }[6], [x21]\n" - "ld1 { v25.b }[6], [x20]\n" + "ld1 { v31.b }[6], [x27]\n" "mov x19, #0x7\n" + "ld1 { v30.b }[6], [x26]\n" + "ld1 { v29.b }[6], [x25]\n" + "ld1 { v28.b }[6], [x24]\n" + "ld1 { v25.b }[6], [x23]\n" + "ld1 { v23.b }[6], [x22]\n" + "ld1 { v27.b }[6], [x21]\n" + "ld1 { v26.b }[6], [x20]\n" "b 7f\n" "4:" // odd_loads_1_4 "mov x19, #0x4\n" "tbz %x[width], #0, 7f\n" - "ld1 { v30.b }[4], [x27]\n" - "ld1 { v29.b }[4], [x26]\n" - "ld1 { v28.b }[4], [x25]\n" - "ld1 { v27.b }[4], [x24]\n" - "ld1 { v23.b }[4], [x23]\n" - "ld1 { v21.b }[4], [x22]\n" - "ld1 { v26.b }[4], [x21]\n" - "ld1 { v25.b }[4], [x20]\n" + "ld1 { v31.b }[4], [x27]\n" + "ld1 { v30.b }[4], [x26]\n" "mov x19, #0x5\n" + "ld1 { v29.b }[4], [x25]\n" + "ld1 { v28.b }[4], [x24]\n" + "ld1 { v25.b }[4], [x23]\n" + "ld1 { v23.b }[4], [x22]\n" + "ld1 { v27.b }[4], [x21]\n" + "ld1 { v26.b }[4], [x20]\n" "b 7f\n" "5:" // odd_loads_2_0 "tbz %x[width], #1, 6f\n" - "ldr h30, [x27], #0x2\n" - "ldr h29, [x26], #0x2\n" - "ldr h28, [x25], #0x2\n" - "ldr h27, [x24], #0x2\n" - "ldr h23, [x23], #0x2\n" - "ldr h21, [x22], #0x2\n" - "ldr h26, [x21], #0x2\n" - "ldr h25, [x20], #0x2\n" + "ldr h31, [x27], #0x2\n" + "ldr h30, [x26], #0x2\n" "mov x19, #0x2\n" + "ldr h29, [x25], #0x2\n" + "ldr h28, [x24], #0x2\n" + "ldr h25, [x23], #0x2\n" + "ldr h23, [x22], #0x2\n" + "ldr h27, [x21], #0x2\n" + "ldr h26, [x20], #0x2\n" "tbz %x[width], #0, 7f\n" - "ld1 { v30.b }[2], [x27]\n" - "ld1 { v29.b }[2], [x26]\n" - "ld1 { v28.b }[2], [x25]\n" - "ld1 { v27.b }[2], [x24]\n" - "ld1 { v23.b }[2], [x23]\n" - "ld1 { v21.b }[2], [x22]\n" - "ld1 { v26.b }[2], [x21]\n" - "ld1 { v25.b }[2], [x20]\n" + "ld1 { v31.b }[2], [x27]\n" "mov x19, #0x3\n" + "ld1 { v30.b }[2], [x26]\n" + "ld1 { v29.b }[2], [x25]\n" + "ld1 { v28.b }[2], [x24]\n" + "ld1 { v25.b }[2], [x23]\n" + "ld1 { v23.b }[2], [x22]\n" + "ld1 { v27.b }[2], [x21]\n" + "ld1 { v26.b }[2], [x20]\n" "b 7f\n" "6:" // odd_loads_1_0 - "ldr b30, [x27, #0x0]\n" - "ldr b29, [x26, #0x0]\n" - "ldr b28, [x25, #0x0]\n" - "ldr b27, [x24, #0x0]\n" - "ldr b23, [x23, #0x0]\n" - "ldr b21, [x22, #0x0]\n" - "ldr b26, [x21, #0x0]\n" - "ldr b25, [x20, #0x0]\n" + "ldr b31, [x27, #0x0]\n" "mov x19, #0x1\n" + "ldr b30, [x26, #0x0]\n" + "ldr b29, [x25, #0x0]\n" + "ldr b28, [x24, #0x0]\n" + "ldr b25, [x23, #0x0]\n" + "ldr b23, [x22, #0x0]\n" + "ldr b27, [x21, #0x0]\n" + "ldr b26, [x20, #0x0]\n" "7:" // Odd load end + "sshll v31.8h, v31.8b, #0x0\n" + "subs x19, x19, #0x1\n" "sshll v30.8h, v30.8b, #0x0\n" "sshll v29.8h, v29.8b, #0x0\n" "sshll v28.8h, v28.8b, #0x0\n" - "sshll v27.8h, v27.8b, #0x0\n" + "sshll v25.8h, v25.8b, #0x0\n" + "zip1 v20.8h, v31.8h, v25.8h\n" "sshll v23.8h, v23.8b, #0x0\n" "zip1 v24.8h, v30.8h, v23.8h\n" - "sshll v21.8h, v21.8b, #0x0\n" + "sshll v27.8h, v27.8b, #0x0\n" + "zip1 v19.8h, v29.8h, v27.8h\n" + "zip1 v22.8h, v20.8h, v19.8h\n" "sshll v26.8h, v26.8b, #0x0\n" - "zip1 v20.8h, v28.8h, v26.8h\n" - "sshll v25.8h, v25.8b, #0x0\n" - "zip1 v22.8h, v29.8h, v21.8h\n" - "subs x19, x19, #0x1\n" - "zip1 v18.8h, v24.8h, v20.8h\n" - "zip1 v19.8h, v27.8h, v25.8h\n" - "zip1 v17.8h, v22.8h, v19.8h\n" - "zip1 v16.8h, v18.8h, v17.8h\n" + "zip1 v18.8h, v28.8h, v26.8h\n" + "zip1 v17.8h, v24.8h, v18.8h\n" + "zip1 v16.8h, v22.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" - "zip2 v16.8h, v18.8h, v17.8h\n" - "subs x19, x19, #0x1\n" + "zip2 v16.8h, v22.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" + "subs x19, x19, #0x1\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" - "zip2 v18.8h, v24.8h, v20.8h\n" - "zip2 v17.8h, v22.8h, v19.8h\n" + "zip2 v21.8h, v20.8h, v19.8h\n" + "zip2 v17.8h, v24.8h, v18.8h\n" "subs x19, x19, #0x1\n" - "zip1 v16.8h, v18.8h, v17.8h\n" + "zip1 v16.8h, v21.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" - "zip2 v16.8h, v18.8h, v17.8h\n" - "subs x19, x19, #0x1\n" + "zip2 v16.8h, v21.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" + "subs x19, x19, #0x1\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" - "zip2 v23.8h, v30.8h, v23.8h\n" - "zip2 v20.8h, v28.8h, v26.8h\n" + "zip2 v25.8h, v31.8h, v25.8h\n" + "zip2 v19.8h, v29.8h, v27.8h\n" "subs x19, x19, #0x1\n" - "zip1 v18.8h, v23.8h, v20.8h\n" - "zip2 v21.8h, v29.8h, v21.8h\n" - "zip2 v19.8h, v27.8h, v25.8h\n" - "zip1 v17.8h, v21.8h, v19.8h\n" - "zip1 v16.8h, v18.8h, v17.8h\n" + "zip1 v20.8h, v25.8h, v19.8h\n" + "zip2 v23.8h, v30.8h, v23.8h\n" + "zip2 v18.8h, v28.8h, v26.8h\n" + "zip1 v17.8h, v23.8h, v18.8h\n" + "zip1 v16.8h, v20.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" - "zip2 v16.8h, v18.8h, v17.8h\n" - "subs x19, x19, #0x1\n" + "zip2 v16.8h, v20.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" + "subs x19, x19, #0x1\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" - "zip2 v18.8h, v23.8h, v20.8h\n" - "zip2 v17.8h, v21.8h, v19.8h\n" - "zip1 v16.8h, v18.8h, v17.8h\n" + "zip2 v19.8h, v25.8h, v19.8h\n" + "zip2 v17.8h, v23.8h, v18.8h\n" + "zip1 v16.8h, v19.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "8:" // Odds skip - : [out_ptr] "+r" (out_ptr), [width] "+r" (width) + : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) - : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" + : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); } diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_s8_s16_summing.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_s8_s16_summing.hpp index 35dc3dc0d4..b710861417 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_s8_s16_summing.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_s8_s16_summing.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020 Arm Limited. + * Copyright (c) 2019-2021 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -96,72 +96,72 @@ void interleave_block<8, 1, VLType::None, true>( "movi v1.8h, #0x0\n" "4:" // no_accumulate_16 "ldr d30, [x27], #0x8\n" - "prfm pldl1keep, [x27, #0x70]\n" + "sshll v30.8h, v30.8b, #0x0\n" "ldr d29, [x26], #0x8\n" + "add x19, x19, #0x1\n" + "sshll v29.8h, v29.8b, #0x0\n" "ldr d28, [x25], #0x8\n" - "prfm pldl1keep, [x26, #0x70]\n" + "subs %x[width], %x[width], #0x8\n" + "sshll v28.8h, v28.8b, #0x0\n" "ldr d27, [x24], #0x8\n" + "cmp %x[width], #0x8\n" + "sshll v27.8h, v27.8b, #0x0\n" + "ldr d24, [x23], #0x8\n" + "ldr d23, [x22], #0x8\n" + "sshll v24.8h, v24.8b, #0x0\n" + "ldr d21, [x21], #0x8\n" + "sshll v23.8h, v23.8b, #0x0\n" + "ldr d26, [x20], #0x8\n" + "zip1 v20.8h, v30.8h, v24.8h\n" + "prfm pldl1keep, [x27, #0x70]\n" + "zip1 v25.8h, v29.8h, v23.8h\n" + "prfm pldl1keep, [x26, #0x70]\n" + "zip2 v24.8h, v30.8h, v24.8h\n" "prfm pldl1keep, [x25, #0x70]\n" - "ldr d23, [x23], #0x8\n" - "ldr d21, [x22], #0x8\n" + "zip2 v23.8h, v29.8h, v23.8h\n" "prfm pldl1keep, [x24, #0x70]\n" - "ldr d26, [x21], #0x8\n" - "ldr d25, [x20], #0x8\n" + "sshll v21.8h, v21.8b, #0x0\n" "prfm pldl1keep, [x23, #0x70]\n" + "zip1 v19.8h, v28.8h, v21.8h\n" "prfm pldl1keep, [x22, #0x70]\n" - "sshll v30.8h, v30.8b, #0x0\n" - "sshll v29.8h, v29.8b, #0x0\n" + "zip1 v22.8h, v20.8h, v19.8h\n" "prfm pldl1keep, [x21, #0x70]\n" - "sshll v28.8h, v28.8b, #0x0\n" + "zip2 v19.8h, v20.8h, v19.8h\n" "prfm pldl1keep, [x20, #0x70]\n" - "sshll v27.8h, v27.8b, #0x0\n" - "sshll v23.8h, v23.8b, #0x0\n" - "zip1 v24.8h, v30.8h, v23.8h\n" - "sshll v21.8h, v21.8b, #0x0\n" - "zip2 v23.8h, v30.8h, v23.8h\n" + "zip2 v20.8h, v28.8h, v21.8h\n" + "zip1 v21.8h, v24.8h, v20.8h\n" + "zip2 v20.8h, v24.8h, v20.8h\n" "sshll v26.8h, v26.8b, #0x0\n" - "sshll v25.8h, v25.8b, #0x0\n" - "zip1 v22.8h, v29.8h, v21.8h\n" - "add x19, x19, #0x1\n" - "zip2 v21.8h, v29.8h, v21.8h\n" - "subs %x[width], %x[width], #0x8\n" - "zip1 v20.8h, v28.8h, v26.8h\n" - "cmp %x[width], #0x8\n" - "zip1 v18.8h, v24.8h, v20.8h\n" - "zip1 v19.8h, v27.8h, v25.8h\n" - "zip1 v17.8h, v22.8h, v19.8h\n" - "zip1 v16.8h, v18.8h, v17.8h\n" + "zip1 v18.8h, v27.8h, v26.8h\n" + "zip1 v17.8h, v25.8h, v18.8h\n" + "zip1 v16.8h, v22.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" "add v1.8h, v1.8h, v16.8h\n" - "zip2 v16.8h, v18.8h, v17.8h\n" - "str q16, [%x[out_ptr], #0x10]\n" - "zip2 v18.8h, v24.8h, v20.8h\n" - "add v1.8h, v1.8h, v16.8h\n" - "zip2 v17.8h, v22.8h, v19.8h\n" - "zip1 v16.8h, v18.8h, v17.8h\n" - "str q16, [%x[out_ptr], #0x20]\n" - "add v1.8h, v1.8h, v16.8h\n" - "zip2 v16.8h, v18.8h, v17.8h\n" + "zip2 v17.8h, v22.8h, v17.8h\n" + "str q17, [%x[out_ptr], #0x10]\n" + "zip2 v16.8h, v25.8h, v18.8h\n" + "add v1.8h, v1.8h, v17.8h\n" + "zip1 v17.8h, v19.8h, v16.8h\n" + "str q17, [%x[out_ptr], #0x20]\n" + "zip2 v16.8h, v19.8h, v16.8h\n" "str q16, [%x[out_ptr], #0x30]\n" - "zip2 v20.8h, v28.8h, v26.8h\n" + "add v1.8h, v1.8h, v17.8h\n" + "zip2 v19.8h, v27.8h, v26.8h\n" + "zip1 v17.8h, v23.8h, v19.8h\n" "add v1.8h, v1.8h, v16.8h\n" - "zip1 v18.8h, v23.8h, v20.8h\n" - "zip2 v19.8h, v27.8h, v25.8h\n" - "zip1 v17.8h, v21.8h, v19.8h\n" - "zip1 v16.8h, v18.8h, v17.8h\n" + "zip1 v16.8h, v21.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x40]\n" + "zip2 v18.8h, v21.8h, v17.8h\n" + "str q18, [%x[out_ptr], #0x50]\n" "add v1.8h, v1.8h, v16.8h\n" - "zip2 v16.8h, v18.8h, v17.8h\n" - "str q16, [%x[out_ptr], #0x50]\n" - "zip2 v18.8h, v23.8h, v20.8h\n" - "add v1.8h, v1.8h, v16.8h\n" - "zip2 v17.8h, v21.8h, v19.8h\n" - "zip1 v16.8h, v18.8h, v17.8h\n" - "str q16, [%x[out_ptr], #0x60]\n" - "add v1.8h, v1.8h, v16.8h\n" - "zip2 v16.8h, v18.8h, v17.8h\n" + "zip2 v16.8h, v23.8h, v19.8h\n" + "zip1 v17.8h, v20.8h, v16.8h\n" + "str q17, [%x[out_ptr], #0x60]\n" + "add v1.8h, v1.8h, v18.8h\n" + "zip2 v16.8h, v20.8h, v16.8h\n" "str q16, [%x[out_ptr], #0x70]\n" "add %x[out_ptr], %x[out_ptr], #0x80\n" + "add v1.8h, v1.8h, v17.8h\n" "add v1.8h, v1.8h, v16.8h\n" "bge 3b\n" "5:" // Main loop skip @@ -171,148 +171,148 @@ void interleave_block<8, 1, VLType::None, true>( "ldr s29, [x26], #0x4\n" "ldr s28, [x25], #0x4\n" "ldr s27, [x24], #0x4\n" - "ldr s23, [x23], #0x4\n" - "ldr s21, [x22], #0x4\n" - "ldr s26, [x21], #0x4\n" - "ldr s25, [x20], #0x4\n" + "ldr s24, [x23], #0x4\n" + "ldr s23, [x22], #0x4\n" + "ldr s21, [x21], #0x4\n" + "ldr s26, [x20], #0x4\n" "tbz %x[width], #1, 6f\n" "ld1 { v30.h }[2], [x27], #0x2\n" + "mov x19, #0x6\n" "ld1 { v29.h }[2], [x26], #0x2\n" "ld1 { v28.h }[2], [x25], #0x2\n" "ld1 { v27.h }[2], [x24], #0x2\n" - "ld1 { v23.h }[2], [x23], #0x2\n" - "ld1 { v21.h }[2], [x22], #0x2\n" - "ld1 { v26.h }[2], [x21], #0x2\n" - "ld1 { v25.h }[2], [x20], #0x2\n" - "mov x19, #0x6\n" + "ld1 { v24.h }[2], [x23], #0x2\n" + "ld1 { v23.h }[2], [x22], #0x2\n" + "ld1 { v21.h }[2], [x21], #0x2\n" + "ld1 { v26.h }[2], [x20], #0x2\n" "tbz %x[width], #0, 9f\n" "ld1 { v30.b }[6], [x27]\n" + "mov x19, #0x7\n" "ld1 { v29.b }[6], [x26]\n" "ld1 { v28.b }[6], [x25]\n" "ld1 { v27.b }[6], [x24]\n" - "ld1 { v23.b }[6], [x23]\n" - "ld1 { v21.b }[6], [x22]\n" - "ld1 { v26.b }[6], [x21]\n" - "ld1 { v25.b }[6], [x20]\n" - "mov x19, #0x7\n" + "ld1 { v24.b }[6], [x23]\n" + "ld1 { v23.b }[6], [x22]\n" + "ld1 { v21.b }[6], [x21]\n" + "ld1 { v26.b }[6], [x20]\n" "b 9f\n" "6:" // odd_loads_1_4 "mov x19, #0x4\n" "tbz %x[width], #0, 9f\n" "ld1 { v30.b }[4], [x27]\n" "ld1 { v29.b }[4], [x26]\n" + "mov x19, #0x5\n" "ld1 { v28.b }[4], [x25]\n" "ld1 { v27.b }[4], [x24]\n" - "ld1 { v23.b }[4], [x23]\n" - "ld1 { v21.b }[4], [x22]\n" - "ld1 { v26.b }[4], [x21]\n" - "ld1 { v25.b }[4], [x20]\n" - "mov x19, #0x5\n" + "ld1 { v24.b }[4], [x23]\n" + "ld1 { v23.b }[4], [x22]\n" + "ld1 { v21.b }[4], [x21]\n" + "ld1 { v26.b }[4], [x20]\n" "b 9f\n" "7:" // odd_loads_2_0 "tbz %x[width], #1, 8f\n" "ldr h30, [x27], #0x2\n" "ldr h29, [x26], #0x2\n" + "mov x19, #0x2\n" "ldr h28, [x25], #0x2\n" "ldr h27, [x24], #0x2\n" - "ldr h23, [x23], #0x2\n" - "ldr h21, [x22], #0x2\n" - "ldr h26, [x21], #0x2\n" - "ldr h25, [x20], #0x2\n" - "mov x19, #0x2\n" + "ldr h24, [x23], #0x2\n" + "ldr h23, [x22], #0x2\n" + "ldr h21, [x21], #0x2\n" + "ldr h26, [x20], #0x2\n" "tbz %x[width], #0, 9f\n" "ld1 { v30.b }[2], [x27]\n" + "mov x19, #0x3\n" "ld1 { v29.b }[2], [x26]\n" "ld1 { v28.b }[2], [x25]\n" "ld1 { v27.b }[2], [x24]\n" - "ld1 { v23.b }[2], [x23]\n" - "ld1 { v21.b }[2], [x22]\n" - "ld1 { v26.b }[2], [x21]\n" - "ld1 { v25.b }[2], [x20]\n" - "mov x19, #0x3\n" + "ld1 { v24.b }[2], [x23]\n" + "ld1 { v23.b }[2], [x22]\n" + "ld1 { v21.b }[2], [x21]\n" + "ld1 { v26.b }[2], [x20]\n" "b 9f\n" "8:" // odd_loads_1_0 "ldr b30, [x27, #0x0]\n" + "mov x19, #0x1\n" "ldr b29, [x26, #0x0]\n" "ldr b28, [x25, #0x0]\n" "ldr b27, [x24, #0x0]\n" - "ldr b23, [x23, #0x0]\n" - "ldr b21, [x22, #0x0]\n" - "ldr b26, [x21, #0x0]\n" - "ldr b25, [x20, #0x0]\n" - "mov x19, #0x1\n" + "ldr b24, [x23, #0x0]\n" + "ldr b23, [x22, #0x0]\n" + "ldr b21, [x21, #0x0]\n" + "ldr b26, [x20, #0x0]\n" "9:" // Odd load end "sshll v30.8h, v30.8b, #0x0\n" + "subs x19, x19, #0x1\n" "sshll v29.8h, v29.8b, #0x0\n" "sshll v28.8h, v28.8b, #0x0\n" "sshll v27.8h, v27.8b, #0x0\n" + "sshll v24.8h, v24.8b, #0x0\n" + "zip1 v20.8h, v30.8h, v24.8h\n" "sshll v23.8h, v23.8b, #0x0\n" - "zip1 v24.8h, v30.8h, v23.8h\n" + "zip1 v25.8h, v29.8h, v23.8h\n" "sshll v21.8h, v21.8b, #0x0\n" + "zip1 v19.8h, v28.8h, v21.8h\n" + "zip1 v22.8h, v20.8h, v19.8h\n" "sshll v26.8h, v26.8b, #0x0\n" - "zip1 v20.8h, v28.8h, v26.8h\n" - "sshll v25.8h, v25.8b, #0x0\n" - "zip1 v22.8h, v29.8h, v21.8h\n" - "subs x19, x19, #0x1\n" - "zip1 v18.8h, v24.8h, v20.8h\n" - "zip1 v19.8h, v27.8h, v25.8h\n" - "zip1 v17.8h, v22.8h, v19.8h\n" - "zip1 v16.8h, v18.8h, v17.8h\n" + "zip1 v18.8h, v27.8h, v26.8h\n" + "zip1 v17.8h, v25.8h, v18.8h\n" + "zip1 v16.8h, v22.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" - "add v1.8h, v1.8h, v16.8h\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" + "add v1.8h, v1.8h, v16.8h\n" "beq 10f\n" - "zip2 v16.8h, v18.8h, v17.8h\n" + "zip2 v17.8h, v22.8h, v17.8h\n" + "str q17, [%x[out_ptr], #0x0]\n" "subs x19, x19, #0x1\n" - "add v1.8h, v1.8h, v16.8h\n" - "str q16, [%x[out_ptr], #0x0]\n" + "add v1.8h, v1.8h, v17.8h\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 10f\n" - "zip2 v18.8h, v24.8h, v20.8h\n" - "zip2 v17.8h, v22.8h, v19.8h\n" + "zip2 v19.8h, v20.8h, v19.8h\n" + "zip2 v16.8h, v25.8h, v18.8h\n" "subs x19, x19, #0x1\n" - "zip1 v16.8h, v18.8h, v17.8h\n" - "str q16, [%x[out_ptr], #0x0]\n" - "add v1.8h, v1.8h, v16.8h\n" + "zip1 v17.8h, v19.8h, v16.8h\n" + "str q17, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" + "add v1.8h, v1.8h, v17.8h\n" "beq 10f\n" - "zip2 v16.8h, v18.8h, v17.8h\n" + "zip2 v16.8h, v19.8h, v16.8h\n" + "str q16, [%x[out_ptr], #0x0]\n" "subs x19, x19, #0x1\n" "add v1.8h, v1.8h, v16.8h\n" - "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 10f\n" - "zip2 v23.8h, v30.8h, v23.8h\n" - "zip2 v20.8h, v28.8h, v26.8h\n" + "zip2 v24.8h, v30.8h, v24.8h\n" + "zip2 v20.8h, v28.8h, v21.8h\n" "subs x19, x19, #0x1\n" - "zip1 v18.8h, v23.8h, v20.8h\n" - "zip2 v21.8h, v29.8h, v21.8h\n" - "zip2 v19.8h, v27.8h, v25.8h\n" - "zip1 v17.8h, v21.8h, v19.8h\n" - "zip1 v16.8h, v18.8h, v17.8h\n" + "zip1 v21.8h, v24.8h, v20.8h\n" + "zip2 v23.8h, v29.8h, v23.8h\n" + "zip2 v19.8h, v27.8h, v26.8h\n" + "zip1 v17.8h, v23.8h, v19.8h\n" + "zip1 v16.8h, v21.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" - "add v1.8h, v1.8h, v16.8h\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" + "add v1.8h, v1.8h, v16.8h\n" "beq 10f\n" - "zip2 v16.8h, v18.8h, v17.8h\n" + "zip2 v18.8h, v21.8h, v17.8h\n" + "str q18, [%x[out_ptr], #0x0]\n" "subs x19, x19, #0x1\n" - "add v1.8h, v1.8h, v16.8h\n" - "str q16, [%x[out_ptr], #0x0]\n" + "add v1.8h, v1.8h, v18.8h\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 10f\n" - "zip2 v18.8h, v23.8h, v20.8h\n" - "zip2 v17.8h, v21.8h, v19.8h\n" - "zip1 v16.8h, v18.8h, v17.8h\n" - "str q16, [%x[out_ptr], #0x0]\n" - "add v1.8h, v1.8h, v16.8h\n" + "zip2 v20.8h, v24.8h, v20.8h\n" + "zip2 v16.8h, v23.8h, v19.8h\n" + "zip1 v17.8h, v20.8h, v16.8h\n" + "str q17, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" + "add v1.8h, v1.8h, v17.8h\n" "10:" // Odds skip "saddw v0.4s, v0.4s, v1.4h\n" "str q0, [%x[out_ptr], #0x0]\n" "saddw2 v31.4s, v31.4s, v1.8h\n" "str q31, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" - : [out_ptr] "+r" (out_ptr), [width] "+r" (width) + : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [first] "r" (first), [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) : "cc", "memory", "v0", "v1", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_u16_u16_summing.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_u16_u16_summing.hpp index bfa8989a4d..24ece9a68e 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_u16_u16_summing.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_u16_u16_summing.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020 Arm Limited. + * Copyright (c) 2019-2021 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -96,58 +96,58 @@ void interleave_block<8, 1, VLType::None, true>( "movi v1.8h, #0x0\n" "4:" // no_accumulate_16 "ldr q30, [x27], #0x10\n" - "prfm pldl1keep, [x27, #0x70]\n" + "add x19, x19, #0x1\n" "ldr q29, [x26], #0x10\n" + "subs %x[width], %x[width], #0x8\n" "ldr q28, [x25], #0x10\n" - "prfm pldl1keep, [x26, #0x70]\n" + "cmp %x[width], #0x8\n" "ldr q27, [x24], #0x10\n" + "ldr q25, [x23], #0x10\n" + "zip1 v26.8h, v30.8h, v25.8h\n" + "ldr q21, [x22], #0x10\n" + "zip2 v25.8h, v30.8h, v25.8h\n" + "ldr q24, [x21], #0x10\n" + "ldr q23, [x20], #0x10\n" + "zip1 v22.8h, v29.8h, v21.8h\n" + "prfm pldl1keep, [x27, #0x70]\n" + "zip2 v21.8h, v29.8h, v21.8h\n" + "prfm pldl1keep, [x26, #0x70]\n" + "zip1 v20.8h, v28.8h, v24.8h\n" "prfm pldl1keep, [x25, #0x70]\n" - "ldr q24, [x23], #0x10\n" - "zip1 v26.8h, v30.8h, v24.8h\n" + "zip1 v18.8h, v26.8h, v20.8h\n" "prfm pldl1keep, [x24, #0x70]\n" - "ldr q25, [x22], #0x10\n" - "zip2 v24.8h, v30.8h, v24.8h\n" + "zip1 v19.8h, v27.8h, v23.8h\n" "prfm pldl1keep, [x23, #0x70]\n" - "ldr q23, [x21], #0x10\n" - "zip1 v21.8h, v29.8h, v25.8h\n" + "zip1 v16.8h, v22.8h, v19.8h\n" "prfm pldl1keep, [x22, #0x70]\n" - "ldr q22, [x20], #0x10\n" - "zip1 v18.8h, v28.8h, v23.8h\n" + "zip1 v17.8h, v18.8h, v16.8h\n" "prfm pldl1keep, [x21, #0x70]\n" - "add x19, x19, #0x1\n" - "zip1 v20.8h, v26.8h, v18.8h\n" - "prfm pldl1keep, [x20, #0x70]\n" - "zip1 v19.8h, v27.8h, v22.8h\n" - "subs %x[width], %x[width], #0x8\n" - "zip1 v17.8h, v21.8h, v19.8h\n" - "cmp %x[width], #0x8\n" - "zip2 v18.8h, v26.8h, v18.8h\n" - "zip1 v16.8h, v20.8h, v17.8h\n" - "str q16, [%x[out_ptr], #0x0]\n" - "add v1.8h, v1.8h, v16.8h\n" - "zip2 v17.8h, v20.8h, v17.8h\n" - "str q17, [%x[out_ptr], #0x10]\n" - "zip2 v16.8h, v21.8h, v19.8h\n" "add v1.8h, v1.8h, v17.8h\n" - "zip1 v17.8h, v18.8h, v16.8h\n" - "str q17, [%x[out_ptr], #0x20]\n" + "prfm pldl1keep, [x20, #0x70]\n" "zip2 v16.8h, v18.8h, v16.8h\n" + "str q17, [%x[out_ptr], #0x0]\n" + "zip2 v18.8h, v26.8h, v20.8h\n" + "str q16, [%x[out_ptr], #0x10]\n" + "add v1.8h, v1.8h, v16.8h\n" + "zip2 v17.8h, v22.8h, v19.8h\n" + "zip1 v16.8h, v18.8h, v17.8h\n" + "str q16, [%x[out_ptr], #0x20]\n" + "add v1.8h, v1.8h, v16.8h\n" + "zip2 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x30]\n" - "add v1.8h, v1.8h, v17.8h\n" - "zip2 v21.8h, v28.8h, v23.8h\n" - "zip1 v18.8h, v24.8h, v21.8h\n" + "zip2 v20.8h, v28.8h, v24.8h\n" "add v1.8h, v1.8h, v16.8h\n" - "zip2 v20.8h, v29.8h, v25.8h\n" - "zip2 v19.8h, v27.8h, v22.8h\n" - "zip1 v17.8h, v20.8h, v19.8h\n" + "zip1 v18.8h, v25.8h, v20.8h\n" + "zip2 v19.8h, v27.8h, v23.8h\n" + "zip1 v17.8h, v21.8h, v19.8h\n" "zip1 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x40]\n" "add v1.8h, v1.8h, v16.8h\n" "zip2 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x50]\n" - "zip2 v18.8h, v24.8h, v21.8h\n" + "zip2 v18.8h, v25.8h, v20.8h\n" "add v1.8h, v1.8h, v16.8h\n" - "zip2 v17.8h, v20.8h, v19.8h\n" + "zip2 v17.8h, v21.8h, v19.8h\n" "zip1 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x60]\n" "add v1.8h, v1.8h, v16.8h\n" @@ -163,140 +163,140 @@ void interleave_block<8, 1, VLType::None, true>( "ldr d29, [x26], #0x8\n" "ldr d28, [x25], #0x8\n" "ldr d27, [x24], #0x8\n" - "ldr d24, [x23], #0x8\n" - "ldr d25, [x22], #0x8\n" - "ldr d23, [x21], #0x8\n" - "ldr d22, [x20], #0x8\n" + "ldr d25, [x23], #0x8\n" + "ldr d21, [x22], #0x8\n" + "ldr d24, [x21], #0x8\n" + "ldr d23, [x20], #0x8\n" "tbz %x[width], #1, 6f\n" "ld1 { v30.s }[2], [x27], #0x4\n" + "mov x19, #0x6\n" "ld1 { v29.s }[2], [x26], #0x4\n" "ld1 { v28.s }[2], [x25], #0x4\n" "ld1 { v27.s }[2], [x24], #0x4\n" - "ld1 { v24.s }[2], [x23], #0x4\n" - "ld1 { v25.s }[2], [x22], #0x4\n" - "ld1 { v23.s }[2], [x21], #0x4\n" - "ld1 { v22.s }[2], [x20], #0x4\n" - "mov x19, #0x6\n" + "ld1 { v25.s }[2], [x23], #0x4\n" + "ld1 { v21.s }[2], [x22], #0x4\n" + "ld1 { v24.s }[2], [x21], #0x4\n" + "ld1 { v23.s }[2], [x20], #0x4\n" "tbz %x[width], #0, 9f\n" "ld1 { v30.h }[6], [x27]\n" + "mov x19, #0x7\n" "ld1 { v29.h }[6], [x26]\n" "ld1 { v28.h }[6], [x25]\n" "ld1 { v27.h }[6], [x24]\n" - "ld1 { v24.h }[6], [x23]\n" - "ld1 { v25.h }[6], [x22]\n" - "ld1 { v23.h }[6], [x21]\n" - "ld1 { v22.h }[6], [x20]\n" - "mov x19, #0x7\n" + "ld1 { v25.h }[6], [x23]\n" + "ld1 { v21.h }[6], [x22]\n" + "ld1 { v24.h }[6], [x21]\n" + "ld1 { v23.h }[6], [x20]\n" "b 9f\n" "6:" // odd_loads_1_4 "mov x19, #0x4\n" "tbz %x[width], #0, 9f\n" "ld1 { v30.h }[4], [x27]\n" "ld1 { v29.h }[4], [x26]\n" + "mov x19, #0x5\n" "ld1 { v28.h }[4], [x25]\n" "ld1 { v27.h }[4], [x24]\n" - "ld1 { v24.h }[4], [x23]\n" - "ld1 { v25.h }[4], [x22]\n" - "ld1 { v23.h }[4], [x21]\n" - "ld1 { v22.h }[4], [x20]\n" - "mov x19, #0x5\n" + "ld1 { v25.h }[4], [x23]\n" + "ld1 { v21.h }[4], [x22]\n" + "ld1 { v24.h }[4], [x21]\n" + "ld1 { v23.h }[4], [x20]\n" "b 9f\n" "7:" // odd_loads_2_0 "tbz %x[width], #1, 8f\n" "ldr s30, [x27], #0x4\n" "ldr s29, [x26], #0x4\n" + "mov x19, #0x2\n" "ldr s28, [x25], #0x4\n" "ldr s27, [x24], #0x4\n" - "ldr s24, [x23], #0x4\n" - "ldr s25, [x22], #0x4\n" - "ldr s23, [x21], #0x4\n" - "ldr s22, [x20], #0x4\n" - "mov x19, #0x2\n" + "ldr s25, [x23], #0x4\n" + "ldr s21, [x22], #0x4\n" + "ldr s24, [x21], #0x4\n" + "ldr s23, [x20], #0x4\n" "tbz %x[width], #0, 9f\n" "ld1 { v30.h }[2], [x27]\n" + "mov x19, #0x3\n" "ld1 { v29.h }[2], [x26]\n" "ld1 { v28.h }[2], [x25]\n" "ld1 { v27.h }[2], [x24]\n" - "ld1 { v24.h }[2], [x23]\n" - "ld1 { v25.h }[2], [x22]\n" - "ld1 { v23.h }[2], [x21]\n" - "ld1 { v22.h }[2], [x20]\n" - "mov x19, #0x3\n" + "ld1 { v25.h }[2], [x23]\n" + "ld1 { v21.h }[2], [x22]\n" + "ld1 { v24.h }[2], [x21]\n" + "ld1 { v23.h }[2], [x20]\n" "b 9f\n" "8:" // odd_loads_1_0 "ldr h30, [x27, #0x0]\n" + "mov x19, #0x1\n" "ldr h29, [x26, #0x0]\n" "ldr h28, [x25, #0x0]\n" "ldr h27, [x24, #0x0]\n" - "ldr h24, [x23, #0x0]\n" - "ldr h25, [x22, #0x0]\n" - "ldr h23, [x21, #0x0]\n" - "ldr h22, [x20, #0x0]\n" - "mov x19, #0x1\n" + "ldr h25, [x23, #0x0]\n" + "ldr h21, [x22, #0x0]\n" + "ldr h24, [x21, #0x0]\n" + "ldr h23, [x20, #0x0]\n" "9:" // Odd load end - "zip1 v26.8h, v30.8h, v24.8h\n" + "zip1 v26.8h, v30.8h, v25.8h\n" "subs x19, x19, #0x1\n" - "zip1 v18.8h, v28.8h, v23.8h\n" - "zip1 v20.8h, v26.8h, v18.8h\n" - "zip1 v21.8h, v29.8h, v25.8h\n" - "zip1 v19.8h, v27.8h, v22.8h\n" - "zip1 v17.8h, v21.8h, v19.8h\n" - "zip1 v16.8h, v20.8h, v17.8h\n" - "str q16, [%x[out_ptr], #0x0]\n" - "add v1.8h, v1.8h, v16.8h\n" + "zip1 v20.8h, v28.8h, v24.8h\n" + "zip1 v18.8h, v26.8h, v20.8h\n" + "zip1 v22.8h, v29.8h, v21.8h\n" + "zip1 v19.8h, v27.8h, v23.8h\n" + "zip1 v16.8h, v22.8h, v19.8h\n" + "zip1 v17.8h, v18.8h, v16.8h\n" + "str q17, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" + "add v1.8h, v1.8h, v17.8h\n" "beq 10f\n" - "zip2 v17.8h, v20.8h, v17.8h\n" + "zip2 v16.8h, v18.8h, v16.8h\n" + "str q16, [%x[out_ptr], #0x0]\n" "subs x19, x19, #0x1\n" - "add v1.8h, v1.8h, v17.8h\n" - "str q17, [%x[out_ptr], #0x0]\n" + "add v1.8h, v1.8h, v16.8h\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 10f\n" - "zip2 v18.8h, v26.8h, v18.8h\n" - "zip2 v16.8h, v21.8h, v19.8h\n" + "zip2 v18.8h, v26.8h, v20.8h\n" + "zip2 v17.8h, v22.8h, v19.8h\n" "subs x19, x19, #0x1\n" - "zip1 v17.8h, v18.8h, v16.8h\n" - "str q17, [%x[out_ptr], #0x0]\n" - "add v1.8h, v1.8h, v17.8h\n" + "zip1 v16.8h, v18.8h, v17.8h\n" + "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" + "add v1.8h, v1.8h, v16.8h\n" "beq 10f\n" - "zip2 v16.8h, v18.8h, v16.8h\n" + "zip2 v16.8h, v18.8h, v17.8h\n" + "str q16, [%x[out_ptr], #0x0]\n" "subs x19, x19, #0x1\n" "add v1.8h, v1.8h, v16.8h\n" - "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 10f\n" - "zip2 v24.8h, v30.8h, v24.8h\n" - "zip2 v21.8h, v28.8h, v23.8h\n" + "zip2 v25.8h, v30.8h, v25.8h\n" + "zip2 v20.8h, v28.8h, v24.8h\n" "subs x19, x19, #0x1\n" - "zip1 v18.8h, v24.8h, v21.8h\n" - "zip2 v20.8h, v29.8h, v25.8h\n" - "zip2 v19.8h, v27.8h, v22.8h\n" - "zip1 v17.8h, v20.8h, v19.8h\n" + "zip1 v18.8h, v25.8h, v20.8h\n" + "zip2 v21.8h, v29.8h, v21.8h\n" + "zip2 v19.8h, v27.8h, v23.8h\n" + "zip1 v17.8h, v21.8h, v19.8h\n" "zip1 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" - "add v1.8h, v1.8h, v16.8h\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" + "add v1.8h, v1.8h, v16.8h\n" "beq 10f\n" "zip2 v16.8h, v18.8h, v17.8h\n" + "str q16, [%x[out_ptr], #0x0]\n" "subs x19, x19, #0x1\n" "add v1.8h, v1.8h, v16.8h\n" - "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 10f\n" - "zip2 v18.8h, v24.8h, v21.8h\n" - "zip2 v17.8h, v20.8h, v19.8h\n" + "zip2 v18.8h, v25.8h, v20.8h\n" + "zip2 v17.8h, v21.8h, v19.8h\n" "zip1 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" - "add v1.8h, v1.8h, v16.8h\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" + "add v1.8h, v1.8h, v16.8h\n" "10:" // Odds skip "uaddw v0.4s, v0.4s, v1.4h\n" "str q0, [%x[out_ptr], #0x0]\n" "uaddw2 v31.4s, v31.4s, v1.8h\n" "str q31, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" - : [out_ptr] "+r" (out_ptr), [width] "+r" (width) + : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [first] "r" (first), [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) : "cc", "memory", "v0", "v1", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_u8_u16.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_u8_u16.hpp index 86b90f1898..0db2f7fd51 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_u8_u16.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_u8_u16.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020 Arm Limited. + * Copyright (c) 2019-2021 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -79,206 +79,206 @@ void interleave_block<8, 1, VLType::None, false>( "prfm pldl1keep, [x20, #0x40]\n" "blt 3f\n" "2:" // Main loop head - "ldr d30, [x27], #0x8\n" + "ldr d31, [x27], #0x8\n" + "ushll v31.8h, v31.8b, #0x0\n" + "ldr d30, [x26], #0x8\n" + "subs %x[width], %x[width], #0x8\n" + "ushll v30.8h, v30.8b, #0x0\n" + "ldr d29, [x25], #0x8\n" + "cmp %x[width], #0x8\n" + "ushll v29.8h, v29.8b, #0x0\n" + "ldr d28, [x24], #0x8\n" + "ldr d25, [x23], #0x8\n" + "ushll v28.8h, v28.8b, #0x0\n" + "ldr d23, [x22], #0x8\n" + "ushll v25.8h, v25.8b, #0x0\n" + "ldr d27, [x21], #0x8\n" + "zip1 v20.8h, v31.8h, v25.8h\n" + "ldr d26, [x20], #0x8\n" + "zip2 v25.8h, v31.8h, v25.8h\n" "prfm pldl1keep, [x27, #0x70]\n" - "ldr d29, [x26], #0x8\n" - "ldr d28, [x25], #0x8\n" "prfm pldl1keep, [x26, #0x70]\n" - "ldr d27, [x24], #0x8\n" + "ushll v23.8h, v23.8b, #0x0\n" "prfm pldl1keep, [x25, #0x70]\n" - "ldr d23, [x23], #0x8\n" - "ldr d21, [x22], #0x8\n" + "zip1 v24.8h, v30.8h, v23.8h\n" + "zip2 v23.8h, v30.8h, v23.8h\n" "prfm pldl1keep, [x24, #0x70]\n" - "ldr d26, [x21], #0x8\n" - "ldr d25, [x20], #0x8\n" + "ushll v27.8h, v27.8b, #0x0\n" "prfm pldl1keep, [x23, #0x70]\n" + "zip1 v19.8h, v29.8h, v27.8h\n" "prfm pldl1keep, [x22, #0x70]\n" - "ushll v30.8h, v30.8b, #0x0\n" - "ushll v29.8h, v29.8b, #0x0\n" + "zip1 v22.8h, v20.8h, v19.8h\n" "prfm pldl1keep, [x21, #0x70]\n" - "ushll v28.8h, v28.8b, #0x0\n" + "zip2 v21.8h, v20.8h, v19.8h\n" "prfm pldl1keep, [x20, #0x70]\n" - "ushll v27.8h, v27.8b, #0x0\n" - "ushll v23.8h, v23.8b, #0x0\n" - "zip1 v24.8h, v30.8h, v23.8h\n" - "ushll v21.8h, v21.8b, #0x0\n" - "zip2 v23.8h, v30.8h, v23.8h\n" + "zip2 v19.8h, v29.8h, v27.8h\n" + "zip1 v20.8h, v25.8h, v19.8h\n" + "zip2 v19.8h, v25.8h, v19.8h\n" "ushll v26.8h, v26.8b, #0x0\n" - "ushll v25.8h, v25.8b, #0x0\n" - "zip1 v22.8h, v29.8h, v21.8h\n" - "subs %x[width], %x[width], #0x8\n" - "zip2 v21.8h, v29.8h, v21.8h\n" - "cmp %x[width], #0x8\n" - "zip1 v20.8h, v28.8h, v26.8h\n" - "zip1 v18.8h, v24.8h, v20.8h\n" - "zip1 v19.8h, v27.8h, v25.8h\n" - "zip1 v17.8h, v22.8h, v19.8h\n" - "zip1 v16.8h, v18.8h, v17.8h\n" + "zip1 v18.8h, v28.8h, v26.8h\n" + "zip1 v17.8h, v24.8h, v18.8h\n" + "zip1 v16.8h, v22.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" - "zip2 v16.8h, v18.8h, v17.8h\n" + "zip2 v16.8h, v22.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x10]\n" - "zip2 v18.8h, v24.8h, v20.8h\n" - "zip2 v17.8h, v22.8h, v19.8h\n" - "zip1 v16.8h, v18.8h, v17.8h\n" + "zip2 v17.8h, v24.8h, v18.8h\n" + "zip1 v16.8h, v21.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x20]\n" - "zip2 v16.8h, v18.8h, v17.8h\n" + "zip2 v16.8h, v21.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x30]\n" - "zip2 v20.8h, v28.8h, v26.8h\n" - "zip1 v18.8h, v23.8h, v20.8h\n" - "zip2 v19.8h, v27.8h, v25.8h\n" - "zip1 v17.8h, v21.8h, v19.8h\n" - "zip1 v16.8h, v18.8h, v17.8h\n" + "zip2 v18.8h, v28.8h, v26.8h\n" + "zip1 v17.8h, v23.8h, v18.8h\n" + "zip1 v16.8h, v20.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x40]\n" - "zip2 v16.8h, v18.8h, v17.8h\n" + "zip2 v16.8h, v20.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x50]\n" - "zip2 v18.8h, v23.8h, v20.8h\n" - "zip2 v17.8h, v21.8h, v19.8h\n" - "zip1 v16.8h, v18.8h, v17.8h\n" + "zip2 v17.8h, v23.8h, v18.8h\n" + "zip1 v16.8h, v19.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x60]\n" - "zip2 v16.8h, v18.8h, v17.8h\n" + "zip2 v16.8h, v19.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x70]\n" "add %x[out_ptr], %x[out_ptr], #0x80\n" "bge 2b\n" "3:" // Main loop skip "cbz %x[width], 8f\n" "tbz %x[width], #2, 5f\n" - "ldr s30, [x27], #0x4\n" - "ldr s29, [x26], #0x4\n" - "ldr s28, [x25], #0x4\n" - "ldr s27, [x24], #0x4\n" - "ldr s23, [x23], #0x4\n" - "ldr s21, [x22], #0x4\n" - "ldr s26, [x21], #0x4\n" - "ldr s25, [x20], #0x4\n" + "ldr s31, [x27], #0x4\n" + "ldr s30, [x26], #0x4\n" + "ldr s29, [x25], #0x4\n" + "ldr s28, [x24], #0x4\n" + "ldr s25, [x23], #0x4\n" + "ldr s23, [x22], #0x4\n" + "ldr s27, [x21], #0x4\n" + "ldr s26, [x20], #0x4\n" "tbz %x[width], #1, 4f\n" - "ld1 { v30.h }[2], [x27], #0x2\n" - "ld1 { v29.h }[2], [x26], #0x2\n" - "ld1 { v28.h }[2], [x25], #0x2\n" - "ld1 { v27.h }[2], [x24], #0x2\n" - "ld1 { v23.h }[2], [x23], #0x2\n" - "ld1 { v21.h }[2], [x22], #0x2\n" - "ld1 { v26.h }[2], [x21], #0x2\n" - "ld1 { v25.h }[2], [x20], #0x2\n" + "ld1 { v31.h }[2], [x27], #0x2\n" "mov x19, #0x6\n" + "ld1 { v30.h }[2], [x26], #0x2\n" + "ld1 { v29.h }[2], [x25], #0x2\n" + "ld1 { v28.h }[2], [x24], #0x2\n" + "ld1 { v25.h }[2], [x23], #0x2\n" + "ld1 { v23.h }[2], [x22], #0x2\n" + "ld1 { v27.h }[2], [x21], #0x2\n" + "ld1 { v26.h }[2], [x20], #0x2\n" "tbz %x[width], #0, 7f\n" - "ld1 { v30.b }[6], [x27]\n" - "ld1 { v29.b }[6], [x26]\n" - "ld1 { v28.b }[6], [x25]\n" - "ld1 { v27.b }[6], [x24]\n" - "ld1 { v23.b }[6], [x23]\n" - "ld1 { v21.b }[6], [x22]\n" - "ld1 { v26.b }[6], [x21]\n" - "ld1 { v25.b }[6], [x20]\n" + "ld1 { v31.b }[6], [x27]\n" "mov x19, #0x7\n" + "ld1 { v30.b }[6], [x26]\n" + "ld1 { v29.b }[6], [x25]\n" + "ld1 { v28.b }[6], [x24]\n" + "ld1 { v25.b }[6], [x23]\n" + "ld1 { v23.b }[6], [x22]\n" + "ld1 { v27.b }[6], [x21]\n" + "ld1 { v26.b }[6], [x20]\n" "b 7f\n" "4:" // odd_loads_1_4 "mov x19, #0x4\n" "tbz %x[width], #0, 7f\n" - "ld1 { v30.b }[4], [x27]\n" - "ld1 { v29.b }[4], [x26]\n" - "ld1 { v28.b }[4], [x25]\n" - "ld1 { v27.b }[4], [x24]\n" - "ld1 { v23.b }[4], [x23]\n" - "ld1 { v21.b }[4], [x22]\n" - "ld1 { v26.b }[4], [x21]\n" - "ld1 { v25.b }[4], [x20]\n" + "ld1 { v31.b }[4], [x27]\n" + "ld1 { v30.b }[4], [x26]\n" "mov x19, #0x5\n" + "ld1 { v29.b }[4], [x25]\n" + "ld1 { v28.b }[4], [x24]\n" + "ld1 { v25.b }[4], [x23]\n" + "ld1 { v23.b }[4], [x22]\n" + "ld1 { v27.b }[4], [x21]\n" + "ld1 { v26.b }[4], [x20]\n" "b 7f\n" "5:" // odd_loads_2_0 "tbz %x[width], #1, 6f\n" - "ldr h30, [x27], #0x2\n" - "ldr h29, [x26], #0x2\n" - "ldr h28, [x25], #0x2\n" - "ldr h27, [x24], #0x2\n" - "ldr h23, [x23], #0x2\n" - "ldr h21, [x22], #0x2\n" - "ldr h26, [x21], #0x2\n" - "ldr h25, [x20], #0x2\n" + "ldr h31, [x27], #0x2\n" + "ldr h30, [x26], #0x2\n" "mov x19, #0x2\n" + "ldr h29, [x25], #0x2\n" + "ldr h28, [x24], #0x2\n" + "ldr h25, [x23], #0x2\n" + "ldr h23, [x22], #0x2\n" + "ldr h27, [x21], #0x2\n" + "ldr h26, [x20], #0x2\n" "tbz %x[width], #0, 7f\n" - "ld1 { v30.b }[2], [x27]\n" - "ld1 { v29.b }[2], [x26]\n" - "ld1 { v28.b }[2], [x25]\n" - "ld1 { v27.b }[2], [x24]\n" - "ld1 { v23.b }[2], [x23]\n" - "ld1 { v21.b }[2], [x22]\n" - "ld1 { v26.b }[2], [x21]\n" - "ld1 { v25.b }[2], [x20]\n" + "ld1 { v31.b }[2], [x27]\n" "mov x19, #0x3\n" + "ld1 { v30.b }[2], [x26]\n" + "ld1 { v29.b }[2], [x25]\n" + "ld1 { v28.b }[2], [x24]\n" + "ld1 { v25.b }[2], [x23]\n" + "ld1 { v23.b }[2], [x22]\n" + "ld1 { v27.b }[2], [x21]\n" + "ld1 { v26.b }[2], [x20]\n" "b 7f\n" "6:" // odd_loads_1_0 - "ldr b30, [x27, #0x0]\n" - "ldr b29, [x26, #0x0]\n" - "ldr b28, [x25, #0x0]\n" - "ldr b27, [x24, #0x0]\n" - "ldr b23, [x23, #0x0]\n" - "ldr b21, [x22, #0x0]\n" - "ldr b26, [x21, #0x0]\n" - "ldr b25, [x20, #0x0]\n" + "ldr b31, [x27, #0x0]\n" "mov x19, #0x1\n" + "ldr b30, [x26, #0x0]\n" + "ldr b29, [x25, #0x0]\n" + "ldr b28, [x24, #0x0]\n" + "ldr b25, [x23, #0x0]\n" + "ldr b23, [x22, #0x0]\n" + "ldr b27, [x21, #0x0]\n" + "ldr b26, [x20, #0x0]\n" "7:" // Odd load end + "ushll v31.8h, v31.8b, #0x0\n" + "subs x19, x19, #0x1\n" "ushll v30.8h, v30.8b, #0x0\n" "ushll v29.8h, v29.8b, #0x0\n" "ushll v28.8h, v28.8b, #0x0\n" - "ushll v27.8h, v27.8b, #0x0\n" + "ushll v25.8h, v25.8b, #0x0\n" + "zip1 v20.8h, v31.8h, v25.8h\n" "ushll v23.8h, v23.8b, #0x0\n" "zip1 v24.8h, v30.8h, v23.8h\n" - "ushll v21.8h, v21.8b, #0x0\n" + "ushll v27.8h, v27.8b, #0x0\n" + "zip1 v19.8h, v29.8h, v27.8h\n" + "zip1 v22.8h, v20.8h, v19.8h\n" "ushll v26.8h, v26.8b, #0x0\n" - "zip1 v20.8h, v28.8h, v26.8h\n" - "ushll v25.8h, v25.8b, #0x0\n" - "zip1 v22.8h, v29.8h, v21.8h\n" - "subs x19, x19, #0x1\n" - "zip1 v18.8h, v24.8h, v20.8h\n" - "zip1 v19.8h, v27.8h, v25.8h\n" - "zip1 v17.8h, v22.8h, v19.8h\n" - "zip1 v16.8h, v18.8h, v17.8h\n" + "zip1 v18.8h, v28.8h, v26.8h\n" + "zip1 v17.8h, v24.8h, v18.8h\n" + "zip1 v16.8h, v22.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" - "zip2 v16.8h, v18.8h, v17.8h\n" - "subs x19, x19, #0x1\n" + "zip2 v16.8h, v22.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" + "subs x19, x19, #0x1\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" - "zip2 v18.8h, v24.8h, v20.8h\n" - "zip2 v17.8h, v22.8h, v19.8h\n" + "zip2 v21.8h, v20.8h, v19.8h\n" + "zip2 v17.8h, v24.8h, v18.8h\n" "subs x19, x19, #0x1\n" - "zip1 v16.8h, v18.8h, v17.8h\n" + "zip1 v16.8h, v21.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" - "zip2 v16.8h, v18.8h, v17.8h\n" - "subs x19, x19, #0x1\n" + "zip2 v16.8h, v21.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" + "subs x19, x19, #0x1\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" - "zip2 v23.8h, v30.8h, v23.8h\n" - "zip2 v20.8h, v28.8h, v26.8h\n" + "zip2 v25.8h, v31.8h, v25.8h\n" + "zip2 v19.8h, v29.8h, v27.8h\n" "subs x19, x19, #0x1\n" - "zip1 v18.8h, v23.8h, v20.8h\n" - "zip2 v21.8h, v29.8h, v21.8h\n" - "zip2 v19.8h, v27.8h, v25.8h\n" - "zip1 v17.8h, v21.8h, v19.8h\n" - "zip1 v16.8h, v18.8h, v17.8h\n" + "zip1 v20.8h, v25.8h, v19.8h\n" + "zip2 v23.8h, v30.8h, v23.8h\n" + "zip2 v18.8h, v28.8h, v26.8h\n" + "zip1 v17.8h, v23.8h, v18.8h\n" + "zip1 v16.8h, v20.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" - "zip2 v16.8h, v18.8h, v17.8h\n" - "subs x19, x19, #0x1\n" + "zip2 v16.8h, v20.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" + "subs x19, x19, #0x1\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" - "zip2 v18.8h, v23.8h, v20.8h\n" - "zip2 v17.8h, v21.8h, v19.8h\n" - "zip1 v16.8h, v18.8h, v17.8h\n" + "zip2 v19.8h, v25.8h, v19.8h\n" + "zip2 v17.8h, v23.8h, v18.8h\n" + "zip1 v16.8h, v19.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "8:" // Odds skip - : [out_ptr] "+r" (out_ptr), [width] "+r" (width) + : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) - : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" + : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); } diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_u8_u16_summing.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_u8_u16_summing.hpp index cefb70c57b..7c7d774a6b 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_u8_u16_summing.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_u8_u16_summing.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020 Arm Limited. + * Copyright (c) 2019-2021 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -96,72 +96,72 @@ void interleave_block<8, 1, VLType::None, true>( "movi v1.8h, #0x0\n" "4:" // no_accumulate_16 "ldr d30, [x27], #0x8\n" - "prfm pldl1keep, [x27, #0x70]\n" + "ushll v30.8h, v30.8b, #0x0\n" "ldr d29, [x26], #0x8\n" + "add x19, x19, #0x1\n" + "ushll v29.8h, v29.8b, #0x0\n" "ldr d28, [x25], #0x8\n" - "prfm pldl1keep, [x26, #0x70]\n" + "subs %x[width], %x[width], #0x8\n" + "ushll v28.8h, v28.8b, #0x0\n" "ldr d27, [x24], #0x8\n" + "cmp %x[width], #0x8\n" + "ushll v27.8h, v27.8b, #0x0\n" + "ldr d24, [x23], #0x8\n" + "ldr d23, [x22], #0x8\n" + "ushll v24.8h, v24.8b, #0x0\n" + "ldr d21, [x21], #0x8\n" + "ushll v23.8h, v23.8b, #0x0\n" + "ldr d26, [x20], #0x8\n" + "zip1 v20.8h, v30.8h, v24.8h\n" + "prfm pldl1keep, [x27, #0x70]\n" + "zip1 v25.8h, v29.8h, v23.8h\n" + "prfm pldl1keep, [x26, #0x70]\n" + "zip2 v24.8h, v30.8h, v24.8h\n" "prfm pldl1keep, [x25, #0x70]\n" - "ldr d23, [x23], #0x8\n" - "ldr d21, [x22], #0x8\n" + "zip2 v23.8h, v29.8h, v23.8h\n" "prfm pldl1keep, [x24, #0x70]\n" - "ldr d26, [x21], #0x8\n" - "ldr d25, [x20], #0x8\n" + "ushll v21.8h, v21.8b, #0x0\n" "prfm pldl1keep, [x23, #0x70]\n" + "zip1 v19.8h, v28.8h, v21.8h\n" "prfm pldl1keep, [x22, #0x70]\n" - "ushll v30.8h, v30.8b, #0x0\n" - "ushll v29.8h, v29.8b, #0x0\n" + "zip1 v22.8h, v20.8h, v19.8h\n" "prfm pldl1keep, [x21, #0x70]\n" - "ushll v28.8h, v28.8b, #0x0\n" + "zip2 v19.8h, v20.8h, v19.8h\n" "prfm pldl1keep, [x20, #0x70]\n" - "ushll v27.8h, v27.8b, #0x0\n" - "ushll v23.8h, v23.8b, #0x0\n" - "zip1 v24.8h, v30.8h, v23.8h\n" - "ushll v21.8h, v21.8b, #0x0\n" - "zip2 v23.8h, v30.8h, v23.8h\n" + "zip2 v20.8h, v28.8h, v21.8h\n" + "zip1 v21.8h, v24.8h, v20.8h\n" + "zip2 v20.8h, v24.8h, v20.8h\n" "ushll v26.8h, v26.8b, #0x0\n" - "ushll v25.8h, v25.8b, #0x0\n" - "zip1 v22.8h, v29.8h, v21.8h\n" - "add x19, x19, #0x1\n" - "zip2 v21.8h, v29.8h, v21.8h\n" - "subs %x[width], %x[width], #0x8\n" - "zip1 v20.8h, v28.8h, v26.8h\n" - "cmp %x[width], #0x8\n" - "zip1 v18.8h, v24.8h, v20.8h\n" - "zip1 v19.8h, v27.8h, v25.8h\n" - "zip1 v17.8h, v22.8h, v19.8h\n" - "zip1 v16.8h, v18.8h, v17.8h\n" + "zip1 v18.8h, v27.8h, v26.8h\n" + "zip1 v17.8h, v25.8h, v18.8h\n" + "zip1 v16.8h, v22.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" "add v1.8h, v1.8h, v16.8h\n" - "zip2 v16.8h, v18.8h, v17.8h\n" - "str q16, [%x[out_ptr], #0x10]\n" - "zip2 v18.8h, v24.8h, v20.8h\n" - "add v1.8h, v1.8h, v16.8h\n" - "zip2 v17.8h, v22.8h, v19.8h\n" - "zip1 v16.8h, v18.8h, v17.8h\n" - "str q16, [%x[out_ptr], #0x20]\n" - "add v1.8h, v1.8h, v16.8h\n" - "zip2 v16.8h, v18.8h, v17.8h\n" + "zip2 v17.8h, v22.8h, v17.8h\n" + "str q17, [%x[out_ptr], #0x10]\n" + "zip2 v16.8h, v25.8h, v18.8h\n" + "add v1.8h, v1.8h, v17.8h\n" + "zip1 v17.8h, v19.8h, v16.8h\n" + "str q17, [%x[out_ptr], #0x20]\n" + "zip2 v16.8h, v19.8h, v16.8h\n" "str q16, [%x[out_ptr], #0x30]\n" - "zip2 v20.8h, v28.8h, v26.8h\n" + "add v1.8h, v1.8h, v17.8h\n" + "zip2 v19.8h, v27.8h, v26.8h\n" + "zip1 v17.8h, v23.8h, v19.8h\n" "add v1.8h, v1.8h, v16.8h\n" - "zip1 v18.8h, v23.8h, v20.8h\n" - "zip2 v19.8h, v27.8h, v25.8h\n" - "zip1 v17.8h, v21.8h, v19.8h\n" - "zip1 v16.8h, v18.8h, v17.8h\n" + "zip1 v16.8h, v21.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x40]\n" + "zip2 v18.8h, v21.8h, v17.8h\n" + "str q18, [%x[out_ptr], #0x50]\n" "add v1.8h, v1.8h, v16.8h\n" - "zip2 v16.8h, v18.8h, v17.8h\n" - "str q16, [%x[out_ptr], #0x50]\n" - "zip2 v18.8h, v23.8h, v20.8h\n" - "add v1.8h, v1.8h, v16.8h\n" - "zip2 v17.8h, v21.8h, v19.8h\n" - "zip1 v16.8h, v18.8h, v17.8h\n" - "str q16, [%x[out_ptr], #0x60]\n" - "add v1.8h, v1.8h, v16.8h\n" - "zip2 v16.8h, v18.8h, v17.8h\n" + "zip2 v16.8h, v23.8h, v19.8h\n" + "zip1 v17.8h, v20.8h, v16.8h\n" + "str q17, [%x[out_ptr], #0x60]\n" + "add v1.8h, v1.8h, v18.8h\n" + "zip2 v16.8h, v20.8h, v16.8h\n" "str q16, [%x[out_ptr], #0x70]\n" "add %x[out_ptr], %x[out_ptr], #0x80\n" + "add v1.8h, v1.8h, v17.8h\n" "add v1.8h, v1.8h, v16.8h\n" "bge 3b\n" "5:" // Main loop skip @@ -171,148 +171,148 @@ void interleave_block<8, 1, VLType::None, true>( "ldr s29, [x26], #0x4\n" "ldr s28, [x25], #0x4\n" "ldr s27, [x24], #0x4\n" - "ldr s23, [x23], #0x4\n" - "ldr s21, [x22], #0x4\n" - "ldr s26, [x21], #0x4\n" - "ldr s25, [x20], #0x4\n" + "ldr s24, [x23], #0x4\n" + "ldr s23, [x22], #0x4\n" + "ldr s21, [x21], #0x4\n" + "ldr s26, [x20], #0x4\n" "tbz %x[width], #1, 6f\n" "ld1 { v30.h }[2], [x27], #0x2\n" + "mov x19, #0x6\n" "ld1 { v29.h }[2], [x26], #0x2\n" "ld1 { v28.h }[2], [x25], #0x2\n" "ld1 { v27.h }[2], [x24], #0x2\n" - "ld1 { v23.h }[2], [x23], #0x2\n" - "ld1 { v21.h }[2], [x22], #0x2\n" - "ld1 { v26.h }[2], [x21], #0x2\n" - "ld1 { v25.h }[2], [x20], #0x2\n" - "mov x19, #0x6\n" + "ld1 { v24.h }[2], [x23], #0x2\n" + "ld1 { v23.h }[2], [x22], #0x2\n" + "ld1 { v21.h }[2], [x21], #0x2\n" + "ld1 { v26.h }[2], [x20], #0x2\n" "tbz %x[width], #0, 9f\n" "ld1 { v30.b }[6], [x27]\n" + "mov x19, #0x7\n" "ld1 { v29.b }[6], [x26]\n" "ld1 { v28.b }[6], [x25]\n" "ld1 { v27.b }[6], [x24]\n" - "ld1 { v23.b }[6], [x23]\n" - "ld1 { v21.b }[6], [x22]\n" - "ld1 { v26.b }[6], [x21]\n" - "ld1 { v25.b }[6], [x20]\n" - "mov x19, #0x7\n" + "ld1 { v24.b }[6], [x23]\n" + "ld1 { v23.b }[6], [x22]\n" + "ld1 { v21.b }[6], [x21]\n" + "ld1 { v26.b }[6], [x20]\n" "b 9f\n" "6:" // odd_loads_1_4 "mov x19, #0x4\n" "tbz %x[width], #0, 9f\n" "ld1 { v30.b }[4], [x27]\n" "ld1 { v29.b }[4], [x26]\n" + "mov x19, #0x5\n" "ld1 { v28.b }[4], [x25]\n" "ld1 { v27.b }[4], [x24]\n" - "ld1 { v23.b }[4], [x23]\n" - "ld1 { v21.b }[4], [x22]\n" - "ld1 { v26.b }[4], [x21]\n" - "ld1 { v25.b }[4], [x20]\n" - "mov x19, #0x5\n" + "ld1 { v24.b }[4], [x23]\n" + "ld1 { v23.b }[4], [x22]\n" + "ld1 { v21.b }[4], [x21]\n" + "ld1 { v26.b }[4], [x20]\n" "b 9f\n" "7:" // odd_loads_2_0 "tbz %x[width], #1, 8f\n" "ldr h30, [x27], #0x2\n" "ldr h29, [x26], #0x2\n" + "mov x19, #0x2\n" "ldr h28, [x25], #0x2\n" "ldr h27, [x24], #0x2\n" - "ldr h23, [x23], #0x2\n" - "ldr h21, [x22], #0x2\n" - "ldr h26, [x21], #0x2\n" - "ldr h25, [x20], #0x2\n" - "mov x19, #0x2\n" + "ldr h24, [x23], #0x2\n" + "ldr h23, [x22], #0x2\n" + "ldr h21, [x21], #0x2\n" + "ldr h26, [x20], #0x2\n" "tbz %x[width], #0, 9f\n" "ld1 { v30.b }[2], [x27]\n" + "mov x19, #0x3\n" "ld1 { v29.b }[2], [x26]\n" "ld1 { v28.b }[2], [x25]\n" "ld1 { v27.b }[2], [x24]\n" - "ld1 { v23.b }[2], [x23]\n" - "ld1 { v21.b }[2], [x22]\n" - "ld1 { v26.b }[2], [x21]\n" - "ld1 { v25.b }[2], [x20]\n" - "mov x19, #0x3\n" + "ld1 { v24.b }[2], [x23]\n" + "ld1 { v23.b }[2], [x22]\n" + "ld1 { v21.b }[2], [x21]\n" + "ld1 { v26.b }[2], [x20]\n" "b 9f\n" "8:" // odd_loads_1_0 "ldr b30, [x27, #0x0]\n" + "mov x19, #0x1\n" "ldr b29, [x26, #0x0]\n" "ldr b28, [x25, #0x0]\n" "ldr b27, [x24, #0x0]\n" - "ldr b23, [x23, #0x0]\n" - "ldr b21, [x22, #0x0]\n" - "ldr b26, [x21, #0x0]\n" - "ldr b25, [x20, #0x0]\n" - "mov x19, #0x1\n" + "ldr b24, [x23, #0x0]\n" + "ldr b23, [x22, #0x0]\n" + "ldr b21, [x21, #0x0]\n" + "ldr b26, [x20, #0x0]\n" "9:" // Odd load end "ushll v30.8h, v30.8b, #0x0\n" + "subs x19, x19, #0x1\n" "ushll v29.8h, v29.8b, #0x0\n" "ushll v28.8h, v28.8b, #0x0\n" "ushll v27.8h, v27.8b, #0x0\n" + "ushll v24.8h, v24.8b, #0x0\n" + "zip1 v20.8h, v30.8h, v24.8h\n" "ushll v23.8h, v23.8b, #0x0\n" - "zip1 v24.8h, v30.8h, v23.8h\n" + "zip1 v25.8h, v29.8h, v23.8h\n" "ushll v21.8h, v21.8b, #0x0\n" + "zip1 v19.8h, v28.8h, v21.8h\n" + "zip1 v22.8h, v20.8h, v19.8h\n" "ushll v26.8h, v26.8b, #0x0\n" - "zip1 v20.8h, v28.8h, v26.8h\n" - "ushll v25.8h, v25.8b, #0x0\n" - "zip1 v22.8h, v29.8h, v21.8h\n" - "subs x19, x19, #0x1\n" - "zip1 v18.8h, v24.8h, v20.8h\n" - "zip1 v19.8h, v27.8h, v25.8h\n" - "zip1 v17.8h, v22.8h, v19.8h\n" - "zip1 v16.8h, v18.8h, v17.8h\n" + "zip1 v18.8h, v27.8h, v26.8h\n" + "zip1 v17.8h, v25.8h, v18.8h\n" + "zip1 v16.8h, v22.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" - "add v1.8h, v1.8h, v16.8h\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" + "add v1.8h, v1.8h, v16.8h\n" "beq 10f\n" - "zip2 v16.8h, v18.8h, v17.8h\n" + "zip2 v17.8h, v22.8h, v17.8h\n" + "str q17, [%x[out_ptr], #0x0]\n" "subs x19, x19, #0x1\n" - "add v1.8h, v1.8h, v16.8h\n" - "str q16, [%x[out_ptr], #0x0]\n" + "add v1.8h, v1.8h, v17.8h\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 10f\n" - "zip2 v18.8h, v24.8h, v20.8h\n" - "zip2 v17.8h, v22.8h, v19.8h\n" + "zip2 v19.8h, v20.8h, v19.8h\n" + "zip2 v16.8h, v25.8h, v18.8h\n" "subs x19, x19, #0x1\n" - "zip1 v16.8h, v18.8h, v17.8h\n" - "str q16, [%x[out_ptr], #0x0]\n" - "add v1.8h, v1.8h, v16.8h\n" + "zip1 v17.8h, v19.8h, v16.8h\n" + "str q17, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" + "add v1.8h, v1.8h, v17.8h\n" "beq 10f\n" - "zip2 v16.8h, v18.8h, v17.8h\n" + "zip2 v16.8h, v19.8h, v16.8h\n" + "str q16, [%x[out_ptr], #0x0]\n" "subs x19, x19, #0x1\n" "add v1.8h, v1.8h, v16.8h\n" - "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 10f\n" - "zip2 v23.8h, v30.8h, v23.8h\n" - "zip2 v20.8h, v28.8h, v26.8h\n" + "zip2 v24.8h, v30.8h, v24.8h\n" + "zip2 v20.8h, v28.8h, v21.8h\n" "subs x19, x19, #0x1\n" - "zip1 v18.8h, v23.8h, v20.8h\n" - "zip2 v21.8h, v29.8h, v21.8h\n" - "zip2 v19.8h, v27.8h, v25.8h\n" - "zip1 v17.8h, v21.8h, v19.8h\n" - "zip1 v16.8h, v18.8h, v17.8h\n" + "zip1 v21.8h, v24.8h, v20.8h\n" + "zip2 v23.8h, v29.8h, v23.8h\n" + "zip2 v19.8h, v27.8h, v26.8h\n" + "zip1 v17.8h, v23.8h, v19.8h\n" + "zip1 v16.8h, v21.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" - "add v1.8h, v1.8h, v16.8h\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" + "add v1.8h, v1.8h, v16.8h\n" "beq 10f\n" - "zip2 v16.8h, v18.8h, v17.8h\n" + "zip2 v18.8h, v21.8h, v17.8h\n" + "str q18, [%x[out_ptr], #0x0]\n" "subs x19, x19, #0x1\n" - "add v1.8h, v1.8h, v16.8h\n" - "str q16, [%x[out_ptr], #0x0]\n" + "add v1.8h, v1.8h, v18.8h\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 10f\n" - "zip2 v18.8h, v23.8h, v20.8h\n" - "zip2 v17.8h, v21.8h, v19.8h\n" - "zip1 v16.8h, v18.8h, v17.8h\n" - "str q16, [%x[out_ptr], #0x0]\n" - "add v1.8h, v1.8h, v16.8h\n" + "zip2 v20.8h, v24.8h, v20.8h\n" + "zip2 v16.8h, v23.8h, v19.8h\n" + "zip1 v17.8h, v20.8h, v16.8h\n" + "str q17, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" + "add v1.8h, v1.8h, v17.8h\n" "10:" // Odds skip "uaddw v0.4s, v0.4s, v1.4h\n" "str q0, [%x[out_ptr], #0x0]\n" "uaddw2 v31.4s, v31.4s, v1.8h\n" "str q31, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" - : [out_ptr] "+r" (out_ptr), [width] "+r" (width) + : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [first] "r" (first), [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) : "cc", "memory", "v0", "v1", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block2_bf16_bf16.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block2_bf16_bf16.hpp index 5377edc1e1..1e5d395667 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block2_bf16_bf16.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block2_bf16_bf16.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020 Arm Limited. + * Copyright (c) 2019-2021 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -80,45 +80,45 @@ void interleave_block<8, 2, VLType::None, false>( "blt 3f\n" "2:" // Main loop head "ldr q28, [x27], #0x10\n" + "subs %x[width], %x[width], #0x8\n" + "ldr q29, [x26], #0x10\n" + "cmp %x[width], #0x8\n" + "ldr q25, [x25], #0x10\n" + "zip1 v22.4s, v28.4s, v25.4s\n" + "ldr q21, [x24], #0x10\n" + "zip2 v28.4s, v28.4s, v25.4s\n" + "ldr q27, [x23], #0x10\n" + "ldr q26, [x22], #0x10\n" + "zip1 v20.4s, v29.4s, v21.4s\n" + "ldr q19, [x21], #0x10\n" + "zip2 v25.4s, v29.4s, v21.4s\n" + "ldr q24, [x20], #0x10\n" + "zip1 v23.4s, v22.4s, v20.4s\n" "prfm pldl1keep, [x27, #0x70]\n" - "ldr q27, [x26], #0x10\n" - "ldr q26, [x25], #0x10\n" - "zip1 v23.4s, v28.4s, v26.4s\n" + "zip2 v22.4s, v22.4s, v20.4s\n" "prfm pldl1keep, [x26, #0x70]\n" - "ldr q22, [x24], #0x10\n" - "zip2 v26.4s, v28.4s, v26.4s\n" + "zip1 v21.4s, v28.4s, v25.4s\n" "prfm pldl1keep, [x25, #0x70]\n" - "ldr q25, [x23], #0x10\n" - "zip1 v20.4s, v27.4s, v22.4s\n" + "zip1 v18.4s, v27.4s, v19.4s\n" "prfm pldl1keep, [x24, #0x70]\n" - "ldr q24, [x22], #0x10\n" - "zip1 v16.4s, v23.4s, v20.4s\n" + "zip1 v16.4s, v26.4s, v24.4s\n" "prfm pldl1keep, [x23, #0x70]\n" - "ldr q19, [x21], #0x10\n" - "zip2 v23.4s, v23.4s, v20.4s\n" + "zip1 v17.4s, v18.4s, v16.4s\n" "prfm pldl1keep, [x22, #0x70]\n" - "zip2 v22.4s, v27.4s, v22.4s\n" - "ldr q21, [x20], #0x10\n" - "zip1 v18.4s, v25.4s, v19.4s\n" + "zip2 v20.4s, v18.4s, v16.4s\n" "prfm pldl1keep, [x21, #0x70]\n" - "str q16, [%x[out_ptr], #0x0]\n" - "zip1 v20.4s, v26.4s, v22.4s\n" + "zip2 v19.4s, v27.4s, v19.4s\n" "prfm pldl1keep, [x20, #0x70]\n" - "zip1 v16.4s, v24.4s, v21.4s\n" - "subs %x[width], %x[width], #0x8\n" - "zip1 v17.4s, v18.4s, v16.4s\n" - "cmp %x[width], #0x8\n" - "zip2 v16.4s, v18.4s, v16.4s\n" + "zip2 v16.4s, v26.4s, v24.4s\n" + "str q23, [%x[out_ptr], #0x0]\n" + "zip1 v18.4s, v19.4s, v16.4s\n" "str q17, [%x[out_ptr], #0x10]\n" - "zip2 v19.4s, v25.4s, v19.4s\n" - "str q23, [%x[out_ptr], #0x20]\n" - "zip2 v18.4s, v24.4s, v21.4s\n" - "str q16, [%x[out_ptr], #0x30]\n" - "zip1 v16.4s, v19.4s, v18.4s\n" - "str q20, [%x[out_ptr], #0x40]\n" - "zip2 v17.4s, v26.4s, v22.4s\n" - "str q16, [%x[out_ptr], #0x50]\n" - "zip2 v16.4s, v19.4s, v18.4s\n" + "zip2 v17.4s, v28.4s, v25.4s\n" + "str q22, [%x[out_ptr], #0x20]\n" + "zip2 v16.4s, v19.4s, v16.4s\n" + "str q20, [%x[out_ptr], #0x30]\n" + "str q21, [%x[out_ptr], #0x40]\n" + "str q18, [%x[out_ptr], #0x50]\n" "str q17, [%x[out_ptr], #0x60]\n" "str q16, [%x[out_ptr], #0x70]\n" "add %x[out_ptr], %x[out_ptr], #0x80\n" @@ -127,119 +127,119 @@ void interleave_block<8, 2, VLType::None, false>( "cbz %x[width], 8f\n" "tbz %x[width], #2, 5f\n" "ldr d28, [x27], #0x8\n" - "ldr d27, [x26], #0x8\n" - "ldr d26, [x25], #0x8\n" - "ldr d22, [x24], #0x8\n" - "ldr d25, [x23], #0x8\n" - "ldr d24, [x22], #0x8\n" + "ldr d29, [x26], #0x8\n" + "ldr d25, [x25], #0x8\n" + "ldr d21, [x24], #0x8\n" + "ldr d27, [x23], #0x8\n" + "ldr d26, [x22], #0x8\n" "ldr d19, [x21], #0x8\n" - "ldr d21, [x20], #0x8\n" + "ldr d24, [x20], #0x8\n" "tbz %x[width], #1, 4f\n" "ld1 { v28.s }[2], [x27], #0x4\n" - "ld1 { v27.s }[2], [x26], #0x4\n" - "ld1 { v26.s }[2], [x25], #0x4\n" - "ld1 { v22.s }[2], [x24], #0x4\n" - "ld1 { v25.s }[2], [x23], #0x4\n" - "ld1 { v24.s }[2], [x22], #0x4\n" - "ld1 { v19.s }[2], [x21], #0x4\n" - "ld1 { v21.s }[2], [x20], #0x4\n" "mov x19, #0x3\n" + "ld1 { v29.s }[2], [x26], #0x4\n" + "ld1 { v25.s }[2], [x25], #0x4\n" + "ld1 { v21.s }[2], [x24], #0x4\n" + "ld1 { v27.s }[2], [x23], #0x4\n" + "ld1 { v26.s }[2], [x22], #0x4\n" + "ld1 { v19.s }[2], [x21], #0x4\n" + "ld1 { v24.s }[2], [x20], #0x4\n" "tbz %x[width], #0, 7f\n" "ld1 { v28.h }[6], [x27]\n" - "ld1 { v27.h }[6], [x26]\n" - "ld1 { v26.h }[6], [x25]\n" - "ld1 { v22.h }[6], [x24]\n" - "ld1 { v25.h }[6], [x23]\n" - "ld1 { v24.h }[6], [x22]\n" - "ld1 { v19.h }[6], [x21]\n" - "ld1 { v21.h }[6], [x20]\n" "mov x19, #0x4\n" + "ld1 { v29.h }[6], [x26]\n" + "ld1 { v25.h }[6], [x25]\n" + "ld1 { v21.h }[6], [x24]\n" + "ld1 { v27.h }[6], [x23]\n" + "ld1 { v26.h }[6], [x22]\n" + "ld1 { v19.h }[6], [x21]\n" + "ld1 { v24.h }[6], [x20]\n" "b 7f\n" "4:" // odd_loads_1_4 "mov x19, #0x2\n" "tbz %x[width], #0, 7f\n" "ld1 { v28.h }[4], [x27]\n" - "ld1 { v27.h }[4], [x26]\n" - "ld1 { v26.h }[4], [x25]\n" - "ld1 { v22.h }[4], [x24]\n" - "ld1 { v25.h }[4], [x23]\n" - "ld1 { v24.h }[4], [x22]\n" - "ld1 { v19.h }[4], [x21]\n" - "ld1 { v21.h }[4], [x20]\n" + "ld1 { v29.h }[4], [x26]\n" "mov x19, #0x3\n" + "ld1 { v25.h }[4], [x25]\n" + "ld1 { v21.h }[4], [x24]\n" + "ld1 { v27.h }[4], [x23]\n" + "ld1 { v26.h }[4], [x22]\n" + "ld1 { v19.h }[4], [x21]\n" + "ld1 { v24.h }[4], [x20]\n" "b 7f\n" "5:" // odd_loads_2_0 "tbz %x[width], #1, 6f\n" "ldr s28, [x27], #0x4\n" - "ldr s27, [x26], #0x4\n" - "ldr s26, [x25], #0x4\n" - "ldr s22, [x24], #0x4\n" - "ldr s25, [x23], #0x4\n" - "ldr s24, [x22], #0x4\n" - "ldr s19, [x21], #0x4\n" - "ldr s21, [x20], #0x4\n" + "ldr s29, [x26], #0x4\n" "mov x19, #0x1\n" + "ldr s25, [x25], #0x4\n" + "ldr s21, [x24], #0x4\n" + "ldr s27, [x23], #0x4\n" + "ldr s26, [x22], #0x4\n" + "ldr s19, [x21], #0x4\n" + "ldr s24, [x20], #0x4\n" "tbz %x[width], #0, 7f\n" "ld1 { v28.h }[2], [x27]\n" - "ld1 { v27.h }[2], [x26]\n" - "ld1 { v26.h }[2], [x25]\n" - "ld1 { v22.h }[2], [x24]\n" - "ld1 { v25.h }[2], [x23]\n" - "ld1 { v24.h }[2], [x22]\n" - "ld1 { v19.h }[2], [x21]\n" - "ld1 { v21.h }[2], [x20]\n" "mov x19, #0x2\n" + "ld1 { v29.h }[2], [x26]\n" + "ld1 { v25.h }[2], [x25]\n" + "ld1 { v21.h }[2], [x24]\n" + "ld1 { v27.h }[2], [x23]\n" + "ld1 { v26.h }[2], [x22]\n" + "ld1 { v19.h }[2], [x21]\n" + "ld1 { v24.h }[2], [x20]\n" "b 7f\n" "6:" // odd_loads_1_0 "ldr h28, [x27, #0x0]\n" - "ldr h27, [x26, #0x0]\n" - "ldr h26, [x25, #0x0]\n" - "ldr h22, [x24, #0x0]\n" - "ldr h25, [x23, #0x0]\n" - "ldr h24, [x22, #0x0]\n" - "ldr h19, [x21, #0x0]\n" - "ldr h21, [x20, #0x0]\n" "mov x19, #0x1\n" + "ldr h29, [x26, #0x0]\n" + "ldr h25, [x25, #0x0]\n" + "ldr h21, [x24, #0x0]\n" + "ldr h27, [x23, #0x0]\n" + "ldr h26, [x22, #0x0]\n" + "ldr h19, [x21, #0x0]\n" + "ldr h24, [x20, #0x0]\n" "7:" // Odd load end - "zip1 v23.4s, v28.4s, v26.4s\n" + "zip1 v22.4s, v28.4s, v25.4s\n" "subs x19, x19, #0x1\n" - "zip1 v20.4s, v27.4s, v22.4s\n" - "zip1 v16.4s, v23.4s, v20.4s\n" - "str q16, [%x[out_ptr], #0x0]\n" - "zip1 v18.4s, v25.4s, v19.4s\n" - "zip1 v16.4s, v24.4s, v21.4s\n" + "zip1 v20.4s, v29.4s, v21.4s\n" + "zip1 v23.4s, v22.4s, v20.4s\n" + "str q23, [%x[out_ptr], #0x0]\n" + "zip1 v18.4s, v27.4s, v19.4s\n" + "zip1 v16.4s, v26.4s, v24.4s\n" "zip1 v17.4s, v18.4s, v16.4s\n" "str q17, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "beq 8f\n" - "zip2 v23.4s, v23.4s, v20.4s\n" - "zip2 v16.4s, v18.4s, v16.4s\n" - "str q23, [%x[out_ptr], #0x0]\n" - "str q16, [%x[out_ptr], #0x10]\n" + "zip2 v22.4s, v22.4s, v20.4s\n" + "str q22, [%x[out_ptr], #0x0]\n" + "zip2 v20.4s, v18.4s, v16.4s\n" "subs x19, x19, #0x1\n" + "str q20, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "beq 8f\n" - "zip2 v26.4s, v28.4s, v26.4s\n" - "zip2 v22.4s, v27.4s, v22.4s\n" + "zip2 v28.4s, v28.4s, v25.4s\n" + "zip2 v25.4s, v29.4s, v21.4s\n" "subs x19, x19, #0x1\n" - "zip1 v20.4s, v26.4s, v22.4s\n" - "str q20, [%x[out_ptr], #0x0]\n" - "zip2 v19.4s, v25.4s, v19.4s\n" - "zip2 v18.4s, v24.4s, v21.4s\n" - "zip1 v16.4s, v19.4s, v18.4s\n" - "str q16, [%x[out_ptr], #0x10]\n" + "zip1 v21.4s, v28.4s, v25.4s\n" + "str q21, [%x[out_ptr], #0x0]\n" + "zip2 v19.4s, v27.4s, v19.4s\n" + "zip2 v16.4s, v26.4s, v24.4s\n" + "zip1 v18.4s, v19.4s, v16.4s\n" + "str q18, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "beq 8f\n" - "zip2 v17.4s, v26.4s, v22.4s\n" - "zip2 v16.4s, v19.4s, v18.4s\n" + "zip2 v17.4s, v28.4s, v25.4s\n" "str q17, [%x[out_ptr], #0x0]\n" + "zip2 v16.4s, v19.4s, v16.4s\n" "str q16, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "8:" // Odds skip - : [out_ptr] "+r" (out_ptr), [width] "+r" (width) + : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) - : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" + : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); } diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block2_fp32_fp32.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block2_fp32_fp32.hpp index 3aea6a8999..064207c0fa 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block2_fp32_fp32.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block2_fp32_fp32.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020 Arm Limited. + * Copyright (c) 2019-2021 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -80,39 +80,39 @@ void interleave_block<8, 2, VLType::None, false>( "blt 3f\n" "2:" // Main loop head "ldr q27, [x27], #0x10\n" - "prfm pldl1keep, [x27, #0x70]\n" + "subs %x[width], %x[width], #0x4\n" "ldr q24, [x26], #0x10\n" "zip1 v26.2d, v27.2d, v24.2d\n" - "prfm pldl1keep, [x26, #0x70]\n" "ldr q25, [x25], #0x10\n" + "cmp %x[width], #0x4\n" "zip2 v24.2d, v27.2d, v24.2d\n" - "prfm pldl1keep, [x25, #0x70]\n" "ldr q21, [x24], #0x10\n" - "zip1 v23.2d, v25.2d, v21.2d\n" - "prfm pldl1keep, [x24, #0x70]\n" - "ldr q22, [x23], #0x10\n" + "ldr q23, [x23], #0x10\n" + "zip1 v22.2d, v25.2d, v21.2d\n" + "ldr q18, [x22], #0x10\n" "zip2 v21.2d, v25.2d, v21.2d\n" + "ldr q20, [x21], #0x10\n" + "ldr q16, [x20], #0x10\n" + "zip1 v19.2d, v23.2d, v18.2d\n" + "prfm pldl1keep, [x27, #0x70]\n" + "zip2 v18.2d, v23.2d, v18.2d\n" + "prfm pldl1keep, [x26, #0x70]\n" + "zip1 v17.2d, v20.2d, v16.2d\n" + "prfm pldl1keep, [x25, #0x70]\n" + "zip2 v16.2d, v20.2d, v16.2d\n" + "prfm pldl1keep, [x24, #0x70]\n" "prfm pldl1keep, [x23, #0x70]\n" - "ldr q18, [x22], #0x10\n" - "zip1 v20.2d, v22.2d, v18.2d\n" "prfm pldl1keep, [x22, #0x70]\n" - "ldr q19, [x21], #0x10\n" - "zip2 v18.2d, v22.2d, v18.2d\n" "prfm pldl1keep, [x21, #0x70]\n" - "ldr q16, [x20], #0x10\n" - "zip1 v17.2d, v19.2d, v16.2d\n" "prfm pldl1keep, [x20, #0x70]\n" "str q26, [%x[out_ptr], #0x0]\n" - "zip2 v16.2d, v19.2d, v16.2d\n" - "str q23, [%x[out_ptr], #0x10]\n" - "str q20, [%x[out_ptr], #0x20]\n" + "str q22, [%x[out_ptr], #0x10]\n" + "str q19, [%x[out_ptr], #0x20]\n" "str q17, [%x[out_ptr], #0x30]\n" "str q24, [%x[out_ptr], #0x40]\n" "str q21, [%x[out_ptr], #0x50]\n" "str q18, [%x[out_ptr], #0x60]\n" "str q16, [%x[out_ptr], #0x70]\n" - "subs %x[width], %x[width], #0x4\n" - "cmp %x[width], #0x4\n" "add %x[out_ptr], %x[out_ptr], #0x80\n" "bge 2b\n" "3:" // Main loop skip @@ -120,58 +120,58 @@ void interleave_block<8, 2, VLType::None, false>( "tbz %x[width], #1, 4f\n" "ldr d27, [x27], #0x8\n" "ldr d24, [x26], #0x8\n" + "mov x19, #0x1\n" "ldr d25, [x25], #0x8\n" "ldr d21, [x24], #0x8\n" - "ldr d22, [x23], #0x8\n" + "ldr d23, [x23], #0x8\n" "ldr d18, [x22], #0x8\n" - "ldr d19, [x21], #0x8\n" + "ldr d20, [x21], #0x8\n" "ldr d16, [x20], #0x8\n" - "mov x19, #0x1\n" "tbz %x[width], #0, 5f\n" "ld1 { v27.s }[2], [x27]\n" + "mov x19, #0x2\n" "ld1 { v24.s }[2], [x26]\n" "ld1 { v25.s }[2], [x25]\n" "ld1 { v21.s }[2], [x24]\n" - "ld1 { v22.s }[2], [x23]\n" + "ld1 { v23.s }[2], [x23]\n" "ld1 { v18.s }[2], [x22]\n" - "ld1 { v19.s }[2], [x21]\n" + "ld1 { v20.s }[2], [x21]\n" "ld1 { v16.s }[2], [x20]\n" - "mov x19, #0x2\n" "b 5f\n" "4:" // odd_loads_1_0 "ldr s27, [x27, #0x0]\n" + "mov x19, #0x1\n" "ldr s24, [x26, #0x0]\n" "ldr s25, [x25, #0x0]\n" "ldr s21, [x24, #0x0]\n" - "ldr s22, [x23, #0x0]\n" + "ldr s23, [x23, #0x0]\n" "ldr s18, [x22, #0x0]\n" - "ldr s19, [x21, #0x0]\n" + "ldr s20, [x21, #0x0]\n" "ldr s16, [x20, #0x0]\n" - "mov x19, #0x1\n" "5:" // Odd load end "zip1 v26.2d, v27.2d, v24.2d\n" - "subs x19, x19, #0x1\n" - "zip1 v23.2d, v25.2d, v21.2d\n" "str q26, [%x[out_ptr], #0x0]\n" - "zip1 v20.2d, v22.2d, v18.2d\n" - "str q23, [%x[out_ptr], #0x10]\n" - "zip1 v17.2d, v19.2d, v16.2d\n" - "str q20, [%x[out_ptr], #0x20]\n" + "zip1 v22.2d, v25.2d, v21.2d\n" + "subs x19, x19, #0x1\n" + "zip1 v19.2d, v23.2d, v18.2d\n" + "str q22, [%x[out_ptr], #0x10]\n" + "zip1 v17.2d, v20.2d, v16.2d\n" + "str q19, [%x[out_ptr], #0x20]\n" "str q17, [%x[out_ptr], #0x30]\n" "add %x[out_ptr], %x[out_ptr], #0x40\n" "beq 6f\n" "zip2 v24.2d, v27.2d, v24.2d\n" - "zip2 v21.2d, v25.2d, v21.2d\n" "str q24, [%x[out_ptr], #0x0]\n" - "zip2 v18.2d, v22.2d, v18.2d\n" + "zip2 v21.2d, v25.2d, v21.2d\n" + "zip2 v18.2d, v23.2d, v18.2d\n" "str q21, [%x[out_ptr], #0x10]\n" - "zip2 v16.2d, v19.2d, v16.2d\n" + "zip2 v16.2d, v20.2d, v16.2d\n" "str q18, [%x[out_ptr], #0x20]\n" "str q16, [%x[out_ptr], #0x30]\n" "add %x[out_ptr], %x[out_ptr], #0x40\n" "6:" // Odds skip - : [out_ptr] "+r" (out_ptr), [width] "+r" (width) + : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block4_bf16_bf16.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block4_bf16_bf16.hpp index 4780b77a4a..1f86722bc1 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block4_bf16_bf16.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block4_bf16_bf16.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020 Arm Limited. + * Copyright (c) 2019-2021 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -80,39 +80,39 @@ void interleave_block<8, 4, VLType::None, false>( "blt 3f\n" "2:" // Main loop head "ldr q27, [x27], #0x10\n" - "prfm pldl1keep, [x27, #0x70]\n" + "subs %x[width], %x[width], #0x8\n" "ldr q24, [x26], #0x10\n" "zip1 v26.2d, v27.2d, v24.2d\n" - "prfm pldl1keep, [x26, #0x70]\n" "ldr q25, [x25], #0x10\n" + "cmp %x[width], #0x8\n" "zip2 v24.2d, v27.2d, v24.2d\n" - "prfm pldl1keep, [x25, #0x70]\n" "ldr q21, [x24], #0x10\n" - "zip1 v23.2d, v25.2d, v21.2d\n" - "prfm pldl1keep, [x24, #0x70]\n" - "ldr q22, [x23], #0x10\n" + "ldr q23, [x23], #0x10\n" + "zip1 v22.2d, v25.2d, v21.2d\n" + "ldr q18, [x22], #0x10\n" "zip2 v21.2d, v25.2d, v21.2d\n" + "ldr q20, [x21], #0x10\n" + "ldr q16, [x20], #0x10\n" + "zip1 v19.2d, v23.2d, v18.2d\n" + "prfm pldl1keep, [x27, #0x70]\n" + "zip2 v18.2d, v23.2d, v18.2d\n" + "prfm pldl1keep, [x26, #0x70]\n" + "zip1 v17.2d, v20.2d, v16.2d\n" + "prfm pldl1keep, [x25, #0x70]\n" + "zip2 v16.2d, v20.2d, v16.2d\n" + "prfm pldl1keep, [x24, #0x70]\n" "prfm pldl1keep, [x23, #0x70]\n" - "ldr q18, [x22], #0x10\n" - "zip1 v20.2d, v22.2d, v18.2d\n" "prfm pldl1keep, [x22, #0x70]\n" - "ldr q19, [x21], #0x10\n" - "zip2 v18.2d, v22.2d, v18.2d\n" "prfm pldl1keep, [x21, #0x70]\n" - "ldr q16, [x20], #0x10\n" - "zip1 v17.2d, v19.2d, v16.2d\n" "prfm pldl1keep, [x20, #0x70]\n" "str q26, [%x[out_ptr], #0x0]\n" - "zip2 v16.2d, v19.2d, v16.2d\n" - "str q23, [%x[out_ptr], #0x10]\n" - "str q20, [%x[out_ptr], #0x20]\n" + "str q22, [%x[out_ptr], #0x10]\n" + "str q19, [%x[out_ptr], #0x20]\n" "str q17, [%x[out_ptr], #0x30]\n" "str q24, [%x[out_ptr], #0x40]\n" "str q21, [%x[out_ptr], #0x50]\n" "str q18, [%x[out_ptr], #0x60]\n" "str q16, [%x[out_ptr], #0x70]\n" - "subs %x[width], %x[width], #0x8\n" - "cmp %x[width], #0x8\n" "add %x[out_ptr], %x[out_ptr], #0x80\n" "bge 2b\n" "3:" // Main loop skip @@ -122,28 +122,28 @@ void interleave_block<8, 4, VLType::None, false>( "ldr d24, [x26], #0x8\n" "ldr d25, [x25], #0x8\n" "ldr d21, [x24], #0x8\n" - "ldr d22, [x23], #0x8\n" + "ldr d23, [x23], #0x8\n" "ldr d18, [x22], #0x8\n" - "ldr d19, [x21], #0x8\n" + "ldr d20, [x21], #0x8\n" "ldr d16, [x20], #0x8\n" "tbz %x[width], #1, 4f\n" "ld1 { v27.s }[2], [x27], #0x4\n" + "mov x19, #0x2\n" "ld1 { v24.s }[2], [x26], #0x4\n" "ld1 { v25.s }[2], [x25], #0x4\n" "ld1 { v21.s }[2], [x24], #0x4\n" - "ld1 { v22.s }[2], [x23], #0x4\n" + "ld1 { v23.s }[2], [x23], #0x4\n" "ld1 { v18.s }[2], [x22], #0x4\n" - "ld1 { v19.s }[2], [x21], #0x4\n" + "ld1 { v20.s }[2], [x21], #0x4\n" "ld1 { v16.s }[2], [x20], #0x4\n" - "mov x19, #0x2\n" "tbz %x[width], #0, 7f\n" "ld1 { v27.h }[6], [x27]\n" "ld1 { v24.h }[6], [x26]\n" "ld1 { v25.h }[6], [x25]\n" "ld1 { v21.h }[6], [x24]\n" - "ld1 { v22.h }[6], [x23]\n" + "ld1 { v23.h }[6], [x23]\n" "ld1 { v18.h }[6], [x22]\n" - "ld1 { v19.h }[6], [x21]\n" + "ld1 { v20.h }[6], [x21]\n" "ld1 { v16.h }[6], [x20]\n" "b 7f\n" "4:" // odd_loads_1_4 @@ -151,69 +151,69 @@ void interleave_block<8, 4, VLType::None, false>( "tbz %x[width], #0, 7f\n" "ld1 { v27.h }[4], [x27]\n" "ld1 { v24.h }[4], [x26]\n" + "mov x19, #0x2\n" "ld1 { v25.h }[4], [x25]\n" "ld1 { v21.h }[4], [x24]\n" - "ld1 { v22.h }[4], [x23]\n" + "ld1 { v23.h }[4], [x23]\n" "ld1 { v18.h }[4], [x22]\n" - "ld1 { v19.h }[4], [x21]\n" + "ld1 { v20.h }[4], [x21]\n" "ld1 { v16.h }[4], [x20]\n" - "mov x19, #0x2\n" "b 7f\n" "5:" // odd_loads_2_0 "tbz %x[width], #1, 6f\n" "ldr s27, [x27], #0x4\n" "ldr s24, [x26], #0x4\n" + "mov x19, #0x1\n" "ldr s25, [x25], #0x4\n" "ldr s21, [x24], #0x4\n" - "ldr s22, [x23], #0x4\n" + "ldr s23, [x23], #0x4\n" "ldr s18, [x22], #0x4\n" - "ldr s19, [x21], #0x4\n" + "ldr s20, [x21], #0x4\n" "ldr s16, [x20], #0x4\n" - "mov x19, #0x1\n" "tbz %x[width], #0, 7f\n" "ld1 { v27.h }[2], [x27]\n" "ld1 { v24.h }[2], [x26]\n" "ld1 { v25.h }[2], [x25]\n" "ld1 { v21.h }[2], [x24]\n" - "ld1 { v22.h }[2], [x23]\n" + "ld1 { v23.h }[2], [x23]\n" "ld1 { v18.h }[2], [x22]\n" - "ld1 { v19.h }[2], [x21]\n" + "ld1 { v20.h }[2], [x21]\n" "ld1 { v16.h }[2], [x20]\n" "b 7f\n" "6:" // odd_loads_1_0 "ldr h27, [x27, #0x0]\n" + "mov x19, #0x1\n" "ldr h24, [x26, #0x0]\n" "ldr h25, [x25, #0x0]\n" "ldr h21, [x24, #0x0]\n" - "ldr h22, [x23, #0x0]\n" + "ldr h23, [x23, #0x0]\n" "ldr h18, [x22, #0x0]\n" - "ldr h19, [x21, #0x0]\n" + "ldr h20, [x21, #0x0]\n" "ldr h16, [x20, #0x0]\n" - "mov x19, #0x1\n" "7:" // Odd load end "zip1 v26.2d, v27.2d, v24.2d\n" - "subs x19, x19, #0x1\n" - "zip1 v23.2d, v25.2d, v21.2d\n" "str q26, [%x[out_ptr], #0x0]\n" - "zip1 v20.2d, v22.2d, v18.2d\n" - "str q23, [%x[out_ptr], #0x10]\n" - "zip1 v17.2d, v19.2d, v16.2d\n" - "str q20, [%x[out_ptr], #0x20]\n" + "zip1 v22.2d, v25.2d, v21.2d\n" + "subs x19, x19, #0x1\n" + "zip1 v19.2d, v23.2d, v18.2d\n" + "str q22, [%x[out_ptr], #0x10]\n" + "zip1 v17.2d, v20.2d, v16.2d\n" + "str q19, [%x[out_ptr], #0x20]\n" "str q17, [%x[out_ptr], #0x30]\n" "add %x[out_ptr], %x[out_ptr], #0x40\n" "beq 8f\n" "zip2 v24.2d, v27.2d, v24.2d\n" - "zip2 v21.2d, v25.2d, v21.2d\n" "str q24, [%x[out_ptr], #0x0]\n" - "zip2 v18.2d, v22.2d, v18.2d\n" + "zip2 v21.2d, v25.2d, v21.2d\n" + "zip2 v18.2d, v23.2d, v18.2d\n" "str q21, [%x[out_ptr], #0x10]\n" - "zip2 v16.2d, v19.2d, v16.2d\n" + "zip2 v16.2d, v20.2d, v16.2d\n" "str q18, [%x[out_ptr], #0x20]\n" "str q16, [%x[out_ptr], #0x30]\n" "add %x[out_ptr], %x[out_ptr], #0x40\n" "8:" // Odds skip - : [out_ptr] "+r" (out_ptr), [width] "+r" (width) + : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block4_s8_s8.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block4_s8_s8.hpp index a9034f5742..659d9947e2 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block4_s8_s8.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block4_s8_s8.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020 Arm Limited. + * Copyright (c) 2019-2021 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -80,45 +80,45 @@ void interleave_block<8, 4, VLType::None, false>( "blt 3f\n" "2:" // Main loop head "ldr q28, [x27], #0x10\n" + "subs %x[width], %x[width], #0x10\n" + "ldr q29, [x26], #0x10\n" + "cmp %x[width], #0x10\n" + "ldr q25, [x25], #0x10\n" + "zip1 v22.4s, v28.4s, v25.4s\n" + "ldr q21, [x24], #0x10\n" + "zip2 v28.4s, v28.4s, v25.4s\n" + "ldr q27, [x23], #0x10\n" + "ldr q26, [x22], #0x10\n" + "zip1 v20.4s, v29.4s, v21.4s\n" + "ldr q19, [x21], #0x10\n" + "zip2 v25.4s, v29.4s, v21.4s\n" + "ldr q24, [x20], #0x10\n" + "zip1 v23.4s, v22.4s, v20.4s\n" "prfm pldl1keep, [x27, #0x70]\n" - "ldr q27, [x26], #0x10\n" - "ldr q26, [x25], #0x10\n" - "zip1 v23.4s, v28.4s, v26.4s\n" + "zip2 v22.4s, v22.4s, v20.4s\n" "prfm pldl1keep, [x26, #0x70]\n" - "ldr q22, [x24], #0x10\n" - "zip2 v26.4s, v28.4s, v26.4s\n" + "zip1 v21.4s, v28.4s, v25.4s\n" "prfm pldl1keep, [x25, #0x70]\n" - "ldr q25, [x23], #0x10\n" - "zip1 v20.4s, v27.4s, v22.4s\n" + "zip1 v18.4s, v27.4s, v19.4s\n" "prfm pldl1keep, [x24, #0x70]\n" - "ldr q24, [x22], #0x10\n" - "zip1 v16.4s, v23.4s, v20.4s\n" + "zip1 v16.4s, v26.4s, v24.4s\n" "prfm pldl1keep, [x23, #0x70]\n" - "ldr q19, [x21], #0x10\n" - "zip2 v23.4s, v23.4s, v20.4s\n" + "zip1 v17.4s, v18.4s, v16.4s\n" "prfm pldl1keep, [x22, #0x70]\n" - "zip2 v22.4s, v27.4s, v22.4s\n" - "ldr q21, [x20], #0x10\n" - "zip1 v18.4s, v25.4s, v19.4s\n" + "zip2 v20.4s, v18.4s, v16.4s\n" "prfm pldl1keep, [x21, #0x70]\n" - "str q16, [%x[out_ptr], #0x0]\n" - "zip1 v20.4s, v26.4s, v22.4s\n" + "zip2 v19.4s, v27.4s, v19.4s\n" "prfm pldl1keep, [x20, #0x70]\n" - "zip1 v16.4s, v24.4s, v21.4s\n" - "subs %x[width], %x[width], #0x10\n" - "zip1 v17.4s, v18.4s, v16.4s\n" - "cmp %x[width], #0x10\n" - "zip2 v16.4s, v18.4s, v16.4s\n" + "zip2 v16.4s, v26.4s, v24.4s\n" + "str q23, [%x[out_ptr], #0x0]\n" + "zip1 v18.4s, v19.4s, v16.4s\n" "str q17, [%x[out_ptr], #0x10]\n" - "zip2 v19.4s, v25.4s, v19.4s\n" - "str q23, [%x[out_ptr], #0x20]\n" - "zip2 v18.4s, v24.4s, v21.4s\n" - "str q16, [%x[out_ptr], #0x30]\n" - "zip1 v16.4s, v19.4s, v18.4s\n" - "str q20, [%x[out_ptr], #0x40]\n" - "zip2 v17.4s, v26.4s, v22.4s\n" - "str q16, [%x[out_ptr], #0x50]\n" - "zip2 v16.4s, v19.4s, v18.4s\n" + "zip2 v17.4s, v28.4s, v25.4s\n" + "str q22, [%x[out_ptr], #0x20]\n" + "zip2 v16.4s, v19.4s, v16.4s\n" + "str q20, [%x[out_ptr], #0x30]\n" + "str q21, [%x[out_ptr], #0x40]\n" + "str q18, [%x[out_ptr], #0x50]\n" "str q17, [%x[out_ptr], #0x60]\n" "str q16, [%x[out_ptr], #0x70]\n" "add %x[out_ptr], %x[out_ptr], #0x80\n" @@ -127,203 +127,203 @@ void interleave_block<8, 4, VLType::None, false>( "cbz %x[width], 12f\n" "tbz %x[width], #3, 7f\n" "ldr d28, [x27], #0x8\n" - "ldr d27, [x26], #0x8\n" - "ldr d26, [x25], #0x8\n" - "ldr d22, [x24], #0x8\n" - "ldr d25, [x23], #0x8\n" - "ldr d24, [x22], #0x8\n" + "ldr d29, [x26], #0x8\n" + "ldr d25, [x25], #0x8\n" + "ldr d21, [x24], #0x8\n" + "ldr d27, [x23], #0x8\n" + "ldr d26, [x22], #0x8\n" "ldr d19, [x21], #0x8\n" - "ldr d21, [x20], #0x8\n" + "ldr d24, [x20], #0x8\n" "tbz %x[width], #2, 5f\n" "ld1 { v28.s }[2], [x27], #0x4\n" - "ld1 { v27.s }[2], [x26], #0x4\n" - "ld1 { v26.s }[2], [x25], #0x4\n" - "ld1 { v22.s }[2], [x24], #0x4\n" - "ld1 { v25.s }[2], [x23], #0x4\n" - "ld1 { v24.s }[2], [x22], #0x4\n" + "ld1 { v29.s }[2], [x26], #0x4\n" + "ld1 { v25.s }[2], [x25], #0x4\n" + "ld1 { v21.s }[2], [x24], #0x4\n" + "ld1 { v27.s }[2], [x23], #0x4\n" + "ld1 { v26.s }[2], [x22], #0x4\n" "ld1 { v19.s }[2], [x21], #0x4\n" - "ld1 { v21.s }[2], [x20], #0x4\n" + "ld1 { v24.s }[2], [x20], #0x4\n" "tbz %x[width], #1, 4f\n" "ld1 { v28.h }[6], [x27], #0x2\n" - "ld1 { v27.h }[6], [x26], #0x2\n" - "ld1 { v26.h }[6], [x25], #0x2\n" - "ld1 { v22.h }[6], [x24], #0x2\n" - "ld1 { v25.h }[6], [x23], #0x2\n" - "ld1 { v24.h }[6], [x22], #0x2\n" - "ld1 { v19.h }[6], [x21], #0x2\n" - "ld1 { v21.h }[6], [x20], #0x2\n" "mov x19, #0x4\n" + "ld1 { v29.h }[6], [x26], #0x2\n" + "ld1 { v25.h }[6], [x25], #0x2\n" + "ld1 { v21.h }[6], [x24], #0x2\n" + "ld1 { v27.h }[6], [x23], #0x2\n" + "ld1 { v26.h }[6], [x22], #0x2\n" + "ld1 { v19.h }[6], [x21], #0x2\n" + "ld1 { v24.h }[6], [x20], #0x2\n" "tbz %x[width], #0, 11f\n" "ld1 { v28.b }[14], [x27]\n" - "ld1 { v27.b }[14], [x26]\n" - "ld1 { v26.b }[14], [x25]\n" - "ld1 { v22.b }[14], [x24]\n" - "ld1 { v25.b }[14], [x23]\n" - "ld1 { v24.b }[14], [x22]\n" + "ld1 { v29.b }[14], [x26]\n" + "ld1 { v25.b }[14], [x25]\n" + "ld1 { v21.b }[14], [x24]\n" + "ld1 { v27.b }[14], [x23]\n" + "ld1 { v26.b }[14], [x22]\n" "ld1 { v19.b }[14], [x21]\n" - "ld1 { v21.b }[14], [x20]\n" + "ld1 { v24.b }[14], [x20]\n" "b 11f\n" "4:" // odd_loads_1_12 "mov x19, #0x3\n" "tbz %x[width], #0, 11f\n" "ld1 { v28.b }[12], [x27]\n" - "ld1 { v27.b }[12], [x26]\n" - "ld1 { v26.b }[12], [x25]\n" - "ld1 { v22.b }[12], [x24]\n" - "ld1 { v25.b }[12], [x23]\n" - "ld1 { v24.b }[12], [x22]\n" - "ld1 { v19.b }[12], [x21]\n" - "ld1 { v21.b }[12], [x20]\n" + "ld1 { v29.b }[12], [x26]\n" "mov x19, #0x4\n" + "ld1 { v25.b }[12], [x25]\n" + "ld1 { v21.b }[12], [x24]\n" + "ld1 { v27.b }[12], [x23]\n" + "ld1 { v26.b }[12], [x22]\n" + "ld1 { v19.b }[12], [x21]\n" + "ld1 { v24.b }[12], [x20]\n" "b 11f\n" "5:" // odd_loads_2_8 "tbz %x[width], #1, 6f\n" "ld1 { v28.h }[4], [x27], #0x2\n" - "ld1 { v27.h }[4], [x26], #0x2\n" - "ld1 { v26.h }[4], [x25], #0x2\n" - "ld1 { v22.h }[4], [x24], #0x2\n" - "ld1 { v25.h }[4], [x23], #0x2\n" - "ld1 { v24.h }[4], [x22], #0x2\n" - "ld1 { v19.h }[4], [x21], #0x2\n" - "ld1 { v21.h }[4], [x20], #0x2\n" + "ld1 { v29.h }[4], [x26], #0x2\n" "mov x19, #0x3\n" + "ld1 { v25.h }[4], [x25], #0x2\n" + "ld1 { v21.h }[4], [x24], #0x2\n" + "ld1 { v27.h }[4], [x23], #0x2\n" + "ld1 { v26.h }[4], [x22], #0x2\n" + "ld1 { v19.h }[4], [x21], #0x2\n" + "ld1 { v24.h }[4], [x20], #0x2\n" "tbz %x[width], #0, 11f\n" "ld1 { v28.b }[10], [x27]\n" - "ld1 { v27.b }[10], [x26]\n" - "ld1 { v26.b }[10], [x25]\n" - "ld1 { v22.b }[10], [x24]\n" - "ld1 { v25.b }[10], [x23]\n" - "ld1 { v24.b }[10], [x22]\n" + "ld1 { v29.b }[10], [x26]\n" + "ld1 { v25.b }[10], [x25]\n" + "ld1 { v21.b }[10], [x24]\n" + "ld1 { v27.b }[10], [x23]\n" + "ld1 { v26.b }[10], [x22]\n" "ld1 { v19.b }[10], [x21]\n" - "ld1 { v21.b }[10], [x20]\n" + "ld1 { v24.b }[10], [x20]\n" "b 11f\n" "6:" // odd_loads_1_8 "mov x19, #0x2\n" "tbz %x[width], #0, 11f\n" "ld1 { v28.b }[8], [x27]\n" - "ld1 { v27.b }[8], [x26]\n" - "ld1 { v26.b }[8], [x25]\n" - "ld1 { v22.b }[8], [x24]\n" - "ld1 { v25.b }[8], [x23]\n" - "ld1 { v24.b }[8], [x22]\n" - "ld1 { v19.b }[8], [x21]\n" - "ld1 { v21.b }[8], [x20]\n" + "ld1 { v29.b }[8], [x26]\n" "mov x19, #0x3\n" + "ld1 { v25.b }[8], [x25]\n" + "ld1 { v21.b }[8], [x24]\n" + "ld1 { v27.b }[8], [x23]\n" + "ld1 { v26.b }[8], [x22]\n" + "ld1 { v19.b }[8], [x21]\n" + "ld1 { v24.b }[8], [x20]\n" "b 11f\n" "7:" // odd_loads_4_0 "tbz %x[width], #2, 9f\n" "ldr s28, [x27], #0x4\n" - "ldr s27, [x26], #0x4\n" - "ldr s26, [x25], #0x4\n" - "ldr s22, [x24], #0x4\n" - "ldr s25, [x23], #0x4\n" - "ldr s24, [x22], #0x4\n" + "ldr s29, [x26], #0x4\n" + "ldr s25, [x25], #0x4\n" + "ldr s21, [x24], #0x4\n" + "ldr s27, [x23], #0x4\n" + "ldr s26, [x22], #0x4\n" "ldr s19, [x21], #0x4\n" - "ldr s21, [x20], #0x4\n" + "ldr s24, [x20], #0x4\n" "tbz %x[width], #1, 8f\n" "ld1 { v28.h }[2], [x27], #0x2\n" - "ld1 { v27.h }[2], [x26], #0x2\n" - "ld1 { v26.h }[2], [x25], #0x2\n" - "ld1 { v22.h }[2], [x24], #0x2\n" - "ld1 { v25.h }[2], [x23], #0x2\n" - "ld1 { v24.h }[2], [x22], #0x2\n" - "ld1 { v19.h }[2], [x21], #0x2\n" - "ld1 { v21.h }[2], [x20], #0x2\n" "mov x19, #0x2\n" + "ld1 { v29.h }[2], [x26], #0x2\n" + "ld1 { v25.h }[2], [x25], #0x2\n" + "ld1 { v21.h }[2], [x24], #0x2\n" + "ld1 { v27.h }[2], [x23], #0x2\n" + "ld1 { v26.h }[2], [x22], #0x2\n" + "ld1 { v19.h }[2], [x21], #0x2\n" + "ld1 { v24.h }[2], [x20], #0x2\n" "tbz %x[width], #0, 11f\n" "ld1 { v28.b }[6], [x27]\n" - "ld1 { v27.b }[6], [x26]\n" - "ld1 { v26.b }[6], [x25]\n" - "ld1 { v22.b }[6], [x24]\n" - "ld1 { v25.b }[6], [x23]\n" - "ld1 { v24.b }[6], [x22]\n" + "ld1 { v29.b }[6], [x26]\n" + "ld1 { v25.b }[6], [x25]\n" + "ld1 { v21.b }[6], [x24]\n" + "ld1 { v27.b }[6], [x23]\n" + "ld1 { v26.b }[6], [x22]\n" "ld1 { v19.b }[6], [x21]\n" - "ld1 { v21.b }[6], [x20]\n" + "ld1 { v24.b }[6], [x20]\n" "b 11f\n" "8:" // odd_loads_1_4 "mov x19, #0x1\n" "tbz %x[width], #0, 11f\n" "ld1 { v28.b }[4], [x27]\n" - "ld1 { v27.b }[4], [x26]\n" - "ld1 { v26.b }[4], [x25]\n" - "ld1 { v22.b }[4], [x24]\n" - "ld1 { v25.b }[4], [x23]\n" - "ld1 { v24.b }[4], [x22]\n" - "ld1 { v19.b }[4], [x21]\n" - "ld1 { v21.b }[4], [x20]\n" + "ld1 { v29.b }[4], [x26]\n" "mov x19, #0x2\n" + "ld1 { v25.b }[4], [x25]\n" + "ld1 { v21.b }[4], [x24]\n" + "ld1 { v27.b }[4], [x23]\n" + "ld1 { v26.b }[4], [x22]\n" + "ld1 { v19.b }[4], [x21]\n" + "ld1 { v24.b }[4], [x20]\n" "b 11f\n" "9:" // odd_loads_2_0 "tbz %x[width], #1, 10f\n" "ldr h28, [x27], #0x2\n" - "ldr h27, [x26], #0x2\n" - "ldr h26, [x25], #0x2\n" - "ldr h22, [x24], #0x2\n" - "ldr h25, [x23], #0x2\n" - "ldr h24, [x22], #0x2\n" - "ldr h19, [x21], #0x2\n" - "ldr h21, [x20], #0x2\n" + "ldr h29, [x26], #0x2\n" "mov x19, #0x1\n" + "ldr h25, [x25], #0x2\n" + "ldr h21, [x24], #0x2\n" + "ldr h27, [x23], #0x2\n" + "ldr h26, [x22], #0x2\n" + "ldr h19, [x21], #0x2\n" + "ldr h24, [x20], #0x2\n" "tbz %x[width], #0, 11f\n" "ld1 { v28.b }[2], [x27]\n" - "ld1 { v27.b }[2], [x26]\n" - "ld1 { v26.b }[2], [x25]\n" - "ld1 { v22.b }[2], [x24]\n" - "ld1 { v25.b }[2], [x23]\n" - "ld1 { v24.b }[2], [x22]\n" + "ld1 { v29.b }[2], [x26]\n" + "ld1 { v25.b }[2], [x25]\n" + "ld1 { v21.b }[2], [x24]\n" + "ld1 { v27.b }[2], [x23]\n" + "ld1 { v26.b }[2], [x22]\n" "ld1 { v19.b }[2], [x21]\n" - "ld1 { v21.b }[2], [x20]\n" + "ld1 { v24.b }[2], [x20]\n" "b 11f\n" "10:" // odd_loads_1_0 "ldr b28, [x27, #0x0]\n" - "ldr b27, [x26, #0x0]\n" - "ldr b26, [x25, #0x0]\n" - "ldr b22, [x24, #0x0]\n" - "ldr b25, [x23, #0x0]\n" - "ldr b24, [x22, #0x0]\n" - "ldr b19, [x21, #0x0]\n" - "ldr b21, [x20, #0x0]\n" "mov x19, #0x1\n" + "ldr b29, [x26, #0x0]\n" + "ldr b25, [x25, #0x0]\n" + "ldr b21, [x24, #0x0]\n" + "ldr b27, [x23, #0x0]\n" + "ldr b26, [x22, #0x0]\n" + "ldr b19, [x21, #0x0]\n" + "ldr b24, [x20, #0x0]\n" "11:" // Odd load end - "zip1 v23.4s, v28.4s, v26.4s\n" + "zip1 v22.4s, v28.4s, v25.4s\n" "subs x19, x19, #0x1\n" - "zip1 v20.4s, v27.4s, v22.4s\n" - "zip1 v16.4s, v23.4s, v20.4s\n" - "str q16, [%x[out_ptr], #0x0]\n" - "zip1 v18.4s, v25.4s, v19.4s\n" - "zip1 v16.4s, v24.4s, v21.4s\n" + "zip1 v20.4s, v29.4s, v21.4s\n" + "zip1 v23.4s, v22.4s, v20.4s\n" + "str q23, [%x[out_ptr], #0x0]\n" + "zip1 v18.4s, v27.4s, v19.4s\n" + "zip1 v16.4s, v26.4s, v24.4s\n" "zip1 v17.4s, v18.4s, v16.4s\n" "str q17, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "beq 12f\n" - "zip2 v23.4s, v23.4s, v20.4s\n" - "zip2 v16.4s, v18.4s, v16.4s\n" - "str q23, [%x[out_ptr], #0x0]\n" - "str q16, [%x[out_ptr], #0x10]\n" + "zip2 v22.4s, v22.4s, v20.4s\n" + "str q22, [%x[out_ptr], #0x0]\n" + "zip2 v20.4s, v18.4s, v16.4s\n" "subs x19, x19, #0x1\n" + "str q20, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "beq 12f\n" - "zip2 v26.4s, v28.4s, v26.4s\n" - "zip2 v22.4s, v27.4s, v22.4s\n" + "zip2 v28.4s, v28.4s, v25.4s\n" + "zip2 v25.4s, v29.4s, v21.4s\n" "subs x19, x19, #0x1\n" - "zip1 v20.4s, v26.4s, v22.4s\n" - "str q20, [%x[out_ptr], #0x0]\n" - "zip2 v19.4s, v25.4s, v19.4s\n" - "zip2 v18.4s, v24.4s, v21.4s\n" - "zip1 v16.4s, v19.4s, v18.4s\n" - "str q16, [%x[out_ptr], #0x10]\n" + "zip1 v21.4s, v28.4s, v25.4s\n" + "str q21, [%x[out_ptr], #0x0]\n" + "zip2 v19.4s, v27.4s, v19.4s\n" + "zip2 v16.4s, v26.4s, v24.4s\n" + "zip1 v18.4s, v19.4s, v16.4s\n" + "str q18, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "beq 12f\n" - "zip2 v17.4s, v26.4s, v22.4s\n" - "zip2 v16.4s, v19.4s, v18.4s\n" + "zip2 v17.4s, v28.4s, v25.4s\n" "str q17, [%x[out_ptr], #0x0]\n" + "zip2 v16.4s, v19.4s, v16.4s\n" "str q16, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "12:" // Odds skip - : [out_ptr] "+r" (out_ptr), [width] "+r" (width) + : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) - : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" + : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); } diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block4_s8_s8_summing.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block4_s8_s8_summing.hpp index 2831cb79a6..dfec94c952 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block4_s8_s8_summing.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block4_s8_s8_summing.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020 Arm Limited. + * Copyright (c) 2019-2021 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -97,270 +97,270 @@ void interleave_block<8, 4, VLType::None, true>( "movi v0.8h, #0x0\n" "mov x19, #0x0\n" "4:" // no_accumulate_16 - "ldr q29, [x27], #0x10\n" + "ldr q28, [x27], #0x10\n" + "add x19, x19, #0x1\n" + "ldr q29, [x26], #0x10\n" + "subs %x[width], %x[width], #0x10\n" + "ldr q25, [x25], #0x10\n" + "zip1 v22.4s, v28.4s, v25.4s\n" + "ldr q21, [x24], #0x10\n" + "cmp %x[width], #0x10\n" + "zip2 v28.4s, v28.4s, v25.4s\n" + "ldr q27, [x23], #0x10\n" + "ldr q26, [x22], #0x10\n" + "zip1 v20.4s, v29.4s, v21.4s\n" + "ldr q19, [x21], #0x10\n" + "zip2 v25.4s, v29.4s, v21.4s\n" + "ldr q24, [x20], #0x10\n" + "zip1 v23.4s, v22.4s, v20.4s\n" "prfm pldl1keep, [x27, #0x70]\n" - "ldr q28, [x26], #0x10\n" - "ldr q27, [x25], #0x10\n" - "zip1 v23.4s, v29.4s, v27.4s\n" + "sadalp v1.8h, v23.16b\n" + "zip2 v22.4s, v22.4s, v20.4s\n" "prfm pldl1keep, [x26, #0x70]\n" - "ldr q21, [x24], #0x10\n" - "zip2 v27.4s, v29.4s, v27.4s\n" + "sadalp v1.8h, v22.16b\n" + "zip1 v18.4s, v27.4s, v19.4s\n" "prfm pldl1keep, [x25, #0x70]\n" - "ldr q26, [x23], #0x10\n" - "zip1 v20.4s, v28.4s, v21.4s\n" + "zip1 v16.4s, v26.4s, v24.4s\n" "prfm pldl1keep, [x24, #0x70]\n" - "ldr q25, [x22], #0x10\n" - "zip1 v16.4s, v23.4s, v20.4s\n" + "zip1 v21.4s, v28.4s, v25.4s\n" "prfm pldl1keep, [x23, #0x70]\n" - "ldr q19, [x21], #0x10\n" - "zip2 v24.4s, v23.4s, v20.4s\n" + "sadalp v1.8h, v21.16b\n" + "zip1 v17.4s, v18.4s, v16.4s\n" "prfm pldl1keep, [x22, #0x70]\n" - "zip2 v23.4s, v28.4s, v21.4s\n" - "ldr q22, [x20], #0x10\n" - "zip1 v18.4s, v26.4s, v19.4s\n" + "zip2 v20.4s, v18.4s, v16.4s\n" "prfm pldl1keep, [x21, #0x70]\n" - "str q16, [%x[out_ptr], #0x0]\n" - "zip1 v21.4s, v27.4s, v23.4s\n" + "sadalp v0.8h, v17.16b\n" + "zip2 v19.4s, v27.4s, v19.4s\n" "prfm pldl1keep, [x20, #0x70]\n" - "zip1 v17.4s, v25.4s, v22.4s\n" - "sadalp v1.8h, v16.16b\n" - "zip1 v16.4s, v18.4s, v17.4s\n" - "add x19, x19, #0x1\n" - "zip2 v20.4s, v18.4s, v17.4s\n" - "str q16, [%x[out_ptr], #0x10]\n" - "zip2 v19.4s, v26.4s, v19.4s\n" - "sadalp v0.8h, v16.16b\n" - "zip2 v16.4s, v25.4s, v22.4s\n" - "str q24, [%x[out_ptr], #0x20]\n" + "sadalp v0.8h, v20.16b\n" + "zip2 v16.4s, v26.4s, v24.4s\n" + "str q23, [%x[out_ptr], #0x0]\n" "zip1 v18.4s, v19.4s, v16.4s\n" - "sadalp v1.8h, v24.16b\n" - "zip2 v17.4s, v27.4s, v23.4s\n" - "str q20, [%x[out_ptr], #0x30]\n" + "str q17, [%x[out_ptr], #0x10]\n" + "sadalp v0.8h, v18.16b\n" + "zip2 v17.4s, v28.4s, v25.4s\n" + "str q22, [%x[out_ptr], #0x20]\n" "zip2 v16.4s, v19.4s, v16.4s\n" + "str q20, [%x[out_ptr], #0x30]\n" + "sadalp v1.8h, v17.16b\n" "str q21, [%x[out_ptr], #0x40]\n" + "sadalp v0.8h, v16.16b\n" "str q18, [%x[out_ptr], #0x50]\n" - "sadalp v0.8h, v20.16b\n" "str q17, [%x[out_ptr], #0x60]\n" - "sadalp v1.8h, v21.16b\n" "str q16, [%x[out_ptr], #0x70]\n" - "subs %x[width], %x[width], #0x10\n" - "sadalp v0.8h, v18.16b\n" - "cmp %x[width], #0x10\n" - "sadalp v1.8h, v17.16b\n" "add %x[out_ptr], %x[out_ptr], #0x80\n" - "sadalp v0.8h, v16.16b\n" "bge 3b\n" "5:" // Main loop skip "cbz %x[width], 14f\n" "tbz %x[width], #3, 9f\n" - "ldr d29, [x27], #0x8\n" - "ldr d28, [x26], #0x8\n" - "ldr d27, [x25], #0x8\n" + "ldr d28, [x27], #0x8\n" + "ldr d29, [x26], #0x8\n" + "ldr d25, [x25], #0x8\n" "ldr d21, [x24], #0x8\n" - "ldr d26, [x23], #0x8\n" - "ldr d25, [x22], #0x8\n" + "ldr d27, [x23], #0x8\n" + "ldr d26, [x22], #0x8\n" "ldr d19, [x21], #0x8\n" - "ldr d22, [x20], #0x8\n" + "ldr d24, [x20], #0x8\n" "tbz %x[width], #2, 7f\n" - "ld1 { v29.s }[2], [x27], #0x4\n" - "ld1 { v28.s }[2], [x26], #0x4\n" - "ld1 { v27.s }[2], [x25], #0x4\n" + "ld1 { v28.s }[2], [x27], #0x4\n" + "ld1 { v29.s }[2], [x26], #0x4\n" + "ld1 { v25.s }[2], [x25], #0x4\n" "ld1 { v21.s }[2], [x24], #0x4\n" - "ld1 { v26.s }[2], [x23], #0x4\n" - "ld1 { v25.s }[2], [x22], #0x4\n" + "ld1 { v27.s }[2], [x23], #0x4\n" + "ld1 { v26.s }[2], [x22], #0x4\n" "ld1 { v19.s }[2], [x21], #0x4\n" - "ld1 { v22.s }[2], [x20], #0x4\n" + "ld1 { v24.s }[2], [x20], #0x4\n" "tbz %x[width], #1, 6f\n" - "ld1 { v29.h }[6], [x27], #0x2\n" - "ld1 { v28.h }[6], [x26], #0x2\n" - "ld1 { v27.h }[6], [x25], #0x2\n" + "ld1 { v28.h }[6], [x27], #0x2\n" + "mov x19, #0x4\n" + "ld1 { v29.h }[6], [x26], #0x2\n" + "ld1 { v25.h }[6], [x25], #0x2\n" "ld1 { v21.h }[6], [x24], #0x2\n" - "ld1 { v26.h }[6], [x23], #0x2\n" - "ld1 { v25.h }[6], [x22], #0x2\n" + "ld1 { v27.h }[6], [x23], #0x2\n" + "ld1 { v26.h }[6], [x22], #0x2\n" "ld1 { v19.h }[6], [x21], #0x2\n" - "ld1 { v22.h }[6], [x20], #0x2\n" - "mov x19, #0x4\n" + "ld1 { v24.h }[6], [x20], #0x2\n" "tbz %x[width], #0, 13f\n" - "ld1 { v29.b }[14], [x27]\n" - "ld1 { v28.b }[14], [x26]\n" - "ld1 { v27.b }[14], [x25]\n" + "ld1 { v28.b }[14], [x27]\n" + "ld1 { v29.b }[14], [x26]\n" + "ld1 { v25.b }[14], [x25]\n" "ld1 { v21.b }[14], [x24]\n" - "ld1 { v26.b }[14], [x23]\n" - "ld1 { v25.b }[14], [x22]\n" + "ld1 { v27.b }[14], [x23]\n" + "ld1 { v26.b }[14], [x22]\n" "ld1 { v19.b }[14], [x21]\n" - "ld1 { v22.b }[14], [x20]\n" + "ld1 { v24.b }[14], [x20]\n" "b 13f\n" "6:" // odd_loads_1_12 "mov x19, #0x3\n" "tbz %x[width], #0, 13f\n" - "ld1 { v29.b }[12], [x27]\n" - "ld1 { v28.b }[12], [x26]\n" - "ld1 { v27.b }[12], [x25]\n" + "ld1 { v28.b }[12], [x27]\n" + "ld1 { v29.b }[12], [x26]\n" + "mov x19, #0x4\n" + "ld1 { v25.b }[12], [x25]\n" "ld1 { v21.b }[12], [x24]\n" - "ld1 { v26.b }[12], [x23]\n" - "ld1 { v25.b }[12], [x22]\n" + "ld1 { v27.b }[12], [x23]\n" + "ld1 { v26.b }[12], [x22]\n" "ld1 { v19.b }[12], [x21]\n" - "ld1 { v22.b }[12], [x20]\n" - "mov x19, #0x4\n" + "ld1 { v24.b }[12], [x20]\n" "b 13f\n" "7:" // odd_loads_2_8 "tbz %x[width], #1, 8f\n" - "ld1 { v29.h }[4], [x27], #0x2\n" - "ld1 { v28.h }[4], [x26], #0x2\n" - "ld1 { v27.h }[4], [x25], #0x2\n" + "ld1 { v28.h }[4], [x27], #0x2\n" + "ld1 { v29.h }[4], [x26], #0x2\n" + "mov x19, #0x3\n" + "ld1 { v25.h }[4], [x25], #0x2\n" "ld1 { v21.h }[4], [x24], #0x2\n" - "ld1 { v26.h }[4], [x23], #0x2\n" - "ld1 { v25.h }[4], [x22], #0x2\n" + "ld1 { v27.h }[4], [x23], #0x2\n" + "ld1 { v26.h }[4], [x22], #0x2\n" "ld1 { v19.h }[4], [x21], #0x2\n" - "ld1 { v22.h }[4], [x20], #0x2\n" - "mov x19, #0x3\n" + "ld1 { v24.h }[4], [x20], #0x2\n" "tbz %x[width], #0, 13f\n" - "ld1 { v29.b }[10], [x27]\n" - "ld1 { v28.b }[10], [x26]\n" - "ld1 { v27.b }[10], [x25]\n" + "ld1 { v28.b }[10], [x27]\n" + "ld1 { v29.b }[10], [x26]\n" + "ld1 { v25.b }[10], [x25]\n" "ld1 { v21.b }[10], [x24]\n" - "ld1 { v26.b }[10], [x23]\n" - "ld1 { v25.b }[10], [x22]\n" + "ld1 { v27.b }[10], [x23]\n" + "ld1 { v26.b }[10], [x22]\n" "ld1 { v19.b }[10], [x21]\n" - "ld1 { v22.b }[10], [x20]\n" + "ld1 { v24.b }[10], [x20]\n" "b 13f\n" "8:" // odd_loads_1_8 "mov x19, #0x2\n" "tbz %x[width], #0, 13f\n" - "ld1 { v29.b }[8], [x27]\n" - "ld1 { v28.b }[8], [x26]\n" - "ld1 { v27.b }[8], [x25]\n" + "ld1 { v28.b }[8], [x27]\n" + "ld1 { v29.b }[8], [x26]\n" + "mov x19, #0x3\n" + "ld1 { v25.b }[8], [x25]\n" "ld1 { v21.b }[8], [x24]\n" - "ld1 { v26.b }[8], [x23]\n" - "ld1 { v25.b }[8], [x22]\n" + "ld1 { v27.b }[8], [x23]\n" + "ld1 { v26.b }[8], [x22]\n" "ld1 { v19.b }[8], [x21]\n" - "ld1 { v22.b }[8], [x20]\n" - "mov x19, #0x3\n" + "ld1 { v24.b }[8], [x20]\n" "b 13f\n" "9:" // odd_loads_4_0 "tbz %x[width], #2, 11f\n" - "ldr s29, [x27], #0x4\n" - "ldr s28, [x26], #0x4\n" - "ldr s27, [x25], #0x4\n" + "ldr s28, [x27], #0x4\n" + "ldr s29, [x26], #0x4\n" + "ldr s25, [x25], #0x4\n" "ldr s21, [x24], #0x4\n" - "ldr s26, [x23], #0x4\n" - "ldr s25, [x22], #0x4\n" + "ldr s27, [x23], #0x4\n" + "ldr s26, [x22], #0x4\n" "ldr s19, [x21], #0x4\n" - "ldr s22, [x20], #0x4\n" + "ldr s24, [x20], #0x4\n" "tbz %x[width], #1, 10f\n" - "ld1 { v29.h }[2], [x27], #0x2\n" - "ld1 { v28.h }[2], [x26], #0x2\n" - "ld1 { v27.h }[2], [x25], #0x2\n" + "ld1 { v28.h }[2], [x27], #0x2\n" + "mov x19, #0x2\n" + "ld1 { v29.h }[2], [x26], #0x2\n" + "ld1 { v25.h }[2], [x25], #0x2\n" "ld1 { v21.h }[2], [x24], #0x2\n" - "ld1 { v26.h }[2], [x23], #0x2\n" - "ld1 { v25.h }[2], [x22], #0x2\n" + "ld1 { v27.h }[2], [x23], #0x2\n" + "ld1 { v26.h }[2], [x22], #0x2\n" "ld1 { v19.h }[2], [x21], #0x2\n" - "ld1 { v22.h }[2], [x20], #0x2\n" - "mov x19, #0x2\n" + "ld1 { v24.h }[2], [x20], #0x2\n" "tbz %x[width], #0, 13f\n" - "ld1 { v29.b }[6], [x27]\n" - "ld1 { v28.b }[6], [x26]\n" - "ld1 { v27.b }[6], [x25]\n" + "ld1 { v28.b }[6], [x27]\n" + "ld1 { v29.b }[6], [x26]\n" + "ld1 { v25.b }[6], [x25]\n" "ld1 { v21.b }[6], [x24]\n" - "ld1 { v26.b }[6], [x23]\n" - "ld1 { v25.b }[6], [x22]\n" + "ld1 { v27.b }[6], [x23]\n" + "ld1 { v26.b }[6], [x22]\n" "ld1 { v19.b }[6], [x21]\n" - "ld1 { v22.b }[6], [x20]\n" + "ld1 { v24.b }[6], [x20]\n" "b 13f\n" "10:" // odd_loads_1_4 "mov x19, #0x1\n" "tbz %x[width], #0, 13f\n" - "ld1 { v29.b }[4], [x27]\n" - "ld1 { v28.b }[4], [x26]\n" - "ld1 { v27.b }[4], [x25]\n" + "ld1 { v28.b }[4], [x27]\n" + "ld1 { v29.b }[4], [x26]\n" + "mov x19, #0x2\n" + "ld1 { v25.b }[4], [x25]\n" "ld1 { v21.b }[4], [x24]\n" - "ld1 { v26.b }[4], [x23]\n" - "ld1 { v25.b }[4], [x22]\n" + "ld1 { v27.b }[4], [x23]\n" + "ld1 { v26.b }[4], [x22]\n" "ld1 { v19.b }[4], [x21]\n" - "ld1 { v22.b }[4], [x20]\n" - "mov x19, #0x2\n" + "ld1 { v24.b }[4], [x20]\n" "b 13f\n" "11:" // odd_loads_2_0 "tbz %x[width], #1, 12f\n" - "ldr h29, [x27], #0x2\n" - "ldr h28, [x26], #0x2\n" - "ldr h27, [x25], #0x2\n" + "ldr h28, [x27], #0x2\n" + "ldr h29, [x26], #0x2\n" + "mov x19, #0x1\n" + "ldr h25, [x25], #0x2\n" "ldr h21, [x24], #0x2\n" - "ldr h26, [x23], #0x2\n" - "ldr h25, [x22], #0x2\n" + "ldr h27, [x23], #0x2\n" + "ldr h26, [x22], #0x2\n" "ldr h19, [x21], #0x2\n" - "ldr h22, [x20], #0x2\n" - "mov x19, #0x1\n" + "ldr h24, [x20], #0x2\n" "tbz %x[width], #0, 13f\n" - "ld1 { v29.b }[2], [x27]\n" - "ld1 { v28.b }[2], [x26]\n" - "ld1 { v27.b }[2], [x25]\n" + "ld1 { v28.b }[2], [x27]\n" + "ld1 { v29.b }[2], [x26]\n" + "ld1 { v25.b }[2], [x25]\n" "ld1 { v21.b }[2], [x24]\n" - "ld1 { v26.b }[2], [x23]\n" - "ld1 { v25.b }[2], [x22]\n" + "ld1 { v27.b }[2], [x23]\n" + "ld1 { v26.b }[2], [x22]\n" "ld1 { v19.b }[2], [x21]\n" - "ld1 { v22.b }[2], [x20]\n" + "ld1 { v24.b }[2], [x20]\n" "b 13f\n" "12:" // odd_loads_1_0 - "ldr b29, [x27, #0x0]\n" - "ldr b28, [x26, #0x0]\n" - "ldr b27, [x25, #0x0]\n" + "ldr b28, [x27, #0x0]\n" + "mov x19, #0x1\n" + "ldr b29, [x26, #0x0]\n" + "ldr b25, [x25, #0x0]\n" "ldr b21, [x24, #0x0]\n" - "ldr b26, [x23, #0x0]\n" - "ldr b25, [x22, #0x0]\n" + "ldr b27, [x23, #0x0]\n" + "ldr b26, [x22, #0x0]\n" "ldr b19, [x21, #0x0]\n" - "ldr b22, [x20, #0x0]\n" - "mov x19, #0x1\n" + "ldr b24, [x20, #0x0]\n" "13:" // Odd load end - "zip1 v23.4s, v29.4s, v27.4s\n" + "zip1 v22.4s, v28.4s, v25.4s\n" "subs x19, x19, #0x1\n" - "zip1 v20.4s, v28.4s, v21.4s\n" - "zip1 v16.4s, v23.4s, v20.4s\n" - "str q16, [%x[out_ptr], #0x0]\n" - "zip1 v18.4s, v26.4s, v19.4s\n" - "sadalp v1.8h, v16.16b\n" - "zip1 v17.4s, v25.4s, v22.4s\n" - "zip1 v16.4s, v18.4s, v17.4s\n" - "str q16, [%x[out_ptr], #0x10]\n" - "sadalp v0.8h, v16.16b\n" + "zip1 v20.4s, v29.4s, v21.4s\n" + "zip1 v23.4s, v22.4s, v20.4s\n" + "str q23, [%x[out_ptr], #0x0]\n" + "sadalp v1.8h, v23.16b\n" + "zip1 v18.4s, v27.4s, v19.4s\n" + "zip1 v16.4s, v26.4s, v24.4s\n" + "zip1 v17.4s, v18.4s, v16.4s\n" + "str q17, [%x[out_ptr], #0x10]\n" + "sadalp v0.8h, v17.16b\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "beq 14f\n" - "zip2 v24.4s, v23.4s, v20.4s\n" - "zip2 v20.4s, v18.4s, v17.4s\n" - "str q24, [%x[out_ptr], #0x0]\n" - "sadalp v1.8h, v24.16b\n" + "zip2 v22.4s, v22.4s, v20.4s\n" + "str q22, [%x[out_ptr], #0x0]\n" + "zip2 v20.4s, v18.4s, v16.4s\n" + "sadalp v1.8h, v22.16b\n" "str q20, [%x[out_ptr], #0x10]\n" - "sadalp v0.8h, v20.16b\n" "subs x19, x19, #0x1\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" + "sadalp v0.8h, v20.16b\n" "beq 14f\n" - "zip2 v27.4s, v29.4s, v27.4s\n" - "zip2 v23.4s, v28.4s, v21.4s\n" + "zip2 v28.4s, v28.4s, v25.4s\n" + "zip2 v25.4s, v29.4s, v21.4s\n" "subs x19, x19, #0x1\n" - "zip1 v21.4s, v27.4s, v23.4s\n" + "zip1 v21.4s, v28.4s, v25.4s\n" "str q21, [%x[out_ptr], #0x0]\n" - "zip2 v19.4s, v26.4s, v19.4s\n" "sadalp v1.8h, v21.16b\n" - "zip2 v16.4s, v25.4s, v22.4s\n" + "zip2 v19.4s, v27.4s, v19.4s\n" + "zip2 v16.4s, v26.4s, v24.4s\n" "zip1 v18.4s, v19.4s, v16.4s\n" "str q18, [%x[out_ptr], #0x10]\n" "sadalp v0.8h, v18.16b\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "beq 14f\n" - "zip2 v17.4s, v27.4s, v23.4s\n" - "zip2 v16.4s, v19.4s, v16.4s\n" + "zip2 v17.4s, v28.4s, v25.4s\n" "str q17, [%x[out_ptr], #0x0]\n" + "zip2 v16.4s, v19.4s, v16.4s\n" "sadalp v1.8h, v17.16b\n" "str q16, [%x[out_ptr], #0x10]\n" - "sadalp v0.8h, v16.16b\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" + "sadalp v0.8h, v16.16b\n" "14:" // Odds skip "sadalp v31.4s, v1.8h\n" - "sadalp v30.4s, v0.8h\n" "str q31, [%x[out_ptr], #0x0]\n" + "sadalp v30.4s, v0.8h\n" "str q30, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" - : [out_ptr] "+r" (out_ptr), [width] "+r" (width) + : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [first] "r" (first), [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) : "cc", "memory", "v0", "v1", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block4_u8_u8_summing.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block4_u8_u8_summing.hpp index 7c7857bcd0..1b94c7f1f1 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block4_u8_u8_summing.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block4_u8_u8_summing.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020 Arm Limited. + * Copyright (c) 2019-2021 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -97,270 +97,270 @@ void interleave_block<8, 4, VLType::None, true>( "movi v0.8h, #0x0\n" "mov x19, #0x0\n" "4:" // no_accumulate_16 - "ldr q29, [x27], #0x10\n" + "ldr q28, [x27], #0x10\n" + "add x19, x19, #0x1\n" + "ldr q29, [x26], #0x10\n" + "subs %x[width], %x[width], #0x10\n" + "ldr q25, [x25], #0x10\n" + "zip1 v22.4s, v28.4s, v25.4s\n" + "ldr q21, [x24], #0x10\n" + "cmp %x[width], #0x10\n" + "zip2 v28.4s, v28.4s, v25.4s\n" + "ldr q27, [x23], #0x10\n" + "ldr q26, [x22], #0x10\n" + "zip1 v20.4s, v29.4s, v21.4s\n" + "ldr q19, [x21], #0x10\n" + "zip2 v25.4s, v29.4s, v21.4s\n" + "ldr q24, [x20], #0x10\n" + "zip1 v23.4s, v22.4s, v20.4s\n" "prfm pldl1keep, [x27, #0x70]\n" - "ldr q28, [x26], #0x10\n" - "ldr q27, [x25], #0x10\n" - "zip1 v23.4s, v29.4s, v27.4s\n" + "uadalp v1.8h, v23.16b\n" + "zip2 v22.4s, v22.4s, v20.4s\n" "prfm pldl1keep, [x26, #0x70]\n" - "ldr q21, [x24], #0x10\n" - "zip2 v27.4s, v29.4s, v27.4s\n" + "uadalp v1.8h, v22.16b\n" + "zip1 v18.4s, v27.4s, v19.4s\n" "prfm pldl1keep, [x25, #0x70]\n" - "ldr q26, [x23], #0x10\n" - "zip1 v20.4s, v28.4s, v21.4s\n" + "zip1 v16.4s, v26.4s, v24.4s\n" "prfm pldl1keep, [x24, #0x70]\n" - "ldr q25, [x22], #0x10\n" - "zip1 v16.4s, v23.4s, v20.4s\n" + "zip1 v21.4s, v28.4s, v25.4s\n" "prfm pldl1keep, [x23, #0x70]\n" - "ldr q19, [x21], #0x10\n" - "zip2 v24.4s, v23.4s, v20.4s\n" + "uadalp v1.8h, v21.16b\n" + "zip1 v17.4s, v18.4s, v16.4s\n" "prfm pldl1keep, [x22, #0x70]\n" - "zip2 v23.4s, v28.4s, v21.4s\n" - "ldr q22, [x20], #0x10\n" - "zip1 v18.4s, v26.4s, v19.4s\n" + "zip2 v20.4s, v18.4s, v16.4s\n" "prfm pldl1keep, [x21, #0x70]\n" - "str q16, [%x[out_ptr], #0x0]\n" - "zip1 v21.4s, v27.4s, v23.4s\n" + "uadalp v0.8h, v17.16b\n" + "zip2 v19.4s, v27.4s, v19.4s\n" "prfm pldl1keep, [x20, #0x70]\n" - "zip1 v17.4s, v25.4s, v22.4s\n" - "uadalp v1.8h, v16.16b\n" - "zip1 v16.4s, v18.4s, v17.4s\n" - "add x19, x19, #0x1\n" - "zip2 v20.4s, v18.4s, v17.4s\n" - "str q16, [%x[out_ptr], #0x10]\n" - "zip2 v19.4s, v26.4s, v19.4s\n" - "uadalp v0.8h, v16.16b\n" - "zip2 v16.4s, v25.4s, v22.4s\n" - "str q24, [%x[out_ptr], #0x20]\n" + "uadalp v0.8h, v20.16b\n" + "zip2 v16.4s, v26.4s, v24.4s\n" + "str q23, [%x[out_ptr], #0x0]\n" "zip1 v18.4s, v19.4s, v16.4s\n" - "uadalp v1.8h, v24.16b\n" - "zip2 v17.4s, v27.4s, v23.4s\n" - "str q20, [%x[out_ptr], #0x30]\n" + "str q17, [%x[out_ptr], #0x10]\n" + "uadalp v0.8h, v18.16b\n" + "zip2 v17.4s, v28.4s, v25.4s\n" + "str q22, [%x[out_ptr], #0x20]\n" "zip2 v16.4s, v19.4s, v16.4s\n" + "str q20, [%x[out_ptr], #0x30]\n" + "uadalp v1.8h, v17.16b\n" "str q21, [%x[out_ptr], #0x40]\n" + "uadalp v0.8h, v16.16b\n" "str q18, [%x[out_ptr], #0x50]\n" - "uadalp v0.8h, v20.16b\n" "str q17, [%x[out_ptr], #0x60]\n" - "uadalp v1.8h, v21.16b\n" "str q16, [%x[out_ptr], #0x70]\n" - "subs %x[width], %x[width], #0x10\n" - "uadalp v0.8h, v18.16b\n" - "cmp %x[width], #0x10\n" - "uadalp v1.8h, v17.16b\n" "add %x[out_ptr], %x[out_ptr], #0x80\n" - "uadalp v0.8h, v16.16b\n" "bge 3b\n" "5:" // Main loop skip "cbz %x[width], 14f\n" "tbz %x[width], #3, 9f\n" - "ldr d29, [x27], #0x8\n" - "ldr d28, [x26], #0x8\n" - "ldr d27, [x25], #0x8\n" + "ldr d28, [x27], #0x8\n" + "ldr d29, [x26], #0x8\n" + "ldr d25, [x25], #0x8\n" "ldr d21, [x24], #0x8\n" - "ldr d26, [x23], #0x8\n" - "ldr d25, [x22], #0x8\n" + "ldr d27, [x23], #0x8\n" + "ldr d26, [x22], #0x8\n" "ldr d19, [x21], #0x8\n" - "ldr d22, [x20], #0x8\n" + "ldr d24, [x20], #0x8\n" "tbz %x[width], #2, 7f\n" - "ld1 { v29.s }[2], [x27], #0x4\n" - "ld1 { v28.s }[2], [x26], #0x4\n" - "ld1 { v27.s }[2], [x25], #0x4\n" + "ld1 { v28.s }[2], [x27], #0x4\n" + "ld1 { v29.s }[2], [x26], #0x4\n" + "ld1 { v25.s }[2], [x25], #0x4\n" "ld1 { v21.s }[2], [x24], #0x4\n" - "ld1 { v26.s }[2], [x23], #0x4\n" - "ld1 { v25.s }[2], [x22], #0x4\n" + "ld1 { v27.s }[2], [x23], #0x4\n" + "ld1 { v26.s }[2], [x22], #0x4\n" "ld1 { v19.s }[2], [x21], #0x4\n" - "ld1 { v22.s }[2], [x20], #0x4\n" + "ld1 { v24.s }[2], [x20], #0x4\n" "tbz %x[width], #1, 6f\n" - "ld1 { v29.h }[6], [x27], #0x2\n" - "ld1 { v28.h }[6], [x26], #0x2\n" - "ld1 { v27.h }[6], [x25], #0x2\n" + "ld1 { v28.h }[6], [x27], #0x2\n" + "mov x19, #0x4\n" + "ld1 { v29.h }[6], [x26], #0x2\n" + "ld1 { v25.h }[6], [x25], #0x2\n" "ld1 { v21.h }[6], [x24], #0x2\n" - "ld1 { v26.h }[6], [x23], #0x2\n" - "ld1 { v25.h }[6], [x22], #0x2\n" + "ld1 { v27.h }[6], [x23], #0x2\n" + "ld1 { v26.h }[6], [x22], #0x2\n" "ld1 { v19.h }[6], [x21], #0x2\n" - "ld1 { v22.h }[6], [x20], #0x2\n" - "mov x19, #0x4\n" + "ld1 { v24.h }[6], [x20], #0x2\n" "tbz %x[width], #0, 13f\n" - "ld1 { v29.b }[14], [x27]\n" - "ld1 { v28.b }[14], [x26]\n" - "ld1 { v27.b }[14], [x25]\n" + "ld1 { v28.b }[14], [x27]\n" + "ld1 { v29.b }[14], [x26]\n" + "ld1 { v25.b }[14], [x25]\n" "ld1 { v21.b }[14], [x24]\n" - "ld1 { v26.b }[14], [x23]\n" - "ld1 { v25.b }[14], [x22]\n" + "ld1 { v27.b }[14], [x23]\n" + "ld1 { v26.b }[14], [x22]\n" "ld1 { v19.b }[14], [x21]\n" - "ld1 { v22.b }[14], [x20]\n" + "ld1 { v24.b }[14], [x20]\n" "b 13f\n" "6:" // odd_loads_1_12 "mov x19, #0x3\n" "tbz %x[width], #0, 13f\n" - "ld1 { v29.b }[12], [x27]\n" - "ld1 { v28.b }[12], [x26]\n" - "ld1 { v27.b }[12], [x25]\n" + "ld1 { v28.b }[12], [x27]\n" + "ld1 { v29.b }[12], [x26]\n" + "mov x19, #0x4\n" + "ld1 { v25.b }[12], [x25]\n" "ld1 { v21.b }[12], [x24]\n" - "ld1 { v26.b }[12], [x23]\n" - "ld1 { v25.b }[12], [x22]\n" + "ld1 { v27.b }[12], [x23]\n" + "ld1 { v26.b }[12], [x22]\n" "ld1 { v19.b }[12], [x21]\n" - "ld1 { v22.b }[12], [x20]\n" - "mov x19, #0x4\n" + "ld1 { v24.b }[12], [x20]\n" "b 13f\n" "7:" // odd_loads_2_8 "tbz %x[width], #1, 8f\n" - "ld1 { v29.h }[4], [x27], #0x2\n" - "ld1 { v28.h }[4], [x26], #0x2\n" - "ld1 { v27.h }[4], [x25], #0x2\n" + "ld1 { v28.h }[4], [x27], #0x2\n" + "ld1 { v29.h }[4], [x26], #0x2\n" + "mov x19, #0x3\n" + "ld1 { v25.h }[4], [x25], #0x2\n" "ld1 { v21.h }[4], [x24], #0x2\n" - "ld1 { v26.h }[4], [x23], #0x2\n" - "ld1 { v25.h }[4], [x22], #0x2\n" + "ld1 { v27.h }[4], [x23], #0x2\n" + "ld1 { v26.h }[4], [x22], #0x2\n" "ld1 { v19.h }[4], [x21], #0x2\n" - "ld1 { v22.h }[4], [x20], #0x2\n" - "mov x19, #0x3\n" + "ld1 { v24.h }[4], [x20], #0x2\n" "tbz %x[width], #0, 13f\n" - "ld1 { v29.b }[10], [x27]\n" - "ld1 { v28.b }[10], [x26]\n" - "ld1 { v27.b }[10], [x25]\n" + "ld1 { v28.b }[10], [x27]\n" + "ld1 { v29.b }[10], [x26]\n" + "ld1 { v25.b }[10], [x25]\n" "ld1 { v21.b }[10], [x24]\n" - "ld1 { v26.b }[10], [x23]\n" - "ld1 { v25.b }[10], [x22]\n" + "ld1 { v27.b }[10], [x23]\n" + "ld1 { v26.b }[10], [x22]\n" "ld1 { v19.b }[10], [x21]\n" - "ld1 { v22.b }[10], [x20]\n" + "ld1 { v24.b }[10], [x20]\n" "b 13f\n" "8:" // odd_loads_1_8 "mov x19, #0x2\n" "tbz %x[width], #0, 13f\n" - "ld1 { v29.b }[8], [x27]\n" - "ld1 { v28.b }[8], [x26]\n" - "ld1 { v27.b }[8], [x25]\n" + "ld1 { v28.b }[8], [x27]\n" + "ld1 { v29.b }[8], [x26]\n" + "mov x19, #0x3\n" + "ld1 { v25.b }[8], [x25]\n" "ld1 { v21.b }[8], [x24]\n" - "ld1 { v26.b }[8], [x23]\n" - "ld1 { v25.b }[8], [x22]\n" + "ld1 { v27.b }[8], [x23]\n" + "ld1 { v26.b }[8], [x22]\n" "ld1 { v19.b }[8], [x21]\n" - "ld1 { v22.b }[8], [x20]\n" - "mov x19, #0x3\n" + "ld1 { v24.b }[8], [x20]\n" "b 13f\n" "9:" // odd_loads_4_0 "tbz %x[width], #2, 11f\n" - "ldr s29, [x27], #0x4\n" - "ldr s28, [x26], #0x4\n" - "ldr s27, [x25], #0x4\n" + "ldr s28, [x27], #0x4\n" + "ldr s29, [x26], #0x4\n" + "ldr s25, [x25], #0x4\n" "ldr s21, [x24], #0x4\n" - "ldr s26, [x23], #0x4\n" - "ldr s25, [x22], #0x4\n" + "ldr s27, [x23], #0x4\n" + "ldr s26, [x22], #0x4\n" "ldr s19, [x21], #0x4\n" - "ldr s22, [x20], #0x4\n" + "ldr s24, [x20], #0x4\n" "tbz %x[width], #1, 10f\n" - "ld1 { v29.h }[2], [x27], #0x2\n" - "ld1 { v28.h }[2], [x26], #0x2\n" - "ld1 { v27.h }[2], [x25], #0x2\n" + "ld1 { v28.h }[2], [x27], #0x2\n" + "mov x19, #0x2\n" + "ld1 { v29.h }[2], [x26], #0x2\n" + "ld1 { v25.h }[2], [x25], #0x2\n" "ld1 { v21.h }[2], [x24], #0x2\n" - "ld1 { v26.h }[2], [x23], #0x2\n" - "ld1 { v25.h }[2], [x22], #0x2\n" + "ld1 { v27.h }[2], [x23], #0x2\n" + "ld1 { v26.h }[2], [x22], #0x2\n" "ld1 { v19.h }[2], [x21], #0x2\n" - "ld1 { v22.h }[2], [x20], #0x2\n" - "mov x19, #0x2\n" + "ld1 { v24.h }[2], [x20], #0x2\n" "tbz %x[width], #0, 13f\n" - "ld1 { v29.b }[6], [x27]\n" - "ld1 { v28.b }[6], [x26]\n" - "ld1 { v27.b }[6], [x25]\n" + "ld1 { v28.b }[6], [x27]\n" + "ld1 { v29.b }[6], [x26]\n" + "ld1 { v25.b }[6], [x25]\n" "ld1 { v21.b }[6], [x24]\n" - "ld1 { v26.b }[6], [x23]\n" - "ld1 { v25.b }[6], [x22]\n" + "ld1 { v27.b }[6], [x23]\n" + "ld1 { v26.b }[6], [x22]\n" "ld1 { v19.b }[6], [x21]\n" - "ld1 { v22.b }[6], [x20]\n" + "ld1 { v24.b }[6], [x20]\n" "b 13f\n" "10:" // odd_loads_1_4 "mov x19, #0x1\n" "tbz %x[width], #0, 13f\n" - "ld1 { v29.b }[4], [x27]\n" - "ld1 { v28.b }[4], [x26]\n" - "ld1 { v27.b }[4], [x25]\n" + "ld1 { v28.b }[4], [x27]\n" + "ld1 { v29.b }[4], [x26]\n" + "mov x19, #0x2\n" + "ld1 { v25.b }[4], [x25]\n" "ld1 { v21.b }[4], [x24]\n" - "ld1 { v26.b }[4], [x23]\n" - "ld1 { v25.b }[4], [x22]\n" + "ld1 { v27.b }[4], [x23]\n" + "ld1 { v26.b }[4], [x22]\n" "ld1 { v19.b }[4], [x21]\n" - "ld1 { v22.b }[4], [x20]\n" - "mov x19, #0x2\n" + "ld1 { v24.b }[4], [x20]\n" "b 13f\n" "11:" // odd_loads_2_0 "tbz %x[width], #1, 12f\n" - "ldr h29, [x27], #0x2\n" - "ldr h28, [x26], #0x2\n" - "ldr h27, [x25], #0x2\n" + "ldr h28, [x27], #0x2\n" + "ldr h29, [x26], #0x2\n" + "mov x19, #0x1\n" + "ldr h25, [x25], #0x2\n" "ldr h21, [x24], #0x2\n" - "ldr h26, [x23], #0x2\n" - "ldr h25, [x22], #0x2\n" + "ldr h27, [x23], #0x2\n" + "ldr h26, [x22], #0x2\n" "ldr h19, [x21], #0x2\n" - "ldr h22, [x20], #0x2\n" - "mov x19, #0x1\n" + "ldr h24, [x20], #0x2\n" "tbz %x[width], #0, 13f\n" - "ld1 { v29.b }[2], [x27]\n" - "ld1 { v28.b }[2], [x26]\n" - "ld1 { v27.b }[2], [x25]\n" + "ld1 { v28.b }[2], [x27]\n" + "ld1 { v29.b }[2], [x26]\n" + "ld1 { v25.b }[2], [x25]\n" "ld1 { v21.b }[2], [x24]\n" - "ld1 { v26.b }[2], [x23]\n" - "ld1 { v25.b }[2], [x22]\n" + "ld1 { v27.b }[2], [x23]\n" + "ld1 { v26.b }[2], [x22]\n" "ld1 { v19.b }[2], [x21]\n" - "ld1 { v22.b }[2], [x20]\n" + "ld1 { v24.b }[2], [x20]\n" "b 13f\n" "12:" // odd_loads_1_0 - "ldr b29, [x27, #0x0]\n" - "ldr b28, [x26, #0x0]\n" - "ldr b27, [x25, #0x0]\n" + "ldr b28, [x27, #0x0]\n" + "mov x19, #0x1\n" + "ldr b29, [x26, #0x0]\n" + "ldr b25, [x25, #0x0]\n" "ldr b21, [x24, #0x0]\n" - "ldr b26, [x23, #0x0]\n" - "ldr b25, [x22, #0x0]\n" + "ldr b27, [x23, #0x0]\n" + "ldr b26, [x22, #0x0]\n" "ldr b19, [x21, #0x0]\n" - "ldr b22, [x20, #0x0]\n" - "mov x19, #0x1\n" + "ldr b24, [x20, #0x0]\n" "13:" // Odd load end - "zip1 v23.4s, v29.4s, v27.4s\n" + "zip1 v22.4s, v28.4s, v25.4s\n" "subs x19, x19, #0x1\n" - "zip1 v20.4s, v28.4s, v21.4s\n" - "zip1 v16.4s, v23.4s, v20.4s\n" - "str q16, [%x[out_ptr], #0x0]\n" - "zip1 v18.4s, v26.4s, v19.4s\n" - "uadalp v1.8h, v16.16b\n" - "zip1 v17.4s, v25.4s, v22.4s\n" - "zip1 v16.4s, v18.4s, v17.4s\n" - "str q16, [%x[out_ptr], #0x10]\n" - "uadalp v0.8h, v16.16b\n" + "zip1 v20.4s, v29.4s, v21.4s\n" + "zip1 v23.4s, v22.4s, v20.4s\n" + "str q23, [%x[out_ptr], #0x0]\n" + "uadalp v1.8h, v23.16b\n" + "zip1 v18.4s, v27.4s, v19.4s\n" + "zip1 v16.4s, v26.4s, v24.4s\n" + "zip1 v17.4s, v18.4s, v16.4s\n" + "str q17, [%x[out_ptr], #0x10]\n" + "uadalp v0.8h, v17.16b\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "beq 14f\n" - "zip2 v24.4s, v23.4s, v20.4s\n" - "zip2 v20.4s, v18.4s, v17.4s\n" - "str q24, [%x[out_ptr], #0x0]\n" - "uadalp v1.8h, v24.16b\n" + "zip2 v22.4s, v22.4s, v20.4s\n" + "str q22, [%x[out_ptr], #0x0]\n" + "zip2 v20.4s, v18.4s, v16.4s\n" + "uadalp v1.8h, v22.16b\n" "str q20, [%x[out_ptr], #0x10]\n" - "uadalp v0.8h, v20.16b\n" "subs x19, x19, #0x1\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" + "uadalp v0.8h, v20.16b\n" "beq 14f\n" - "zip2 v27.4s, v29.4s, v27.4s\n" - "zip2 v23.4s, v28.4s, v21.4s\n" + "zip2 v28.4s, v28.4s, v25.4s\n" + "zip2 v25.4s, v29.4s, v21.4s\n" "subs x19, x19, #0x1\n" - "zip1 v21.4s, v27.4s, v23.4s\n" + "zip1 v21.4s, v28.4s, v25.4s\n" "str q21, [%x[out_ptr], #0x0]\n" - "zip2 v19.4s, v26.4s, v19.4s\n" "uadalp v1.8h, v21.16b\n" - "zip2 v16.4s, v25.4s, v22.4s\n" + "zip2 v19.4s, v27.4s, v19.4s\n" + "zip2 v16.4s, v26.4s, v24.4s\n" "zip1 v18.4s, v19.4s, v16.4s\n" "str q18, [%x[out_ptr], #0x10]\n" "uadalp v0.8h, v18.16b\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "beq 14f\n" - "zip2 v17.4s, v27.4s, v23.4s\n" - "zip2 v16.4s, v19.4s, v16.4s\n" + "zip2 v17.4s, v28.4s, v25.4s\n" "str q17, [%x[out_ptr], #0x0]\n" + "zip2 v16.4s, v19.4s, v16.4s\n" "uadalp v1.8h, v17.16b\n" "str q16, [%x[out_ptr], #0x10]\n" - "uadalp v0.8h, v16.16b\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" + "uadalp v0.8h, v16.16b\n" "14:" // Odds skip "uadalp v31.4s, v1.8h\n" - "uadalp v30.4s, v0.8h\n" "str q31, [%x[out_ptr], #0x0]\n" + "uadalp v30.4s, v0.8h\n" "str q30, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" - : [out_ptr] "+r" (out_ptr), [width] "+r" (width) + : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [first] "r" (first), [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) : "cc", "memory", "v0", "v1", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block8_s8_s8.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block8_s8_s8.hpp index 704a4c9210..1330593cbf 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block8_s8_s8.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block8_s8_s8.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020 Arm Limited. + * Copyright (c) 2019-2021 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -80,39 +80,39 @@ void interleave_block<8, 8, VLType::None, false>( "blt 3f\n" "2:" // Main loop head "ldr q27, [x27], #0x10\n" - "prfm pldl1keep, [x27, #0x70]\n" + "subs %x[width], %x[width], #0x10\n" "ldr q24, [x26], #0x10\n" "zip1 v26.2d, v27.2d, v24.2d\n" - "prfm pldl1keep, [x26, #0x70]\n" "ldr q25, [x25], #0x10\n" + "cmp %x[width], #0x10\n" "zip2 v24.2d, v27.2d, v24.2d\n" - "prfm pldl1keep, [x25, #0x70]\n" "ldr q21, [x24], #0x10\n" - "zip1 v23.2d, v25.2d, v21.2d\n" - "prfm pldl1keep, [x24, #0x70]\n" - "ldr q22, [x23], #0x10\n" + "ldr q23, [x23], #0x10\n" + "zip1 v22.2d, v25.2d, v21.2d\n" + "ldr q18, [x22], #0x10\n" "zip2 v21.2d, v25.2d, v21.2d\n" + "ldr q20, [x21], #0x10\n" + "ldr q16, [x20], #0x10\n" + "zip1 v19.2d, v23.2d, v18.2d\n" + "prfm pldl1keep, [x27, #0x70]\n" + "zip2 v18.2d, v23.2d, v18.2d\n" + "prfm pldl1keep, [x26, #0x70]\n" + "zip1 v17.2d, v20.2d, v16.2d\n" + "prfm pldl1keep, [x25, #0x70]\n" + "zip2 v16.2d, v20.2d, v16.2d\n" + "prfm pldl1keep, [x24, #0x70]\n" "prfm pldl1keep, [x23, #0x70]\n" - "ldr q18, [x22], #0x10\n" - "zip1 v20.2d, v22.2d, v18.2d\n" "prfm pldl1keep, [x22, #0x70]\n" - "ldr q19, [x21], #0x10\n" - "zip2 v18.2d, v22.2d, v18.2d\n" "prfm pldl1keep, [x21, #0x70]\n" - "ldr q16, [x20], #0x10\n" - "zip1 v17.2d, v19.2d, v16.2d\n" "prfm pldl1keep, [x20, #0x70]\n" "str q26, [%x[out_ptr], #0x0]\n" - "zip2 v16.2d, v19.2d, v16.2d\n" - "str q23, [%x[out_ptr], #0x10]\n" - "str q20, [%x[out_ptr], #0x20]\n" + "str q22, [%x[out_ptr], #0x10]\n" + "str q19, [%x[out_ptr], #0x20]\n" "str q17, [%x[out_ptr], #0x30]\n" "str q24, [%x[out_ptr], #0x40]\n" "str q21, [%x[out_ptr], #0x50]\n" "str q18, [%x[out_ptr], #0x60]\n" "str q16, [%x[out_ptr], #0x70]\n" - "subs %x[width], %x[width], #0x10\n" - "cmp %x[width], #0x10\n" "add %x[out_ptr], %x[out_ptr], #0x80\n" "bge 2b\n" "3:" // Main loop skip @@ -122,37 +122,37 @@ void interleave_block<8, 8, VLType::None, false>( "ldr d24, [x26], #0x8\n" "ldr d25, [x25], #0x8\n" "ldr d21, [x24], #0x8\n" - "ldr d22, [x23], #0x8\n" + "ldr d23, [x23], #0x8\n" "ldr d18, [x22], #0x8\n" - "ldr d19, [x21], #0x8\n" + "ldr d20, [x21], #0x8\n" "ldr d16, [x20], #0x8\n" "tbz %x[width], #2, 5f\n" "ld1 { v27.s }[2], [x27], #0x4\n" "ld1 { v24.s }[2], [x26], #0x4\n" "ld1 { v25.s }[2], [x25], #0x4\n" "ld1 { v21.s }[2], [x24], #0x4\n" - "ld1 { v22.s }[2], [x23], #0x4\n" + "ld1 { v23.s }[2], [x23], #0x4\n" "ld1 { v18.s }[2], [x22], #0x4\n" - "ld1 { v19.s }[2], [x21], #0x4\n" + "ld1 { v20.s }[2], [x21], #0x4\n" "ld1 { v16.s }[2], [x20], #0x4\n" "tbz %x[width], #1, 4f\n" "ld1 { v27.h }[6], [x27], #0x2\n" + "mov x19, #0x2\n" "ld1 { v24.h }[6], [x26], #0x2\n" "ld1 { v25.h }[6], [x25], #0x2\n" "ld1 { v21.h }[6], [x24], #0x2\n" - "ld1 { v22.h }[6], [x23], #0x2\n" + "ld1 { v23.h }[6], [x23], #0x2\n" "ld1 { v18.h }[6], [x22], #0x2\n" - "ld1 { v19.h }[6], [x21], #0x2\n" + "ld1 { v20.h }[6], [x21], #0x2\n" "ld1 { v16.h }[6], [x20], #0x2\n" - "mov x19, #0x2\n" "tbz %x[width], #0, 11f\n" "ld1 { v27.b }[14], [x27]\n" "ld1 { v24.b }[14], [x26]\n" "ld1 { v25.b }[14], [x25]\n" "ld1 { v21.b }[14], [x24]\n" - "ld1 { v22.b }[14], [x23]\n" + "ld1 { v23.b }[14], [x23]\n" "ld1 { v18.b }[14], [x22]\n" - "ld1 { v19.b }[14], [x21]\n" + "ld1 { v20.b }[14], [x21]\n" "ld1 { v16.b }[14], [x20]\n" "b 11f\n" "4:" // odd_loads_1_12 @@ -162,30 +162,30 @@ void interleave_block<8, 8, VLType::None, false>( "ld1 { v24.b }[12], [x26]\n" "ld1 { v25.b }[12], [x25]\n" "ld1 { v21.b }[12], [x24]\n" - "ld1 { v22.b }[12], [x23]\n" + "ld1 { v23.b }[12], [x23]\n" "ld1 { v18.b }[12], [x22]\n" - "ld1 { v19.b }[12], [x21]\n" + "ld1 { v20.b }[12], [x21]\n" "ld1 { v16.b }[12], [x20]\n" "b 11f\n" "5:" // odd_loads_2_8 "tbz %x[width], #1, 6f\n" "ld1 { v27.h }[4], [x27], #0x2\n" "ld1 { v24.h }[4], [x26], #0x2\n" + "mov x19, #0x2\n" "ld1 { v25.h }[4], [x25], #0x2\n" "ld1 { v21.h }[4], [x24], #0x2\n" - "ld1 { v22.h }[4], [x23], #0x2\n" + "ld1 { v23.h }[4], [x23], #0x2\n" "ld1 { v18.h }[4], [x22], #0x2\n" - "ld1 { v19.h }[4], [x21], #0x2\n" + "ld1 { v20.h }[4], [x21], #0x2\n" "ld1 { v16.h }[4], [x20], #0x2\n" - "mov x19, #0x2\n" "tbz %x[width], #0, 11f\n" "ld1 { v27.b }[10], [x27]\n" "ld1 { v24.b }[10], [x26]\n" "ld1 { v25.b }[10], [x25]\n" "ld1 { v21.b }[10], [x24]\n" - "ld1 { v22.b }[10], [x23]\n" + "ld1 { v23.b }[10], [x23]\n" "ld1 { v18.b }[10], [x22]\n" - "ld1 { v19.b }[10], [x21]\n" + "ld1 { v20.b }[10], [x21]\n" "ld1 { v16.b }[10], [x20]\n" "b 11f\n" "6:" // odd_loads_1_8 @@ -193,13 +193,13 @@ void interleave_block<8, 8, VLType::None, false>( "tbz %x[width], #0, 11f\n" "ld1 { v27.b }[8], [x27]\n" "ld1 { v24.b }[8], [x26]\n" + "mov x19, #0x2\n" "ld1 { v25.b }[8], [x25]\n" "ld1 { v21.b }[8], [x24]\n" - "ld1 { v22.b }[8], [x23]\n" + "ld1 { v23.b }[8], [x23]\n" "ld1 { v18.b }[8], [x22]\n" - "ld1 { v19.b }[8], [x21]\n" + "ld1 { v20.b }[8], [x21]\n" "ld1 { v16.b }[8], [x20]\n" - "mov x19, #0x2\n" "b 11f\n" "7:" // odd_loads_4_0 "tbz %x[width], #2, 9f\n" @@ -207,28 +207,28 @@ void interleave_block<8, 8, VLType::None, false>( "ldr s24, [x26], #0x4\n" "ldr s25, [x25], #0x4\n" "ldr s21, [x24], #0x4\n" - "ldr s22, [x23], #0x4\n" + "ldr s23, [x23], #0x4\n" "ldr s18, [x22], #0x4\n" - "ldr s19, [x21], #0x4\n" + "ldr s20, [x21], #0x4\n" "ldr s16, [x20], #0x4\n" "tbz %x[width], #1, 8f\n" "ld1 { v27.h }[2], [x27], #0x2\n" + "mov x19, #0x1\n" "ld1 { v24.h }[2], [x26], #0x2\n" "ld1 { v25.h }[2], [x25], #0x2\n" "ld1 { v21.h }[2], [x24], #0x2\n" - "ld1 { v22.h }[2], [x23], #0x2\n" + "ld1 { v23.h }[2], [x23], #0x2\n" "ld1 { v18.h }[2], [x22], #0x2\n" - "ld1 { v19.h }[2], [x21], #0x2\n" + "ld1 { v20.h }[2], [x21], #0x2\n" "ld1 { v16.h }[2], [x20], #0x2\n" - "mov x19, #0x1\n" "tbz %x[width], #0, 11f\n" "ld1 { v27.b }[6], [x27]\n" "ld1 { v24.b }[6], [x26]\n" "ld1 { v25.b }[6], [x25]\n" "ld1 { v21.b }[6], [x24]\n" - "ld1 { v22.b }[6], [x23]\n" + "ld1 { v23.b }[6], [x23]\n" "ld1 { v18.b }[6], [x22]\n" - "ld1 { v19.b }[6], [x21]\n" + "ld1 { v20.b }[6], [x21]\n" "ld1 { v16.b }[6], [x20]\n" "b 11f\n" "8:" // odd_loads_1_4 @@ -238,66 +238,66 @@ void interleave_block<8, 8, VLType::None, false>( "ld1 { v24.b }[4], [x26]\n" "ld1 { v25.b }[4], [x25]\n" "ld1 { v21.b }[4], [x24]\n" - "ld1 { v22.b }[4], [x23]\n" + "ld1 { v23.b }[4], [x23]\n" "ld1 { v18.b }[4], [x22]\n" - "ld1 { v19.b }[4], [x21]\n" + "ld1 { v20.b }[4], [x21]\n" "ld1 { v16.b }[4], [x20]\n" "b 11f\n" "9:" // odd_loads_2_0 "tbz %x[width], #1, 10f\n" "ldr h27, [x27], #0x2\n" "ldr h24, [x26], #0x2\n" + "mov x19, #0x1\n" "ldr h25, [x25], #0x2\n" "ldr h21, [x24], #0x2\n" - "ldr h22, [x23], #0x2\n" + "ldr h23, [x23], #0x2\n" "ldr h18, [x22], #0x2\n" - "ldr h19, [x21], #0x2\n" + "ldr h20, [x21], #0x2\n" "ldr h16, [x20], #0x2\n" - "mov x19, #0x1\n" "tbz %x[width], #0, 11f\n" "ld1 { v27.b }[2], [x27]\n" "ld1 { v24.b }[2], [x26]\n" "ld1 { v25.b }[2], [x25]\n" "ld1 { v21.b }[2], [x24]\n" - "ld1 { v22.b }[2], [x23]\n" + "ld1 { v23.b }[2], [x23]\n" "ld1 { v18.b }[2], [x22]\n" - "ld1 { v19.b }[2], [x21]\n" + "ld1 { v20.b }[2], [x21]\n" "ld1 { v16.b }[2], [x20]\n" "b 11f\n" "10:" // odd_loads_1_0 "ldr b27, [x27, #0x0]\n" + "mov x19, #0x1\n" "ldr b24, [x26, #0x0]\n" "ldr b25, [x25, #0x0]\n" "ldr b21, [x24, #0x0]\n" - "ldr b22, [x23, #0x0]\n" + "ldr b23, [x23, #0x0]\n" "ldr b18, [x22, #0x0]\n" - "ldr b19, [x21, #0x0]\n" + "ldr b20, [x21, #0x0]\n" "ldr b16, [x20, #0x0]\n" - "mov x19, #0x1\n" "11:" // Odd load end "zip1 v26.2d, v27.2d, v24.2d\n" - "subs x19, x19, #0x1\n" - "zip1 v23.2d, v25.2d, v21.2d\n" "str q26, [%x[out_ptr], #0x0]\n" - "zip1 v20.2d, v22.2d, v18.2d\n" - "str q23, [%x[out_ptr], #0x10]\n" - "zip1 v17.2d, v19.2d, v16.2d\n" - "str q20, [%x[out_ptr], #0x20]\n" + "zip1 v22.2d, v25.2d, v21.2d\n" + "subs x19, x19, #0x1\n" + "zip1 v19.2d, v23.2d, v18.2d\n" + "str q22, [%x[out_ptr], #0x10]\n" + "zip1 v17.2d, v20.2d, v16.2d\n" + "str q19, [%x[out_ptr], #0x20]\n" "str q17, [%x[out_ptr], #0x30]\n" "add %x[out_ptr], %x[out_ptr], #0x40\n" "beq 12f\n" "zip2 v24.2d, v27.2d, v24.2d\n" - "zip2 v21.2d, v25.2d, v21.2d\n" "str q24, [%x[out_ptr], #0x0]\n" - "zip2 v18.2d, v22.2d, v18.2d\n" + "zip2 v21.2d, v25.2d, v21.2d\n" + "zip2 v18.2d, v23.2d, v18.2d\n" "str q21, [%x[out_ptr], #0x10]\n" - "zip2 v16.2d, v19.2d, v16.2d\n" + "zip2 v16.2d, v20.2d, v16.2d\n" "str q18, [%x[out_ptr], #0x20]\n" "str q16, [%x[out_ptr], #0x30]\n" "add %x[out_ptr], %x[out_ptr], #0x40\n" "12:" // Odds skip - : [out_ptr] "+r" (out_ptr), [width] "+r" (width) + : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block8_s8_s8_summing.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block8_s8_s8_summing.hpp index 2317ece790..3550830fc3 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block8_s8_s8_summing.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block8_s8_s8_summing.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020 Arm Limited. + * Copyright (c) 2019-2021 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -108,48 +108,48 @@ void interleave_block<8, 8, VLType::None, true>( "mov x19, #0x0\n" "4:" // no_accumulate_16 "ldr q27, [x27], #0x10\n" - "prfm pldl1keep, [x27, #0x70]\n" + "add x19, x19, #0x1\n" "ldr q24, [x26], #0x10\n" "zip1 v26.2d, v27.2d, v24.2d\n" - "prfm pldl1keep, [x26, #0x70]\n" "ldr q25, [x25], #0x10\n" + "subs %x[width], %x[width], #0x10\n" "zip2 v24.2d, v27.2d, v24.2d\n" - "prfm pldl1keep, [x25, #0x70]\n" "ldr q21, [x24], #0x10\n" + "sadalp v5.8h, v26.16b\n" "zip1 v23.2d, v25.2d, v21.2d\n" - "prfm pldl1keep, [x24, #0x70]\n" "ldr q22, [x23], #0x10\n" + "cmp %x[width], #0x10\n" "zip2 v21.2d, v25.2d, v21.2d\n" - "prfm pldl1keep, [x23, #0x70]\n" "ldr q18, [x22], #0x10\n" + "sadalp v4.8h, v23.16b\n" "zip1 v20.2d, v22.2d, v18.2d\n" - "prfm pldl1keep, [x22, #0x70]\n" "ldr q19, [x21], #0x10\n" + "sadalp v5.8h, v24.16b\n" "zip2 v18.2d, v22.2d, v18.2d\n" - "prfm pldl1keep, [x21, #0x70]\n" "ldr q16, [x20], #0x10\n" + "sadalp v3.8h, v20.16b\n" "zip1 v17.2d, v19.2d, v16.2d\n" + "prfm pldl1keep, [x27, #0x70]\n" + "sadalp v4.8h, v21.16b\n" + "zip2 v16.2d, v19.2d, v16.2d\n" + "prfm pldl1keep, [x26, #0x70]\n" + "sadalp v2.8h, v17.16b\n" + "prfm pldl1keep, [x25, #0x70]\n" + "sadalp v3.8h, v18.16b\n" + "prfm pldl1keep, [x24, #0x70]\n" + "sadalp v2.8h, v16.16b\n" + "prfm pldl1keep, [x23, #0x70]\n" + "prfm pldl1keep, [x22, #0x70]\n" + "prfm pldl1keep, [x21, #0x70]\n" "prfm pldl1keep, [x20, #0x70]\n" "str q26, [%x[out_ptr], #0x0]\n" - "zip2 v16.2d, v19.2d, v16.2d\n" - "sadalp v5.8h, v26.16b\n" "str q23, [%x[out_ptr], #0x10]\n" - "sadalp v4.8h, v23.16b\n" "str q20, [%x[out_ptr], #0x20]\n" - "sadalp v3.8h, v20.16b\n" "str q17, [%x[out_ptr], #0x30]\n" - "sadalp v2.8h, v17.16b\n" "str q24, [%x[out_ptr], #0x40]\n" - "sadalp v5.8h, v24.16b\n" "str q21, [%x[out_ptr], #0x50]\n" - "sadalp v4.8h, v21.16b\n" "str q18, [%x[out_ptr], #0x60]\n" - "sadalp v3.8h, v18.16b\n" "str q16, [%x[out_ptr], #0x70]\n" - "sadalp v2.8h, v16.16b\n" - "add x19, x19, #0x1\n" - "subs %x[width], %x[width], #0x10\n" - "cmp %x[width], #0x10\n" "add %x[out_ptr], %x[out_ptr], #0x80\n" "bge 3b\n" "5:" // Main loop skip @@ -174,6 +174,7 @@ void interleave_block<8, 8, VLType::None, true>( "ld1 { v16.s }[2], [x20], #0x4\n" "tbz %x[width], #1, 6f\n" "ld1 { v27.h }[6], [x27], #0x2\n" + "mov x19, #0x2\n" "ld1 { v24.h }[6], [x26], #0x2\n" "ld1 { v25.h }[6], [x25], #0x2\n" "ld1 { v21.h }[6], [x24], #0x2\n" @@ -181,7 +182,6 @@ void interleave_block<8, 8, VLType::None, true>( "ld1 { v18.h }[6], [x22], #0x2\n" "ld1 { v19.h }[6], [x21], #0x2\n" "ld1 { v16.h }[6], [x20], #0x2\n" - "mov x19, #0x2\n" "tbz %x[width], #0, 13f\n" "ld1 { v27.b }[14], [x27]\n" "ld1 { v24.b }[14], [x26]\n" @@ -208,13 +208,13 @@ void interleave_block<8, 8, VLType::None, true>( "tbz %x[width], #1, 8f\n" "ld1 { v27.h }[4], [x27], #0x2\n" "ld1 { v24.h }[4], [x26], #0x2\n" + "mov x19, #0x2\n" "ld1 { v25.h }[4], [x25], #0x2\n" "ld1 { v21.h }[4], [x24], #0x2\n" "ld1 { v22.h }[4], [x23], #0x2\n" "ld1 { v18.h }[4], [x22], #0x2\n" "ld1 { v19.h }[4], [x21], #0x2\n" "ld1 { v16.h }[4], [x20], #0x2\n" - "mov x19, #0x2\n" "tbz %x[width], #0, 13f\n" "ld1 { v27.b }[10], [x27]\n" "ld1 { v24.b }[10], [x26]\n" @@ -230,13 +230,13 @@ void interleave_block<8, 8, VLType::None, true>( "tbz %x[width], #0, 13f\n" "ld1 { v27.b }[8], [x27]\n" "ld1 { v24.b }[8], [x26]\n" + "mov x19, #0x2\n" "ld1 { v25.b }[8], [x25]\n" "ld1 { v21.b }[8], [x24]\n" "ld1 { v22.b }[8], [x23]\n" "ld1 { v18.b }[8], [x22]\n" "ld1 { v19.b }[8], [x21]\n" "ld1 { v16.b }[8], [x20]\n" - "mov x19, #0x2\n" "b 13f\n" "9:" // odd_loads_4_0 "tbz %x[width], #2, 11f\n" @@ -250,6 +250,7 @@ void interleave_block<8, 8, VLType::None, true>( "ldr s16, [x20], #0x4\n" "tbz %x[width], #1, 10f\n" "ld1 { v27.h }[2], [x27], #0x2\n" + "mov x19, #0x1\n" "ld1 { v24.h }[2], [x26], #0x2\n" "ld1 { v25.h }[2], [x25], #0x2\n" "ld1 { v21.h }[2], [x24], #0x2\n" @@ -257,7 +258,6 @@ void interleave_block<8, 8, VLType::None, true>( "ld1 { v18.h }[2], [x22], #0x2\n" "ld1 { v19.h }[2], [x21], #0x2\n" "ld1 { v16.h }[2], [x20], #0x2\n" - "mov x19, #0x1\n" "tbz %x[width], #0, 13f\n" "ld1 { v27.b }[6], [x27]\n" "ld1 { v24.b }[6], [x26]\n" @@ -284,13 +284,13 @@ void interleave_block<8, 8, VLType::None, true>( "tbz %x[width], #1, 12f\n" "ldr h27, [x27], #0x2\n" "ldr h24, [x26], #0x2\n" + "mov x19, #0x1\n" "ldr h25, [x25], #0x2\n" "ldr h21, [x24], #0x2\n" "ldr h22, [x23], #0x2\n" "ldr h18, [x22], #0x2\n" "ldr h19, [x21], #0x2\n" "ldr h16, [x20], #0x2\n" - "mov x19, #0x1\n" "tbz %x[width], #0, 13f\n" "ld1 { v27.b }[2], [x27]\n" "ld1 { v24.b }[2], [x26]\n" @@ -303,6 +303,7 @@ void interleave_block<8, 8, VLType::None, true>( "b 13f\n" "12:" // odd_loads_1_0 "ldr b27, [x27, #0x0]\n" + "mov x19, #0x1\n" "ldr b24, [x26, #0x0]\n" "ldr b25, [x25, #0x0]\n" "ldr b21, [x24, #0x0]\n" @@ -310,31 +311,30 @@ void interleave_block<8, 8, VLType::None, true>( "ldr b18, [x22, #0x0]\n" "ldr b19, [x21, #0x0]\n" "ldr b16, [x20, #0x0]\n" - "mov x19, #0x1\n" "13:" // Odd load end "zip1 v26.2d, v27.2d, v24.2d\n" - "subs x19, x19, #0x1\n" - "zip1 v23.2d, v25.2d, v21.2d\n" "str q26, [%x[out_ptr], #0x0]\n" - "zip1 v20.2d, v22.2d, v18.2d\n" + "zip1 v23.2d, v25.2d, v21.2d\n" "sadalp v5.8h, v26.16b\n" - "zip1 v17.2d, v19.2d, v16.2d\n" + "zip1 v20.2d, v22.2d, v18.2d\n" "str q23, [%x[out_ptr], #0x10]\n" "sadalp v4.8h, v23.16b\n" + "zip1 v17.2d, v19.2d, v16.2d\n" "str q20, [%x[out_ptr], #0x20]\n" "sadalp v3.8h, v20.16b\n" "str q17, [%x[out_ptr], #0x30]\n" "sadalp v2.8h, v17.16b\n" + "subs x19, x19, #0x1\n" "add %x[out_ptr], %x[out_ptr], #0x40\n" "beq 14f\n" "zip2 v24.2d, v27.2d, v24.2d\n" - "zip2 v21.2d, v25.2d, v21.2d\n" "str q24, [%x[out_ptr], #0x0]\n" - "zip2 v18.2d, v22.2d, v18.2d\n" + "zip2 v21.2d, v25.2d, v21.2d\n" "sadalp v5.8h, v24.16b\n" - "zip2 v16.2d, v19.2d, v16.2d\n" + "zip2 v18.2d, v22.2d, v18.2d\n" "str q21, [%x[out_ptr], #0x10]\n" "sadalp v4.8h, v21.16b\n" + "zip2 v16.2d, v19.2d, v16.2d\n" "str q18, [%x[out_ptr], #0x20]\n" "sadalp v3.8h, v18.16b\n" "str q16, [%x[out_ptr], #0x30]\n" @@ -352,7 +352,7 @@ void interleave_block<8, 8, VLType::None, true>( "add v0.4s, v0.4s, v28.4s\n" "str q0, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" - : [out_ptr] "+r" (out_ptr), [width] "+r" (width) + : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [first] "r" (first), [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block8_u8_u8_summing.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block8_u8_u8_summing.hpp index 07164d6b24..454260ef1a 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block8_u8_u8_summing.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block8_u8_u8_summing.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020 Arm Limited. + * Copyright (c) 2019-2021 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -108,48 +108,48 @@ void interleave_block<8, 8, VLType::None, true>( "mov x19, #0x0\n" "4:" // no_accumulate_16 "ldr q27, [x27], #0x10\n" - "prfm pldl1keep, [x27, #0x70]\n" + "add x19, x19, #0x1\n" "ldr q24, [x26], #0x10\n" "zip1 v26.2d, v27.2d, v24.2d\n" - "prfm pldl1keep, [x26, #0x70]\n" "ldr q25, [x25], #0x10\n" + "subs %x[width], %x[width], #0x10\n" "zip2 v24.2d, v27.2d, v24.2d\n" - "prfm pldl1keep, [x25, #0x70]\n" "ldr q21, [x24], #0x10\n" + "uadalp v5.8h, v26.16b\n" "zip1 v23.2d, v25.2d, v21.2d\n" - "prfm pldl1keep, [x24, #0x70]\n" "ldr q22, [x23], #0x10\n" + "cmp %x[width], #0x10\n" "zip2 v21.2d, v25.2d, v21.2d\n" - "prfm pldl1keep, [x23, #0x70]\n" "ldr q18, [x22], #0x10\n" + "uadalp v4.8h, v23.16b\n" "zip1 v20.2d, v22.2d, v18.2d\n" - "prfm pldl1keep, [x22, #0x70]\n" "ldr q19, [x21], #0x10\n" + "uadalp v5.8h, v24.16b\n" "zip2 v18.2d, v22.2d, v18.2d\n" - "prfm pldl1keep, [x21, #0x70]\n" "ldr q16, [x20], #0x10\n" + "uadalp v3.8h, v20.16b\n" "zip1 v17.2d, v19.2d, v16.2d\n" + "prfm pldl1keep, [x27, #0x70]\n" + "uadalp v4.8h, v21.16b\n" + "zip2 v16.2d, v19.2d, v16.2d\n" + "prfm pldl1keep, [x26, #0x70]\n" + "uadalp v2.8h, v17.16b\n" + "prfm pldl1keep, [x25, #0x70]\n" + "uadalp v3.8h, v18.16b\n" + "prfm pldl1keep, [x24, #0x70]\n" + "uadalp v2.8h, v16.16b\n" + "prfm pldl1keep, [x23, #0x70]\n" + "prfm pldl1keep, [x22, #0x70]\n" + "prfm pldl1keep, [x21, #0x70]\n" "prfm pldl1keep, [x20, #0x70]\n" "str q26, [%x[out_ptr], #0x0]\n" - "zip2 v16.2d, v19.2d, v16.2d\n" - "uadalp v5.8h, v26.16b\n" "str q23, [%x[out_ptr], #0x10]\n" - "uadalp v4.8h, v23.16b\n" "str q20, [%x[out_ptr], #0x20]\n" - "uadalp v3.8h, v20.16b\n" "str q17, [%x[out_ptr], #0x30]\n" - "uadalp v2.8h, v17.16b\n" "str q24, [%x[out_ptr], #0x40]\n" - "uadalp v5.8h, v24.16b\n" "str q21, [%x[out_ptr], #0x50]\n" - "uadalp v4.8h, v21.16b\n" "str q18, [%x[out_ptr], #0x60]\n" - "uadalp v3.8h, v18.16b\n" "str q16, [%x[out_ptr], #0x70]\n" - "uadalp v2.8h, v16.16b\n" - "add x19, x19, #0x1\n" - "subs %x[width], %x[width], #0x10\n" - "cmp %x[width], #0x10\n" "add %x[out_ptr], %x[out_ptr], #0x80\n" "bge 3b\n" "5:" // Main loop skip @@ -174,6 +174,7 @@ void interleave_block<8, 8, VLType::None, true>( "ld1 { v16.s }[2], [x20], #0x4\n" "tbz %x[width], #1, 6f\n" "ld1 { v27.h }[6], [x27], #0x2\n" + "mov x19, #0x2\n" "ld1 { v24.h }[6], [x26], #0x2\n" "ld1 { v25.h }[6], [x25], #0x2\n" "ld1 { v21.h }[6], [x24], #0x2\n" @@ -181,7 +182,6 @@ void interleave_block<8, 8, VLType::None, true>( "ld1 { v18.h }[6], [x22], #0x2\n" "ld1 { v19.h }[6], [x21], #0x2\n" "ld1 { v16.h }[6], [x20], #0x2\n" - "mov x19, #0x2\n" "tbz %x[width], #0, 13f\n" "ld1 { v27.b }[14], [x27]\n" "ld1 { v24.b }[14], [x26]\n" @@ -208,13 +208,13 @@ void interleave_block<8, 8, VLType::None, true>( "tbz %x[width], #1, 8f\n" "ld1 { v27.h }[4], [x27], #0x2\n" "ld1 { v24.h }[4], [x26], #0x2\n" + "mov x19, #0x2\n" "ld1 { v25.h }[4], [x25], #0x2\n" "ld1 { v21.h }[4], [x24], #0x2\n" "ld1 { v22.h }[4], [x23], #0x2\n" "ld1 { v18.h }[4], [x22], #0x2\n" "ld1 { v19.h }[4], [x21], #0x2\n" "ld1 { v16.h }[4], [x20], #0x2\n" - "mov x19, #0x2\n" "tbz %x[width], #0, 13f\n" "ld1 { v27.b }[10], [x27]\n" "ld1 { v24.b }[10], [x26]\n" @@ -230,13 +230,13 @@ void interleave_block<8, 8, VLType::None, true>( "tbz %x[width], #0, 13f\n" "ld1 { v27.b }[8], [x27]\n" "ld1 { v24.b }[8], [x26]\n" + "mov x19, #0x2\n" "ld1 { v25.b }[8], [x25]\n" "ld1 { v21.b }[8], [x24]\n" "ld1 { v22.b }[8], [x23]\n" "ld1 { v18.b }[8], [x22]\n" "ld1 { v19.b }[8], [x21]\n" "ld1 { v16.b }[8], [x20]\n" - "mov x19, #0x2\n" "b 13f\n" "9:" // odd_loads_4_0 "tbz %x[width], #2, 11f\n" @@ -250,6 +250,7 @@ void interleave_block<8, 8, VLType::None, true>( "ldr s16, [x20], #0x4\n" "tbz %x[width], #1, 10f\n" "ld1 { v27.h }[2], [x27], #0x2\n" + "mov x19, #0x1\n" "ld1 { v24.h }[2], [x26], #0x2\n" "ld1 { v25.h }[2], [x25], #0x2\n" "ld1 { v21.h }[2], [x24], #0x2\n" @@ -257,7 +258,6 @@ void interleave_block<8, 8, VLType::None, true>( "ld1 { v18.h }[2], [x22], #0x2\n" "ld1 { v19.h }[2], [x21], #0x2\n" "ld1 { v16.h }[2], [x20], #0x2\n" - "mov x19, #0x1\n" "tbz %x[width], #0, 13f\n" "ld1 { v27.b }[6], [x27]\n" "ld1 { v24.b }[6], [x26]\n" @@ -284,13 +284,13 @@ void interleave_block<8, 8, VLType::None, true>( "tbz %x[width], #1, 12f\n" "ldr h27, [x27], #0x2\n" "ldr h24, [x26], #0x2\n" + "mov x19, #0x1\n" "ldr h25, [x25], #0x2\n" "ldr h21, [x24], #0x2\n" "ldr h22, [x23], #0x2\n" "ldr h18, [x22], #0x2\n" "ldr h19, [x21], #0x2\n" "ldr h16, [x20], #0x2\n" - "mov x19, #0x1\n" "tbz %x[width], #0, 13f\n" "ld1 { v27.b }[2], [x27]\n" "ld1 { v24.b }[2], [x26]\n" @@ -303,6 +303,7 @@ void interleave_block<8, 8, VLType::None, true>( "b 13f\n" "12:" // odd_loads_1_0 "ldr b27, [x27, #0x0]\n" + "mov x19, #0x1\n" "ldr b24, [x26, #0x0]\n" "ldr b25, [x25, #0x0]\n" "ldr b21, [x24, #0x0]\n" @@ -310,31 +311,30 @@ void interleave_block<8, 8, VLType::None, true>( "ldr b18, [x22, #0x0]\n" "ldr b19, [x21, #0x0]\n" "ldr b16, [x20, #0x0]\n" - "mov x19, #0x1\n" "13:" // Odd load end "zip1 v26.2d, v27.2d, v24.2d\n" - "subs x19, x19, #0x1\n" - "zip1 v23.2d, v25.2d, v21.2d\n" "str q26, [%x[out_ptr], #0x0]\n" - "zip1 v20.2d, v22.2d, v18.2d\n" + "zip1 v23.2d, v25.2d, v21.2d\n" "uadalp v5.8h, v26.16b\n" - "zip1 v17.2d, v19.2d, v16.2d\n" + "zip1 v20.2d, v22.2d, v18.2d\n" "str q23, [%x[out_ptr], #0x10]\n" "uadalp v4.8h, v23.16b\n" + "zip1 v17.2d, v19.2d, v16.2d\n" "str q20, [%x[out_ptr], #0x20]\n" "uadalp v3.8h, v20.16b\n" "str q17, [%x[out_ptr], #0x30]\n" "uadalp v2.8h, v17.16b\n" + "subs x19, x19, #0x1\n" "add %x[out_ptr], %x[out_ptr], #0x40\n" "beq 14f\n" "zip2 v24.2d, v27.2d, v24.2d\n" - "zip2 v21.2d, v25.2d, v21.2d\n" "str q24, [%x[out_ptr], #0x0]\n" - "zip2 v18.2d, v22.2d, v18.2d\n" + "zip2 v21.2d, v25.2d, v21.2d\n" "uadalp v5.8h, v24.16b\n" - "zip2 v16.2d, v19.2d, v16.2d\n" + "zip2 v18.2d, v22.2d, v18.2d\n" "str q21, [%x[out_ptr], #0x10]\n" "uadalp v4.8h, v21.16b\n" + "zip2 v16.2d, v19.2d, v16.2d\n" "str q18, [%x[out_ptr], #0x20]\n" "uadalp v3.8h, v18.16b\n" "str q16, [%x[out_ptr], #0x30]\n" @@ -352,7 +352,7 @@ void interleave_block<8, 8, VLType::None, true>( "add v0.4s, v0.4s, v28.4s\n" "str q0, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" - : [out_ptr] "+r" (out_ptr), [width] "+r" (width) + : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [first] "r" (first), [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); |