diff options
Diffstat (limited to 'src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block8_u8_u8_summing.hpp')
| -rw-r--r-- | src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block8_u8_u8_summing.hpp | 68 |
1 files changed, 34 insertions, 34 deletions
diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block8_u8_u8_summing.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block8_u8_u8_summing.hpp index 07164d6b24..454260ef1a 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block8_u8_u8_summing.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block8_u8_u8_summing.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020 Arm Limited. + * Copyright (c) 2019-2021 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -108,48 +108,48 @@ void interleave_block<8, 8, VLType::None, true>( "mov x19, #0x0\n" "4:" // no_accumulate_16 "ldr q27, [x27], #0x10\n" - "prfm pldl1keep, [x27, #0x70]\n" + "add x19, x19, #0x1\n" "ldr q24, [x26], #0x10\n" "zip1 v26.2d, v27.2d, v24.2d\n" - "prfm pldl1keep, [x26, #0x70]\n" "ldr q25, [x25], #0x10\n" + "subs %x[width], %x[width], #0x10\n" "zip2 v24.2d, v27.2d, v24.2d\n" - "prfm pldl1keep, [x25, #0x70]\n" "ldr q21, [x24], #0x10\n" + "uadalp v5.8h, v26.16b\n" "zip1 v23.2d, v25.2d, v21.2d\n" - "prfm pldl1keep, [x24, #0x70]\n" "ldr q22, [x23], #0x10\n" + "cmp %x[width], #0x10\n" "zip2 v21.2d, v25.2d, v21.2d\n" - "prfm pldl1keep, [x23, #0x70]\n" "ldr q18, [x22], #0x10\n" + "uadalp v4.8h, v23.16b\n" "zip1 v20.2d, v22.2d, v18.2d\n" - "prfm pldl1keep, [x22, #0x70]\n" "ldr q19, [x21], #0x10\n" + "uadalp v5.8h, v24.16b\n" "zip2 v18.2d, v22.2d, v18.2d\n" - "prfm pldl1keep, [x21, #0x70]\n" "ldr q16, [x20], #0x10\n" + "uadalp v3.8h, v20.16b\n" "zip1 v17.2d, v19.2d, v16.2d\n" + "prfm pldl1keep, [x27, #0x70]\n" + "uadalp v4.8h, v21.16b\n" + "zip2 v16.2d, v19.2d, v16.2d\n" + "prfm pldl1keep, [x26, #0x70]\n" + "uadalp v2.8h, v17.16b\n" + "prfm pldl1keep, [x25, #0x70]\n" + "uadalp v3.8h, v18.16b\n" + "prfm pldl1keep, [x24, #0x70]\n" + "uadalp v2.8h, v16.16b\n" + "prfm pldl1keep, [x23, #0x70]\n" + "prfm pldl1keep, [x22, #0x70]\n" + "prfm pldl1keep, [x21, #0x70]\n" "prfm pldl1keep, [x20, #0x70]\n" "str q26, [%x[out_ptr], #0x0]\n" - "zip2 v16.2d, v19.2d, v16.2d\n" - "uadalp v5.8h, v26.16b\n" "str q23, [%x[out_ptr], #0x10]\n" - "uadalp v4.8h, v23.16b\n" "str q20, [%x[out_ptr], #0x20]\n" - "uadalp v3.8h, v20.16b\n" "str q17, [%x[out_ptr], #0x30]\n" - "uadalp v2.8h, v17.16b\n" "str q24, [%x[out_ptr], #0x40]\n" - "uadalp v5.8h, v24.16b\n" "str q21, [%x[out_ptr], #0x50]\n" - "uadalp v4.8h, v21.16b\n" "str q18, [%x[out_ptr], #0x60]\n" - "uadalp v3.8h, v18.16b\n" "str q16, [%x[out_ptr], #0x70]\n" - "uadalp v2.8h, v16.16b\n" - "add x19, x19, #0x1\n" - "subs %x[width], %x[width], #0x10\n" - "cmp %x[width], #0x10\n" "add %x[out_ptr], %x[out_ptr], #0x80\n" "bge 3b\n" "5:" // Main loop skip @@ -174,6 +174,7 @@ void interleave_block<8, 8, VLType::None, true>( "ld1 { v16.s }[2], [x20], #0x4\n" "tbz %x[width], #1, 6f\n" "ld1 { v27.h }[6], [x27], #0x2\n" + "mov x19, #0x2\n" "ld1 { v24.h }[6], [x26], #0x2\n" "ld1 { v25.h }[6], [x25], #0x2\n" "ld1 { v21.h }[6], [x24], #0x2\n" @@ -181,7 +182,6 @@ void interleave_block<8, 8, VLType::None, true>( "ld1 { v18.h }[6], [x22], #0x2\n" "ld1 { v19.h }[6], [x21], #0x2\n" "ld1 { v16.h }[6], [x20], #0x2\n" - "mov x19, #0x2\n" "tbz %x[width], #0, 13f\n" "ld1 { v27.b }[14], [x27]\n" "ld1 { v24.b }[14], [x26]\n" @@ -208,13 +208,13 @@ void interleave_block<8, 8, VLType::None, true>( "tbz %x[width], #1, 8f\n" "ld1 { v27.h }[4], [x27], #0x2\n" "ld1 { v24.h }[4], [x26], #0x2\n" + "mov x19, #0x2\n" "ld1 { v25.h }[4], [x25], #0x2\n" "ld1 { v21.h }[4], [x24], #0x2\n" "ld1 { v22.h }[4], [x23], #0x2\n" "ld1 { v18.h }[4], [x22], #0x2\n" "ld1 { v19.h }[4], [x21], #0x2\n" "ld1 { v16.h }[4], [x20], #0x2\n" - "mov x19, #0x2\n" "tbz %x[width], #0, 13f\n" "ld1 { v27.b }[10], [x27]\n" "ld1 { v24.b }[10], [x26]\n" @@ -230,13 +230,13 @@ void interleave_block<8, 8, VLType::None, true>( "tbz %x[width], #0, 13f\n" "ld1 { v27.b }[8], [x27]\n" "ld1 { v24.b }[8], [x26]\n" + "mov x19, #0x2\n" "ld1 { v25.b }[8], [x25]\n" "ld1 { v21.b }[8], [x24]\n" "ld1 { v22.b }[8], [x23]\n" "ld1 { v18.b }[8], [x22]\n" "ld1 { v19.b }[8], [x21]\n" "ld1 { v16.b }[8], [x20]\n" - "mov x19, #0x2\n" "b 13f\n" "9:" // odd_loads_4_0 "tbz %x[width], #2, 11f\n" @@ -250,6 +250,7 @@ void interleave_block<8, 8, VLType::None, true>( "ldr s16, [x20], #0x4\n" "tbz %x[width], #1, 10f\n" "ld1 { v27.h }[2], [x27], #0x2\n" + "mov x19, #0x1\n" "ld1 { v24.h }[2], [x26], #0x2\n" "ld1 { v25.h }[2], [x25], #0x2\n" "ld1 { v21.h }[2], [x24], #0x2\n" @@ -257,7 +258,6 @@ void interleave_block<8, 8, VLType::None, true>( "ld1 { v18.h }[2], [x22], #0x2\n" "ld1 { v19.h }[2], [x21], #0x2\n" "ld1 { v16.h }[2], [x20], #0x2\n" - "mov x19, #0x1\n" "tbz %x[width], #0, 13f\n" "ld1 { v27.b }[6], [x27]\n" "ld1 { v24.b }[6], [x26]\n" @@ -284,13 +284,13 @@ void interleave_block<8, 8, VLType::None, true>( "tbz %x[width], #1, 12f\n" "ldr h27, [x27], #0x2\n" "ldr h24, [x26], #0x2\n" + "mov x19, #0x1\n" "ldr h25, [x25], #0x2\n" "ldr h21, [x24], #0x2\n" "ldr h22, [x23], #0x2\n" "ldr h18, [x22], #0x2\n" "ldr h19, [x21], #0x2\n" "ldr h16, [x20], #0x2\n" - "mov x19, #0x1\n" "tbz %x[width], #0, 13f\n" "ld1 { v27.b }[2], [x27]\n" "ld1 { v24.b }[2], [x26]\n" @@ -303,6 +303,7 @@ void interleave_block<8, 8, VLType::None, true>( "b 13f\n" "12:" // odd_loads_1_0 "ldr b27, [x27, #0x0]\n" + "mov x19, #0x1\n" "ldr b24, [x26, #0x0]\n" "ldr b25, [x25, #0x0]\n" "ldr b21, [x24, #0x0]\n" @@ -310,31 +311,30 @@ void interleave_block<8, 8, VLType::None, true>( "ldr b18, [x22, #0x0]\n" "ldr b19, [x21, #0x0]\n" "ldr b16, [x20, #0x0]\n" - "mov x19, #0x1\n" "13:" // Odd load end "zip1 v26.2d, v27.2d, v24.2d\n" - "subs x19, x19, #0x1\n" - "zip1 v23.2d, v25.2d, v21.2d\n" "str q26, [%x[out_ptr], #0x0]\n" - "zip1 v20.2d, v22.2d, v18.2d\n" + "zip1 v23.2d, v25.2d, v21.2d\n" "uadalp v5.8h, v26.16b\n" - "zip1 v17.2d, v19.2d, v16.2d\n" + "zip1 v20.2d, v22.2d, v18.2d\n" "str q23, [%x[out_ptr], #0x10]\n" "uadalp v4.8h, v23.16b\n" + "zip1 v17.2d, v19.2d, v16.2d\n" "str q20, [%x[out_ptr], #0x20]\n" "uadalp v3.8h, v20.16b\n" "str q17, [%x[out_ptr], #0x30]\n" "uadalp v2.8h, v17.16b\n" + "subs x19, x19, #0x1\n" "add %x[out_ptr], %x[out_ptr], #0x40\n" "beq 14f\n" "zip2 v24.2d, v27.2d, v24.2d\n" - "zip2 v21.2d, v25.2d, v21.2d\n" "str q24, [%x[out_ptr], #0x0]\n" - "zip2 v18.2d, v22.2d, v18.2d\n" + "zip2 v21.2d, v25.2d, v21.2d\n" "uadalp v5.8h, v24.16b\n" - "zip2 v16.2d, v19.2d, v16.2d\n" + "zip2 v18.2d, v22.2d, v18.2d\n" "str q21, [%x[out_ptr], #0x10]\n" "uadalp v4.8h, v21.16b\n" + "zip2 v16.2d, v19.2d, v16.2d\n" "str q18, [%x[out_ptr], #0x20]\n" "uadalp v3.8h, v18.16b\n" "str q16, [%x[out_ptr], #0x30]\n" @@ -352,7 +352,7 @@ void interleave_block<8, 8, VLType::None, true>( "add v0.4s, v0.4s, v28.4s\n" "str q0, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" - : [out_ptr] "+r" (out_ptr), [width] "+r" (width) + : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [first] "r" (first), [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); |