diff options
Diffstat (limited to 'src/core/NEON/kernels/arm_conv/pooling/kernels')
79 files changed, 4679 insertions, 4551 deletions
diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp index a670bb81bb..6b3ebe6664 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -24,7 +24,7 @@ #pragma once -#if defined(__ARM_FP16_ARGS) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +#if defined(__aarch64__) && defined(__ARM_FP16_ARGS) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) namespace arm_conv { namespace pooling { @@ -48,4 +48,4 @@ struct a64_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst : public DepthfirstStrategy } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FP16_ARGS) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +#endif // defined(__aarch64__) && defined(__ARM_FP16_ARGS) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp index 647103d3a4..5df848d1dd 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp @@ -196,38 +196,38 @@ void a64_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst_impl( "add x5, x5, #0x10\n" "cbz x3, 4f\n" "3:" // Oddments - "ldr h6, [x11, x4]\n" - "ldr h5, [x10, x4]\n" - "fadd v17.8h, v6.8h, v5.8h\n" + "ldr h17, [x11, x4]\n" + "ldr h16, [x10, x4]\n" + "fadd v18.8h, v17.8h, v16.8h\n" "subs x3, x3, #0x1\n" - "ldr h4, [x27, x4]\n" - "ldr h3, [x26, x4]\n" - "fadd v16.8h, v4.8h, v3.8h\n" - "fadd v19.8h, v17.8h, v16.8h\n" - "ldr h2, [x15, x4]\n" - "ldr h1, [x14, x4]\n" - "fadd v18.8h, v2.8h, v1.8h\n" - "fadd v21.8h, v18.8h, v19.8h\n" - "ldr h0, [x12, x4]\n" - "ldr h31, [x28, x4]\n" - "fadd v17.8h, v0.8h, v31.8h\n" - "ldr h30, [x9, x4]\n" - "ldr h29, [x25, x4]\n" - "fadd v22.8h, v30.8h, v29.8h\n" - "ldr h28, [x23, x4]\n" - "ldr h27, [x22, x4]\n" - "fadd v16.8h, v28.8h, v27.8h\n" - "fadd v20.8h, v16.8h, v19.8h\n" - "ldr h26, [x16, x4]\n" - "ldr h25, [x13, x4]\n" - "fadd v19.8h, v26.8h, v17.8h\n" - "fadd v18.8h, v25.8h, v22.8h\n" - "ldr h24, [x24, x4]\n" - "ldr h23, [x21, x4]\n" - "fadd v17.8h, v24.8h, v17.8h\n" - "fadd v16.8h, v23.8h, v22.8h\n" - "fadd v19.8h, v21.8h, v19.8h\n" - "fadd v18.8h, v21.8h, v18.8h\n" + "ldr h17, [x27, x4]\n" + "ldr h16, [x26, x4]\n" + "fadd v16.8h, v17.8h, v16.8h\n" + "fadd v18.8h, v18.8h, v16.8h\n" + "ldr h17, [x15, x4]\n" + "ldr h16, [x14, x4]\n" + "fadd v16.8h, v17.8h, v16.8h\n" + "fadd v23.8h, v16.8h, v18.8h\n" + "ldr h17, [x12, x4]\n" + "ldr h16, [x28, x4]\n" + "fadd v22.8h, v17.8h, v16.8h\n" + "ldr h17, [x9, x4]\n" + "ldr h16, [x25, x4]\n" + "fadd v21.8h, v17.8h, v16.8h\n" + "ldr h17, [x23, x4]\n" + "ldr h16, [x22, x4]\n" + "fadd v16.8h, v17.8h, v16.8h\n" + "fadd v20.8h, v16.8h, v18.8h\n" + "ldr h17, [x16, x4]\n" + "ldr h16, [x13, x4]\n" + "fadd v19.8h, v17.8h, v22.8h\n" + "fadd v18.8h, v16.8h, v21.8h\n" + "ldr h17, [x24, x4]\n" + "ldr h16, [x21, x4]\n" + "fadd v17.8h, v17.8h, v22.8h\n" + "fadd v16.8h, v16.8h, v21.8h\n" + "fadd v19.8h, v23.8h, v19.8h\n" + "fadd v18.8h, v23.8h, v18.8h\n" "add x4, x4, #0x2\n" "fadd v17.8h, v17.8h, v20.8h\n" "fadd v16.8h, v16.8h, v20.8h\n" diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_avg_generic_depthfirst/generic.cpp index 44adb4ffcf..f7be92e53f 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_avg_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_avg_generic_depthfirst/generic.cpp @@ -22,7 +22,6 @@ * SOFTWARE. */ - #include <cstdint> #include <cstddef> @@ -45,77 +44,77 @@ void a64_fp16_nhwc_avg_generic_depthfirst_impl( __asm__ __volatile__( "ld1r { v9.8h }, [%x[rescale_ptr]]\n" "cmp %x[n_channels], #0x20\n" - "mov x9, #0x0\n" - "mov x28, #0x10\n" // cntb _, ALL, #1 - "mov x27, #0x20\n" // cntb _, ALL, #2 - "mov x26, #0x30\n" // cntb _, ALL, #3 + "mov x27, #0x0\n" + "mov x26, #0x10\n" // cntb _, ALL, #1 + "mov x24, #0x20\n" // cntb _, ALL, #2 + "mov x23, #0x30\n" // cntb _, ALL, #3 "blt 7f\n" "1:" // 4-vectors of channels "lsr x25, %x[n_valid_cells], #0x2\n" "movi v8.16b, #0x0\n" "movi v7.16b, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "movi v6.16b, #0x0\n" "movi v5.16b, #0x0\n" "cbz x25, 4f\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldr q4, [x24, x9]\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" "subs x25, x25, #0x1\n" - "ldr q3, [x23, x9]\n" - "ldr q2, [x24, x28]\n" - "ldr q1, [x23, x28]\n" - "ldr q0, [x24, x27]\n" - "ldr q31, [x23, x27]\n" - "ldr q30, [x24, x26]\n" - "ldr q29, [x23, x26]\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" - "ldr q28, [x22, x9]\n" - "ldr q22, [x21, x9]\n" - "ldr q27, [x22, x28]\n" - "ldr q21, [x21, x28]\n" - "ldr q26, [x22, x27]\n" - "ldr q20, [x21, x27]\n" - "ldr q25, [x22, x26]\n" - "ldr q24, [x21, x26]\n" + "ldr q3, [x20, x27]\n" + "ldr q2, [x21, x26]\n" + "ldr q1, [x20, x26]\n" + "ldr q0, [x21, x24]\n" + "ldr q31, [x20, x24]\n" + "ldr q30, [x21, x23]\n" + "ldr q29, [x20, x23]\n" + "ldp x21, x20, [x22, #0x10]\n" + "add x22, x22, #0x20\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" + "ldr q27, [x21, x26]\n" + "ldr q21, [x20, x26]\n" + "ldr q26, [x21, x24]\n" + "ldr q20, [x20, x24]\n" + "ldr q25, [x21, x23]\n" + "ldr q24, [x20, x23]\n" "beq 3f\n" "2:" // 4-vectors of channels: 4 inputs loop "fadd v23.8h, v4.8h, v3.8h\n" "fadd v19.8h, v28.8h, v22.8h\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldr q4, [x24, x9]\n" - "ldr q3, [x23, x9]\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "ldr q3, [x20, x27]\n" "fadd v22.8h, v2.8h, v1.8h\n" - "ldr q2, [x24, x28]\n" + "ldr q2, [x21, x26]\n" "fadd v18.8h, v27.8h, v21.8h\n" - "ldr q1, [x23, x28]\n" + "ldr q1, [x20, x26]\n" "fadd v21.8h, v0.8h, v31.8h\n" - "ldr q0, [x24, x27]\n" + "ldr q0, [x21, x24]\n" "fadd v17.8h, v26.8h, v20.8h\n" - "ldr q31, [x23, x27]\n" + "ldr q31, [x20, x24]\n" "fadd v20.8h, v30.8h, v29.8h\n" - "ldr q30, [x24, x26]\n" + "ldr q30, [x21, x23]\n" "fadd v16.8h, v25.8h, v24.8h\n" - "ldr q29, [x23, x26]\n" + "ldr q29, [x20, x23]\n" "fadd v19.8h, v23.8h, v19.8h\n" "fadd v18.8h, v22.8h, v18.8h\n" - "ldp x22, x21, [x20, #0x10]\n" - "ldr q28, [x22, x9]\n" - "ldr q22, [x21, x9]\n" + "ldp x21, x20, [x22, #0x10]\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" "fadd v17.8h, v21.8h, v17.8h\n" "fadd v16.8h, v20.8h, v16.8h\n" - "ldr q27, [x22, x28]\n" - "ldr q21, [x21, x28]\n" + "ldr q27, [x21, x26]\n" + "ldr q21, [x20, x26]\n" "subs x25, x25, #0x1\n" "fadd v8.8h, v8.8h, v19.8h\n" - "ldr q26, [x22, x27]\n" - "ldr q20, [x21, x27]\n" + "ldr q26, [x21, x24]\n" + "ldr q20, [x20, x24]\n" "fadd v7.8h, v7.8h, v18.8h\n" "fadd v6.8h, v6.8h, v17.8h\n" - "ldr q25, [x22, x26]\n" - "ldr q24, [x21, x26]\n" + "ldr q25, [x21, x23]\n" + "ldr q24, [x20, x23]\n" "fadd v5.8h, v5.8h, v16.8h\n" - "add x20, x20, #0x20\n" + "add x22, x22, #0x20\n" "bgt 2b\n" "3:" // 4-vectors of channels: 4 inputs tail "fadd v23.8h, v4.8h, v3.8h\n" @@ -138,16 +137,16 @@ void a64_fp16_nhwc_avg_generic_depthfirst_impl( "ands x21, %x[n_valid_cells], #0x3\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x24, [x20], #0x8\n" - "ldr q4, [x24, x9]\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" "subs x21, x21, #0x1\n" - "fadd v8.8h, v8.8h, v4.8h\n" - "ldr q2, [x24, x28]\n" - "ldr q0, [x24, x27]\n" - "fadd v7.8h, v7.8h, v2.8h\n" - "fadd v6.8h, v6.8h, v0.8h\n" - "ldr q30, [x24, x26]\n" - "fadd v5.8h, v5.8h, v30.8h\n" + "fadd v8.8h, v8.8h, v16.8h\n" + "ldr q17, [x20, x26]\n" + "ldr q16, [x20, x24]\n" + "fadd v7.8h, v7.8h, v17.8h\n" + "fadd v6.8h, v6.8h, v16.8h\n" + "ldr q16, [x20, x23]\n" + "fadd v5.8h, v5.8h, v16.8h\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End "sub %x[n_channels], %x[n_channels], #0x20\n" @@ -156,14 +155,14 @@ void a64_fp16_nhwc_avg_generic_depthfirst_impl( "fmul v7.8h, v7.8h, v9.8h\n" "fmul v6.8h, v6.8h, v9.8h\n" "fmul v5.8h, v5.8h, v9.8h\n" - "str q8, [%x[outptr], x9]\n" - "add x9, x9, #0x40\n" - "str q7, [%x[outptr], x28]\n" - "add x28, x28, #0x40\n" - "str q6, [%x[outptr], x27]\n" + "str q8, [%x[outptr], x27]\n" "add x27, x27, #0x40\n" - "str q5, [%x[outptr], x26]\n" + "str q7, [%x[outptr], x26]\n" "add x26, x26, #0x40\n" + "str q6, [%x[outptr], x24]\n" + "add x24, x24, #0x40\n" + "str q5, [%x[outptr], x23]\n" + "add x23, x23, #0x40\n" "bge 1b\n" "cbz %x[n_channels], 31f\n" "7:" // Single vector of channels @@ -172,146 +171,146 @@ void a64_fp16_nhwc_avg_generic_depthfirst_impl( "8:" // Single vector of channels: Loop "lsr x25, %x[n_valid_cells], #0x2\n" "movi v8.16b, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "cbz x25, 11f\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldr q4, [x24, x9]\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" "subs x25, x25, #0x1\n" - "ldr q3, [x23, x9]\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" - "ldr q28, [x22, x9]\n" - "ldr q22, [x21, x9]\n" + "ldr q3, [x20, x27]\n" + "ldp x21, x20, [x22, #0x10]\n" + "add x22, x22, #0x20\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 4 inputs loop - "fadd v23.8h, v4.8h, v3.8h\n" - "fadd v19.8h, v28.8h, v22.8h\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldr q4, [x24, x9]\n" - "ldr q3, [x23, x9]\n" - "fadd v19.8h, v23.8h, v19.8h\n" - "ldp x22, x21, [x20, #0x10]\n" + "fadd v17.8h, v4.8h, v3.8h\n" + "fadd v16.8h, v28.8h, v22.8h\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "ldr q3, [x20, x27]\n" + "fadd v16.8h, v17.8h, v16.8h\n" + "ldp x21, x20, [x22, #0x10]\n" "subs x25, x25, #0x1\n" - "ldr q28, [x22, x9]\n" - "ldr q22, [x21, x9]\n" - "fadd v8.8h, v8.8h, v19.8h\n" - "add x20, x20, #0x20\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" + "fadd v8.8h, v8.8h, v16.8h\n" + "add x22, x22, #0x20\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 4 inputs tail - "fadd v23.8h, v4.8h, v3.8h\n" - "fadd v19.8h, v28.8h, v22.8h\n" - "fadd v19.8h, v23.8h, v19.8h\n" - "fadd v8.8h, v8.8h, v19.8h\n" + "fadd v17.8h, v4.8h, v3.8h\n" + "fadd v16.8h, v28.8h, v22.8h\n" + "fadd v16.8h, v17.8h, v16.8h\n" + "fadd v8.8h, v8.8h, v16.8h\n" "11:" // Single vector of channels: Loop: After loop "ands x21, %x[n_valid_cells], #0x3\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x24, [x20], #0x8\n" - "ldr q4, [x24, x9]\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" "subs x21, x21, #0x1\n" - "fadd v8.8h, v8.8h, v4.8h\n" + "fadd v8.8h, v8.8h, v16.8h\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End "sub %x[n_channels], %x[n_channels], #0x8\n" "cmp %x[n_channels], #0x8\n" "fmul v8.8h, v8.8h, v9.8h\n" - "str q8, [%x[outptr], x9]\n" - "add x9, x9, #0x10\n" + "str q8, [%x[outptr], x27]\n" + "add x27, x27, #0x10\n" "bge 8b\n" "cbz %x[n_channels], 31f\n" "14:" // Oddments "lsr x25, %x[n_valid_cells], #0x2\n" - "add %x[outptr], %x[outptr], x9\n" + "add %x[outptr], %x[outptr], x27\n" "movi v8.16b, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "cbz x25, 20f\n" "15:" // Oddments: 4 inputs loop - "ldp x24, x23, [x20, #0x0]\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" - "add x24, x24, x9\n" - "add x23, x23, x9\n" - "add x22, x22, x9\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "add x23, x23, x27\n" + "add x22, x22, x27\n" + "add x21, x21, x27\n" "movi v4.16b, #0x0\n" "movi v3.16b, #0x0\n" - "add x21, x21, x9\n" + "add x20, x20, x27\n" "movi v28.16b, #0x0\n" "movi v22.16b, #0x0\n" "tbz %x[n_channels], #2, 17f\n" - "ldr d4, [x24], #0x8\n" - "ldr d3, [x23], #0x8\n" - "ldr d28, [x22], #0x8\n" - "ldr d22, [x21], #0x8\n" + "ldr d4, [x23], #0x8\n" + "ldr d3, [x22], #0x8\n" + "ldr d28, [x21], #0x8\n" + "ldr d22, [x20], #0x8\n" "tbz %x[n_channels], #1, 16f\n" - "ld1 { v4.s }[2], [x24], #0x4\n" - "ld1 { v3.s }[2], [x23], #0x4\n" - "ld1 { v28.s }[2], [x22], #0x4\n" - "ld1 { v22.s }[2], [x21], #0x4\n" + "ld1 { v4.s }[2], [x23], #0x4\n" + "ld1 { v3.s }[2], [x22], #0x4\n" + "ld1 { v28.s }[2], [x21], #0x4\n" + "ld1 { v22.s }[2], [x20], #0x4\n" "tbz %x[n_channels], #0, 19f\n" - "ld1 { v4.h }[6], [x24], #0x2\n" - "ld1 { v3.h }[6], [x23], #0x2\n" - "ld1 { v28.h }[6], [x22], #0x2\n" - "ld1 { v22.h }[6], [x21], #0x2\n" + "ld1 { v4.h }[6], [x23], #0x2\n" + "ld1 { v3.h }[6], [x22], #0x2\n" + "ld1 { v28.h }[6], [x21], #0x2\n" + "ld1 { v22.h }[6], [x20], #0x2\n" "b 19f\n" "16:" // Oddments: 4 inputs loop: Load: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 19f\n" - "ld1 { v4.h }[4], [x24], #0x2\n" - "ld1 { v3.h }[4], [x23], #0x2\n" - "ld1 { v28.h }[4], [x22], #0x2\n" - "ld1 { v22.h }[4], [x21], #0x2\n" + "ld1 { v4.h }[4], [x23], #0x2\n" + "ld1 { v3.h }[4], [x22], #0x2\n" + "ld1 { v28.h }[4], [x21], #0x2\n" + "ld1 { v22.h }[4], [x20], #0x2\n" "b 19f\n" "17:" // Oddments: 4 inputs loop: Load: Bit 2: Unset "tbz %x[n_channels], #1, 18f\n" - "ldr s4, [x24], #0x4\n" - "ldr s3, [x23], #0x4\n" - "ldr s28, [x22], #0x4\n" - "ldr s22, [x21], #0x4\n" + "ldr s4, [x23], #0x4\n" + "ldr s3, [x22], #0x4\n" + "ldr s28, [x21], #0x4\n" + "ldr s22, [x20], #0x4\n" "tbz %x[n_channels], #0, 19f\n" - "ld1 { v4.h }[2], [x24], #0x2\n" - "ld1 { v3.h }[2], [x23], #0x2\n" - "ld1 { v28.h }[2], [x22], #0x2\n" - "ld1 { v22.h }[2], [x21], #0x2\n" + "ld1 { v4.h }[2], [x23], #0x2\n" + "ld1 { v3.h }[2], [x22], #0x2\n" + "ld1 { v28.h }[2], [x21], #0x2\n" + "ld1 { v22.h }[2], [x20], #0x2\n" "b 19f\n" "18:" // Oddments: 4 inputs loop: Load: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 19f\n" - "ldr h4, [x24], #0x2\n" - "ldr h3, [x23], #0x2\n" - "ldr h28, [x22], #0x2\n" - "ldr h22, [x21], #0x2\n" + "ldr h4, [x23], #0x2\n" + "ldr h3, [x22], #0x2\n" + "ldr h28, [x21], #0x2\n" + "ldr h22, [x20], #0x2\n" "19:" // Oddments: 4 inputs loop: Load: Bit 2: End - "fadd v23.8h, v4.8h, v3.8h\n" - "fadd v19.8h, v28.8h, v22.8h\n" + "fadd v17.8h, v4.8h, v3.8h\n" + "fadd v16.8h, v28.8h, v22.8h\n" "subs x25, x25, #0x1\n" - "fadd v19.8h, v23.8h, v19.8h\n" - "fadd v8.8h, v8.8h, v19.8h\n" + "fadd v16.8h, v17.8h, v16.8h\n" + "fadd v8.8h, v8.8h, v16.8h\n" "bgt 15b\n" "20:" // Oddments: After loop "ands x21, %x[n_valid_cells], #0x3\n" "beq 26f\n" "21:" // Oddments: Single input loop - "ldr x24, [x20], #0x8\n" - "add x24, x24, x9\n" + "ldr x23, [x24], #0x8\n" + "add x23, x23, x27\n" "movi v4.16b, #0x0\n" "tbz %x[n_channels], #2, 23f\n" - "ldr d4, [x24], #0x8\n" + "ldr d4, [x23], #0x8\n" "tbz %x[n_channels], #1, 22f\n" - "ld1 { v4.s }[2], [x24], #0x4\n" + "ld1 { v4.s }[2], [x23], #0x4\n" "tbz %x[n_channels], #0, 25f\n" - "ld1 { v4.h }[6], [x24], #0x2\n" + "ld1 { v4.h }[6], [x23], #0x2\n" "b 25f\n" "22:" // Oddments: Single input loop: Load: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 25f\n" - "ld1 { v4.h }[4], [x24], #0x2\n" + "ld1 { v4.h }[4], [x23], #0x2\n" "b 25f\n" "23:" // Oddments: Single input loop: Load: Bit 2: Unset "tbz %x[n_channels], #1, 24f\n" - "ldr s4, [x24], #0x4\n" + "ldr s4, [x23], #0x4\n" "tbz %x[n_channels], #0, 25f\n" - "ld1 { v4.h }[2], [x24], #0x2\n" + "ld1 { v4.h }[2], [x23], #0x2\n" "b 25f\n" "24:" // Oddments: Single input loop: Load: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 25f\n" - "ldr h4, [x24], #0x2\n" + "ldr h4, [x23], #0x2\n" "25:" // Oddments: Single input loop: Load: Bit 2: End "subs x21, x21, #0x1\n" "fadd v8.8h, v8.8h, v4.8h\n" @@ -342,7 +341,7 @@ void a64_fp16_nhwc_avg_generic_depthfirst_impl( "31:" // End : [n_channels] "+&r" (n_channels), [outptr] "+&r" (outptr) : [inptrs] "r" (inptrs), [n_valid_cells] "r" (n_valid_cells), [rescale_ptr] "r" (&rescale_value) - : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x9", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" + : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); } diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_max_2x2_s1_output2x2_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_max_2x2_s1_output2x2_depthfirst.hpp index 23a9164b76..b65ac7e9fa 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_max_2x2_s1_output2x2_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_max_2x2_s1_output2x2_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -24,7 +24,7 @@ #pragma once -#if defined(__ARM_FP16_ARGS) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +#if defined(__aarch64__) && defined(__ARM_FP16_ARGS) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) namespace arm_conv { namespace pooling { @@ -48,4 +48,4 @@ struct a64_fp16_nhwc_max_2x2_s1_output2x2_depthfirst : public DepthfirstStrategy } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FP16_ARGS) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +#endif // defined(__aarch64__) && defined(__ARM_FP16_ARGS) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp index 8041453cb1..4b073b9076 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp @@ -22,6 +22,7 @@ * SOFTWARE. */ + #include <cstddef> #include <cstdint> @@ -111,7 +112,7 @@ void a64_fp16_nhwc_max_2x2_s1_output2x2_depthfirst_impl( "fmax v18.8h, v18.8h, v21.8h\n" "fmax v17.8h, v17.8h, v20.8h\n" "add x15, x15, #0x10\n" - "fmax v16.8h, v16.8h, v20.8h\n" + "fmax v16.8h, v20.8h, v16.8h\n" "str q19, [x14, x12]\n" "str q18, [x13, x12]\n" "str q17, [x11, x12]\n" @@ -121,43 +122,43 @@ void a64_fp16_nhwc_max_2x2_s1_output2x2_depthfirst_impl( "2:" // Vector: Tail "fmax v21.8h, v30.8h, v29.8h\n" "fmax v20.8h, v29.8h, v28.8h\n" - "fmax v19.8h, v27.8h, v26.8h\n" + "fmax v16.8h, v27.8h, v26.8h\n" "fmax v18.8h, v25.8h, v24.8h\n" "fmax v17.8h, v27.8h, v23.8h\n" - "fmax v16.8h, v24.8h, v22.8h\n" - "fmax v19.8h, v21.8h, v19.8h\n" + "fmax v19.8h, v24.8h, v22.8h\n" + "fmax v16.8h, v21.8h, v16.8h\n" "fmax v18.8h, v18.8h, v21.8h\n" - "str q19, [x14, x12]\n" + "str q16, [x14, x12]\n" "fmax v17.8h, v17.8h, v20.8h\n" - "fmax v16.8h, v16.8h, v20.8h\n" + "fmax v16.8h, v20.8h, v19.8h\n" "str q18, [x13, x12]\n" "str q17, [x11, x12]\n" "str q16, [x10, x12]\n" "add x12, x12, #0x10\n" "cbz x16, 4f\n" "3:" // Oddments - "ldr h30, [x28, x15]\n" - "ldr h29, [x25, x15]\n" - "fmax v21.8h, v30.8h, v29.8h\n" + "ldr h16, [x28, x15]\n" + "ldr h17, [x25, x15]\n" + "fmax v23.8h, v16.8h, v17.8h\n" "subs x16, x16, #0x1\n" - "ldr h28, [x22, x15]\n" - "ldr h27, [x26, x15]\n" - "fmax v20.8h, v29.8h, v28.8h\n" - "ldr h26, [x9, x15]\n" - "ldr h25, [x27, x15]\n" - "fmax v19.8h, v27.8h, v26.8h\n" - "fmax v19.8h, v21.8h, v19.8h\n" - "ldr h24, [x24, x15]\n" - "ldr h23, [x23, x15]\n" - "fmax v18.8h, v25.8h, v24.8h\n" - "fmax v17.8h, v27.8h, v23.8h\n" - "ldr h22, [x21, x15]\n" - "fmax v16.8h, v24.8h, v22.8h\n" + "ldr h16, [x22, x15]\n" + "ldr h22, [x26, x15]\n" + "fmax v21.8h, v17.8h, v16.8h\n" + "ldr h16, [x9, x15]\n" + "ldr h17, [x27, x15]\n" + "fmax v16.8h, v22.8h, v16.8h\n" + "fmax v20.8h, v23.8h, v16.8h\n" + "ldr h19, [x24, x15]\n" + "ldr h16, [x23, x15]\n" + "fmax v18.8h, v17.8h, v19.8h\n" + "fmax v17.8h, v22.8h, v16.8h\n" + "ldr h16, [x21, x15]\n" + "fmax v16.8h, v19.8h, v16.8h\n" "add x15, x15, #0x2\n" - "fmax v18.8h, v18.8h, v21.8h\n" - "fmax v17.8h, v17.8h, v20.8h\n" - "fmax v16.8h, v16.8h, v20.8h\n" - "str h19, [x14, x12]\n" + "fmax v18.8h, v18.8h, v23.8h\n" + "fmax v17.8h, v17.8h, v21.8h\n" + "fmax v16.8h, v21.8h, v16.8h\n" + "str h20, [x14, x12]\n" "str h18, [x13, x12]\n" "str h17, [x11, x12]\n" "str h16, [x10, x12]\n" diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_max_generic_depthfirst/generic.cpp index e4de9fb79c..c92e2cdebd 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_max_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_max_generic_depthfirst/generic.cpp @@ -41,10 +41,10 @@ void a64_fp16_nhwc_max_generic_depthfirst_impl( { __asm__ __volatile__( "cmp %x[n_channels], #0x20\n" - "mov x9, #0x0\n" - "mov x28, #0x10\n" // cntb _, ALL, #1 - "mov x27, #0x20\n" // cntb _, ALL, #2 - "mov x26, #0x30\n" // cntb _, ALL, #3 + "mov x27, #0x0\n" + "mov x26, #0x10\n" // cntb _, ALL, #1 + "mov x24, #0x20\n" // cntb _, ALL, #2 + "mov x23, #0x30\n" // cntb _, ALL, #3 "blt 7f\n" "1:" // 4-vectors of channels "mov w20, #0xfc00\n" @@ -53,66 +53,66 @@ void a64_fp16_nhwc_max_generic_depthfirst_impl( "dup v7.8h, w20\n" "dup v6.8h, w20\n" "dup v5.8h, w20\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "cbz x25, 4f\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldr q4, [x24, x9]\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" "subs x25, x25, #0x1\n" - "ldr q3, [x23, x9]\n" - "ldr q2, [x24, x28]\n" - "ldr q1, [x23, x28]\n" - "ldr q0, [x24, x27]\n" - "ldr q31, [x23, x27]\n" - "ldr q30, [x24, x26]\n" - "ldr q29, [x23, x26]\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" - "ldr q28, [x22, x9]\n" - "ldr q22, [x21, x9]\n" - "ldr q27, [x22, x28]\n" - "ldr q21, [x21, x28]\n" - "ldr q26, [x22, x27]\n" - "ldr q20, [x21, x27]\n" - "ldr q25, [x22, x26]\n" - "ldr q24, [x21, x26]\n" + "ldr q3, [x20, x27]\n" + "ldr q2, [x21, x26]\n" + "ldr q1, [x20, x26]\n" + "ldr q0, [x21, x24]\n" + "ldr q31, [x20, x24]\n" + "ldr q30, [x21, x23]\n" + "ldr q29, [x20, x23]\n" + "ldp x21, x20, [x22, #0x10]\n" + "add x22, x22, #0x20\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" + "ldr q27, [x21, x26]\n" + "ldr q21, [x20, x26]\n" + "ldr q26, [x21, x24]\n" + "ldr q20, [x20, x24]\n" + "ldr q25, [x21, x23]\n" + "ldr q24, [x20, x23]\n" "beq 3f\n" "2:" // 4-vectors of channels: 4 inputs loop "fmax v23.8h, v4.8h, v3.8h\n" "fmax v19.8h, v28.8h, v22.8h\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldr q4, [x24, x9]\n" - "ldr q3, [x23, x9]\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "ldr q3, [x20, x27]\n" "fmax v22.8h, v2.8h, v1.8h\n" - "ldr q2, [x24, x28]\n" + "ldr q2, [x21, x26]\n" "fmax v18.8h, v27.8h, v21.8h\n" - "ldr q1, [x23, x28]\n" + "ldr q1, [x20, x26]\n" "fmax v21.8h, v0.8h, v31.8h\n" - "ldr q0, [x24, x27]\n" + "ldr q0, [x21, x24]\n" "fmax v17.8h, v26.8h, v20.8h\n" - "ldr q31, [x23, x27]\n" + "ldr q31, [x20, x24]\n" "fmax v20.8h, v30.8h, v29.8h\n" - "ldr q30, [x24, x26]\n" + "ldr q30, [x21, x23]\n" "fmax v16.8h, v25.8h, v24.8h\n" - "ldr q29, [x23, x26]\n" + "ldr q29, [x20, x23]\n" "fmax v19.8h, v23.8h, v19.8h\n" "fmax v18.8h, v22.8h, v18.8h\n" - "ldp x22, x21, [x20, #0x10]\n" - "ldr q28, [x22, x9]\n" - "ldr q22, [x21, x9]\n" + "ldp x21, x20, [x22, #0x10]\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" "fmax v17.8h, v21.8h, v17.8h\n" "fmax v16.8h, v20.8h, v16.8h\n" - "ldr q27, [x22, x28]\n" - "ldr q21, [x21, x28]\n" + "ldr q27, [x21, x26]\n" + "ldr q21, [x20, x26]\n" "subs x25, x25, #0x1\n" "fmax v8.8h, v8.8h, v19.8h\n" - "ldr q26, [x22, x27]\n" - "ldr q20, [x21, x27]\n" + "ldr q26, [x21, x24]\n" + "ldr q20, [x20, x24]\n" "fmax v7.8h, v7.8h, v18.8h\n" "fmax v6.8h, v6.8h, v17.8h\n" - "ldr q25, [x22, x26]\n" - "ldr q24, [x21, x26]\n" + "ldr q25, [x21, x23]\n" + "ldr q24, [x20, x23]\n" "fmax v5.8h, v5.8h, v16.8h\n" - "add x20, x20, #0x20\n" + "add x22, x22, #0x20\n" "bgt 2b\n" "3:" // 4-vectors of channels: 4 inputs tail "fmax v23.8h, v4.8h, v3.8h\n" @@ -135,28 +135,28 @@ void a64_fp16_nhwc_max_generic_depthfirst_impl( "ands x21, %x[n_valid_cells], #0x3\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x24, [x20], #0x8\n" - "ldr q4, [x24, x9]\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" "subs x21, x21, #0x1\n" - "fmax v8.8h, v8.8h, v4.8h\n" - "ldr q2, [x24, x28]\n" - "ldr q0, [x24, x27]\n" - "fmax v7.8h, v7.8h, v2.8h\n" - "fmax v6.8h, v6.8h, v0.8h\n" - "ldr q30, [x24, x26]\n" - "fmax v5.8h, v5.8h, v30.8h\n" + "fmax v8.8h, v8.8h, v16.8h\n" + "ldr q17, [x20, x26]\n" + "ldr q16, [x20, x24]\n" + "fmax v7.8h, v7.8h, v17.8h\n" + "fmax v6.8h, v6.8h, v16.8h\n" + "ldr q16, [x20, x23]\n" + "fmax v5.8h, v5.8h, v16.8h\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End "sub %x[n_channels], %x[n_channels], #0x20\n" "cmp %x[n_channels], #0x20\n" - "str q8, [%x[outptr], x9]\n" - "str q7, [%x[outptr], x28]\n" - "add x9, x9, #0x40\n" - "add x28, x28, #0x40\n" - "str q6, [%x[outptr], x27]\n" + "str q8, [%x[outptr], x27]\n" + "str q7, [%x[outptr], x26]\n" "add x27, x27, #0x40\n" - "str q5, [%x[outptr], x26]\n" "add x26, x26, #0x40\n" + "str q6, [%x[outptr], x24]\n" + "add x24, x24, #0x40\n" + "str q5, [%x[outptr], x23]\n" + "add x23, x23, #0x40\n" "bge 1b\n" "cbz %x[n_channels], 31f\n" "7:" // Single vector of channels @@ -166,146 +166,146 @@ void a64_fp16_nhwc_max_generic_depthfirst_impl( "mov w20, #0xfc00\n" "lsr x25, %x[n_valid_cells], #0x2\n" "dup v8.8h, w20\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "cbz x25, 11f\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldr q4, [x24, x9]\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" "subs x25, x25, #0x1\n" - "ldr q3, [x23, x9]\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" - "ldr q28, [x22, x9]\n" - "ldr q22, [x21, x9]\n" + "ldr q3, [x20, x27]\n" + "ldp x21, x20, [x22, #0x10]\n" + "add x22, x22, #0x20\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 4 inputs loop - "fmax v23.8h, v4.8h, v3.8h\n" - "fmax v19.8h, v28.8h, v22.8h\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldr q4, [x24, x9]\n" - "ldr q3, [x23, x9]\n" - "fmax v19.8h, v23.8h, v19.8h\n" - "ldp x22, x21, [x20, #0x10]\n" + "fmax v17.8h, v4.8h, v3.8h\n" + "fmax v16.8h, v28.8h, v22.8h\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "ldr q3, [x20, x27]\n" + "fmax v16.8h, v17.8h, v16.8h\n" + "ldp x21, x20, [x22, #0x10]\n" "subs x25, x25, #0x1\n" - "ldr q28, [x22, x9]\n" - "ldr q22, [x21, x9]\n" - "fmax v8.8h, v8.8h, v19.8h\n" - "add x20, x20, #0x20\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" + "fmax v8.8h, v8.8h, v16.8h\n" + "add x22, x22, #0x20\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 4 inputs tail - "fmax v23.8h, v4.8h, v3.8h\n" - "fmax v19.8h, v28.8h, v22.8h\n" - "fmax v19.8h, v23.8h, v19.8h\n" - "fmax v8.8h, v8.8h, v19.8h\n" + "fmax v17.8h, v4.8h, v3.8h\n" + "fmax v16.8h, v28.8h, v22.8h\n" + "fmax v16.8h, v17.8h, v16.8h\n" + "fmax v8.8h, v8.8h, v16.8h\n" "11:" // Single vector of channels: Loop: After loop "ands x21, %x[n_valid_cells], #0x3\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x24, [x20], #0x8\n" - "ldr q4, [x24, x9]\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" "subs x21, x21, #0x1\n" - "fmax v8.8h, v8.8h, v4.8h\n" + "fmax v8.8h, v8.8h, v16.8h\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End "sub %x[n_channels], %x[n_channels], #0x8\n" "cmp %x[n_channels], #0x8\n" - "str q8, [%x[outptr], x9]\n" - "add x9, x9, #0x10\n" + "str q8, [%x[outptr], x27]\n" + "add x27, x27, #0x10\n" "bge 8b\n" "cbz %x[n_channels], 31f\n" "14:" // Oddments "mov w20, #0xfc00\n" "lsr x25, %x[n_valid_cells], #0x2\n" "dup v8.8h, w20\n" - "add %x[outptr], %x[outptr], x9\n" - "mov x20, %x[inptrs]\n" + "add %x[outptr], %x[outptr], x27\n" + "mov x24, %x[inptrs]\n" "cbz x25, 20f\n" "15:" // Oddments: 4 inputs loop - "ldp x24, x23, [x20, #0x0]\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" - "add x24, x24, x9\n" - "add x23, x23, x9\n" - "add x22, x22, x9\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "add x23, x23, x27\n" + "add x22, x22, x27\n" + "add x21, x21, x27\n" "movi v4.16b, #0x0\n" "movi v3.16b, #0x0\n" - "add x21, x21, x9\n" + "add x20, x20, x27\n" "movi v28.16b, #0x0\n" "movi v22.16b, #0x0\n" "tbz %x[n_channels], #2, 17f\n" - "ldr d4, [x24], #0x8\n" - "ldr d3, [x23], #0x8\n" - "ldr d28, [x22], #0x8\n" - "ldr d22, [x21], #0x8\n" + "ldr d4, [x23], #0x8\n" + "ldr d3, [x22], #0x8\n" + "ldr d28, [x21], #0x8\n" + "ldr d22, [x20], #0x8\n" "tbz %x[n_channels], #1, 16f\n" - "ld1 { v4.s }[2], [x24], #0x4\n" - "ld1 { v3.s }[2], [x23], #0x4\n" - "ld1 { v28.s }[2], [x22], #0x4\n" - "ld1 { v22.s }[2], [x21], #0x4\n" + "ld1 { v4.s }[2], [x23], #0x4\n" + "ld1 { v3.s }[2], [x22], #0x4\n" + "ld1 { v28.s }[2], [x21], #0x4\n" + "ld1 { v22.s }[2], [x20], #0x4\n" "tbz %x[n_channels], #0, 19f\n" - "ld1 { v4.h }[6], [x24], #0x2\n" - "ld1 { v3.h }[6], [x23], #0x2\n" - "ld1 { v28.h }[6], [x22], #0x2\n" - "ld1 { v22.h }[6], [x21], #0x2\n" + "ld1 { v4.h }[6], [x23], #0x2\n" + "ld1 { v3.h }[6], [x22], #0x2\n" + "ld1 { v28.h }[6], [x21], #0x2\n" + "ld1 { v22.h }[6], [x20], #0x2\n" "b 19f\n" "16:" // Oddments: 4 inputs loop: Load: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 19f\n" - "ld1 { v4.h }[4], [x24], #0x2\n" - "ld1 { v3.h }[4], [x23], #0x2\n" - "ld1 { v28.h }[4], [x22], #0x2\n" - "ld1 { v22.h }[4], [x21], #0x2\n" + "ld1 { v4.h }[4], [x23], #0x2\n" + "ld1 { v3.h }[4], [x22], #0x2\n" + "ld1 { v28.h }[4], [x21], #0x2\n" + "ld1 { v22.h }[4], [x20], #0x2\n" "b 19f\n" "17:" // Oddments: 4 inputs loop: Load: Bit 2: Unset "tbz %x[n_channels], #1, 18f\n" - "ldr s4, [x24], #0x4\n" - "ldr s3, [x23], #0x4\n" - "ldr s28, [x22], #0x4\n" - "ldr s22, [x21], #0x4\n" + "ldr s4, [x23], #0x4\n" + "ldr s3, [x22], #0x4\n" + "ldr s28, [x21], #0x4\n" + "ldr s22, [x20], #0x4\n" "tbz %x[n_channels], #0, 19f\n" - "ld1 { v4.h }[2], [x24], #0x2\n" - "ld1 { v3.h }[2], [x23], #0x2\n" - "ld1 { v28.h }[2], [x22], #0x2\n" - "ld1 { v22.h }[2], [x21], #0x2\n" + "ld1 { v4.h }[2], [x23], #0x2\n" + "ld1 { v3.h }[2], [x22], #0x2\n" + "ld1 { v28.h }[2], [x21], #0x2\n" + "ld1 { v22.h }[2], [x20], #0x2\n" "b 19f\n" "18:" // Oddments: 4 inputs loop: Load: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 19f\n" - "ldr h4, [x24], #0x2\n" - "ldr h3, [x23], #0x2\n" - "ldr h28, [x22], #0x2\n" - "ldr h22, [x21], #0x2\n" + "ldr h4, [x23], #0x2\n" + "ldr h3, [x22], #0x2\n" + "ldr h28, [x21], #0x2\n" + "ldr h22, [x20], #0x2\n" "19:" // Oddments: 4 inputs loop: Load: Bit 2: End - "fmax v23.8h, v4.8h, v3.8h\n" - "fmax v19.8h, v28.8h, v22.8h\n" + "fmax v17.8h, v4.8h, v3.8h\n" + "fmax v16.8h, v28.8h, v22.8h\n" "subs x25, x25, #0x1\n" - "fmax v19.8h, v23.8h, v19.8h\n" - "fmax v8.8h, v8.8h, v19.8h\n" + "fmax v16.8h, v17.8h, v16.8h\n" + "fmax v8.8h, v8.8h, v16.8h\n" "bgt 15b\n" "20:" // Oddments: After loop "ands x21, %x[n_valid_cells], #0x3\n" "beq 26f\n" "21:" // Oddments: Single input loop - "ldr x24, [x20], #0x8\n" - "add x24, x24, x9\n" + "ldr x23, [x24], #0x8\n" + "add x23, x23, x27\n" "movi v4.16b, #0x0\n" "tbz %x[n_channels], #2, 23f\n" - "ldr d4, [x24], #0x8\n" + "ldr d4, [x23], #0x8\n" "tbz %x[n_channels], #1, 22f\n" - "ld1 { v4.s }[2], [x24], #0x4\n" + "ld1 { v4.s }[2], [x23], #0x4\n" "tbz %x[n_channels], #0, 25f\n" - "ld1 { v4.h }[6], [x24], #0x2\n" + "ld1 { v4.h }[6], [x23], #0x2\n" "b 25f\n" "22:" // Oddments: Single input loop: Load: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 25f\n" - "ld1 { v4.h }[4], [x24], #0x2\n" + "ld1 { v4.h }[4], [x23], #0x2\n" "b 25f\n" "23:" // Oddments: Single input loop: Load: Bit 2: Unset "tbz %x[n_channels], #1, 24f\n" - "ldr s4, [x24], #0x4\n" + "ldr s4, [x23], #0x4\n" "tbz %x[n_channels], #0, 25f\n" - "ld1 { v4.h }[2], [x24], #0x2\n" + "ld1 { v4.h }[2], [x23], #0x2\n" "b 25f\n" "24:" // Oddments: Single input loop: Load: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 25f\n" - "ldr h4, [x24], #0x2\n" + "ldr h4, [x23], #0x2\n" "25:" // Oddments: Single input loop: Load: Bit 2: End "subs x21, x21, #0x1\n" "fmax v8.8h, v8.8h, v4.8h\n" @@ -335,7 +335,7 @@ void a64_fp16_nhwc_max_generic_depthfirst_impl( "31:" // End : [n_channels] "+&r" (n_channels), [outptr] "+&r" (outptr) : [inptrs] "r" (inptrs), [n_valid_cells] "r" (n_valid_cells) - : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x9", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" + : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); } diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp index 813e685606..7add5feb1d 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -24,6 +24,8 @@ #pragma once +#if defined(__aarch64__) + namespace arm_conv { namespace pooling { @@ -45,3 +47,5 @@ struct a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst : public DepthfirstStrategy } // namespace pooling } // namespace arm_conv + +#endif // defined(__aarch64__) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp index 9db65d62b0..cf0047638e 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp @@ -22,12 +22,12 @@ * SOFTWARE. */ -#if defined(__aarch64__) - #include <algorithm> #include <cstddef> #include <cstdint> +#if defined(__aarch64__) + namespace arm_conv { namespace pooling { @@ -196,38 +196,38 @@ void a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst_impl( "add x5, x5, #0x10\n" "cbz x3, 4f\n" "3:" // Oddments - "ldr s6, [x11, x4]\n" - "ldr s5, [x10, x4]\n" - "fadd v17.4s, v6.4s, v5.4s\n" + "ldr s17, [x11, x4]\n" + "ldr s16, [x10, x4]\n" + "fadd v18.4s, v17.4s, v16.4s\n" "subs x3, x3, #0x1\n" - "ldr s4, [x27, x4]\n" - "ldr s3, [x26, x4]\n" - "fadd v16.4s, v4.4s, v3.4s\n" - "fadd v19.4s, v17.4s, v16.4s\n" - "ldr s2, [x15, x4]\n" - "ldr s1, [x14, x4]\n" - "fadd v18.4s, v2.4s, v1.4s\n" - "fadd v21.4s, v18.4s, v19.4s\n" - "ldr s0, [x12, x4]\n" - "ldr s31, [x28, x4]\n" - "fadd v17.4s, v0.4s, v31.4s\n" - "ldr s30, [x9, x4]\n" - "ldr s29, [x25, x4]\n" - "fadd v22.4s, v30.4s, v29.4s\n" - "ldr s28, [x23, x4]\n" - "ldr s27, [x22, x4]\n" - "fadd v16.4s, v28.4s, v27.4s\n" - "fadd v20.4s, v16.4s, v19.4s\n" - "ldr s26, [x16, x4]\n" - "ldr s25, [x13, x4]\n" - "fadd v19.4s, v26.4s, v17.4s\n" - "fadd v18.4s, v25.4s, v22.4s\n" - "ldr s24, [x24, x4]\n" - "ldr s23, [x21, x4]\n" - "fadd v17.4s, v24.4s, v17.4s\n" - "fadd v16.4s, v23.4s, v22.4s\n" - "fadd v19.4s, v21.4s, v19.4s\n" - "fadd v18.4s, v21.4s, v18.4s\n" + "ldr s17, [x27, x4]\n" + "ldr s16, [x26, x4]\n" + "fadd v16.4s, v17.4s, v16.4s\n" + "fadd v18.4s, v18.4s, v16.4s\n" + "ldr s17, [x15, x4]\n" + "ldr s16, [x14, x4]\n" + "fadd v16.4s, v17.4s, v16.4s\n" + "fadd v23.4s, v16.4s, v18.4s\n" + "ldr s17, [x12, x4]\n" + "ldr s16, [x28, x4]\n" + "fadd v22.4s, v17.4s, v16.4s\n" + "ldr s17, [x9, x4]\n" + "ldr s16, [x25, x4]\n" + "fadd v21.4s, v17.4s, v16.4s\n" + "ldr s17, [x23, x4]\n" + "ldr s16, [x22, x4]\n" + "fadd v16.4s, v17.4s, v16.4s\n" + "fadd v20.4s, v16.4s, v18.4s\n" + "ldr s17, [x16, x4]\n" + "ldr s16, [x13, x4]\n" + "fadd v19.4s, v17.4s, v22.4s\n" + "fadd v18.4s, v16.4s, v21.4s\n" + "ldr s17, [x24, x4]\n" + "ldr s16, [x21, x4]\n" + "fadd v17.4s, v17.4s, v22.4s\n" + "fadd v16.4s, v16.4s, v21.4s\n" + "fadd v19.4s, v23.4s, v19.4s\n" + "fadd v18.4s, v23.4s, v18.4s\n" "add x4, x4, #0x4\n" "fadd v17.4s, v17.4s, v20.4s\n" "fadd v16.4s, v16.4s, v20.4s\n" @@ -250,4 +250,5 @@ void a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst_impl( } // namespace pooling } // namespace arm_conv + #endif // defined(__aarch64__) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_generic_depthfirst/generic.cpp index 3f90610591..d236f07b1c 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_generic_depthfirst/generic.cpp @@ -22,11 +22,11 @@ * SOFTWARE. */ -#if defined(__aarch64__) - #include <cstdint> #include <cstddef> +#if defined(__aarch64__) + namespace arm_conv { namespace pooling { @@ -44,77 +44,77 @@ void a64_fp32_nhwc_avg_generic_depthfirst_impl( __asm__ __volatile__( "ld1r { v9.4s }, [%x[rescale_ptr]]\n" "cmp %x[n_channels], #0x10\n" - "mov x9, #0x0\n" - "mov x28, #0x10\n" // cntb _, ALL, #1 - "mov x27, #0x20\n" // cntb _, ALL, #2 - "mov x26, #0x30\n" // cntb _, ALL, #3 + "mov x27, #0x0\n" + "mov x26, #0x10\n" // cntb _, ALL, #1 + "mov x24, #0x20\n" // cntb _, ALL, #2 + "mov x23, #0x30\n" // cntb _, ALL, #3 "blt 7f\n" "1:" // 4-vectors of channels "lsr x25, %x[n_valid_cells], #0x2\n" "movi v8.16b, #0x0\n" "movi v7.16b, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "movi v6.16b, #0x0\n" "movi v5.16b, #0x0\n" "cbz x25, 4f\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldr q4, [x24, x9]\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" "subs x25, x25, #0x1\n" - "ldr q3, [x23, x9]\n" - "ldr q2, [x24, x28]\n" - "ldr q1, [x23, x28]\n" - "ldr q0, [x24, x27]\n" - "ldr q31, [x23, x27]\n" - "ldr q30, [x24, x26]\n" - "ldr q29, [x23, x26]\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" - "ldr q28, [x22, x9]\n" - "ldr q22, [x21, x9]\n" - "ldr q27, [x22, x28]\n" - "ldr q21, [x21, x28]\n" - "ldr q26, [x22, x27]\n" - "ldr q20, [x21, x27]\n" - "ldr q25, [x22, x26]\n" - "ldr q24, [x21, x26]\n" + "ldr q3, [x20, x27]\n" + "ldr q2, [x21, x26]\n" + "ldr q1, [x20, x26]\n" + "ldr q0, [x21, x24]\n" + "ldr q31, [x20, x24]\n" + "ldr q30, [x21, x23]\n" + "ldr q29, [x20, x23]\n" + "ldp x21, x20, [x22, #0x10]\n" + "add x22, x22, #0x20\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" + "ldr q27, [x21, x26]\n" + "ldr q21, [x20, x26]\n" + "ldr q26, [x21, x24]\n" + "ldr q20, [x20, x24]\n" + "ldr q25, [x21, x23]\n" + "ldr q24, [x20, x23]\n" "beq 3f\n" "2:" // 4-vectors of channels: 4 inputs loop "fadd v23.4s, v4.4s, v3.4s\n" "fadd v19.4s, v28.4s, v22.4s\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldr q4, [x24, x9]\n" - "ldr q3, [x23, x9]\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "ldr q3, [x20, x27]\n" "fadd v22.4s, v2.4s, v1.4s\n" - "ldr q2, [x24, x28]\n" + "ldr q2, [x21, x26]\n" "fadd v18.4s, v27.4s, v21.4s\n" - "ldr q1, [x23, x28]\n" + "ldr q1, [x20, x26]\n" "fadd v21.4s, v0.4s, v31.4s\n" - "ldr q0, [x24, x27]\n" + "ldr q0, [x21, x24]\n" "fadd v17.4s, v26.4s, v20.4s\n" - "ldr q31, [x23, x27]\n" + "ldr q31, [x20, x24]\n" "fadd v20.4s, v30.4s, v29.4s\n" - "ldr q30, [x24, x26]\n" + "ldr q30, [x21, x23]\n" "fadd v16.4s, v25.4s, v24.4s\n" - "ldr q29, [x23, x26]\n" + "ldr q29, [x20, x23]\n" "fadd v19.4s, v23.4s, v19.4s\n" "fadd v18.4s, v22.4s, v18.4s\n" - "ldp x22, x21, [x20, #0x10]\n" - "ldr q28, [x22, x9]\n" - "ldr q22, [x21, x9]\n" + "ldp x21, x20, [x22, #0x10]\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" "fadd v17.4s, v21.4s, v17.4s\n" "fadd v16.4s, v20.4s, v16.4s\n" - "ldr q27, [x22, x28]\n" - "ldr q21, [x21, x28]\n" + "ldr q27, [x21, x26]\n" + "ldr q21, [x20, x26]\n" "subs x25, x25, #0x1\n" "fadd v8.4s, v8.4s, v19.4s\n" - "ldr q26, [x22, x27]\n" - "ldr q20, [x21, x27]\n" + "ldr q26, [x21, x24]\n" + "ldr q20, [x20, x24]\n" "fadd v7.4s, v7.4s, v18.4s\n" "fadd v6.4s, v6.4s, v17.4s\n" - "ldr q25, [x22, x26]\n" - "ldr q24, [x21, x26]\n" + "ldr q25, [x21, x23]\n" + "ldr q24, [x20, x23]\n" "fadd v5.4s, v5.4s, v16.4s\n" - "add x20, x20, #0x20\n" + "add x22, x22, #0x20\n" "bgt 2b\n" "3:" // 4-vectors of channels: 4 inputs tail "fadd v23.4s, v4.4s, v3.4s\n" @@ -137,16 +137,16 @@ void a64_fp32_nhwc_avg_generic_depthfirst_impl( "ands x21, %x[n_valid_cells], #0x3\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x24, [x20], #0x8\n" - "ldr q4, [x24, x9]\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" "subs x21, x21, #0x1\n" - "fadd v8.4s, v8.4s, v4.4s\n" - "ldr q2, [x24, x28]\n" - "ldr q0, [x24, x27]\n" - "fadd v7.4s, v7.4s, v2.4s\n" - "fadd v6.4s, v6.4s, v0.4s\n" - "ldr q30, [x24, x26]\n" - "fadd v5.4s, v5.4s, v30.4s\n" + "fadd v8.4s, v8.4s, v16.4s\n" + "ldr q17, [x20, x26]\n" + "ldr q16, [x20, x24]\n" + "fadd v7.4s, v7.4s, v17.4s\n" + "fadd v6.4s, v6.4s, v16.4s\n" + "ldr q16, [x20, x23]\n" + "fadd v5.4s, v5.4s, v16.4s\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End "sub %x[n_channels], %x[n_channels], #0x10\n" @@ -155,14 +155,14 @@ void a64_fp32_nhwc_avg_generic_depthfirst_impl( "fmul v7.4s, v7.4s, v9.4s\n" "fmul v6.4s, v6.4s, v9.4s\n" "fmul v5.4s, v5.4s, v9.4s\n" - "str q8, [%x[outptr], x9]\n" - "add x9, x9, #0x40\n" - "str q7, [%x[outptr], x28]\n" - "add x28, x28, #0x40\n" - "str q6, [%x[outptr], x27]\n" + "str q8, [%x[outptr], x27]\n" "add x27, x27, #0x40\n" - "str q5, [%x[outptr], x26]\n" + "str q7, [%x[outptr], x26]\n" "add x26, x26, #0x40\n" + "str q6, [%x[outptr], x24]\n" + "add x24, x24, #0x40\n" + "str q5, [%x[outptr], x23]\n" + "add x23, x23, #0x40\n" "bge 1b\n" "cbz %x[n_channels], 25f\n" "7:" // Single vector of channels @@ -171,110 +171,110 @@ void a64_fp32_nhwc_avg_generic_depthfirst_impl( "8:" // Single vector of channels: Loop "lsr x25, %x[n_valid_cells], #0x2\n" "movi v8.16b, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "cbz x25, 11f\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldr q4, [x24, x9]\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" "subs x25, x25, #0x1\n" - "ldr q3, [x23, x9]\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" - "ldr q28, [x22, x9]\n" - "ldr q22, [x21, x9]\n" + "ldr q3, [x20, x27]\n" + "ldp x21, x20, [x22, #0x10]\n" + "add x22, x22, #0x20\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 4 inputs loop - "fadd v23.4s, v4.4s, v3.4s\n" - "fadd v19.4s, v28.4s, v22.4s\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldr q4, [x24, x9]\n" - "ldr q3, [x23, x9]\n" - "fadd v19.4s, v23.4s, v19.4s\n" - "ldp x22, x21, [x20, #0x10]\n" + "fadd v17.4s, v4.4s, v3.4s\n" + "fadd v16.4s, v28.4s, v22.4s\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "ldr q3, [x20, x27]\n" + "fadd v16.4s, v17.4s, v16.4s\n" + "ldp x21, x20, [x22, #0x10]\n" "subs x25, x25, #0x1\n" - "ldr q28, [x22, x9]\n" - "ldr q22, [x21, x9]\n" - "fadd v8.4s, v8.4s, v19.4s\n" - "add x20, x20, #0x20\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" + "fadd v8.4s, v8.4s, v16.4s\n" + "add x22, x22, #0x20\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 4 inputs tail - "fadd v23.4s, v4.4s, v3.4s\n" - "fadd v19.4s, v28.4s, v22.4s\n" - "fadd v19.4s, v23.4s, v19.4s\n" - "fadd v8.4s, v8.4s, v19.4s\n" + "fadd v17.4s, v4.4s, v3.4s\n" + "fadd v16.4s, v28.4s, v22.4s\n" + "fadd v16.4s, v17.4s, v16.4s\n" + "fadd v8.4s, v8.4s, v16.4s\n" "11:" // Single vector of channels: Loop: After loop "ands x21, %x[n_valid_cells], #0x3\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x24, [x20], #0x8\n" - "ldr q4, [x24, x9]\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" "subs x21, x21, #0x1\n" - "fadd v8.4s, v8.4s, v4.4s\n" + "fadd v8.4s, v8.4s, v16.4s\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End "sub %x[n_channels], %x[n_channels], #0x4\n" "cmp %x[n_channels], #0x4\n" "fmul v8.4s, v8.4s, v9.4s\n" - "str q8, [%x[outptr], x9]\n" - "add x9, x9, #0x10\n" + "str q8, [%x[outptr], x27]\n" + "add x27, x27, #0x10\n" "bge 8b\n" "cbz %x[n_channels], 25f\n" "14:" // Oddments "lsr x25, %x[n_valid_cells], #0x2\n" - "add %x[outptr], %x[outptr], x9\n" + "add %x[outptr], %x[outptr], x27\n" "movi v8.16b, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "cbz x25, 18f\n" "15:" // Oddments: 4 inputs loop - "ldp x24, x23, [x20, #0x0]\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" - "add x24, x24, x9\n" - "add x23, x23, x9\n" - "add x22, x22, x9\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "add x23, x23, x27\n" + "add x22, x22, x27\n" + "add x21, x21, x27\n" "movi v4.16b, #0x0\n" "movi v3.16b, #0x0\n" - "add x21, x21, x9\n" + "add x20, x20, x27\n" "movi v28.16b, #0x0\n" "movi v22.16b, #0x0\n" "tbz %x[n_channels], #1, 16f\n" - "ldr d4, [x24], #0x8\n" - "ldr d3, [x23], #0x8\n" - "ldr d28, [x22], #0x8\n" - "ldr d22, [x21], #0x8\n" + "ldr d4, [x23], #0x8\n" + "ldr d3, [x22], #0x8\n" + "ldr d28, [x21], #0x8\n" + "ldr d22, [x20], #0x8\n" "tbz %x[n_channels], #0, 17f\n" - "ld1 { v4.s }[2], [x24], #0x4\n" - "ld1 { v3.s }[2], [x23], #0x4\n" - "ld1 { v28.s }[2], [x22], #0x4\n" - "ld1 { v22.s }[2], [x21], #0x4\n" + "ld1 { v4.s }[2], [x23], #0x4\n" + "ld1 { v3.s }[2], [x22], #0x4\n" + "ld1 { v28.s }[2], [x21], #0x4\n" + "ld1 { v22.s }[2], [x20], #0x4\n" "b 17f\n" "16:" // Oddments: 4 inputs loop: Load: Bit 1: Unset "tbz %x[n_channels], #0, 17f\n" - "ldr s4, [x24], #0x4\n" - "ldr s3, [x23], #0x4\n" - "ldr s28, [x22], #0x4\n" - "ldr s22, [x21], #0x4\n" + "ldr s4, [x23], #0x4\n" + "ldr s3, [x22], #0x4\n" + "ldr s28, [x21], #0x4\n" + "ldr s22, [x20], #0x4\n" "17:" // Oddments: 4 inputs loop: Load: Bit 1: End - "fadd v23.4s, v4.4s, v3.4s\n" - "fadd v19.4s, v28.4s, v22.4s\n" + "fadd v17.4s, v4.4s, v3.4s\n" + "fadd v16.4s, v28.4s, v22.4s\n" "subs x25, x25, #0x1\n" - "fadd v19.4s, v23.4s, v19.4s\n" - "fadd v8.4s, v8.4s, v19.4s\n" + "fadd v16.4s, v17.4s, v16.4s\n" + "fadd v8.4s, v8.4s, v16.4s\n" "bgt 15b\n" "18:" // Oddments: After loop "ands x21, %x[n_valid_cells], #0x3\n" "beq 22f\n" "19:" // Oddments: Single input loop - "ldr x24, [x20], #0x8\n" - "add x24, x24, x9\n" + "ldr x23, [x24], #0x8\n" + "add x23, x23, x27\n" "movi v4.16b, #0x0\n" "tbz %x[n_channels], #1, 20f\n" - "ldr d4, [x24], #0x8\n" + "ldr d4, [x23], #0x8\n" "tbz %x[n_channels], #0, 21f\n" - "ld1 { v4.s }[2], [x24], #0x4\n" + "ld1 { v4.s }[2], [x23], #0x4\n" "b 21f\n" "20:" // Oddments: Single input loop: Load: Bit 1: Unset "tbz %x[n_channels], #0, 21f\n" - "ldr s4, [x24], #0x4\n" + "ldr s4, [x23], #0x4\n" "21:" // Oddments: Single input loop: Load: Bit 1: End "subs x21, x21, #0x1\n" "fadd v8.4s, v8.4s, v4.4s\n" @@ -293,10 +293,11 @@ void a64_fp32_nhwc_avg_generic_depthfirst_impl( "25:" // End : [n_channels] "+&r" (n_channels), [outptr] "+&r" (outptr) : [inptrs] "r" (inptrs), [n_valid_cells] "r" (n_valid_cells), [rescale_ptr] "r" (&rescale_value) - : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x9", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" + : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); } } // namespace pooling } // namespace arm_conv + #endif // defined(__aarch64__) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst.hpp index 4bf5770857..2f72b59d70 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -24,6 +24,8 @@ #pragma once +#if defined(__aarch64__) + namespace arm_conv { namespace pooling { @@ -45,3 +47,5 @@ struct a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst : public DepthfirstStrategy } // namespace pooling } // namespace arm_conv + +#endif // defined(__aarch64__) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp index 2e7fb3c5b1..f4202de1ed 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp @@ -22,11 +22,12 @@ * SOFTWARE. */ -#if defined(__aarch64__) #include <cstddef> #include <cstdint> +#if defined(__aarch64__) + namespace arm_conv { namespace pooling { @@ -111,7 +112,7 @@ void a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst_impl( "fmax v18.4s, v18.4s, v21.4s\n" "fmax v17.4s, v17.4s, v20.4s\n" "add x15, x15, #0x10\n" - "fmax v16.4s, v16.4s, v20.4s\n" + "fmax v16.4s, v20.4s, v16.4s\n" "str q19, [x14, x12]\n" "str q18, [x13, x12]\n" "str q17, [x11, x12]\n" @@ -121,43 +122,43 @@ void a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst_impl( "2:" // Vector: Tail "fmax v21.4s, v30.4s, v29.4s\n" "fmax v20.4s, v29.4s, v28.4s\n" - "fmax v19.4s, v27.4s, v26.4s\n" + "fmax v16.4s, v27.4s, v26.4s\n" "fmax v18.4s, v25.4s, v24.4s\n" "fmax v17.4s, v27.4s, v23.4s\n" - "fmax v16.4s, v24.4s, v22.4s\n" - "fmax v19.4s, v21.4s, v19.4s\n" + "fmax v19.4s, v24.4s, v22.4s\n" + "fmax v16.4s, v21.4s, v16.4s\n" "fmax v18.4s, v18.4s, v21.4s\n" - "str q19, [x14, x12]\n" + "str q16, [x14, x12]\n" "fmax v17.4s, v17.4s, v20.4s\n" - "fmax v16.4s, v16.4s, v20.4s\n" + "fmax v16.4s, v20.4s, v19.4s\n" "str q18, [x13, x12]\n" "str q17, [x11, x12]\n" "str q16, [x10, x12]\n" "add x12, x12, #0x10\n" "cbz x16, 4f\n" "3:" // Oddments - "ldr s30, [x28, x15]\n" - "ldr s29, [x25, x15]\n" - "fmax v21.4s, v30.4s, v29.4s\n" + "ldr s16, [x28, x15]\n" + "ldr s17, [x25, x15]\n" + "fmax v23.4s, v16.4s, v17.4s\n" "subs x16, x16, #0x1\n" - "ldr s28, [x22, x15]\n" - "ldr s27, [x26, x15]\n" - "fmax v20.4s, v29.4s, v28.4s\n" - "ldr s26, [x9, x15]\n" - "ldr s25, [x27, x15]\n" - "fmax v19.4s, v27.4s, v26.4s\n" - "fmax v19.4s, v21.4s, v19.4s\n" - "ldr s24, [x24, x15]\n" - "ldr s23, [x23, x15]\n" - "fmax v18.4s, v25.4s, v24.4s\n" - "fmax v17.4s, v27.4s, v23.4s\n" - "ldr s22, [x21, x15]\n" - "fmax v16.4s, v24.4s, v22.4s\n" + "ldr s16, [x22, x15]\n" + "ldr s22, [x26, x15]\n" + "fmax v21.4s, v17.4s, v16.4s\n" + "ldr s16, [x9, x15]\n" + "ldr s17, [x27, x15]\n" + "fmax v16.4s, v22.4s, v16.4s\n" + "fmax v20.4s, v23.4s, v16.4s\n" + "ldr s19, [x24, x15]\n" + "ldr s16, [x23, x15]\n" + "fmax v18.4s, v17.4s, v19.4s\n" + "fmax v17.4s, v22.4s, v16.4s\n" + "ldr s16, [x21, x15]\n" + "fmax v16.4s, v19.4s, v16.4s\n" "add x15, x15, #0x4\n" - "fmax v18.4s, v18.4s, v21.4s\n" - "fmax v17.4s, v17.4s, v20.4s\n" - "fmax v16.4s, v16.4s, v20.4s\n" - "str s19, [x14, x12]\n" + "fmax v18.4s, v18.4s, v23.4s\n" + "fmax v17.4s, v17.4s, v21.4s\n" + "fmax v16.4s, v21.4s, v16.4s\n" + "str s20, [x14, x12]\n" "str s18, [x13, x12]\n" "str s17, [x11, x12]\n" "str s16, [x10, x12]\n" @@ -172,4 +173,5 @@ void a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst_impl( } // namespace pooling } // namespace arm_conv + #endif // defined(__aarch64__) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_generic_depthfirst/generic.cpp index 4f1af09e08..f4706635dc 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_generic_depthfirst/generic.cpp @@ -22,11 +22,11 @@ * SOFTWARE. */ -#if defined(__aarch64__) - #include <cstdint> #include <cstddef> +#if defined(__aarch64__) + namespace arm_conv { namespace pooling { @@ -41,10 +41,10 @@ void a64_fp32_nhwc_max_generic_depthfirst_impl( { __asm__ __volatile__( "cmp %x[n_channels], #0x10\n" - "mov x9, #0x0\n" - "mov x28, #0x10\n" // cntb _, ALL, #1 - "mov x27, #0x20\n" // cntb _, ALL, #2 - "mov x26, #0x30\n" // cntb _, ALL, #3 + "mov x27, #0x0\n" + "mov x26, #0x10\n" // cntb _, ALL, #1 + "mov x24, #0x20\n" // cntb _, ALL, #2 + "mov x23, #0x30\n" // cntb _, ALL, #3 "blt 7f\n" "1:" // 4-vectors of channels "mov w20, #0xff800000\n" @@ -53,66 +53,66 @@ void a64_fp32_nhwc_max_generic_depthfirst_impl( "dup v7.4s, w20\n" "dup v6.4s, w20\n" "dup v5.4s, w20\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "cbz x25, 4f\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldr q4, [x24, x9]\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" "subs x25, x25, #0x1\n" - "ldr q3, [x23, x9]\n" - "ldr q2, [x24, x28]\n" - "ldr q1, [x23, x28]\n" - "ldr q0, [x24, x27]\n" - "ldr q31, [x23, x27]\n" - "ldr q30, [x24, x26]\n" - "ldr q29, [x23, x26]\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" - "ldr q28, [x22, x9]\n" - "ldr q22, [x21, x9]\n" - "ldr q27, [x22, x28]\n" - "ldr q21, [x21, x28]\n" - "ldr q26, [x22, x27]\n" - "ldr q20, [x21, x27]\n" - "ldr q25, [x22, x26]\n" - "ldr q24, [x21, x26]\n" + "ldr q3, [x20, x27]\n" + "ldr q2, [x21, x26]\n" + "ldr q1, [x20, x26]\n" + "ldr q0, [x21, x24]\n" + "ldr q31, [x20, x24]\n" + "ldr q30, [x21, x23]\n" + "ldr q29, [x20, x23]\n" + "ldp x21, x20, [x22, #0x10]\n" + "add x22, x22, #0x20\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" + "ldr q27, [x21, x26]\n" + "ldr q21, [x20, x26]\n" + "ldr q26, [x21, x24]\n" + "ldr q20, [x20, x24]\n" + "ldr q25, [x21, x23]\n" + "ldr q24, [x20, x23]\n" "beq 3f\n" "2:" // 4-vectors of channels: 4 inputs loop "fmax v23.4s, v4.4s, v3.4s\n" "fmax v19.4s, v28.4s, v22.4s\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldr q4, [x24, x9]\n" - "ldr q3, [x23, x9]\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "ldr q3, [x20, x27]\n" "fmax v22.4s, v2.4s, v1.4s\n" - "ldr q2, [x24, x28]\n" + "ldr q2, [x21, x26]\n" "fmax v18.4s, v27.4s, v21.4s\n" - "ldr q1, [x23, x28]\n" + "ldr q1, [x20, x26]\n" "fmax v21.4s, v0.4s, v31.4s\n" - "ldr q0, [x24, x27]\n" + "ldr q0, [x21, x24]\n" "fmax v17.4s, v26.4s, v20.4s\n" - "ldr q31, [x23, x27]\n" + "ldr q31, [x20, x24]\n" "fmax v20.4s, v30.4s, v29.4s\n" - "ldr q30, [x24, x26]\n" + "ldr q30, [x21, x23]\n" "fmax v16.4s, v25.4s, v24.4s\n" - "ldr q29, [x23, x26]\n" + "ldr q29, [x20, x23]\n" "fmax v19.4s, v23.4s, v19.4s\n" "fmax v18.4s, v22.4s, v18.4s\n" - "ldp x22, x21, [x20, #0x10]\n" - "ldr q28, [x22, x9]\n" - "ldr q22, [x21, x9]\n" + "ldp x21, x20, [x22, #0x10]\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" "fmax v17.4s, v21.4s, v17.4s\n" "fmax v16.4s, v20.4s, v16.4s\n" - "ldr q27, [x22, x28]\n" - "ldr q21, [x21, x28]\n" + "ldr q27, [x21, x26]\n" + "ldr q21, [x20, x26]\n" "subs x25, x25, #0x1\n" "fmax v8.4s, v8.4s, v19.4s\n" - "ldr q26, [x22, x27]\n" - "ldr q20, [x21, x27]\n" + "ldr q26, [x21, x24]\n" + "ldr q20, [x20, x24]\n" "fmax v7.4s, v7.4s, v18.4s\n" "fmax v6.4s, v6.4s, v17.4s\n" - "ldr q25, [x22, x26]\n" - "ldr q24, [x21, x26]\n" + "ldr q25, [x21, x23]\n" + "ldr q24, [x20, x23]\n" "fmax v5.4s, v5.4s, v16.4s\n" - "add x20, x20, #0x20\n" + "add x22, x22, #0x20\n" "bgt 2b\n" "3:" // 4-vectors of channels: 4 inputs tail "fmax v23.4s, v4.4s, v3.4s\n" @@ -135,28 +135,28 @@ void a64_fp32_nhwc_max_generic_depthfirst_impl( "ands x21, %x[n_valid_cells], #0x3\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x24, [x20], #0x8\n" - "ldr q4, [x24, x9]\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" "subs x21, x21, #0x1\n" - "fmax v8.4s, v8.4s, v4.4s\n" - "ldr q2, [x24, x28]\n" - "ldr q0, [x24, x27]\n" - "fmax v7.4s, v7.4s, v2.4s\n" - "fmax v6.4s, v6.4s, v0.4s\n" - "ldr q30, [x24, x26]\n" - "fmax v5.4s, v5.4s, v30.4s\n" + "fmax v8.4s, v8.4s, v16.4s\n" + "ldr q17, [x20, x26]\n" + "ldr q16, [x20, x24]\n" + "fmax v7.4s, v7.4s, v17.4s\n" + "fmax v6.4s, v6.4s, v16.4s\n" + "ldr q16, [x20, x23]\n" + "fmax v5.4s, v5.4s, v16.4s\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End "sub %x[n_channels], %x[n_channels], #0x10\n" "cmp %x[n_channels], #0x10\n" - "str q8, [%x[outptr], x9]\n" - "str q7, [%x[outptr], x28]\n" - "add x9, x9, #0x40\n" - "add x28, x28, #0x40\n" - "str q6, [%x[outptr], x27]\n" + "str q8, [%x[outptr], x27]\n" + "str q7, [%x[outptr], x26]\n" "add x27, x27, #0x40\n" - "str q5, [%x[outptr], x26]\n" "add x26, x26, #0x40\n" + "str q6, [%x[outptr], x24]\n" + "add x24, x24, #0x40\n" + "str q5, [%x[outptr], x23]\n" + "add x23, x23, #0x40\n" "bge 1b\n" "cbz %x[n_channels], 25f\n" "7:" // Single vector of channels @@ -166,110 +166,110 @@ void a64_fp32_nhwc_max_generic_depthfirst_impl( "mov w20, #0xff800000\n" "lsr x25, %x[n_valid_cells], #0x2\n" "dup v8.4s, w20\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "cbz x25, 11f\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldr q4, [x24, x9]\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" "subs x25, x25, #0x1\n" - "ldr q3, [x23, x9]\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" - "ldr q28, [x22, x9]\n" - "ldr q22, [x21, x9]\n" + "ldr q3, [x20, x27]\n" + "ldp x21, x20, [x22, #0x10]\n" + "add x22, x22, #0x20\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 4 inputs loop - "fmax v23.4s, v4.4s, v3.4s\n" - "fmax v19.4s, v28.4s, v22.4s\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldr q4, [x24, x9]\n" - "ldr q3, [x23, x9]\n" - "fmax v19.4s, v23.4s, v19.4s\n" - "ldp x22, x21, [x20, #0x10]\n" + "fmax v17.4s, v4.4s, v3.4s\n" + "fmax v16.4s, v28.4s, v22.4s\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "ldr q3, [x20, x27]\n" + "fmax v16.4s, v17.4s, v16.4s\n" + "ldp x21, x20, [x22, #0x10]\n" "subs x25, x25, #0x1\n" - "ldr q28, [x22, x9]\n" - "ldr q22, [x21, x9]\n" - "fmax v8.4s, v8.4s, v19.4s\n" - "add x20, x20, #0x20\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" + "fmax v8.4s, v8.4s, v16.4s\n" + "add x22, x22, #0x20\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 4 inputs tail - "fmax v23.4s, v4.4s, v3.4s\n" - "fmax v19.4s, v28.4s, v22.4s\n" - "fmax v19.4s, v23.4s, v19.4s\n" - "fmax v8.4s, v8.4s, v19.4s\n" + "fmax v17.4s, v4.4s, v3.4s\n" + "fmax v16.4s, v28.4s, v22.4s\n" + "fmax v16.4s, v17.4s, v16.4s\n" + "fmax v8.4s, v8.4s, v16.4s\n" "11:" // Single vector of channels: Loop: After loop "ands x21, %x[n_valid_cells], #0x3\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x24, [x20], #0x8\n" - "ldr q4, [x24, x9]\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" "subs x21, x21, #0x1\n" - "fmax v8.4s, v8.4s, v4.4s\n" + "fmax v8.4s, v8.4s, v16.4s\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End "sub %x[n_channels], %x[n_channels], #0x4\n" "cmp %x[n_channels], #0x4\n" - "str q8, [%x[outptr], x9]\n" - "add x9, x9, #0x10\n" + "str q8, [%x[outptr], x27]\n" + "add x27, x27, #0x10\n" "bge 8b\n" "cbz %x[n_channels], 25f\n" "14:" // Oddments "mov w20, #0xff800000\n" "lsr x25, %x[n_valid_cells], #0x2\n" "dup v8.4s, w20\n" - "add %x[outptr], %x[outptr], x9\n" - "mov x20, %x[inptrs]\n" + "add %x[outptr], %x[outptr], x27\n" + "mov x24, %x[inptrs]\n" "cbz x25, 18f\n" "15:" // Oddments: 4 inputs loop - "ldp x24, x23, [x20, #0x0]\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" - "add x24, x24, x9\n" - "add x23, x23, x9\n" - "add x22, x22, x9\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "add x23, x23, x27\n" + "add x22, x22, x27\n" + "add x21, x21, x27\n" "movi v4.16b, #0x0\n" "movi v3.16b, #0x0\n" - "add x21, x21, x9\n" + "add x20, x20, x27\n" "movi v28.16b, #0x0\n" "movi v22.16b, #0x0\n" "tbz %x[n_channels], #1, 16f\n" - "ldr d4, [x24], #0x8\n" - "ldr d3, [x23], #0x8\n" - "ldr d28, [x22], #0x8\n" - "ldr d22, [x21], #0x8\n" + "ldr d4, [x23], #0x8\n" + "ldr d3, [x22], #0x8\n" + "ldr d28, [x21], #0x8\n" + "ldr d22, [x20], #0x8\n" "tbz %x[n_channels], #0, 17f\n" - "ld1 { v4.s }[2], [x24], #0x4\n" - "ld1 { v3.s }[2], [x23], #0x4\n" - "ld1 { v28.s }[2], [x22], #0x4\n" - "ld1 { v22.s }[2], [x21], #0x4\n" + "ld1 { v4.s }[2], [x23], #0x4\n" + "ld1 { v3.s }[2], [x22], #0x4\n" + "ld1 { v28.s }[2], [x21], #0x4\n" + "ld1 { v22.s }[2], [x20], #0x4\n" "b 17f\n" "16:" // Oddments: 4 inputs loop: Load: Bit 1: Unset "tbz %x[n_channels], #0, 17f\n" - "ldr s4, [x24], #0x4\n" - "ldr s3, [x23], #0x4\n" - "ldr s28, [x22], #0x4\n" - "ldr s22, [x21], #0x4\n" + "ldr s4, [x23], #0x4\n" + "ldr s3, [x22], #0x4\n" + "ldr s28, [x21], #0x4\n" + "ldr s22, [x20], #0x4\n" "17:" // Oddments: 4 inputs loop: Load: Bit 1: End - "fmax v23.4s, v4.4s, v3.4s\n" - "fmax v19.4s, v28.4s, v22.4s\n" + "fmax v17.4s, v4.4s, v3.4s\n" + "fmax v16.4s, v28.4s, v22.4s\n" "subs x25, x25, #0x1\n" - "fmax v19.4s, v23.4s, v19.4s\n" - "fmax v8.4s, v8.4s, v19.4s\n" + "fmax v16.4s, v17.4s, v16.4s\n" + "fmax v8.4s, v8.4s, v16.4s\n" "bgt 15b\n" "18:" // Oddments: After loop "ands x21, %x[n_valid_cells], #0x3\n" "beq 22f\n" "19:" // Oddments: Single input loop - "ldr x24, [x20], #0x8\n" - "add x24, x24, x9\n" + "ldr x23, [x24], #0x8\n" + "add x23, x23, x27\n" "movi v4.16b, #0x0\n" "tbz %x[n_channels], #1, 20f\n" - "ldr d4, [x24], #0x8\n" + "ldr d4, [x23], #0x8\n" "tbz %x[n_channels], #0, 21f\n" - "ld1 { v4.s }[2], [x24], #0x4\n" + "ld1 { v4.s }[2], [x23], #0x4\n" "b 21f\n" "20:" // Oddments: Single input loop: Load: Bit 1: Unset "tbz %x[n_channels], #0, 21f\n" - "ldr s4, [x24], #0x4\n" + "ldr s4, [x23], #0x4\n" "21:" // Oddments: Single input loop: Load: Bit 1: End "subs x21, x21, #0x1\n" "fmax v8.4s, v8.4s, v4.4s\n" @@ -287,10 +287,11 @@ void a64_fp32_nhwc_max_generic_depthfirst_impl( "25:" // End : [n_channels] "+&r" (n_channels), [outptr] "+&r" (outptr) : [inptrs] "r" (inptrs), [n_valid_cells] "r" (n_valid_cells) - : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x9", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" + : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); } } // namespace pooling } // namespace arm_conv + #endif // defined(__aarch64__) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8_nhwc_avg_generic_depthfirst/generic.cpp index 5a7e5f981b..5d082102b3 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8_nhwc_avg_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8_nhwc_avg_generic_depthfirst/generic.cpp @@ -22,14 +22,14 @@ * SOFTWARE. */ -#if defined(__aarch64__) - #include <cstdint> #include <cstddef> #include <cstring> #include <cmath> +#if defined(__aarch64__) + namespace arm_conv { namespace pooling { @@ -105,7 +105,7 @@ void a64_s8_nhwc_avg_generic_depthfirst_impl( "lsr x23, %x[n_valid_cells], #0x1\n" "movi v15.4s, #0x0\n" "movi v14.4s, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "movi v13.4s, #0x0\n" "movi v12.4s, #0x0\n" "movi v11.4s, #0x0\n" @@ -121,42 +121,42 @@ void a64_s8_nhwc_avg_generic_depthfirst_impl( "movi v1.4s, #0x0\n" "movi v0.4s, #0x0\n" "cbz x23, 4f\n" - "ldp x22, x21, [x20, #0x0]\n" - "ldr q31, [x22, x27]\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q31, [x21, x27]\n" "subs x23, x23, #0x1\n" - "add x20, x20, #0x10\n" - "ldr q30, [x21, x27]\n" - "ldr q29, [x22, x26]\n" - "ldr q28, [x21, x26]\n" - "ldr q27, [x22, x25]\n" - "ldr q26, [x21, x25]\n" - "ldr q25, [x22, x24]\n" - "ldr q24, [x21, x24]\n" + "add x22, x22, #0x10\n" + "ldr q30, [x20, x27]\n" + "ldr q29, [x21, x26]\n" + "ldr q28, [x20, x26]\n" + "ldr q27, [x21, x25]\n" + "ldr q26, [x20, x25]\n" + "ldr q25, [x21, x24]\n" + "ldr q24, [x20, x24]\n" "beq 3f\n" "2:" // 4-vectors of channels: 2 inputs loop "saddl v23.8h, v31.8b, v30.8b\n" "saddl2 v22.8h, v31.16b, v30.16b\n" - "ldp x22, x21, [x20, #0x0]\n" - "ldr q31, [x22, x27]\n" - "ldr q30, [x21, x27]\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q31, [x21, x27]\n" + "ldr q30, [x20, x27]\n" "saddl v21.8h, v29.8b, v28.8b\n" "saddl2 v20.8h, v29.16b, v28.16b\n" - "ldr q29, [x22, x26]\n" - "ldr q28, [x21, x26]\n" + "ldr q29, [x21, x26]\n" + "ldr q28, [x20, x26]\n" "saddl v19.8h, v27.8b, v26.8b\n" "saddl2 v18.8h, v27.16b, v26.16b\n" - "ldr q27, [x22, x25]\n" - "ldr q26, [x21, x25]\n" + "ldr q27, [x21, x25]\n" + "ldr q26, [x20, x25]\n" + "saddl v17.8h, v25.8b, v24.8b\n" + "saddl2 v16.8h, v25.16b, v24.16b\n" + "ldr q25, [x21, x24]\n" + "ldr q24, [x20, x24]\n" "subs x23, x23, #0x1\n" "saddw v15.4s, v15.4s, v23.4h\n" "saddw2 v14.4s, v14.4s, v23.8h\n" - "saddl v17.8h, v25.8b, v24.8b\n" - "saddl2 v16.8h, v25.16b, v24.16b\n" - "ldr q25, [x22, x24]\n" - "add x20, x20, #0x10\n" "saddw v13.4s, v13.4s, v22.4h\n" "saddw2 v12.4s, v12.4s, v22.8h\n" - "ldr q24, [x21, x24]\n" + "add x22, x22, #0x10\n" "saddw v11.4s, v11.4s, v21.4h\n" "saddw2 v10.4s, v10.4s, v21.8h\n" "saddw v9.4s, v9.4s, v20.4h\n" @@ -196,23 +196,23 @@ void a64_s8_nhwc_avg_generic_depthfirst_impl( "saddw v1.4s, v1.4s, v16.4h\n" "saddw2 v0.4s, v0.4s, v16.8h\n" "4:" // 4-vectors of channels: After loop - "ands x21, %x[n_valid_cells], #0x1\n" + "ands x23, %x[n_valid_cells], #0x1\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x22, [x20], #0x8\n" - "ldr q31, [x22, x27]\n" - "sxtl v23.8h, v31.8b\n" - "sxtl2 v22.8h, v31.16b\n" - "ldr q29, [x22, x26]\n" - "ldr q27, [x22, x25]\n" - "sxtl v21.8h, v29.8b\n" - "sxtl2 v20.8h, v29.16b\n" - "ldr q25, [x22, x24]\n" - "sxtl v19.8h, v27.8b\n" - "sxtl2 v18.8h, v27.16b\n" - "subs x21, x21, #0x1\n" - "sxtl v17.8h, v25.8b\n" - "sxtl2 v16.8h, v25.16b\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" + "sxtl v23.8h, v16.8b\n" + "sxtl2 v22.8h, v16.16b\n" + "ldr q16, [x20, x26]\n" + "ldr q17, [x20, x25]\n" + "sxtl v21.8h, v16.8b\n" + "sxtl2 v20.8h, v16.16b\n" + "ldr q16, [x20, x24]\n" + "sxtl v19.8h, v17.8b\n" + "sxtl2 v18.8h, v17.16b\n" + "subs x23, x23, #0x1\n" + "sxtl v17.8h, v16.8b\n" + "sxtl2 v16.8h, v16.16b\n" "saddw v15.4s, v15.4s, v23.4h\n" "saddw2 v14.4s, v14.4s, v23.8h\n" "saddw v13.4s, v13.4s, v22.4h\n" @@ -330,49 +330,49 @@ void a64_s8_nhwc_avg_generic_depthfirst_impl( "lsr x23, %x[n_valid_cells], #0x1\n" "movi v15.4s, #0x0\n" "movi v14.4s, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "movi v13.4s, #0x0\n" "movi v12.4s, #0x0\n" "cbz x23, 11f\n" - "ldp x22, x21, [x20, #0x0]\n" - "ldr q31, [x22, x27]\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q31, [x21, x27]\n" "subs x23, x23, #0x1\n" - "add x20, x20, #0x10\n" - "ldr q30, [x21, x27]\n" + "add x22, x22, #0x10\n" + "ldr q30, [x20, x27]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 2 inputs loop - "saddl v23.8h, v31.8b, v30.8b\n" - "saddl2 v22.8h, v31.16b, v30.16b\n" - "ldp x22, x21, [x20, #0x0]\n" - "ldr q31, [x22, x27]\n" - "ldr q30, [x21, x27]\n" + "saddl v17.8h, v31.8b, v30.8b\n" + "saddl2 v16.8h, v31.16b, v30.16b\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q31, [x21, x27]\n" + "ldr q30, [x20, x27]\n" "subs x23, x23, #0x1\n" - "saddw v15.4s, v15.4s, v23.4h\n" - "saddw2 v14.4s, v14.4s, v23.8h\n" - "saddw v13.4s, v13.4s, v22.4h\n" - "saddw2 v12.4s, v12.4s, v22.8h\n" - "add x20, x20, #0x10\n" + "saddw v15.4s, v15.4s, v17.4h\n" + "saddw2 v14.4s, v14.4s, v17.8h\n" + "saddw v13.4s, v13.4s, v16.4h\n" + "saddw2 v12.4s, v12.4s, v16.8h\n" + "add x22, x22, #0x10\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 2 inputs tail - "saddl v23.8h, v31.8b, v30.8b\n" - "saddl2 v22.8h, v31.16b, v30.16b\n" - "saddw v15.4s, v15.4s, v23.4h\n" - "saddw2 v14.4s, v14.4s, v23.8h\n" - "saddw v13.4s, v13.4s, v22.4h\n" - "saddw2 v12.4s, v12.4s, v22.8h\n" + "saddl v17.8h, v31.8b, v30.8b\n" + "saddl2 v16.8h, v31.16b, v30.16b\n" + "saddw v15.4s, v15.4s, v17.4h\n" + "saddw2 v14.4s, v14.4s, v17.8h\n" + "saddw v13.4s, v13.4s, v16.4h\n" + "saddw2 v12.4s, v12.4s, v16.8h\n" "11:" // Single vector of channels: Loop: After loop - "ands x21, %x[n_valid_cells], #0x1\n" + "ands x23, %x[n_valid_cells], #0x1\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x22, [x20], #0x8\n" - "ldr q31, [x22, x27]\n" - "sxtl v23.8h, v31.8b\n" - "sxtl2 v22.8h, v31.16b\n" - "subs x21, x21, #0x1\n" - "saddw v15.4s, v15.4s, v23.4h\n" - "saddw2 v14.4s, v14.4s, v23.8h\n" - "saddw v13.4s, v13.4s, v22.4h\n" - "saddw2 v12.4s, v12.4s, v22.8h\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" + "sxtl v17.8h, v16.8b\n" + "sxtl2 v16.8h, v16.16b\n" + "subs x23, x23, #0x1\n" + "saddw v15.4s, v15.4s, v17.4h\n" + "saddw2 v14.4s, v14.4s, v17.8h\n" + "saddw v13.4s, v13.4s, v16.4h\n" + "saddw2 v12.4s, v12.4s, v16.8h\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End "ld1r { v17.4s }, [%x[rescale_ptr]]\n" @@ -397,9 +397,9 @@ void a64_s8_nhwc_avg_generic_depthfirst_impl( "smin v14.4s, v14.4s, v17.4s\n" "smin v13.4s, v13.4s, v17.4s\n" "smin v12.4s, v12.4s, v17.4s\n" - "uzp1 v23.16b, v15.16b, v14.16b\n" + "uzp1 v17.16b, v15.16b, v14.16b\n" "uzp1 v16.16b, v13.16b, v12.16b\n" - "uzp1 v16.16b, v23.16b, v16.16b\n" + "uzp1 v16.16b, v17.16b, v16.16b\n" "str q16, [%x[outptr], x27]\n" "add x27, x27, #0x10\n" "bge 8b\n" @@ -411,142 +411,142 @@ void a64_s8_nhwc_avg_generic_depthfirst_impl( "movi v14.4s, #0x0\n" "movi v13.4s, #0x0\n" "movi v12.4s, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "cbz x23, 24f\n" "15:" // Oddments: 2 inputs loop - "ldp x22, x21, [x20, #0x0]\n" - "add x20, x20, #0x10\n" - "add x22, x22, x27\n" - "movi v31.16b, #0x0\n" + "ldp x21, x20, [x22, #0x0]\n" + "add x22, x22, #0x10\n" "add x21, x21, x27\n" + "movi v31.16b, #0x0\n" + "add x20, x20, x27\n" "movi v30.16b, #0x0\n" "tbz %x[n_channels], #3, 19f\n" - "ldr d31, [x22], #0x8\n" - "ldr d30, [x21], #0x8\n" + "ldr d31, [x21], #0x8\n" + "ldr d30, [x20], #0x8\n" "tbz %x[n_channels], #2, 17f\n" - "ld1 { v31.s }[2], [x22], #0x4\n" - "ld1 { v30.s }[2], [x21], #0x4\n" + "ld1 { v31.s }[2], [x21], #0x4\n" + "ld1 { v30.s }[2], [x20], #0x4\n" "tbz %x[n_channels], #1, 16f\n" - "ld1 { v31.h }[6], [x22], #0x2\n" - "ld1 { v30.h }[6], [x21], #0x2\n" + "ld1 { v31.h }[6], [x21], #0x2\n" + "ld1 { v30.h }[6], [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v31.b }[14], [x22], #0x1\n" - "ld1 { v30.b }[14], [x21], #0x1\n" + "ld1 { v31.b }[14], [x21], #0x1\n" + "ld1 { v30.b }[14], [x20], #0x1\n" "b 23f\n" "16:" // Oddments: 2 inputs loop: Load: Bit 3: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ld1 { v31.b }[12], [x22], #0x1\n" - "ld1 { v30.b }[12], [x21], #0x1\n" + "ld1 { v31.b }[12], [x21], #0x1\n" + "ld1 { v30.b }[12], [x20], #0x1\n" "b 23f\n" "17:" // Oddments: 2 inputs loop: Load: Bit 3: Bit 2: Unset "tbz %x[n_channels], #1, 18f\n" - "ld1 { v31.h }[4], [x22], #0x2\n" - "ld1 { v30.h }[4], [x21], #0x2\n" + "ld1 { v31.h }[4], [x21], #0x2\n" + "ld1 { v30.h }[4], [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v31.b }[10], [x22], #0x1\n" - "ld1 { v30.b }[10], [x21], #0x1\n" + "ld1 { v31.b }[10], [x21], #0x1\n" + "ld1 { v30.b }[10], [x20], #0x1\n" "b 23f\n" "18:" // Oddments: 2 inputs loop: Load: Bit 3: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ld1 { v31.b }[8], [x22], #0x1\n" - "ld1 { v30.b }[8], [x21], #0x1\n" + "ld1 { v31.b }[8], [x21], #0x1\n" + "ld1 { v30.b }[8], [x20], #0x1\n" "b 23f\n" "19:" // Oddments: 2 inputs loop: Load: Bit 3: Unset "tbz %x[n_channels], #2, 21f\n" - "ldr s31, [x22], #0x4\n" - "ldr s30, [x21], #0x4\n" + "ldr s31, [x21], #0x4\n" + "ldr s30, [x20], #0x4\n" "tbz %x[n_channels], #1, 20f\n" - "ld1 { v31.h }[2], [x22], #0x2\n" - "ld1 { v30.h }[2], [x21], #0x2\n" + "ld1 { v31.h }[2], [x21], #0x2\n" + "ld1 { v30.h }[2], [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v31.b }[6], [x22], #0x1\n" - "ld1 { v30.b }[6], [x21], #0x1\n" + "ld1 { v31.b }[6], [x21], #0x1\n" + "ld1 { v30.b }[6], [x20], #0x1\n" "b 23f\n" "20:" // Oddments: 2 inputs loop: Load: Bit 3: Unset: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ld1 { v31.b }[4], [x22], #0x1\n" - "ld1 { v30.b }[4], [x21], #0x1\n" + "ld1 { v31.b }[4], [x21], #0x1\n" + "ld1 { v30.b }[4], [x20], #0x1\n" "b 23f\n" "21:" // Oddments: 2 inputs loop: Load: Bit 3: Unset: Bit 2: Unset "tbz %x[n_channels], #1, 22f\n" - "ldr h31, [x22], #0x2\n" - "ldr h30, [x21], #0x2\n" + "ldr h31, [x21], #0x2\n" + "ldr h30, [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v31.b }[2], [x22], #0x1\n" - "ld1 { v30.b }[2], [x21], #0x1\n" + "ld1 { v31.b }[2], [x21], #0x1\n" + "ld1 { v30.b }[2], [x20], #0x1\n" "b 23f\n" "22:" // Oddments: 2 inputs loop: Load: Bit 3: Unset: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ldr b31, [x22], #0x1\n" - "ldr b30, [x21], #0x1\n" + "ldr b31, [x21], #0x1\n" + "ldr b30, [x20], #0x1\n" "23:" // Oddments: 2 inputs loop: Load: Bit 3: End - "saddl v23.8h, v31.8b, v30.8b\n" - "saddl2 v22.8h, v31.16b, v30.16b\n" + "saddl v17.8h, v31.8b, v30.8b\n" + "saddl2 v16.8h, v31.16b, v30.16b\n" "subs x23, x23, #0x1\n" - "saddw v15.4s, v15.4s, v23.4h\n" - "saddw2 v14.4s, v14.4s, v23.8h\n" - "saddw v13.4s, v13.4s, v22.4h\n" - "saddw2 v12.4s, v12.4s, v22.8h\n" + "saddw v15.4s, v15.4s, v17.4h\n" + "saddw2 v14.4s, v14.4s, v17.8h\n" + "saddw v13.4s, v13.4s, v16.4h\n" + "saddw2 v12.4s, v12.4s, v16.8h\n" "bgt 15b\n" "24:" // Oddments: After loop - "ands x21, %x[n_valid_cells], #0x1\n" + "ands x23, %x[n_valid_cells], #0x1\n" "beq 34f\n" "25:" // Oddments: Single input loop - "ldr x22, [x20], #0x8\n" - "add x22, x22, x27\n" + "ldr x21, [x22], #0x8\n" + "add x21, x21, x27\n" "movi v31.16b, #0x0\n" "tbz %x[n_channels], #3, 29f\n" - "ldr d31, [x22], #0x8\n" + "ldr d31, [x21], #0x8\n" "tbz %x[n_channels], #2, 27f\n" - "ld1 { v31.s }[2], [x22], #0x4\n" + "ld1 { v31.s }[2], [x21], #0x4\n" "tbz %x[n_channels], #1, 26f\n" - "ld1 { v31.h }[6], [x22], #0x2\n" + "ld1 { v31.h }[6], [x21], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v31.b }[14], [x22], #0x1\n" + "ld1 { v31.b }[14], [x21], #0x1\n" "b 33f\n" "26:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ld1 { v31.b }[12], [x22], #0x1\n" + "ld1 { v31.b }[12], [x21], #0x1\n" "b 33f\n" "27:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Unset "tbz %x[n_channels], #1, 28f\n" - "ld1 { v31.h }[4], [x22], #0x2\n" + "ld1 { v31.h }[4], [x21], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v31.b }[10], [x22], #0x1\n" + "ld1 { v31.b }[10], [x21], #0x1\n" "b 33f\n" "28:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ld1 { v31.b }[8], [x22], #0x1\n" + "ld1 { v31.b }[8], [x21], #0x1\n" "b 33f\n" "29:" // Oddments: Single input loop: Load: Bit 3: Unset "tbz %x[n_channels], #2, 31f\n" - "ldr s31, [x22], #0x4\n" + "ldr s31, [x21], #0x4\n" "tbz %x[n_channels], #1, 30f\n" - "ld1 { v31.h }[2], [x22], #0x2\n" + "ld1 { v31.h }[2], [x21], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v31.b }[6], [x22], #0x1\n" + "ld1 { v31.b }[6], [x21], #0x1\n" "b 33f\n" "30:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ld1 { v31.b }[4], [x22], #0x1\n" + "ld1 { v31.b }[4], [x21], #0x1\n" "b 33f\n" "31:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Unset "tbz %x[n_channels], #1, 32f\n" - "ldr h31, [x22], #0x2\n" + "ldr h31, [x21], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v31.b }[2], [x22], #0x1\n" + "ld1 { v31.b }[2], [x21], #0x1\n" "b 33f\n" "32:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ldr b31, [x22], #0x1\n" + "ldr b31, [x21], #0x1\n" "33:" // Oddments: Single input loop: Load: Bit 3: End - "sxtl v23.8h, v31.8b\n" - "sxtl2 v22.8h, v31.16b\n" - "subs x21, x21, #0x1\n" - "saddw v15.4s, v15.4s, v23.4h\n" - "saddw2 v14.4s, v14.4s, v23.8h\n" - "saddw v13.4s, v13.4s, v22.4h\n" - "saddw2 v12.4s, v12.4s, v22.8h\n" + "sxtl v17.8h, v31.8b\n" + "sxtl2 v16.8h, v31.16b\n" + "subs x23, x23, #0x1\n" + "saddw v15.4s, v15.4s, v17.4h\n" + "saddw2 v14.4s, v14.4s, v17.8h\n" + "saddw v13.4s, v13.4s, v16.4h\n" + "saddw2 v12.4s, v12.4s, v16.8h\n" "bgt 25b\n" "34:" // Oddments: Single input loop: End "ld1r { v17.4s }, [%x[rescale_ptr]]\n" @@ -569,9 +569,9 @@ void a64_s8_nhwc_avg_generic_depthfirst_impl( "smin v14.4s, v14.4s, v17.4s\n" "smin v13.4s, v13.4s, v17.4s\n" "smin v12.4s, v12.4s, v17.4s\n" - "uzp1 v23.16b, v15.16b, v14.16b\n" + "uzp1 v17.16b, v15.16b, v14.16b\n" "uzp1 v16.16b, v13.16b, v12.16b\n" - "uzp1 v16.16b, v23.16b, v16.16b\n" + "uzp1 v16.16b, v17.16b, v16.16b\n" "tbz %x[n_channels], #3, 38f\n" "st1 { v16.d }[0], [%x[outptr]], #0x8\n" "tbz %x[n_channels], #2, 36f\n" @@ -626,4 +626,5 @@ void a64_s8_nhwc_avg_generic_depthfirst_impl( } // namespace pooling } // namespace arm_conv + #endif // defined(__aarch64__) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp index 234b4442c8..f8f1134866 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -24,6 +24,8 @@ #pragma once +#if defined(__aarch64__) + namespace arm_conv { namespace pooling { @@ -45,3 +47,5 @@ struct a64_s8_nhwc_max_2x2_s1_output2x2_depthfirst : public DepthfirstStrategy<i } // namespace pooling } // namespace arm_conv + +#endif // defined(__aarch64__) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp index bd14408c74..7e62ac1afc 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp @@ -22,11 +22,12 @@ * SOFTWARE. */ -#if defined(__aarch64__) #include <cstddef> #include <cstdint> +#if defined(__aarch64__) + namespace arm_conv { namespace pooling { @@ -111,7 +112,7 @@ void a64_s8_nhwc_max_2x2_s1_output2x2_depthfirst_impl( "smax v18.16b, v18.16b, v21.16b\n" "smax v17.16b, v17.16b, v20.16b\n" "add x15, x15, #0x10\n" - "smax v16.16b, v16.16b, v20.16b\n" + "smax v16.16b, v20.16b, v16.16b\n" "str q19, [x14, x12]\n" "str q18, [x13, x12]\n" "str q17, [x11, x12]\n" @@ -121,43 +122,43 @@ void a64_s8_nhwc_max_2x2_s1_output2x2_depthfirst_impl( "2:" // Vector: Tail "smax v21.16b, v30.16b, v29.16b\n" "smax v20.16b, v29.16b, v28.16b\n" - "smax v19.16b, v27.16b, v26.16b\n" + "smax v16.16b, v27.16b, v26.16b\n" "smax v18.16b, v25.16b, v24.16b\n" "smax v17.16b, v27.16b, v23.16b\n" - "smax v16.16b, v24.16b, v22.16b\n" - "smax v19.16b, v21.16b, v19.16b\n" + "smax v19.16b, v24.16b, v22.16b\n" + "smax v16.16b, v21.16b, v16.16b\n" "smax v18.16b, v18.16b, v21.16b\n" - "str q19, [x14, x12]\n" + "str q16, [x14, x12]\n" "smax v17.16b, v17.16b, v20.16b\n" - "smax v16.16b, v16.16b, v20.16b\n" + "smax v16.16b, v20.16b, v19.16b\n" "str q18, [x13, x12]\n" "str q17, [x11, x12]\n" "str q16, [x10, x12]\n" "add x12, x12, #0x10\n" "cbz x16, 4f\n" "3:" // Oddments - "ldr b30, [x28, x15]\n" - "ldr b29, [x25, x15]\n" - "smax v21.16b, v30.16b, v29.16b\n" + "ldr b16, [x28, x15]\n" + "ldr b17, [x25, x15]\n" + "smax v23.16b, v16.16b, v17.16b\n" "subs x16, x16, #0x1\n" - "ldr b28, [x22, x15]\n" - "ldr b27, [x26, x15]\n" - "smax v20.16b, v29.16b, v28.16b\n" - "ldr b26, [x9, x15]\n" - "ldr b25, [x27, x15]\n" - "smax v19.16b, v27.16b, v26.16b\n" - "smax v19.16b, v21.16b, v19.16b\n" - "ldr b24, [x24, x15]\n" - "ldr b23, [x23, x15]\n" - "smax v18.16b, v25.16b, v24.16b\n" - "smax v17.16b, v27.16b, v23.16b\n" - "ldr b22, [x21, x15]\n" - "smax v16.16b, v24.16b, v22.16b\n" + "ldr b16, [x22, x15]\n" + "ldr b22, [x26, x15]\n" + "smax v21.16b, v17.16b, v16.16b\n" + "ldr b16, [x9, x15]\n" + "ldr b17, [x27, x15]\n" + "smax v16.16b, v22.16b, v16.16b\n" + "smax v20.16b, v23.16b, v16.16b\n" + "ldr b19, [x24, x15]\n" + "ldr b16, [x23, x15]\n" + "smax v18.16b, v17.16b, v19.16b\n" + "smax v17.16b, v22.16b, v16.16b\n" + "ldr b16, [x21, x15]\n" + "smax v16.16b, v19.16b, v16.16b\n" "add x15, x15, #0x1\n" - "smax v18.16b, v18.16b, v21.16b\n" - "smax v17.16b, v17.16b, v20.16b\n" - "smax v16.16b, v16.16b, v20.16b\n" - "str b19, [x14, x12]\n" + "smax v18.16b, v18.16b, v23.16b\n" + "smax v17.16b, v17.16b, v21.16b\n" + "smax v16.16b, v21.16b, v16.16b\n" + "str b20, [x14, x12]\n" "str b18, [x13, x12]\n" "str b17, [x11, x12]\n" "str b16, [x10, x12]\n" @@ -172,4 +173,5 @@ void a64_s8_nhwc_max_2x2_s1_output2x2_depthfirst_impl( } // namespace pooling } // namespace arm_conv + #endif // defined(__aarch64__) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8_nhwc_max_generic_depthfirst/generic.cpp index 6168a57ca4..411fd11460 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8_nhwc_max_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8_nhwc_max_generic_depthfirst/generic.cpp @@ -22,11 +22,11 @@ * SOFTWARE. */ -#if defined(__aarch64__) - #include <cstdint> #include <cstddef> +#if defined(__aarch64__) + namespace arm_conv { namespace pooling { @@ -41,77 +41,77 @@ void a64_s8_nhwc_max_generic_depthfirst_impl( { __asm__ __volatile__( "cmp %x[n_channels], #0x40\n" - "mov x9, #0x0\n" - "mov x28, #0x10\n" // cntb _, ALL, #1 - "mov x27, #0x20\n" // cntb _, ALL, #2 - "mov x26, #0x30\n" // cntb _, ALL, #3 + "mov x27, #0x0\n" + "mov x26, #0x10\n" // cntb _, ALL, #1 + "mov x24, #0x20\n" // cntb _, ALL, #2 + "mov x23, #0x30\n" // cntb _, ALL, #3 "blt 7f\n" "1:" // 4-vectors of channels "lsr x25, %x[n_valid_cells], #0x2\n" "movi v8.16b, #0x80\n" "movi v7.16b, #0x80\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "movi v6.16b, #0x80\n" "movi v5.16b, #0x80\n" "cbz x25, 4f\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldr q4, [x24, x9]\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" "subs x25, x25, #0x1\n" - "ldr q3, [x23, x9]\n" - "ldr q2, [x24, x28]\n" - "ldr q1, [x23, x28]\n" - "ldr q0, [x24, x27]\n" - "ldr q31, [x23, x27]\n" - "ldr q30, [x24, x26]\n" - "ldr q29, [x23, x26]\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" - "ldr q28, [x22, x9]\n" - "ldr q22, [x21, x9]\n" - "ldr q27, [x22, x28]\n" - "ldr q21, [x21, x28]\n" - "ldr q26, [x22, x27]\n" - "ldr q20, [x21, x27]\n" - "ldr q25, [x22, x26]\n" - "ldr q24, [x21, x26]\n" + "ldr q3, [x20, x27]\n" + "ldr q2, [x21, x26]\n" + "ldr q1, [x20, x26]\n" + "ldr q0, [x21, x24]\n" + "ldr q31, [x20, x24]\n" + "ldr q30, [x21, x23]\n" + "ldr q29, [x20, x23]\n" + "ldp x21, x20, [x22, #0x10]\n" + "add x22, x22, #0x20\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" + "ldr q27, [x21, x26]\n" + "ldr q21, [x20, x26]\n" + "ldr q26, [x21, x24]\n" + "ldr q20, [x20, x24]\n" + "ldr q25, [x21, x23]\n" + "ldr q24, [x20, x23]\n" "beq 3f\n" "2:" // 4-vectors of channels: 4 inputs loop "smax v23.16b, v4.16b, v3.16b\n" "smax v19.16b, v28.16b, v22.16b\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldr q4, [x24, x9]\n" - "ldr q3, [x23, x9]\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "ldr q3, [x20, x27]\n" "smax v22.16b, v2.16b, v1.16b\n" - "ldr q2, [x24, x28]\n" + "ldr q2, [x21, x26]\n" "smax v18.16b, v27.16b, v21.16b\n" - "ldr q1, [x23, x28]\n" + "ldr q1, [x20, x26]\n" "smax v21.16b, v0.16b, v31.16b\n" - "ldr q0, [x24, x27]\n" + "ldr q0, [x21, x24]\n" "smax v17.16b, v26.16b, v20.16b\n" - "ldr q31, [x23, x27]\n" + "ldr q31, [x20, x24]\n" "smax v20.16b, v30.16b, v29.16b\n" - "ldr q30, [x24, x26]\n" + "ldr q30, [x21, x23]\n" "smax v16.16b, v25.16b, v24.16b\n" - "ldr q29, [x23, x26]\n" + "ldr q29, [x20, x23]\n" "smax v19.16b, v23.16b, v19.16b\n" "smax v18.16b, v22.16b, v18.16b\n" - "ldp x22, x21, [x20, #0x10]\n" - "ldr q28, [x22, x9]\n" - "ldr q22, [x21, x9]\n" + "ldp x21, x20, [x22, #0x10]\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" "smax v17.16b, v21.16b, v17.16b\n" "smax v16.16b, v20.16b, v16.16b\n" - "ldr q27, [x22, x28]\n" - "ldr q21, [x21, x28]\n" + "ldr q27, [x21, x26]\n" + "ldr q21, [x20, x26]\n" "subs x25, x25, #0x1\n" "smax v8.16b, v8.16b, v19.16b\n" - "ldr q26, [x22, x27]\n" - "ldr q20, [x21, x27]\n" + "ldr q26, [x21, x24]\n" + "ldr q20, [x20, x24]\n" "smax v7.16b, v7.16b, v18.16b\n" "smax v6.16b, v6.16b, v17.16b\n" - "ldr q25, [x22, x26]\n" - "ldr q24, [x21, x26]\n" + "ldr q25, [x21, x23]\n" + "ldr q24, [x20, x23]\n" "smax v5.16b, v5.16b, v16.16b\n" - "add x20, x20, #0x20\n" + "add x22, x22, #0x20\n" "bgt 2b\n" "3:" // 4-vectors of channels: 4 inputs tail "smax v23.16b, v4.16b, v3.16b\n" @@ -134,28 +134,28 @@ void a64_s8_nhwc_max_generic_depthfirst_impl( "ands x21, %x[n_valid_cells], #0x3\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x24, [x20], #0x8\n" - "ldr q4, [x24, x9]\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" "subs x21, x21, #0x1\n" - "smax v8.16b, v8.16b, v4.16b\n" - "ldr q2, [x24, x28]\n" - "ldr q0, [x24, x27]\n" - "smax v7.16b, v7.16b, v2.16b\n" - "smax v6.16b, v6.16b, v0.16b\n" - "ldr q30, [x24, x26]\n" - "smax v5.16b, v5.16b, v30.16b\n" + "smax v8.16b, v8.16b, v16.16b\n" + "ldr q17, [x20, x26]\n" + "ldr q16, [x20, x24]\n" + "smax v7.16b, v7.16b, v17.16b\n" + "smax v6.16b, v6.16b, v16.16b\n" + "ldr q16, [x20, x23]\n" + "smax v5.16b, v5.16b, v16.16b\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End "sub %x[n_channels], %x[n_channels], #0x40\n" "cmp %x[n_channels], #0x40\n" - "str q8, [%x[outptr], x9]\n" - "str q7, [%x[outptr], x28]\n" - "add x9, x9, #0x40\n" - "add x28, x28, #0x40\n" - "str q6, [%x[outptr], x27]\n" + "str q8, [%x[outptr], x27]\n" + "str q7, [%x[outptr], x26]\n" "add x27, x27, #0x40\n" - "str q5, [%x[outptr], x26]\n" "add x26, x26, #0x40\n" + "str q6, [%x[outptr], x24]\n" + "add x24, x24, #0x40\n" + "str q5, [%x[outptr], x23]\n" + "add x23, x23, #0x40\n" "bge 1b\n" "cbz %x[n_channels], 43f\n" "7:" // Single vector of channels @@ -164,217 +164,217 @@ void a64_s8_nhwc_max_generic_depthfirst_impl( "8:" // Single vector of channels: Loop "lsr x25, %x[n_valid_cells], #0x2\n" "movi v8.16b, #0x80\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "cbz x25, 11f\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldr q4, [x24, x9]\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" "subs x25, x25, #0x1\n" - "ldr q3, [x23, x9]\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" - "ldr q28, [x22, x9]\n" - "ldr q22, [x21, x9]\n" + "ldr q3, [x20, x27]\n" + "ldp x21, x20, [x22, #0x10]\n" + "add x22, x22, #0x20\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 4 inputs loop - "smax v23.16b, v4.16b, v3.16b\n" - "smax v19.16b, v28.16b, v22.16b\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldr q4, [x24, x9]\n" - "ldr q3, [x23, x9]\n" - "smax v19.16b, v23.16b, v19.16b\n" - "ldp x22, x21, [x20, #0x10]\n" + "smax v17.16b, v4.16b, v3.16b\n" + "smax v16.16b, v28.16b, v22.16b\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "ldr q3, [x20, x27]\n" + "smax v16.16b, v17.16b, v16.16b\n" + "ldp x21, x20, [x22, #0x10]\n" "subs x25, x25, #0x1\n" - "ldr q28, [x22, x9]\n" - "ldr q22, [x21, x9]\n" - "smax v8.16b, v8.16b, v19.16b\n" - "add x20, x20, #0x20\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" + "smax v8.16b, v8.16b, v16.16b\n" + "add x22, x22, #0x20\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 4 inputs tail - "smax v23.16b, v4.16b, v3.16b\n" - "smax v19.16b, v28.16b, v22.16b\n" - "smax v19.16b, v23.16b, v19.16b\n" - "smax v8.16b, v8.16b, v19.16b\n" + "smax v17.16b, v4.16b, v3.16b\n" + "smax v16.16b, v28.16b, v22.16b\n" + "smax v16.16b, v17.16b, v16.16b\n" + "smax v8.16b, v8.16b, v16.16b\n" "11:" // Single vector of channels: Loop: After loop "ands x21, %x[n_valid_cells], #0x3\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x24, [x20], #0x8\n" - "ldr q4, [x24, x9]\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" "subs x21, x21, #0x1\n" - "smax v8.16b, v8.16b, v4.16b\n" + "smax v8.16b, v8.16b, v16.16b\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End "sub %x[n_channels], %x[n_channels], #0x10\n" "cmp %x[n_channels], #0x10\n" - "str q8, [%x[outptr], x9]\n" - "add x9, x9, #0x10\n" + "str q8, [%x[outptr], x27]\n" + "add x27, x27, #0x10\n" "bge 8b\n" "cbz %x[n_channels], 43f\n" "14:" // Oddments "lsr x25, %x[n_valid_cells], #0x2\n" - "add %x[outptr], %x[outptr], x9\n" + "add %x[outptr], %x[outptr], x27\n" "movi v8.16b, #0x80\n" - "mov x20, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "cbz x25, 24f\n" "15:" // Oddments: 4 inputs loop - "ldp x24, x23, [x20, #0x0]\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" - "add x24, x24, x9\n" - "add x23, x23, x9\n" - "add x22, x22, x9\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "add x23, x23, x27\n" + "add x22, x22, x27\n" + "add x21, x21, x27\n" "movi v4.16b, #0x0\n" "movi v3.16b, #0x0\n" - "add x21, x21, x9\n" + "add x20, x20, x27\n" "movi v28.16b, #0x0\n" "movi v22.16b, #0x0\n" "tbz %x[n_channels], #3, 19f\n" - "ldr d4, [x24], #0x8\n" - "ldr d3, [x23], #0x8\n" - "ldr d28, [x22], #0x8\n" - "ldr d22, [x21], #0x8\n" + "ldr d4, [x23], #0x8\n" + "ldr d3, [x22], #0x8\n" + "ldr d28, [x21], #0x8\n" + "ldr d22, [x20], #0x8\n" "tbz %x[n_channels], #2, 17f\n" - "ld1 { v4.s }[2], [x24], #0x4\n" - "ld1 { v3.s }[2], [x23], #0x4\n" - "ld1 { v28.s }[2], [x22], #0x4\n" - "ld1 { v22.s }[2], [x21], #0x4\n" + "ld1 { v4.s }[2], [x23], #0x4\n" + "ld1 { v3.s }[2], [x22], #0x4\n" + "ld1 { v28.s }[2], [x21], #0x4\n" + "ld1 { v22.s }[2], [x20], #0x4\n" "tbz %x[n_channels], #1, 16f\n" - "ld1 { v4.h }[6], [x24], #0x2\n" - "ld1 { v3.h }[6], [x23], #0x2\n" - "ld1 { v28.h }[6], [x22], #0x2\n" - "ld1 { v22.h }[6], [x21], #0x2\n" + "ld1 { v4.h }[6], [x23], #0x2\n" + "ld1 { v3.h }[6], [x22], #0x2\n" + "ld1 { v28.h }[6], [x21], #0x2\n" + "ld1 { v22.h }[6], [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v4.b }[14], [x24], #0x1\n" - "ld1 { v3.b }[14], [x23], #0x1\n" - "ld1 { v28.b }[14], [x22], #0x1\n" - "ld1 { v22.b }[14], [x21], #0x1\n" + "ld1 { v4.b }[14], [x23], #0x1\n" + "ld1 { v3.b }[14], [x22], #0x1\n" + "ld1 { v28.b }[14], [x21], #0x1\n" + "ld1 { v22.b }[14], [x20], #0x1\n" "b 23f\n" "16:" // Oddments: 4 inputs loop: Load: Bit 3: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ld1 { v4.b }[12], [x24], #0x1\n" - "ld1 { v3.b }[12], [x23], #0x1\n" - "ld1 { v28.b }[12], [x22], #0x1\n" - "ld1 { v22.b }[12], [x21], #0x1\n" + "ld1 { v4.b }[12], [x23], #0x1\n" + "ld1 { v3.b }[12], [x22], #0x1\n" + "ld1 { v28.b }[12], [x21], #0x1\n" + "ld1 { v22.b }[12], [x20], #0x1\n" "b 23f\n" "17:" // Oddments: 4 inputs loop: Load: Bit 3: Bit 2: Unset "tbz %x[n_channels], #1, 18f\n" - "ld1 { v4.h }[4], [x24], #0x2\n" - "ld1 { v3.h }[4], [x23], #0x2\n" - "ld1 { v28.h }[4], [x22], #0x2\n" - "ld1 { v22.h }[4], [x21], #0x2\n" + "ld1 { v4.h }[4], [x23], #0x2\n" + "ld1 { v3.h }[4], [x22], #0x2\n" + "ld1 { v28.h }[4], [x21], #0x2\n" + "ld1 { v22.h }[4], [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v4.b }[10], [x24], #0x1\n" - "ld1 { v3.b }[10], [x23], #0x1\n" - "ld1 { v28.b }[10], [x22], #0x1\n" - "ld1 { v22.b }[10], [x21], #0x1\n" + "ld1 { v4.b }[10], [x23], #0x1\n" + "ld1 { v3.b }[10], [x22], #0x1\n" + "ld1 { v28.b }[10], [x21], #0x1\n" + "ld1 { v22.b }[10], [x20], #0x1\n" "b 23f\n" "18:" // Oddments: 4 inputs loop: Load: Bit 3: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ld1 { v4.b }[8], [x24], #0x1\n" - "ld1 { v3.b }[8], [x23], #0x1\n" - "ld1 { v28.b }[8], [x22], #0x1\n" - "ld1 { v22.b }[8], [x21], #0x1\n" + "ld1 { v4.b }[8], [x23], #0x1\n" + "ld1 { v3.b }[8], [x22], #0x1\n" + "ld1 { v28.b }[8], [x21], #0x1\n" + "ld1 { v22.b }[8], [x20], #0x1\n" "b 23f\n" "19:" // Oddments: 4 inputs loop: Load: Bit 3: Unset "tbz %x[n_channels], #2, 21f\n" - "ldr s4, [x24], #0x4\n" - "ldr s3, [x23], #0x4\n" - "ldr s28, [x22], #0x4\n" - "ldr s22, [x21], #0x4\n" + "ldr s4, [x23], #0x4\n" + "ldr s3, [x22], #0x4\n" + "ldr s28, [x21], #0x4\n" + "ldr s22, [x20], #0x4\n" "tbz %x[n_channels], #1, 20f\n" - "ld1 { v4.h }[2], [x24], #0x2\n" - "ld1 { v3.h }[2], [x23], #0x2\n" - "ld1 { v28.h }[2], [x22], #0x2\n" - "ld1 { v22.h }[2], [x21], #0x2\n" + "ld1 { v4.h }[2], [x23], #0x2\n" + "ld1 { v3.h }[2], [x22], #0x2\n" + "ld1 { v28.h }[2], [x21], #0x2\n" + "ld1 { v22.h }[2], [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v4.b }[6], [x24], #0x1\n" - "ld1 { v3.b }[6], [x23], #0x1\n" - "ld1 { v28.b }[6], [x22], #0x1\n" - "ld1 { v22.b }[6], [x21], #0x1\n" + "ld1 { v4.b }[6], [x23], #0x1\n" + "ld1 { v3.b }[6], [x22], #0x1\n" + "ld1 { v28.b }[6], [x21], #0x1\n" + "ld1 { v22.b }[6], [x20], #0x1\n" "b 23f\n" "20:" // Oddments: 4 inputs loop: Load: Bit 3: Unset: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ld1 { v4.b }[4], [x24], #0x1\n" - "ld1 { v3.b }[4], [x23], #0x1\n" - "ld1 { v28.b }[4], [x22], #0x1\n" - "ld1 { v22.b }[4], [x21], #0x1\n" + "ld1 { v4.b }[4], [x23], #0x1\n" + "ld1 { v3.b }[4], [x22], #0x1\n" + "ld1 { v28.b }[4], [x21], #0x1\n" + "ld1 { v22.b }[4], [x20], #0x1\n" "b 23f\n" "21:" // Oddments: 4 inputs loop: Load: Bit 3: Unset: Bit 2: Unset "tbz %x[n_channels], #1, 22f\n" - "ldr h4, [x24], #0x2\n" - "ldr h3, [x23], #0x2\n" - "ldr h28, [x22], #0x2\n" - "ldr h22, [x21], #0x2\n" + "ldr h4, [x23], #0x2\n" + "ldr h3, [x22], #0x2\n" + "ldr h28, [x21], #0x2\n" + "ldr h22, [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v4.b }[2], [x24], #0x1\n" - "ld1 { v3.b }[2], [x23], #0x1\n" - "ld1 { v28.b }[2], [x22], #0x1\n" - "ld1 { v22.b }[2], [x21], #0x1\n" + "ld1 { v4.b }[2], [x23], #0x1\n" + "ld1 { v3.b }[2], [x22], #0x1\n" + "ld1 { v28.b }[2], [x21], #0x1\n" + "ld1 { v22.b }[2], [x20], #0x1\n" "b 23f\n" "22:" // Oddments: 4 inputs loop: Load: Bit 3: Unset: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ldr b4, [x24], #0x1\n" - "ldr b3, [x23], #0x1\n" - "ldr b28, [x22], #0x1\n" - "ldr b22, [x21], #0x1\n" + "ldr b4, [x23], #0x1\n" + "ldr b3, [x22], #0x1\n" + "ldr b28, [x21], #0x1\n" + "ldr b22, [x20], #0x1\n" "23:" // Oddments: 4 inputs loop: Load: Bit 3: End - "smax v23.16b, v4.16b, v3.16b\n" - "smax v19.16b, v28.16b, v22.16b\n" + "smax v17.16b, v4.16b, v3.16b\n" + "smax v16.16b, v28.16b, v22.16b\n" "subs x25, x25, #0x1\n" - "smax v19.16b, v23.16b, v19.16b\n" - "smax v8.16b, v8.16b, v19.16b\n" + "smax v16.16b, v17.16b, v16.16b\n" + "smax v8.16b, v8.16b, v16.16b\n" "bgt 15b\n" "24:" // Oddments: After loop "ands x21, %x[n_valid_cells], #0x3\n" "beq 34f\n" "25:" // Oddments: Single input loop - "ldr x24, [x20], #0x8\n" - "add x24, x24, x9\n" + "ldr x23, [x24], #0x8\n" + "add x23, x23, x27\n" "movi v4.16b, #0x0\n" "tbz %x[n_channels], #3, 29f\n" - "ldr d4, [x24], #0x8\n" + "ldr d4, [x23], #0x8\n" "tbz %x[n_channels], #2, 27f\n" - "ld1 { v4.s }[2], [x24], #0x4\n" + "ld1 { v4.s }[2], [x23], #0x4\n" "tbz %x[n_channels], #1, 26f\n" - "ld1 { v4.h }[6], [x24], #0x2\n" + "ld1 { v4.h }[6], [x23], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v4.b }[14], [x24], #0x1\n" + "ld1 { v4.b }[14], [x23], #0x1\n" "b 33f\n" "26:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ld1 { v4.b }[12], [x24], #0x1\n" + "ld1 { v4.b }[12], [x23], #0x1\n" "b 33f\n" "27:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Unset "tbz %x[n_channels], #1, 28f\n" - "ld1 { v4.h }[4], [x24], #0x2\n" + "ld1 { v4.h }[4], [x23], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v4.b }[10], [x24], #0x1\n" + "ld1 { v4.b }[10], [x23], #0x1\n" "b 33f\n" "28:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ld1 { v4.b }[8], [x24], #0x1\n" + "ld1 { v4.b }[8], [x23], #0x1\n" "b 33f\n" "29:" // Oddments: Single input loop: Load: Bit 3: Unset "tbz %x[n_channels], #2, 31f\n" - "ldr s4, [x24], #0x4\n" + "ldr s4, [x23], #0x4\n" "tbz %x[n_channels], #1, 30f\n" - "ld1 { v4.h }[2], [x24], #0x2\n" + "ld1 { v4.h }[2], [x23], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v4.b }[6], [x24], #0x1\n" + "ld1 { v4.b }[6], [x23], #0x1\n" "b 33f\n" "30:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ld1 { v4.b }[4], [x24], #0x1\n" + "ld1 { v4.b }[4], [x23], #0x1\n" "b 33f\n" "31:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Unset "tbz %x[n_channels], #1, 32f\n" - "ldr h4, [x24], #0x2\n" + "ldr h4, [x23], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v4.b }[2], [x24], #0x1\n" + "ld1 { v4.b }[2], [x23], #0x1\n" "b 33f\n" "32:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ldr b4, [x24], #0x1\n" + "ldr b4, [x23], #0x1\n" "33:" // Oddments: Single input loop: Load: Bit 3: End "subs x21, x21, #0x1\n" "smax v8.16b, v8.16b, v4.16b\n" @@ -428,10 +428,11 @@ void a64_s8_nhwc_max_generic_depthfirst_impl( "43:" // End : [n_channels] "+&r" (n_channels), [outptr] "+&r" (outptr) : [inptrs] "r" (inptrs), [n_valid_cells] "r" (n_valid_cells) - : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x9", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" + : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); } } // namespace pooling } // namespace arm_conv + #endif // defined(__aarch64__) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_avg_generic_depthfirst/generic.cpp index e889782fa3..019f402911 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_avg_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_avg_generic_depthfirst/generic.cpp @@ -22,8 +22,6 @@ * SOFTWARE. */ -#if defined(__aarch64__) - #include "pooling.hpp" #include <cstdint> #include <cstddef> @@ -31,6 +29,8 @@ #include <cmath> +#if defined(__aarch64__) + namespace arm_conv { namespace pooling { @@ -124,7 +124,7 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( "lsr x23, %x[n_valid_cells], #0x1\n" "movi v15.4s, #0x0\n" "movi v14.4s, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "movi v13.4s, #0x0\n" "movi v12.4s, #0x0\n" "movi v11.4s, #0x0\n" @@ -140,42 +140,42 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( "movi v1.4s, #0x0\n" "movi v0.4s, #0x0\n" "cbz x23, 4f\n" - "ldp x22, x21, [x20, #0x0]\n" - "ldr q31, [x22, x27]\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q31, [x21, x27]\n" "subs x23, x23, #0x1\n" - "add x20, x20, #0x10\n" - "ldr q30, [x21, x27]\n" - "ldr q29, [x22, x26]\n" - "ldr q28, [x21, x26]\n" - "ldr q27, [x22, x25]\n" - "ldr q26, [x21, x25]\n" - "ldr q25, [x22, x24]\n" - "ldr q24, [x21, x24]\n" + "add x22, x22, #0x10\n" + "ldr q30, [x20, x27]\n" + "ldr q29, [x21, x26]\n" + "ldr q28, [x20, x26]\n" + "ldr q27, [x21, x25]\n" + "ldr q26, [x20, x25]\n" + "ldr q25, [x21, x24]\n" + "ldr q24, [x20, x24]\n" "beq 3f\n" "2:" // 4-vectors of channels: 2 inputs loop "saddl v23.8h, v31.8b, v30.8b\n" "saddl2 v22.8h, v31.16b, v30.16b\n" - "ldp x22, x21, [x20, #0x0]\n" - "ldr q31, [x22, x27]\n" - "ldr q30, [x21, x27]\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q31, [x21, x27]\n" + "ldr q30, [x20, x27]\n" "saddl v21.8h, v29.8b, v28.8b\n" "saddl2 v20.8h, v29.16b, v28.16b\n" - "ldr q29, [x22, x26]\n" - "ldr q28, [x21, x26]\n" + "ldr q29, [x21, x26]\n" + "ldr q28, [x20, x26]\n" "saddl v19.8h, v27.8b, v26.8b\n" "saddl2 v18.8h, v27.16b, v26.16b\n" - "ldr q27, [x22, x25]\n" - "ldr q26, [x21, x25]\n" + "ldr q27, [x21, x25]\n" + "ldr q26, [x20, x25]\n" + "saddl v17.8h, v25.8b, v24.8b\n" + "saddl2 v16.8h, v25.16b, v24.16b\n" + "ldr q25, [x21, x24]\n" + "ldr q24, [x20, x24]\n" "subs x23, x23, #0x1\n" "saddw v15.4s, v15.4s, v23.4h\n" "saddw2 v14.4s, v14.4s, v23.8h\n" - "saddl v17.8h, v25.8b, v24.8b\n" - "saddl2 v16.8h, v25.16b, v24.16b\n" - "ldr q25, [x22, x24]\n" - "add x20, x20, #0x10\n" "saddw v13.4s, v13.4s, v22.4h\n" "saddw2 v12.4s, v12.4s, v22.8h\n" - "ldr q24, [x21, x24]\n" + "add x22, x22, #0x10\n" "saddw v11.4s, v11.4s, v21.4h\n" "saddw2 v10.4s, v10.4s, v21.8h\n" "saddw v9.4s, v9.4s, v20.4h\n" @@ -215,23 +215,23 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( "saddw v1.4s, v1.4s, v16.4h\n" "saddw2 v0.4s, v0.4s, v16.8h\n" "4:" // 4-vectors of channels: After loop - "ands x21, %x[n_valid_cells], #0x1\n" + "ands x23, %x[n_valid_cells], #0x1\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x22, [x20], #0x8\n" - "ldr q31, [x22, x27]\n" - "sxtl v23.8h, v31.8b\n" - "sxtl2 v22.8h, v31.16b\n" - "ldr q29, [x22, x26]\n" - "ldr q27, [x22, x25]\n" - "sxtl v21.8h, v29.8b\n" - "sxtl2 v20.8h, v29.16b\n" - "ldr q25, [x22, x24]\n" - "sxtl v19.8h, v27.8b\n" - "sxtl2 v18.8h, v27.16b\n" - "subs x21, x21, #0x1\n" - "sxtl v17.8h, v25.8b\n" - "sxtl2 v16.8h, v25.16b\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" + "sxtl v23.8h, v16.8b\n" + "sxtl2 v22.8h, v16.16b\n" + "ldr q16, [x20, x26]\n" + "ldr q17, [x20, x25]\n" + "sxtl v21.8h, v16.8b\n" + "sxtl2 v20.8h, v16.16b\n" + "ldr q16, [x20, x24]\n" + "sxtl v19.8h, v17.8b\n" + "sxtl2 v18.8h, v17.16b\n" + "subs x23, x23, #0x1\n" + "sxtl v17.8h, v16.8b\n" + "sxtl2 v16.8h, v16.16b\n" "saddw v15.4s, v15.4s, v23.4h\n" "saddw2 v14.4s, v14.4s, v23.8h\n" "saddw v13.4s, v13.4s, v22.4h\n" @@ -366,49 +366,49 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( "lsr x23, %x[n_valid_cells], #0x1\n" "movi v15.4s, #0x0\n" "movi v14.4s, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "movi v13.4s, #0x0\n" "movi v12.4s, #0x0\n" "cbz x23, 11f\n" - "ldp x22, x21, [x20, #0x0]\n" - "ldr q31, [x22, x27]\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q31, [x21, x27]\n" "subs x23, x23, #0x1\n" - "add x20, x20, #0x10\n" - "ldr q30, [x21, x27]\n" + "add x22, x22, #0x10\n" + "ldr q30, [x20, x27]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 2 inputs loop - "saddl v23.8h, v31.8b, v30.8b\n" - "saddl2 v22.8h, v31.16b, v30.16b\n" - "ldp x22, x21, [x20, #0x0]\n" - "ldr q31, [x22, x27]\n" - "ldr q30, [x21, x27]\n" + "saddl v17.8h, v31.8b, v30.8b\n" + "saddl2 v16.8h, v31.16b, v30.16b\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q31, [x21, x27]\n" + "ldr q30, [x20, x27]\n" "subs x23, x23, #0x1\n" - "saddw v15.4s, v15.4s, v23.4h\n" - "saddw2 v14.4s, v14.4s, v23.8h\n" - "saddw v13.4s, v13.4s, v22.4h\n" - "saddw2 v12.4s, v12.4s, v22.8h\n" - "add x20, x20, #0x10\n" + "saddw v15.4s, v15.4s, v17.4h\n" + "saddw2 v14.4s, v14.4s, v17.8h\n" + "saddw v13.4s, v13.4s, v16.4h\n" + "saddw2 v12.4s, v12.4s, v16.8h\n" + "add x22, x22, #0x10\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 2 inputs tail - "saddl v23.8h, v31.8b, v30.8b\n" - "saddl2 v22.8h, v31.16b, v30.16b\n" - "saddw v15.4s, v15.4s, v23.4h\n" - "saddw2 v14.4s, v14.4s, v23.8h\n" - "saddw v13.4s, v13.4s, v22.4h\n" - "saddw2 v12.4s, v12.4s, v22.8h\n" + "saddl v17.8h, v31.8b, v30.8b\n" + "saddl2 v16.8h, v31.16b, v30.16b\n" + "saddw v15.4s, v15.4s, v17.4h\n" + "saddw2 v14.4s, v14.4s, v17.8h\n" + "saddw v13.4s, v13.4s, v16.4h\n" + "saddw2 v12.4s, v12.4s, v16.8h\n" "11:" // Single vector of channels: Loop: After loop - "ands x21, %x[n_valid_cells], #0x1\n" + "ands x23, %x[n_valid_cells], #0x1\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x22, [x20], #0x8\n" - "ldr q31, [x22, x27]\n" - "sxtl v23.8h, v31.8b\n" - "sxtl2 v22.8h, v31.16b\n" - "subs x21, x21, #0x1\n" - "saddw v15.4s, v15.4s, v23.4h\n" - "saddw2 v14.4s, v14.4s, v23.8h\n" - "saddw v13.4s, v13.4s, v22.4h\n" - "saddw2 v12.4s, v12.4s, v22.8h\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" + "sxtl v17.8h, v16.8b\n" + "sxtl2 v16.8h, v16.16b\n" + "subs x23, x23, #0x1\n" + "saddw v15.4s, v15.4s, v17.4h\n" + "saddw2 v14.4s, v14.4s, v17.8h\n" + "saddw v13.4s, v13.4s, v16.4h\n" + "saddw2 v12.4s, v12.4s, v16.8h\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End "ld1r { v18.4s }, [%x[left_shift]]\n" @@ -438,9 +438,9 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( "smin v14.4s, v14.4s, v17.4s\n" "smin v13.4s, v13.4s, v17.4s\n" "smin v12.4s, v12.4s, v17.4s\n" - "uzp1 v23.16b, v15.16b, v14.16b\n" + "uzp1 v17.16b, v15.16b, v14.16b\n" "uzp1 v16.16b, v13.16b, v12.16b\n" - "uzp1 v16.16b, v23.16b, v16.16b\n" + "uzp1 v16.16b, v17.16b, v16.16b\n" "str q16, [%x[outptr], x27]\n" "add x27, x27, #0x10\n" "bge 8b\n" @@ -452,142 +452,142 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( "movi v14.4s, #0x0\n" "movi v13.4s, #0x0\n" "movi v12.4s, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "cbz x23, 24f\n" "15:" // Oddments: 2 inputs loop - "ldp x22, x21, [x20, #0x0]\n" - "add x20, x20, #0x10\n" - "add x22, x22, x27\n" - "movi v31.16b, #0x0\n" + "ldp x21, x20, [x22, #0x0]\n" + "add x22, x22, #0x10\n" "add x21, x21, x27\n" + "movi v31.16b, #0x0\n" + "add x20, x20, x27\n" "movi v30.16b, #0x0\n" "tbz %x[n_channels], #3, 19f\n" - "ldr d31, [x22], #0x8\n" - "ldr d30, [x21], #0x8\n" + "ldr d31, [x21], #0x8\n" + "ldr d30, [x20], #0x8\n" "tbz %x[n_channels], #2, 17f\n" - "ld1 { v31.s }[2], [x22], #0x4\n" - "ld1 { v30.s }[2], [x21], #0x4\n" + "ld1 { v31.s }[2], [x21], #0x4\n" + "ld1 { v30.s }[2], [x20], #0x4\n" "tbz %x[n_channels], #1, 16f\n" - "ld1 { v31.h }[6], [x22], #0x2\n" - "ld1 { v30.h }[6], [x21], #0x2\n" + "ld1 { v31.h }[6], [x21], #0x2\n" + "ld1 { v30.h }[6], [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v31.b }[14], [x22], #0x1\n" - "ld1 { v30.b }[14], [x21], #0x1\n" + "ld1 { v31.b }[14], [x21], #0x1\n" + "ld1 { v30.b }[14], [x20], #0x1\n" "b 23f\n" "16:" // Oddments: 2 inputs loop: Load: Bit 3: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ld1 { v31.b }[12], [x22], #0x1\n" - "ld1 { v30.b }[12], [x21], #0x1\n" + "ld1 { v31.b }[12], [x21], #0x1\n" + "ld1 { v30.b }[12], [x20], #0x1\n" "b 23f\n" "17:" // Oddments: 2 inputs loop: Load: Bit 3: Bit 2: Unset "tbz %x[n_channels], #1, 18f\n" - "ld1 { v31.h }[4], [x22], #0x2\n" - "ld1 { v30.h }[4], [x21], #0x2\n" + "ld1 { v31.h }[4], [x21], #0x2\n" + "ld1 { v30.h }[4], [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v31.b }[10], [x22], #0x1\n" - "ld1 { v30.b }[10], [x21], #0x1\n" + "ld1 { v31.b }[10], [x21], #0x1\n" + "ld1 { v30.b }[10], [x20], #0x1\n" "b 23f\n" "18:" // Oddments: 2 inputs loop: Load: Bit 3: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ld1 { v31.b }[8], [x22], #0x1\n" - "ld1 { v30.b }[8], [x21], #0x1\n" + "ld1 { v31.b }[8], [x21], #0x1\n" + "ld1 { v30.b }[8], [x20], #0x1\n" "b 23f\n" "19:" // Oddments: 2 inputs loop: Load: Bit 3: Unset "tbz %x[n_channels], #2, 21f\n" - "ldr s31, [x22], #0x4\n" - "ldr s30, [x21], #0x4\n" + "ldr s31, [x21], #0x4\n" + "ldr s30, [x20], #0x4\n" "tbz %x[n_channels], #1, 20f\n" - "ld1 { v31.h }[2], [x22], #0x2\n" - "ld1 { v30.h }[2], [x21], #0x2\n" + "ld1 { v31.h }[2], [x21], #0x2\n" + "ld1 { v30.h }[2], [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v31.b }[6], [x22], #0x1\n" - "ld1 { v30.b }[6], [x21], #0x1\n" + "ld1 { v31.b }[6], [x21], #0x1\n" + "ld1 { v30.b }[6], [x20], #0x1\n" "b 23f\n" "20:" // Oddments: 2 inputs loop: Load: Bit 3: Unset: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ld1 { v31.b }[4], [x22], #0x1\n" - "ld1 { v30.b }[4], [x21], #0x1\n" + "ld1 { v31.b }[4], [x21], #0x1\n" + "ld1 { v30.b }[4], [x20], #0x1\n" "b 23f\n" "21:" // Oddments: 2 inputs loop: Load: Bit 3: Unset: Bit 2: Unset "tbz %x[n_channels], #1, 22f\n" - "ldr h31, [x22], #0x2\n" - "ldr h30, [x21], #0x2\n" + "ldr h31, [x21], #0x2\n" + "ldr h30, [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v31.b }[2], [x22], #0x1\n" - "ld1 { v30.b }[2], [x21], #0x1\n" + "ld1 { v31.b }[2], [x21], #0x1\n" + "ld1 { v30.b }[2], [x20], #0x1\n" "b 23f\n" "22:" // Oddments: 2 inputs loop: Load: Bit 3: Unset: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ldr b31, [x22], #0x1\n" - "ldr b30, [x21], #0x1\n" + "ldr b31, [x21], #0x1\n" + "ldr b30, [x20], #0x1\n" "23:" // Oddments: 2 inputs loop: Load: Bit 3: End - "saddl v23.8h, v31.8b, v30.8b\n" - "saddl2 v22.8h, v31.16b, v30.16b\n" + "saddl v17.8h, v31.8b, v30.8b\n" + "saddl2 v16.8h, v31.16b, v30.16b\n" "subs x23, x23, #0x1\n" - "saddw v15.4s, v15.4s, v23.4h\n" - "saddw2 v14.4s, v14.4s, v23.8h\n" - "saddw v13.4s, v13.4s, v22.4h\n" - "saddw2 v12.4s, v12.4s, v22.8h\n" + "saddw v15.4s, v15.4s, v17.4h\n" + "saddw2 v14.4s, v14.4s, v17.8h\n" + "saddw v13.4s, v13.4s, v16.4h\n" + "saddw2 v12.4s, v12.4s, v16.8h\n" "bgt 15b\n" "24:" // Oddments: After loop - "ands x21, %x[n_valid_cells], #0x1\n" + "ands x23, %x[n_valid_cells], #0x1\n" "beq 34f\n" "25:" // Oddments: Single input loop - "ldr x22, [x20], #0x8\n" - "add x22, x22, x27\n" + "ldr x21, [x22], #0x8\n" + "add x21, x21, x27\n" "movi v31.16b, #0x0\n" "tbz %x[n_channels], #3, 29f\n" - "ldr d31, [x22], #0x8\n" + "ldr d31, [x21], #0x8\n" "tbz %x[n_channels], #2, 27f\n" - "ld1 { v31.s }[2], [x22], #0x4\n" + "ld1 { v31.s }[2], [x21], #0x4\n" "tbz %x[n_channels], #1, 26f\n" - "ld1 { v31.h }[6], [x22], #0x2\n" + "ld1 { v31.h }[6], [x21], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v31.b }[14], [x22], #0x1\n" + "ld1 { v31.b }[14], [x21], #0x1\n" "b 33f\n" "26:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ld1 { v31.b }[12], [x22], #0x1\n" + "ld1 { v31.b }[12], [x21], #0x1\n" "b 33f\n" "27:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Unset "tbz %x[n_channels], #1, 28f\n" - "ld1 { v31.h }[4], [x22], #0x2\n" + "ld1 { v31.h }[4], [x21], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v31.b }[10], [x22], #0x1\n" + "ld1 { v31.b }[10], [x21], #0x1\n" "b 33f\n" "28:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ld1 { v31.b }[8], [x22], #0x1\n" + "ld1 { v31.b }[8], [x21], #0x1\n" "b 33f\n" "29:" // Oddments: Single input loop: Load: Bit 3: Unset "tbz %x[n_channels], #2, 31f\n" - "ldr s31, [x22], #0x4\n" + "ldr s31, [x21], #0x4\n" "tbz %x[n_channels], #1, 30f\n" - "ld1 { v31.h }[2], [x22], #0x2\n" + "ld1 { v31.h }[2], [x21], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v31.b }[6], [x22], #0x1\n" + "ld1 { v31.b }[6], [x21], #0x1\n" "b 33f\n" "30:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ld1 { v31.b }[4], [x22], #0x1\n" + "ld1 { v31.b }[4], [x21], #0x1\n" "b 33f\n" "31:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Unset "tbz %x[n_channels], #1, 32f\n" - "ldr h31, [x22], #0x2\n" + "ldr h31, [x21], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v31.b }[2], [x22], #0x1\n" + "ld1 { v31.b }[2], [x21], #0x1\n" "b 33f\n" "32:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ldr b31, [x22], #0x1\n" + "ldr b31, [x21], #0x1\n" "33:" // Oddments: Single input loop: Load: Bit 3: End - "sxtl v23.8h, v31.8b\n" - "sxtl2 v22.8h, v31.16b\n" - "subs x21, x21, #0x1\n" - "saddw v15.4s, v15.4s, v23.4h\n" - "saddw2 v14.4s, v14.4s, v23.8h\n" - "saddw v13.4s, v13.4s, v22.4h\n" - "saddw2 v12.4s, v12.4s, v22.8h\n" + "sxtl v17.8h, v31.8b\n" + "sxtl2 v16.8h, v31.16b\n" + "subs x23, x23, #0x1\n" + "saddw v15.4s, v15.4s, v17.4h\n" + "saddw2 v14.4s, v14.4s, v17.8h\n" + "saddw v13.4s, v13.4s, v16.4h\n" + "saddw2 v12.4s, v12.4s, v16.8h\n" "bgt 25b\n" "34:" // Oddments: Single input loop: End "ld1r { v18.4s }, [%x[left_shift]]\n" @@ -615,9 +615,9 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( "smin v14.4s, v14.4s, v17.4s\n" "smin v13.4s, v13.4s, v17.4s\n" "smin v12.4s, v12.4s, v17.4s\n" - "uzp1 v23.16b, v15.16b, v14.16b\n" + "uzp1 v17.16b, v15.16b, v14.16b\n" "uzp1 v16.16b, v13.16b, v12.16b\n" - "uzp1 v16.16b, v23.16b, v16.16b\n" + "uzp1 v16.16b, v17.16b, v16.16b\n" "tbz %x[n_channels], #3, 38f\n" "st1 { v16.d }[0], [%x[outptr]], #0x8\n" "tbz %x[n_channels], #2, 36f\n" @@ -672,4 +672,5 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( } // namespace pooling } // namespace arm_conv + #endif // defined(__aarch64__) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_max_generic_depthfirst/generic.cpp index 90a31ec677..f7b8dc761c 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_max_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_max_generic_depthfirst/generic.cpp @@ -21,12 +21,13 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ -#if defined(__aarch64__) #include "pooling.hpp" #include <cstdint> #include <cstddef> +#if defined(__aarch64__) + namespace arm_conv { namespace pooling { @@ -42,77 +43,77 @@ void a64_s8q_nhwc_max_generic_depthfirst_impl( { __asm__ __volatile__( "cmp %x[n_channels], #0x40\n" - "mov x9, #0x0\n" - "mov x28, #0x10\n" // cntb _, ALL, #1 - "mov x27, #0x20\n" // cntb _, ALL, #2 - "mov x26, #0x30\n" // cntb _, ALL, #3 + "mov x27, #0x0\n" + "mov x26, #0x10\n" // cntb _, ALL, #1 + "mov x24, #0x20\n" // cntb _, ALL, #2 + "mov x23, #0x30\n" // cntb _, ALL, #3 "blt 7f\n" "1:" // 4-vectors of channels "lsr x25, %x[n_valid_cells], #0x2\n" "movi v8.16b, #0x80\n" "movi v7.16b, #0x80\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "movi v6.16b, #0x80\n" "movi v5.16b, #0x80\n" "cbz x25, 4f\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldr q4, [x24, x9]\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" "subs x25, x25, #0x1\n" - "ldr q3, [x23, x9]\n" - "ldr q2, [x24, x28]\n" - "ldr q1, [x23, x28]\n" - "ldr q0, [x24, x27]\n" - "ldr q31, [x23, x27]\n" - "ldr q30, [x24, x26]\n" - "ldr q29, [x23, x26]\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" - "ldr q28, [x22, x9]\n" - "ldr q22, [x21, x9]\n" - "ldr q27, [x22, x28]\n" - "ldr q21, [x21, x28]\n" - "ldr q26, [x22, x27]\n" - "ldr q20, [x21, x27]\n" - "ldr q25, [x22, x26]\n" - "ldr q24, [x21, x26]\n" + "ldr q3, [x20, x27]\n" + "ldr q2, [x21, x26]\n" + "ldr q1, [x20, x26]\n" + "ldr q0, [x21, x24]\n" + "ldr q31, [x20, x24]\n" + "ldr q30, [x21, x23]\n" + "ldr q29, [x20, x23]\n" + "ldp x21, x20, [x22, #0x10]\n" + "add x22, x22, #0x20\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" + "ldr q27, [x21, x26]\n" + "ldr q21, [x20, x26]\n" + "ldr q26, [x21, x24]\n" + "ldr q20, [x20, x24]\n" + "ldr q25, [x21, x23]\n" + "ldr q24, [x20, x23]\n" "beq 3f\n" "2:" // 4-vectors of channels: 4 inputs loop "smax v23.16b, v4.16b, v3.16b\n" "smax v19.16b, v28.16b, v22.16b\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldr q4, [x24, x9]\n" - "ldr q3, [x23, x9]\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "ldr q3, [x20, x27]\n" "smax v22.16b, v2.16b, v1.16b\n" - "ldr q2, [x24, x28]\n" + "ldr q2, [x21, x26]\n" "smax v18.16b, v27.16b, v21.16b\n" - "ldr q1, [x23, x28]\n" + "ldr q1, [x20, x26]\n" "smax v21.16b, v0.16b, v31.16b\n" - "ldr q0, [x24, x27]\n" + "ldr q0, [x21, x24]\n" "smax v17.16b, v26.16b, v20.16b\n" - "ldr q31, [x23, x27]\n" + "ldr q31, [x20, x24]\n" "smax v20.16b, v30.16b, v29.16b\n" - "ldr q30, [x24, x26]\n" + "ldr q30, [x21, x23]\n" "smax v16.16b, v25.16b, v24.16b\n" - "ldr q29, [x23, x26]\n" + "ldr q29, [x20, x23]\n" "smax v19.16b, v23.16b, v19.16b\n" "smax v18.16b, v22.16b, v18.16b\n" - "ldp x22, x21, [x20, #0x10]\n" - "ldr q28, [x22, x9]\n" - "ldr q22, [x21, x9]\n" + "ldp x21, x20, [x22, #0x10]\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" "smax v17.16b, v21.16b, v17.16b\n" "smax v16.16b, v20.16b, v16.16b\n" - "ldr q27, [x22, x28]\n" - "ldr q21, [x21, x28]\n" + "ldr q27, [x21, x26]\n" + "ldr q21, [x20, x26]\n" "subs x25, x25, #0x1\n" "smax v8.16b, v8.16b, v19.16b\n" - "ldr q26, [x22, x27]\n" - "ldr q20, [x21, x27]\n" + "ldr q26, [x21, x24]\n" + "ldr q20, [x20, x24]\n" "smax v7.16b, v7.16b, v18.16b\n" "smax v6.16b, v6.16b, v17.16b\n" - "ldr q25, [x22, x26]\n" - "ldr q24, [x21, x26]\n" + "ldr q25, [x21, x23]\n" + "ldr q24, [x20, x23]\n" "smax v5.16b, v5.16b, v16.16b\n" - "add x20, x20, #0x20\n" + "add x22, x22, #0x20\n" "bgt 2b\n" "3:" // 4-vectors of channels: 4 inputs tail "smax v23.16b, v4.16b, v3.16b\n" @@ -135,16 +136,16 @@ void a64_s8q_nhwc_max_generic_depthfirst_impl( "ands x21, %x[n_valid_cells], #0x3\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x24, [x20], #0x8\n" - "ldr q4, [x24, x9]\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" "subs x21, x21, #0x1\n" - "smax v8.16b, v8.16b, v4.16b\n" - "ldr q2, [x24, x28]\n" - "ldr q0, [x24, x27]\n" - "smax v7.16b, v7.16b, v2.16b\n" - "smax v6.16b, v6.16b, v0.16b\n" - "ldr q30, [x24, x26]\n" - "smax v5.16b, v5.16b, v30.16b\n" + "smax v8.16b, v8.16b, v16.16b\n" + "ldr q17, [x20, x26]\n" + "ldr q16, [x20, x24]\n" + "smax v7.16b, v7.16b, v17.16b\n" + "smax v6.16b, v6.16b, v16.16b\n" + "ldr q16, [x20, x23]\n" + "smax v5.16b, v5.16b, v16.16b\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End "sxtl v23.8h, v8.8b\n" @@ -271,16 +272,16 @@ void a64_s8q_nhwc_max_generic_depthfirst_impl( "uzp1 v19.16b, v24.16b, v19.16b\n" "uzp1 v16.16b, v23.16b, v16.16b\n" "uzp1 v18.16b, v22.16b, v18.16b\n" - "str q16, [%x[outptr], x9]\n" - "add x9, x9, #0x40\n" + "str q16, [%x[outptr], x27]\n" + "add x27, x27, #0x40\n" "uzp1 v17.16b, v21.16b, v17.16b\n" "uzp1 v16.16b, v20.16b, v19.16b\n" - "str q18, [%x[outptr], x28]\n" - "add x28, x28, #0x40\n" - "str q17, [%x[outptr], x27]\n" - "add x27, x27, #0x40\n" - "str q16, [%x[outptr], x26]\n" + "str q18, [%x[outptr], x26]\n" "add x26, x26, #0x40\n" + "str q17, [%x[outptr], x24]\n" + "add x24, x24, #0x40\n" + "str q16, [%x[outptr], x23]\n" + "add x23, x23, #0x40\n" "bge 1b\n" "cbz %x[n_channels], 43f\n" "7:" // Single vector of channels @@ -289,296 +290,296 @@ void a64_s8q_nhwc_max_generic_depthfirst_impl( "8:" // Single vector of channels: Loop "lsr x25, %x[n_valid_cells], #0x2\n" "movi v8.16b, #0x80\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "cbz x25, 11f\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldr q4, [x24, x9]\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" "subs x25, x25, #0x1\n" - "ldr q3, [x23, x9]\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" - "ldr q28, [x22, x9]\n" - "ldr q22, [x21, x9]\n" + "ldr q3, [x20, x27]\n" + "ldp x21, x20, [x22, #0x10]\n" + "add x22, x22, #0x20\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 4 inputs loop - "smax v23.16b, v4.16b, v3.16b\n" - "smax v19.16b, v28.16b, v22.16b\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldr q4, [x24, x9]\n" - "ldr q3, [x23, x9]\n" - "smax v19.16b, v23.16b, v19.16b\n" - "ldp x22, x21, [x20, #0x10]\n" + "smax v17.16b, v4.16b, v3.16b\n" + "smax v16.16b, v28.16b, v22.16b\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "ldr q3, [x20, x27]\n" + "smax v16.16b, v17.16b, v16.16b\n" + "ldp x21, x20, [x22, #0x10]\n" "subs x25, x25, #0x1\n" - "ldr q28, [x22, x9]\n" - "ldr q22, [x21, x9]\n" - "smax v8.16b, v8.16b, v19.16b\n" - "add x20, x20, #0x20\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" + "smax v8.16b, v8.16b, v16.16b\n" + "add x22, x22, #0x20\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 4 inputs tail - "smax v23.16b, v4.16b, v3.16b\n" - "smax v19.16b, v28.16b, v22.16b\n" - "smax v19.16b, v23.16b, v19.16b\n" - "smax v8.16b, v8.16b, v19.16b\n" + "smax v17.16b, v4.16b, v3.16b\n" + "smax v16.16b, v28.16b, v22.16b\n" + "smax v16.16b, v17.16b, v16.16b\n" + "smax v8.16b, v8.16b, v16.16b\n" "11:" // Single vector of channels: Loop: After loop "ands x21, %x[n_valid_cells], #0x3\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x24, [x20], #0x8\n" - "ldr q4, [x24, x9]\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" "subs x21, x21, #0x1\n" - "smax v8.16b, v8.16b, v4.16b\n" + "smax v8.16b, v8.16b, v16.16b\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End - "sxtl v23.8h, v8.8b\n" - "sxtl2 v22.8h, v8.16b\n" + "sxtl v17.8h, v8.8b\n" + "sxtl2 v16.8h, v8.16b\n" "add x20, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n" - "ld1r { v4.4s }, [x20]\n" - "sxtl v1.4s, v23.4h\n" - "sxtl2 v23.4s, v23.8h\n" + "ld1r { v22.4s }, [x20]\n" + "sxtl v21.4s, v17.4h\n" + "sxtl2 v20.4s, v17.8h\n" "add x20, %x[quant_params], %[offsetof_qp_per_layer_mul]\n" - "ld1r { v3.4s }, [x20]\n" - "sxtl v0.4s, v22.4h\n" - "sxtl2 v31.4s, v22.8h\n" + "ld1r { v17.4s }, [x20]\n" + "sxtl v19.4s, v16.4h\n" + "sxtl2 v18.4s, v16.8h\n" "add x20, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n" - "ld1r { v2.4s }, [x20]\n" - "srshl v1.4s, v1.4s, v4.4s\n" - "srshl v23.4s, v23.4s, v4.4s\n" + "ld1r { v16.4s }, [x20]\n" + "srshl v21.4s, v21.4s, v22.4s\n" + "srshl v20.4s, v20.4s, v22.4s\n" "sub %x[n_channels], %x[n_channels], #0x10\n" "cmp %x[n_channels], #0x10\n" - "srshl v0.4s, v0.4s, v4.4s\n" - "srshl v31.4s, v31.4s, v4.4s\n" - "sqrdmulh v1.4s, v1.4s, v3.4s\n" - "sqrdmulh v23.4s, v23.4s, v3.4s\n" - "sqrdmulh v0.4s, v0.4s, v3.4s\n" - "sqrdmulh v31.4s, v31.4s, v3.4s\n" + "srshl v19.4s, v19.4s, v22.4s\n" + "srshl v18.4s, v18.4s, v22.4s\n" + "sqrdmulh v21.4s, v21.4s, v17.4s\n" + "sqrdmulh v20.4s, v20.4s, v17.4s\n" + "sqrdmulh v19.4s, v19.4s, v17.4s\n" + "sqrdmulh v18.4s, v18.4s, v17.4s\n" "movi v17.4s, #0x7f\n" - "srshl v1.4s, v1.4s, v2.4s\n" - "srshl v23.4s, v23.4s, v2.4s\n" - "srshl v0.4s, v0.4s, v2.4s\n" - "srshl v31.4s, v31.4s, v2.4s\n" + "srshl v21.4s, v21.4s, v16.4s\n" + "srshl v20.4s, v20.4s, v16.4s\n" + "srshl v19.4s, v19.4s, v16.4s\n" + "srshl v18.4s, v18.4s, v16.4s\n" "not v16.16b, v17.16b\n" - "smax v1.4s, v1.4s, v16.4s\n" - "smax v23.4s, v23.4s, v16.4s\n" - "smax v0.4s, v0.4s, v16.4s\n" - "smax v31.4s, v31.4s, v16.4s\n" - "smin v1.4s, v1.4s, v17.4s\n" - "smin v23.4s, v23.4s, v17.4s\n" - "smin v0.4s, v0.4s, v17.4s\n" - "smin v31.4s, v31.4s, v17.4s\n" - "uzp1 v23.16b, v1.16b, v23.16b\n" - "uzp1 v16.16b, v0.16b, v31.16b\n" - "uzp1 v16.16b, v23.16b, v16.16b\n" - "str q16, [%x[outptr], x9]\n" - "add x9, x9, #0x10\n" + "smax v21.4s, v21.4s, v16.4s\n" + "smax v20.4s, v20.4s, v16.4s\n" + "smax v19.4s, v19.4s, v16.4s\n" + "smax v18.4s, v18.4s, v16.4s\n" + "smin v21.4s, v21.4s, v17.4s\n" + "smin v20.4s, v20.4s, v17.4s\n" + "smin v19.4s, v19.4s, v17.4s\n" + "smin v18.4s, v18.4s, v17.4s\n" + "uzp1 v17.16b, v21.16b, v20.16b\n" + "uzp1 v16.16b, v19.16b, v18.16b\n" + "uzp1 v16.16b, v17.16b, v16.16b\n" + "str q16, [%x[outptr], x27]\n" + "add x27, x27, #0x10\n" "bge 8b\n" "cbz %x[n_channels], 43f\n" "14:" // Oddments "lsr x25, %x[n_valid_cells], #0x2\n" - "add %x[outptr], %x[outptr], x9\n" + "add %x[outptr], %x[outptr], x27\n" "movi v8.16b, #0x80\n" - "mov x20, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "cbz x25, 24f\n" "15:" // Oddments: 4 inputs loop - "ldp x24, x23, [x20, #0x0]\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" - "add x24, x24, x9\n" - "add x23, x23, x9\n" - "add x22, x22, x9\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "add x23, x23, x27\n" + "add x22, x22, x27\n" + "add x21, x21, x27\n" "movi v4.16b, #0x0\n" "movi v3.16b, #0x0\n" - "add x21, x21, x9\n" + "add x20, x20, x27\n" "movi v28.16b, #0x0\n" "movi v22.16b, #0x0\n" "tbz %x[n_channels], #3, 19f\n" - "ldr d4, [x24], #0x8\n" - "ldr d3, [x23], #0x8\n" - "ldr d28, [x22], #0x8\n" - "ldr d22, [x21], #0x8\n" + "ldr d4, [x23], #0x8\n" + "ldr d3, [x22], #0x8\n" + "ldr d28, [x21], #0x8\n" + "ldr d22, [x20], #0x8\n" "tbz %x[n_channels], #2, 17f\n" - "ld1 { v4.s }[2], [x24], #0x4\n" - "ld1 { v3.s }[2], [x23], #0x4\n" - "ld1 { v28.s }[2], [x22], #0x4\n" - "ld1 { v22.s }[2], [x21], #0x4\n" + "ld1 { v4.s }[2], [x23], #0x4\n" + "ld1 { v3.s }[2], [x22], #0x4\n" + "ld1 { v28.s }[2], [x21], #0x4\n" + "ld1 { v22.s }[2], [x20], #0x4\n" "tbz %x[n_channels], #1, 16f\n" - "ld1 { v4.h }[6], [x24], #0x2\n" - "ld1 { v3.h }[6], [x23], #0x2\n" - "ld1 { v28.h }[6], [x22], #0x2\n" - "ld1 { v22.h }[6], [x21], #0x2\n" + "ld1 { v4.h }[6], [x23], #0x2\n" + "ld1 { v3.h }[6], [x22], #0x2\n" + "ld1 { v28.h }[6], [x21], #0x2\n" + "ld1 { v22.h }[6], [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v4.b }[14], [x24], #0x1\n" - "ld1 { v3.b }[14], [x23], #0x1\n" - "ld1 { v28.b }[14], [x22], #0x1\n" - "ld1 { v22.b }[14], [x21], #0x1\n" + "ld1 { v4.b }[14], [x23], #0x1\n" + "ld1 { v3.b }[14], [x22], #0x1\n" + "ld1 { v28.b }[14], [x21], #0x1\n" + "ld1 { v22.b }[14], [x20], #0x1\n" "b 23f\n" "16:" // Oddments: 4 inputs loop: Load: Bit 3: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ld1 { v4.b }[12], [x24], #0x1\n" - "ld1 { v3.b }[12], [x23], #0x1\n" - "ld1 { v28.b }[12], [x22], #0x1\n" - "ld1 { v22.b }[12], [x21], #0x1\n" + "ld1 { v4.b }[12], [x23], #0x1\n" + "ld1 { v3.b }[12], [x22], #0x1\n" + "ld1 { v28.b }[12], [x21], #0x1\n" + "ld1 { v22.b }[12], [x20], #0x1\n" "b 23f\n" "17:" // Oddments: 4 inputs loop: Load: Bit 3: Bit 2: Unset "tbz %x[n_channels], #1, 18f\n" - "ld1 { v4.h }[4], [x24], #0x2\n" - "ld1 { v3.h }[4], [x23], #0x2\n" - "ld1 { v28.h }[4], [x22], #0x2\n" - "ld1 { v22.h }[4], [x21], #0x2\n" + "ld1 { v4.h }[4], [x23], #0x2\n" + "ld1 { v3.h }[4], [x22], #0x2\n" + "ld1 { v28.h }[4], [x21], #0x2\n" + "ld1 { v22.h }[4], [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v4.b }[10], [x24], #0x1\n" - "ld1 { v3.b }[10], [x23], #0x1\n" - "ld1 { v28.b }[10], [x22], #0x1\n" - "ld1 { v22.b }[10], [x21], #0x1\n" + "ld1 { v4.b }[10], [x23], #0x1\n" + "ld1 { v3.b }[10], [x22], #0x1\n" + "ld1 { v28.b }[10], [x21], #0x1\n" + "ld1 { v22.b }[10], [x20], #0x1\n" "b 23f\n" "18:" // Oddments: 4 inputs loop: Load: Bit 3: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ld1 { v4.b }[8], [x24], #0x1\n" - "ld1 { v3.b }[8], [x23], #0x1\n" - "ld1 { v28.b }[8], [x22], #0x1\n" - "ld1 { v22.b }[8], [x21], #0x1\n" + "ld1 { v4.b }[8], [x23], #0x1\n" + "ld1 { v3.b }[8], [x22], #0x1\n" + "ld1 { v28.b }[8], [x21], #0x1\n" + "ld1 { v22.b }[8], [x20], #0x1\n" "b 23f\n" "19:" // Oddments: 4 inputs loop: Load: Bit 3: Unset "tbz %x[n_channels], #2, 21f\n" - "ldr s4, [x24], #0x4\n" - "ldr s3, [x23], #0x4\n" - "ldr s28, [x22], #0x4\n" - "ldr s22, [x21], #0x4\n" + "ldr s4, [x23], #0x4\n" + "ldr s3, [x22], #0x4\n" + "ldr s28, [x21], #0x4\n" + "ldr s22, [x20], #0x4\n" "tbz %x[n_channels], #1, 20f\n" - "ld1 { v4.h }[2], [x24], #0x2\n" - "ld1 { v3.h }[2], [x23], #0x2\n" - "ld1 { v28.h }[2], [x22], #0x2\n" - "ld1 { v22.h }[2], [x21], #0x2\n" + "ld1 { v4.h }[2], [x23], #0x2\n" + "ld1 { v3.h }[2], [x22], #0x2\n" + "ld1 { v28.h }[2], [x21], #0x2\n" + "ld1 { v22.h }[2], [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v4.b }[6], [x24], #0x1\n" - "ld1 { v3.b }[6], [x23], #0x1\n" - "ld1 { v28.b }[6], [x22], #0x1\n" - "ld1 { v22.b }[6], [x21], #0x1\n" + "ld1 { v4.b }[6], [x23], #0x1\n" + "ld1 { v3.b }[6], [x22], #0x1\n" + "ld1 { v28.b }[6], [x21], #0x1\n" + "ld1 { v22.b }[6], [x20], #0x1\n" "b 23f\n" "20:" // Oddments: 4 inputs loop: Load: Bit 3: Unset: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ld1 { v4.b }[4], [x24], #0x1\n" - "ld1 { v3.b }[4], [x23], #0x1\n" - "ld1 { v28.b }[4], [x22], #0x1\n" - "ld1 { v22.b }[4], [x21], #0x1\n" + "ld1 { v4.b }[4], [x23], #0x1\n" + "ld1 { v3.b }[4], [x22], #0x1\n" + "ld1 { v28.b }[4], [x21], #0x1\n" + "ld1 { v22.b }[4], [x20], #0x1\n" "b 23f\n" "21:" // Oddments: 4 inputs loop: Load: Bit 3: Unset: Bit 2: Unset "tbz %x[n_channels], #1, 22f\n" - "ldr h4, [x24], #0x2\n" - "ldr h3, [x23], #0x2\n" - "ldr h28, [x22], #0x2\n" - "ldr h22, [x21], #0x2\n" + "ldr h4, [x23], #0x2\n" + "ldr h3, [x22], #0x2\n" + "ldr h28, [x21], #0x2\n" + "ldr h22, [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v4.b }[2], [x24], #0x1\n" - "ld1 { v3.b }[2], [x23], #0x1\n" - "ld1 { v28.b }[2], [x22], #0x1\n" - "ld1 { v22.b }[2], [x21], #0x1\n" + "ld1 { v4.b }[2], [x23], #0x1\n" + "ld1 { v3.b }[2], [x22], #0x1\n" + "ld1 { v28.b }[2], [x21], #0x1\n" + "ld1 { v22.b }[2], [x20], #0x1\n" "b 23f\n" "22:" // Oddments: 4 inputs loop: Load: Bit 3: Unset: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ldr b4, [x24], #0x1\n" - "ldr b3, [x23], #0x1\n" - "ldr b28, [x22], #0x1\n" - "ldr b22, [x21], #0x1\n" + "ldr b4, [x23], #0x1\n" + "ldr b3, [x22], #0x1\n" + "ldr b28, [x21], #0x1\n" + "ldr b22, [x20], #0x1\n" "23:" // Oddments: 4 inputs loop: Load: Bit 3: End - "smax v23.16b, v4.16b, v3.16b\n" - "smax v19.16b, v28.16b, v22.16b\n" + "smax v17.16b, v4.16b, v3.16b\n" + "smax v16.16b, v28.16b, v22.16b\n" "subs x25, x25, #0x1\n" - "smax v19.16b, v23.16b, v19.16b\n" - "smax v8.16b, v8.16b, v19.16b\n" + "smax v16.16b, v17.16b, v16.16b\n" + "smax v8.16b, v8.16b, v16.16b\n" "bgt 15b\n" "24:" // Oddments: After loop "ands x21, %x[n_valid_cells], #0x3\n" "beq 34f\n" "25:" // Oddments: Single input loop - "ldr x24, [x20], #0x8\n" - "add x24, x24, x9\n" + "ldr x23, [x24], #0x8\n" + "add x23, x23, x27\n" "movi v4.16b, #0x0\n" "tbz %x[n_channels], #3, 29f\n" - "ldr d4, [x24], #0x8\n" + "ldr d4, [x23], #0x8\n" "tbz %x[n_channels], #2, 27f\n" - "ld1 { v4.s }[2], [x24], #0x4\n" + "ld1 { v4.s }[2], [x23], #0x4\n" "tbz %x[n_channels], #1, 26f\n" - "ld1 { v4.h }[6], [x24], #0x2\n" + "ld1 { v4.h }[6], [x23], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v4.b }[14], [x24], #0x1\n" + "ld1 { v4.b }[14], [x23], #0x1\n" "b 33f\n" "26:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ld1 { v4.b }[12], [x24], #0x1\n" + "ld1 { v4.b }[12], [x23], #0x1\n" "b 33f\n" "27:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Unset "tbz %x[n_channels], #1, 28f\n" - "ld1 { v4.h }[4], [x24], #0x2\n" + "ld1 { v4.h }[4], [x23], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v4.b }[10], [x24], #0x1\n" + "ld1 { v4.b }[10], [x23], #0x1\n" "b 33f\n" "28:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ld1 { v4.b }[8], [x24], #0x1\n" + "ld1 { v4.b }[8], [x23], #0x1\n" "b 33f\n" "29:" // Oddments: Single input loop: Load: Bit 3: Unset "tbz %x[n_channels], #2, 31f\n" - "ldr s4, [x24], #0x4\n" + "ldr s4, [x23], #0x4\n" "tbz %x[n_channels], #1, 30f\n" - "ld1 { v4.h }[2], [x24], #0x2\n" + "ld1 { v4.h }[2], [x23], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v4.b }[6], [x24], #0x1\n" + "ld1 { v4.b }[6], [x23], #0x1\n" "b 33f\n" "30:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ld1 { v4.b }[4], [x24], #0x1\n" + "ld1 { v4.b }[4], [x23], #0x1\n" "b 33f\n" "31:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Unset "tbz %x[n_channels], #1, 32f\n" - "ldr h4, [x24], #0x2\n" + "ldr h4, [x23], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v4.b }[2], [x24], #0x1\n" + "ld1 { v4.b }[2], [x23], #0x1\n" "b 33f\n" "32:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ldr b4, [x24], #0x1\n" + "ldr b4, [x23], #0x1\n" "33:" // Oddments: Single input loop: Load: Bit 3: End "subs x21, x21, #0x1\n" "smax v8.16b, v8.16b, v4.16b\n" "bgt 25b\n" "34:" // Oddments: Single input loop: End - "sxtl v23.8h, v8.8b\n" - "sxtl2 v22.8h, v8.16b\n" + "sxtl v17.8h, v8.8b\n" + "sxtl2 v16.8h, v8.16b\n" "add x20, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n" - "ld1r { v4.4s }, [x20]\n" - "sxtl v1.4s, v23.4h\n" - "sxtl2 v23.4s, v23.8h\n" + "ld1r { v22.4s }, [x20]\n" + "sxtl v21.4s, v17.4h\n" + "sxtl2 v20.4s, v17.8h\n" "add x20, %x[quant_params], %[offsetof_qp_per_layer_mul]\n" - "ld1r { v3.4s }, [x20]\n" - "sxtl v0.4s, v22.4h\n" - "sxtl2 v31.4s, v22.8h\n" + "ld1r { v17.4s }, [x20]\n" + "sxtl v19.4s, v16.4h\n" + "sxtl2 v18.4s, v16.8h\n" "add x20, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n" - "ld1r { v2.4s }, [x20]\n" - "srshl v1.4s, v1.4s, v4.4s\n" - "srshl v23.4s, v23.4s, v4.4s\n" - "srshl v0.4s, v0.4s, v4.4s\n" - "srshl v31.4s, v31.4s, v4.4s\n" - "sqrdmulh v1.4s, v1.4s, v3.4s\n" - "sqrdmulh v23.4s, v23.4s, v3.4s\n" - "sqrdmulh v0.4s, v0.4s, v3.4s\n" - "sqrdmulh v31.4s, v31.4s, v3.4s\n" + "ld1r { v16.4s }, [x20]\n" + "srshl v21.4s, v21.4s, v22.4s\n" + "srshl v20.4s, v20.4s, v22.4s\n" + "srshl v19.4s, v19.4s, v22.4s\n" + "srshl v18.4s, v18.4s, v22.4s\n" + "sqrdmulh v21.4s, v21.4s, v17.4s\n" + "sqrdmulh v20.4s, v20.4s, v17.4s\n" + "sqrdmulh v19.4s, v19.4s, v17.4s\n" + "sqrdmulh v18.4s, v18.4s, v17.4s\n" "movi v17.4s, #0x7f\n" - "srshl v1.4s, v1.4s, v2.4s\n" - "srshl v23.4s, v23.4s, v2.4s\n" - "srshl v0.4s, v0.4s, v2.4s\n" - "srshl v31.4s, v31.4s, v2.4s\n" + "srshl v21.4s, v21.4s, v16.4s\n" + "srshl v20.4s, v20.4s, v16.4s\n" + "srshl v19.4s, v19.4s, v16.4s\n" + "srshl v18.4s, v18.4s, v16.4s\n" "not v16.16b, v17.16b\n" - "smax v1.4s, v1.4s, v16.4s\n" - "smax v23.4s, v23.4s, v16.4s\n" - "smax v0.4s, v0.4s, v16.4s\n" - "smax v31.4s, v31.4s, v16.4s\n" - "smin v1.4s, v1.4s, v17.4s\n" - "smin v23.4s, v23.4s, v17.4s\n" - "smin v0.4s, v0.4s, v17.4s\n" - "smin v31.4s, v31.4s, v17.4s\n" - "uzp1 v23.16b, v1.16b, v23.16b\n" - "uzp1 v16.16b, v0.16b, v31.16b\n" - "uzp1 v16.16b, v23.16b, v16.16b\n" + "smax v21.4s, v21.4s, v16.4s\n" + "smax v20.4s, v20.4s, v16.4s\n" + "smax v19.4s, v19.4s, v16.4s\n" + "smax v18.4s, v18.4s, v16.4s\n" + "smin v21.4s, v21.4s, v17.4s\n" + "smin v20.4s, v20.4s, v17.4s\n" + "smin v19.4s, v19.4s, v17.4s\n" + "smin v18.4s, v18.4s, v17.4s\n" + "uzp1 v17.16b, v21.16b, v20.16b\n" + "uzp1 v16.16b, v19.16b, v18.16b\n" + "uzp1 v16.16b, v17.16b, v16.16b\n" "tbz %x[n_channels], #3, 38f\n" "st1 { v16.d }[0], [%x[outptr]], #0x8\n" "tbz %x[n_channels], #2, 36f\n" @@ -627,10 +628,11 @@ void a64_s8q_nhwc_max_generic_depthfirst_impl( "43:" // End : [n_channels] "+&r" (n_channels), [outptr] "+&r" (outptr) : [inptrs] "r" (inptrs), [n_valid_cells] "r" (n_valid_cells), [offsetof_qp_per_layer_left_shift] "I" (offsetof(Requantize32, per_layer_left_shift)), [offsetof_qp_per_layer_mul] "I" (offsetof(Requantize32, per_layer_mul)), [offsetof_qp_per_layer_right_shift] "I" (offsetof(Requantize32, per_layer_right_shift)), [quant_params] "r" (&qp) - : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x9", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" + : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); } } // namespace pooling } // namespace arm_conv + #endif // defined(__aarch64__) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8_nhwc_avg_generic_depthfirst/generic.cpp index 76828a911e..f8984c451c 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8_nhwc_avg_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8_nhwc_avg_generic_depthfirst/generic.cpp @@ -22,14 +22,14 @@ * SOFTWARE. */ -#if defined(__aarch64__) - #include <cstdint> #include <cstddef> #include <cstring> #include <cmath> +#if defined(__aarch64__) + namespace arm_conv { namespace pooling { @@ -105,7 +105,7 @@ void a64_u8_nhwc_avg_generic_depthfirst_impl( "lsr x23, %x[n_valid_cells], #0x1\n" "movi v15.4s, #0x0\n" "movi v14.4s, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "movi v13.4s, #0x0\n" "movi v12.4s, #0x0\n" "movi v11.4s, #0x0\n" @@ -121,42 +121,42 @@ void a64_u8_nhwc_avg_generic_depthfirst_impl( "movi v1.4s, #0x0\n" "movi v0.4s, #0x0\n" "cbz x23, 4f\n" - "ldp x22, x21, [x20, #0x0]\n" - "ldr q31, [x22, x27]\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q31, [x21, x27]\n" "subs x23, x23, #0x1\n" - "add x20, x20, #0x10\n" - "ldr q30, [x21, x27]\n" - "ldr q29, [x22, x26]\n" - "ldr q28, [x21, x26]\n" - "ldr q27, [x22, x25]\n" - "ldr q26, [x21, x25]\n" - "ldr q25, [x22, x24]\n" - "ldr q24, [x21, x24]\n" + "add x22, x22, #0x10\n" + "ldr q30, [x20, x27]\n" + "ldr q29, [x21, x26]\n" + "ldr q28, [x20, x26]\n" + "ldr q27, [x21, x25]\n" + "ldr q26, [x20, x25]\n" + "ldr q25, [x21, x24]\n" + "ldr q24, [x20, x24]\n" "beq 3f\n" "2:" // 4-vectors of channels: 2 inputs loop "uaddl v23.8h, v31.8b, v30.8b\n" "uaddl2 v22.8h, v31.16b, v30.16b\n" - "ldp x22, x21, [x20, #0x0]\n" - "ldr q31, [x22, x27]\n" - "ldr q30, [x21, x27]\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q31, [x21, x27]\n" + "ldr q30, [x20, x27]\n" "uaddl v21.8h, v29.8b, v28.8b\n" "uaddl2 v20.8h, v29.16b, v28.16b\n" - "ldr q29, [x22, x26]\n" - "ldr q28, [x21, x26]\n" + "ldr q29, [x21, x26]\n" + "ldr q28, [x20, x26]\n" "uaddl v19.8h, v27.8b, v26.8b\n" "uaddl2 v18.8h, v27.16b, v26.16b\n" - "ldr q27, [x22, x25]\n" - "ldr q26, [x21, x25]\n" + "ldr q27, [x21, x25]\n" + "ldr q26, [x20, x25]\n" + "uaddl v17.8h, v25.8b, v24.8b\n" + "uaddl2 v16.8h, v25.16b, v24.16b\n" + "ldr q25, [x21, x24]\n" + "ldr q24, [x20, x24]\n" "subs x23, x23, #0x1\n" "uaddw v15.4s, v15.4s, v23.4h\n" "uaddw2 v14.4s, v14.4s, v23.8h\n" - "uaddl v17.8h, v25.8b, v24.8b\n" - "uaddl2 v16.8h, v25.16b, v24.16b\n" - "ldr q25, [x22, x24]\n" - "add x20, x20, #0x10\n" "uaddw v13.4s, v13.4s, v22.4h\n" "uaddw2 v12.4s, v12.4s, v22.8h\n" - "ldr q24, [x21, x24]\n" + "add x22, x22, #0x10\n" "uaddw v11.4s, v11.4s, v21.4h\n" "uaddw2 v10.4s, v10.4s, v21.8h\n" "uaddw v9.4s, v9.4s, v20.4h\n" @@ -196,23 +196,23 @@ void a64_u8_nhwc_avg_generic_depthfirst_impl( "uaddw v1.4s, v1.4s, v16.4h\n" "uaddw2 v0.4s, v0.4s, v16.8h\n" "4:" // 4-vectors of channels: After loop - "ands x21, %x[n_valid_cells], #0x1\n" + "ands x23, %x[n_valid_cells], #0x1\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x22, [x20], #0x8\n" - "ldr q31, [x22, x27]\n" - "uxtl v23.8h, v31.8b\n" - "uxtl2 v22.8h, v31.16b\n" - "ldr q29, [x22, x26]\n" - "ldr q27, [x22, x25]\n" - "uxtl v21.8h, v29.8b\n" - "uxtl2 v20.8h, v29.16b\n" - "ldr q25, [x22, x24]\n" - "uxtl v19.8h, v27.8b\n" - "uxtl2 v18.8h, v27.16b\n" - "subs x21, x21, #0x1\n" - "uxtl v17.8h, v25.8b\n" - "uxtl2 v16.8h, v25.16b\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" + "uxtl v23.8h, v16.8b\n" + "uxtl2 v22.8h, v16.16b\n" + "ldr q16, [x20, x26]\n" + "ldr q17, [x20, x25]\n" + "uxtl v21.8h, v16.8b\n" + "uxtl2 v20.8h, v16.16b\n" + "ldr q16, [x20, x24]\n" + "uxtl v19.8h, v17.8b\n" + "uxtl2 v18.8h, v17.16b\n" + "subs x23, x23, #0x1\n" + "uxtl v17.8h, v16.8b\n" + "uxtl2 v16.8h, v16.16b\n" "uaddw v15.4s, v15.4s, v23.4h\n" "uaddw2 v14.4s, v14.4s, v23.8h\n" "uaddw v13.4s, v13.4s, v22.4h\n" @@ -330,49 +330,49 @@ void a64_u8_nhwc_avg_generic_depthfirst_impl( "lsr x23, %x[n_valid_cells], #0x1\n" "movi v15.4s, #0x0\n" "movi v14.4s, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "movi v13.4s, #0x0\n" "movi v12.4s, #0x0\n" "cbz x23, 11f\n" - "ldp x22, x21, [x20, #0x0]\n" - "ldr q31, [x22, x27]\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q31, [x21, x27]\n" "subs x23, x23, #0x1\n" - "add x20, x20, #0x10\n" - "ldr q30, [x21, x27]\n" + "add x22, x22, #0x10\n" + "ldr q30, [x20, x27]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 2 inputs loop - "uaddl v23.8h, v31.8b, v30.8b\n" - "uaddl2 v22.8h, v31.16b, v30.16b\n" - "ldp x22, x21, [x20, #0x0]\n" - "ldr q31, [x22, x27]\n" - "ldr q30, [x21, x27]\n" + "uaddl v17.8h, v31.8b, v30.8b\n" + "uaddl2 v16.8h, v31.16b, v30.16b\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q31, [x21, x27]\n" + "ldr q30, [x20, x27]\n" "subs x23, x23, #0x1\n" - "uaddw v15.4s, v15.4s, v23.4h\n" - "uaddw2 v14.4s, v14.4s, v23.8h\n" - "uaddw v13.4s, v13.4s, v22.4h\n" - "uaddw2 v12.4s, v12.4s, v22.8h\n" - "add x20, x20, #0x10\n" + "uaddw v15.4s, v15.4s, v17.4h\n" + "uaddw2 v14.4s, v14.4s, v17.8h\n" + "uaddw v13.4s, v13.4s, v16.4h\n" + "uaddw2 v12.4s, v12.4s, v16.8h\n" + "add x22, x22, #0x10\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 2 inputs tail - "uaddl v23.8h, v31.8b, v30.8b\n" - "uaddl2 v22.8h, v31.16b, v30.16b\n" - "uaddw v15.4s, v15.4s, v23.4h\n" - "uaddw2 v14.4s, v14.4s, v23.8h\n" - "uaddw v13.4s, v13.4s, v22.4h\n" - "uaddw2 v12.4s, v12.4s, v22.8h\n" + "uaddl v17.8h, v31.8b, v30.8b\n" + "uaddl2 v16.8h, v31.16b, v30.16b\n" + "uaddw v15.4s, v15.4s, v17.4h\n" + "uaddw2 v14.4s, v14.4s, v17.8h\n" + "uaddw v13.4s, v13.4s, v16.4h\n" + "uaddw2 v12.4s, v12.4s, v16.8h\n" "11:" // Single vector of channels: Loop: After loop - "ands x21, %x[n_valid_cells], #0x1\n" + "ands x23, %x[n_valid_cells], #0x1\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x22, [x20], #0x8\n" - "ldr q31, [x22, x27]\n" - "uxtl v23.8h, v31.8b\n" - "uxtl2 v22.8h, v31.16b\n" - "subs x21, x21, #0x1\n" - "uaddw v15.4s, v15.4s, v23.4h\n" - "uaddw2 v14.4s, v14.4s, v23.8h\n" - "uaddw v13.4s, v13.4s, v22.4h\n" - "uaddw2 v12.4s, v12.4s, v22.8h\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" + "uxtl v17.8h, v16.8b\n" + "uxtl2 v16.8h, v16.16b\n" + "subs x23, x23, #0x1\n" + "uaddw v15.4s, v15.4s, v17.4h\n" + "uaddw2 v14.4s, v14.4s, v17.8h\n" + "uaddw v13.4s, v13.4s, v16.4h\n" + "uaddw2 v12.4s, v12.4s, v16.8h\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End "ld1r { v17.4s }, [%x[rescale_ptr]]\n" @@ -397,9 +397,9 @@ void a64_u8_nhwc_avg_generic_depthfirst_impl( "smin v14.4s, v14.4s, v16.4s\n" "smin v13.4s, v13.4s, v16.4s\n" "smin v12.4s, v12.4s, v16.4s\n" - "uzp1 v23.16b, v15.16b, v14.16b\n" + "uzp1 v17.16b, v15.16b, v14.16b\n" "uzp1 v16.16b, v13.16b, v12.16b\n" - "uzp1 v16.16b, v23.16b, v16.16b\n" + "uzp1 v16.16b, v17.16b, v16.16b\n" "str q16, [%x[outptr], x27]\n" "add x27, x27, #0x10\n" "bge 8b\n" @@ -411,142 +411,142 @@ void a64_u8_nhwc_avg_generic_depthfirst_impl( "movi v14.4s, #0x0\n" "movi v13.4s, #0x0\n" "movi v12.4s, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "cbz x23, 24f\n" "15:" // Oddments: 2 inputs loop - "ldp x22, x21, [x20, #0x0]\n" - "add x20, x20, #0x10\n" - "add x22, x22, x27\n" - "movi v31.16b, #0x0\n" + "ldp x21, x20, [x22, #0x0]\n" + "add x22, x22, #0x10\n" "add x21, x21, x27\n" + "movi v31.16b, #0x0\n" + "add x20, x20, x27\n" "movi v30.16b, #0x0\n" "tbz %x[n_channels], #3, 19f\n" - "ldr d31, [x22], #0x8\n" - "ldr d30, [x21], #0x8\n" + "ldr d31, [x21], #0x8\n" + "ldr d30, [x20], #0x8\n" "tbz %x[n_channels], #2, 17f\n" - "ld1 { v31.s }[2], [x22], #0x4\n" - "ld1 { v30.s }[2], [x21], #0x4\n" + "ld1 { v31.s }[2], [x21], #0x4\n" + "ld1 { v30.s }[2], [x20], #0x4\n" "tbz %x[n_channels], #1, 16f\n" - "ld1 { v31.h }[6], [x22], #0x2\n" - "ld1 { v30.h }[6], [x21], #0x2\n" + "ld1 { v31.h }[6], [x21], #0x2\n" + "ld1 { v30.h }[6], [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v31.b }[14], [x22], #0x1\n" - "ld1 { v30.b }[14], [x21], #0x1\n" + "ld1 { v31.b }[14], [x21], #0x1\n" + "ld1 { v30.b }[14], [x20], #0x1\n" "b 23f\n" "16:" // Oddments: 2 inputs loop: Load: Bit 3: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ld1 { v31.b }[12], [x22], #0x1\n" - "ld1 { v30.b }[12], [x21], #0x1\n" + "ld1 { v31.b }[12], [x21], #0x1\n" + "ld1 { v30.b }[12], [x20], #0x1\n" "b 23f\n" "17:" // Oddments: 2 inputs loop: Load: Bit 3: Bit 2: Unset "tbz %x[n_channels], #1, 18f\n" - "ld1 { v31.h }[4], [x22], #0x2\n" - "ld1 { v30.h }[4], [x21], #0x2\n" + "ld1 { v31.h }[4], [x21], #0x2\n" + "ld1 { v30.h }[4], [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v31.b }[10], [x22], #0x1\n" - "ld1 { v30.b }[10], [x21], #0x1\n" + "ld1 { v31.b }[10], [x21], #0x1\n" + "ld1 { v30.b }[10], [x20], #0x1\n" "b 23f\n" "18:" // Oddments: 2 inputs loop: Load: Bit 3: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ld1 { v31.b }[8], [x22], #0x1\n" - "ld1 { v30.b }[8], [x21], #0x1\n" + "ld1 { v31.b }[8], [x21], #0x1\n" + "ld1 { v30.b }[8], [x20], #0x1\n" "b 23f\n" "19:" // Oddments: 2 inputs loop: Load: Bit 3: Unset "tbz %x[n_channels], #2, 21f\n" - "ldr s31, [x22], #0x4\n" - "ldr s30, [x21], #0x4\n" + "ldr s31, [x21], #0x4\n" + "ldr s30, [x20], #0x4\n" "tbz %x[n_channels], #1, 20f\n" - "ld1 { v31.h }[2], [x22], #0x2\n" - "ld1 { v30.h }[2], [x21], #0x2\n" + "ld1 { v31.h }[2], [x21], #0x2\n" + "ld1 { v30.h }[2], [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v31.b }[6], [x22], #0x1\n" - "ld1 { v30.b }[6], [x21], #0x1\n" + "ld1 { v31.b }[6], [x21], #0x1\n" + "ld1 { v30.b }[6], [x20], #0x1\n" "b 23f\n" "20:" // Oddments: 2 inputs loop: Load: Bit 3: Unset: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ld1 { v31.b }[4], [x22], #0x1\n" - "ld1 { v30.b }[4], [x21], #0x1\n" + "ld1 { v31.b }[4], [x21], #0x1\n" + "ld1 { v30.b }[4], [x20], #0x1\n" "b 23f\n" "21:" // Oddments: 2 inputs loop: Load: Bit 3: Unset: Bit 2: Unset "tbz %x[n_channels], #1, 22f\n" - "ldr h31, [x22], #0x2\n" - "ldr h30, [x21], #0x2\n" + "ldr h31, [x21], #0x2\n" + "ldr h30, [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v31.b }[2], [x22], #0x1\n" - "ld1 { v30.b }[2], [x21], #0x1\n" + "ld1 { v31.b }[2], [x21], #0x1\n" + "ld1 { v30.b }[2], [x20], #0x1\n" "b 23f\n" "22:" // Oddments: 2 inputs loop: Load: Bit 3: Unset: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ldr b31, [x22], #0x1\n" - "ldr b30, [x21], #0x1\n" + "ldr b31, [x21], #0x1\n" + "ldr b30, [x20], #0x1\n" "23:" // Oddments: 2 inputs loop: Load: Bit 3: End - "uaddl v23.8h, v31.8b, v30.8b\n" - "uaddl2 v22.8h, v31.16b, v30.16b\n" + "uaddl v17.8h, v31.8b, v30.8b\n" + "uaddl2 v16.8h, v31.16b, v30.16b\n" "subs x23, x23, #0x1\n" - "uaddw v15.4s, v15.4s, v23.4h\n" - "uaddw2 v14.4s, v14.4s, v23.8h\n" - "uaddw v13.4s, v13.4s, v22.4h\n" - "uaddw2 v12.4s, v12.4s, v22.8h\n" + "uaddw v15.4s, v15.4s, v17.4h\n" + "uaddw2 v14.4s, v14.4s, v17.8h\n" + "uaddw v13.4s, v13.4s, v16.4h\n" + "uaddw2 v12.4s, v12.4s, v16.8h\n" "bgt 15b\n" "24:" // Oddments: After loop - "ands x21, %x[n_valid_cells], #0x1\n" + "ands x23, %x[n_valid_cells], #0x1\n" "beq 34f\n" "25:" // Oddments: Single input loop - "ldr x22, [x20], #0x8\n" - "add x22, x22, x27\n" + "ldr x21, [x22], #0x8\n" + "add x21, x21, x27\n" "movi v31.16b, #0x0\n" "tbz %x[n_channels], #3, 29f\n" - "ldr d31, [x22], #0x8\n" + "ldr d31, [x21], #0x8\n" "tbz %x[n_channels], #2, 27f\n" - "ld1 { v31.s }[2], [x22], #0x4\n" + "ld1 { v31.s }[2], [x21], #0x4\n" "tbz %x[n_channels], #1, 26f\n" - "ld1 { v31.h }[6], [x22], #0x2\n" + "ld1 { v31.h }[6], [x21], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v31.b }[14], [x22], #0x1\n" + "ld1 { v31.b }[14], [x21], #0x1\n" "b 33f\n" "26:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ld1 { v31.b }[12], [x22], #0x1\n" + "ld1 { v31.b }[12], [x21], #0x1\n" "b 33f\n" "27:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Unset "tbz %x[n_channels], #1, 28f\n" - "ld1 { v31.h }[4], [x22], #0x2\n" + "ld1 { v31.h }[4], [x21], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v31.b }[10], [x22], #0x1\n" + "ld1 { v31.b }[10], [x21], #0x1\n" "b 33f\n" "28:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ld1 { v31.b }[8], [x22], #0x1\n" + "ld1 { v31.b }[8], [x21], #0x1\n" "b 33f\n" "29:" // Oddments: Single input loop: Load: Bit 3: Unset "tbz %x[n_channels], #2, 31f\n" - "ldr s31, [x22], #0x4\n" + "ldr s31, [x21], #0x4\n" "tbz %x[n_channels], #1, 30f\n" - "ld1 { v31.h }[2], [x22], #0x2\n" + "ld1 { v31.h }[2], [x21], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v31.b }[6], [x22], #0x1\n" + "ld1 { v31.b }[6], [x21], #0x1\n" "b 33f\n" "30:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ld1 { v31.b }[4], [x22], #0x1\n" + "ld1 { v31.b }[4], [x21], #0x1\n" "b 33f\n" "31:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Unset "tbz %x[n_channels], #1, 32f\n" - "ldr h31, [x22], #0x2\n" + "ldr h31, [x21], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v31.b }[2], [x22], #0x1\n" + "ld1 { v31.b }[2], [x21], #0x1\n" "b 33f\n" "32:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ldr b31, [x22], #0x1\n" + "ldr b31, [x21], #0x1\n" "33:" // Oddments: Single input loop: Load: Bit 3: End - "uxtl v23.8h, v31.8b\n" - "uxtl2 v22.8h, v31.16b\n" - "subs x21, x21, #0x1\n" - "uaddw v15.4s, v15.4s, v23.4h\n" - "uaddw2 v14.4s, v14.4s, v23.8h\n" - "uaddw v13.4s, v13.4s, v22.4h\n" - "uaddw2 v12.4s, v12.4s, v22.8h\n" + "uxtl v17.8h, v31.8b\n" + "uxtl2 v16.8h, v31.16b\n" + "subs x23, x23, #0x1\n" + "uaddw v15.4s, v15.4s, v17.4h\n" + "uaddw2 v14.4s, v14.4s, v17.8h\n" + "uaddw v13.4s, v13.4s, v16.4h\n" + "uaddw2 v12.4s, v12.4s, v16.8h\n" "bgt 25b\n" "34:" // Oddments: Single input loop: End "ld1r { v17.4s }, [%x[rescale_ptr]]\n" @@ -569,9 +569,9 @@ void a64_u8_nhwc_avg_generic_depthfirst_impl( "smin v14.4s, v14.4s, v16.4s\n" "smin v13.4s, v13.4s, v16.4s\n" "smin v12.4s, v12.4s, v16.4s\n" - "uzp1 v23.16b, v15.16b, v14.16b\n" + "uzp1 v17.16b, v15.16b, v14.16b\n" "uzp1 v16.16b, v13.16b, v12.16b\n" - "uzp1 v16.16b, v23.16b, v16.16b\n" + "uzp1 v16.16b, v17.16b, v16.16b\n" "tbz %x[n_channels], #3, 38f\n" "st1 { v16.d }[0], [%x[outptr]], #0x8\n" "tbz %x[n_channels], #2, 36f\n" @@ -626,4 +626,5 @@ void a64_u8_nhwc_avg_generic_depthfirst_impl( } // namespace pooling } // namespace arm_conv + #endif // defined(__aarch64__) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp index 556d833681..9d160bf8f8 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -24,6 +24,8 @@ #pragma once +#if defined(__aarch64__) + namespace arm_conv { namespace pooling { @@ -45,3 +47,5 @@ struct a64_u8_nhwc_max_2x2_s1_output2x2_depthfirst : public DepthfirstStrategy<u } // namespace pooling } // namespace arm_conv + +#endif // defined(__aarch64__) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp index 149566197a..66cdb7f849 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp @@ -22,11 +22,12 @@ * SOFTWARE. */ -#if defined(__aarch64__) #include <cstddef> #include <cstdint> +#if defined(__aarch64__) + namespace arm_conv { namespace pooling { @@ -111,7 +112,7 @@ void a64_u8_nhwc_max_2x2_s1_output2x2_depthfirst_impl( "umax v18.16b, v18.16b, v21.16b\n" "umax v17.16b, v17.16b, v20.16b\n" "add x15, x15, #0x10\n" - "umax v16.16b, v16.16b, v20.16b\n" + "umax v16.16b, v20.16b, v16.16b\n" "str q19, [x14, x12]\n" "str q18, [x13, x12]\n" "str q17, [x11, x12]\n" @@ -121,43 +122,43 @@ void a64_u8_nhwc_max_2x2_s1_output2x2_depthfirst_impl( "2:" // Vector: Tail "umax v21.16b, v30.16b, v29.16b\n" "umax v20.16b, v29.16b, v28.16b\n" - "umax v19.16b, v27.16b, v26.16b\n" + "umax v16.16b, v27.16b, v26.16b\n" "umax v18.16b, v25.16b, v24.16b\n" "umax v17.16b, v27.16b, v23.16b\n" - "umax v16.16b, v24.16b, v22.16b\n" - "umax v19.16b, v21.16b, v19.16b\n" + "umax v19.16b, v24.16b, v22.16b\n" + "umax v16.16b, v21.16b, v16.16b\n" "umax v18.16b, v18.16b, v21.16b\n" - "str q19, [x14, x12]\n" + "str q16, [x14, x12]\n" "umax v17.16b, v17.16b, v20.16b\n" - "umax v16.16b, v16.16b, v20.16b\n" + "umax v16.16b, v20.16b, v19.16b\n" "str q18, [x13, x12]\n" "str q17, [x11, x12]\n" "str q16, [x10, x12]\n" "add x12, x12, #0x10\n" "cbz x16, 4f\n" "3:" // Oddments - "ldr b30, [x28, x15]\n" - "ldr b29, [x25, x15]\n" - "umax v21.16b, v30.16b, v29.16b\n" + "ldr b16, [x28, x15]\n" + "ldr b17, [x25, x15]\n" + "umax v23.16b, v16.16b, v17.16b\n" "subs x16, x16, #0x1\n" - "ldr b28, [x22, x15]\n" - "ldr b27, [x26, x15]\n" - "umax v20.16b, v29.16b, v28.16b\n" - "ldr b26, [x9, x15]\n" - "ldr b25, [x27, x15]\n" - "umax v19.16b, v27.16b, v26.16b\n" - "umax v19.16b, v21.16b, v19.16b\n" - "ldr b24, [x24, x15]\n" - "ldr b23, [x23, x15]\n" - "umax v18.16b, v25.16b, v24.16b\n" - "umax v17.16b, v27.16b, v23.16b\n" - "ldr b22, [x21, x15]\n" - "umax v16.16b, v24.16b, v22.16b\n" + "ldr b16, [x22, x15]\n" + "ldr b22, [x26, x15]\n" + "umax v21.16b, v17.16b, v16.16b\n" + "ldr b16, [x9, x15]\n" + "ldr b17, [x27, x15]\n" + "umax v16.16b, v22.16b, v16.16b\n" + "umax v20.16b, v23.16b, v16.16b\n" + "ldr b19, [x24, x15]\n" + "ldr b16, [x23, x15]\n" + "umax v18.16b, v17.16b, v19.16b\n" + "umax v17.16b, v22.16b, v16.16b\n" + "ldr b16, [x21, x15]\n" + "umax v16.16b, v19.16b, v16.16b\n" "add x15, x15, #0x1\n" - "umax v18.16b, v18.16b, v21.16b\n" - "umax v17.16b, v17.16b, v20.16b\n" - "umax v16.16b, v16.16b, v20.16b\n" - "str b19, [x14, x12]\n" + "umax v18.16b, v18.16b, v23.16b\n" + "umax v17.16b, v17.16b, v21.16b\n" + "umax v16.16b, v21.16b, v16.16b\n" + "str b20, [x14, x12]\n" "str b18, [x13, x12]\n" "str b17, [x11, x12]\n" "str b16, [x10, x12]\n" @@ -172,4 +173,5 @@ void a64_u8_nhwc_max_2x2_s1_output2x2_depthfirst_impl( } // namespace pooling } // namespace arm_conv + #endif // defined(__aarch64__) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8_nhwc_max_generic_depthfirst/generic.cpp index 98f5b8351c..2ceef125ca 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8_nhwc_max_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8_nhwc_max_generic_depthfirst/generic.cpp @@ -22,11 +22,11 @@ * SOFTWARE. */ -#if defined(__aarch64__) - #include <cstdint> #include <cstddef> +#if defined(__aarch64__) + namespace arm_conv { namespace pooling { @@ -41,77 +41,77 @@ void a64_u8_nhwc_max_generic_depthfirst_impl( { __asm__ __volatile__( "cmp %x[n_channels], #0x40\n" - "mov x9, #0x0\n" - "mov x28, #0x10\n" // cntb _, ALL, #1 - "mov x27, #0x20\n" // cntb _, ALL, #2 - "mov x26, #0x30\n" // cntb _, ALL, #3 + "mov x27, #0x0\n" + "mov x26, #0x10\n" // cntb _, ALL, #1 + "mov x24, #0x20\n" // cntb _, ALL, #2 + "mov x23, #0x30\n" // cntb _, ALL, #3 "blt 7f\n" "1:" // 4-vectors of channels "lsr x25, %x[n_valid_cells], #0x2\n" "movi v8.16b, #0x0\n" "movi v7.16b, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "movi v6.16b, #0x0\n" "movi v5.16b, #0x0\n" "cbz x25, 4f\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldr q4, [x24, x9]\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" "subs x25, x25, #0x1\n" - "ldr q3, [x23, x9]\n" - "ldr q2, [x24, x28]\n" - "ldr q1, [x23, x28]\n" - "ldr q0, [x24, x27]\n" - "ldr q31, [x23, x27]\n" - "ldr q30, [x24, x26]\n" - "ldr q29, [x23, x26]\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" - "ldr q28, [x22, x9]\n" - "ldr q22, [x21, x9]\n" - "ldr q27, [x22, x28]\n" - "ldr q21, [x21, x28]\n" - "ldr q26, [x22, x27]\n" - "ldr q20, [x21, x27]\n" - "ldr q25, [x22, x26]\n" - "ldr q24, [x21, x26]\n" + "ldr q3, [x20, x27]\n" + "ldr q2, [x21, x26]\n" + "ldr q1, [x20, x26]\n" + "ldr q0, [x21, x24]\n" + "ldr q31, [x20, x24]\n" + "ldr q30, [x21, x23]\n" + "ldr q29, [x20, x23]\n" + "ldp x21, x20, [x22, #0x10]\n" + "add x22, x22, #0x20\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" + "ldr q27, [x21, x26]\n" + "ldr q21, [x20, x26]\n" + "ldr q26, [x21, x24]\n" + "ldr q20, [x20, x24]\n" + "ldr q25, [x21, x23]\n" + "ldr q24, [x20, x23]\n" "beq 3f\n" "2:" // 4-vectors of channels: 4 inputs loop "umax v23.16b, v4.16b, v3.16b\n" "umax v19.16b, v28.16b, v22.16b\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldr q4, [x24, x9]\n" - "ldr q3, [x23, x9]\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "ldr q3, [x20, x27]\n" "umax v22.16b, v2.16b, v1.16b\n" - "ldr q2, [x24, x28]\n" + "ldr q2, [x21, x26]\n" "umax v18.16b, v27.16b, v21.16b\n" - "ldr q1, [x23, x28]\n" + "ldr q1, [x20, x26]\n" "umax v21.16b, v0.16b, v31.16b\n" - "ldr q0, [x24, x27]\n" + "ldr q0, [x21, x24]\n" "umax v17.16b, v26.16b, v20.16b\n" - "ldr q31, [x23, x27]\n" + "ldr q31, [x20, x24]\n" "umax v20.16b, v30.16b, v29.16b\n" - "ldr q30, [x24, x26]\n" + "ldr q30, [x21, x23]\n" "umax v16.16b, v25.16b, v24.16b\n" - "ldr q29, [x23, x26]\n" + "ldr q29, [x20, x23]\n" "umax v19.16b, v23.16b, v19.16b\n" "umax v18.16b, v22.16b, v18.16b\n" - "ldp x22, x21, [x20, #0x10]\n" - "ldr q28, [x22, x9]\n" - "ldr q22, [x21, x9]\n" + "ldp x21, x20, [x22, #0x10]\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" "umax v17.16b, v21.16b, v17.16b\n" "umax v16.16b, v20.16b, v16.16b\n" - "ldr q27, [x22, x28]\n" - "ldr q21, [x21, x28]\n" + "ldr q27, [x21, x26]\n" + "ldr q21, [x20, x26]\n" "subs x25, x25, #0x1\n" "umax v8.16b, v8.16b, v19.16b\n" - "ldr q26, [x22, x27]\n" - "ldr q20, [x21, x27]\n" + "ldr q26, [x21, x24]\n" + "ldr q20, [x20, x24]\n" "umax v7.16b, v7.16b, v18.16b\n" "umax v6.16b, v6.16b, v17.16b\n" - "ldr q25, [x22, x26]\n" - "ldr q24, [x21, x26]\n" + "ldr q25, [x21, x23]\n" + "ldr q24, [x20, x23]\n" "umax v5.16b, v5.16b, v16.16b\n" - "add x20, x20, #0x20\n" + "add x22, x22, #0x20\n" "bgt 2b\n" "3:" // 4-vectors of channels: 4 inputs tail "umax v23.16b, v4.16b, v3.16b\n" @@ -134,28 +134,28 @@ void a64_u8_nhwc_max_generic_depthfirst_impl( "ands x21, %x[n_valid_cells], #0x3\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x24, [x20], #0x8\n" - "ldr q4, [x24, x9]\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" "subs x21, x21, #0x1\n" - "umax v8.16b, v8.16b, v4.16b\n" - "ldr q2, [x24, x28]\n" - "ldr q0, [x24, x27]\n" - "umax v7.16b, v7.16b, v2.16b\n" - "umax v6.16b, v6.16b, v0.16b\n" - "ldr q30, [x24, x26]\n" - "umax v5.16b, v5.16b, v30.16b\n" + "umax v8.16b, v8.16b, v16.16b\n" + "ldr q17, [x20, x26]\n" + "ldr q16, [x20, x24]\n" + "umax v7.16b, v7.16b, v17.16b\n" + "umax v6.16b, v6.16b, v16.16b\n" + "ldr q16, [x20, x23]\n" + "umax v5.16b, v5.16b, v16.16b\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End "sub %x[n_channels], %x[n_channels], #0x40\n" "cmp %x[n_channels], #0x40\n" - "str q8, [%x[outptr], x9]\n" - "str q7, [%x[outptr], x28]\n" - "add x9, x9, #0x40\n" - "add x28, x28, #0x40\n" - "str q6, [%x[outptr], x27]\n" + "str q8, [%x[outptr], x27]\n" + "str q7, [%x[outptr], x26]\n" "add x27, x27, #0x40\n" - "str q5, [%x[outptr], x26]\n" "add x26, x26, #0x40\n" + "str q6, [%x[outptr], x24]\n" + "add x24, x24, #0x40\n" + "str q5, [%x[outptr], x23]\n" + "add x23, x23, #0x40\n" "bge 1b\n" "cbz %x[n_channels], 43f\n" "7:" // Single vector of channels @@ -164,217 +164,217 @@ void a64_u8_nhwc_max_generic_depthfirst_impl( "8:" // Single vector of channels: Loop "lsr x25, %x[n_valid_cells], #0x2\n" "movi v8.16b, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "cbz x25, 11f\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldr q4, [x24, x9]\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" "subs x25, x25, #0x1\n" - "ldr q3, [x23, x9]\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" - "ldr q28, [x22, x9]\n" - "ldr q22, [x21, x9]\n" + "ldr q3, [x20, x27]\n" + "ldp x21, x20, [x22, #0x10]\n" + "add x22, x22, #0x20\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 4 inputs loop - "umax v23.16b, v4.16b, v3.16b\n" - "umax v19.16b, v28.16b, v22.16b\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldr q4, [x24, x9]\n" - "ldr q3, [x23, x9]\n" - "umax v19.16b, v23.16b, v19.16b\n" - "ldp x22, x21, [x20, #0x10]\n" + "umax v17.16b, v4.16b, v3.16b\n" + "umax v16.16b, v28.16b, v22.16b\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "ldr q3, [x20, x27]\n" + "umax v16.16b, v17.16b, v16.16b\n" + "ldp x21, x20, [x22, #0x10]\n" "subs x25, x25, #0x1\n" - "ldr q28, [x22, x9]\n" - "ldr q22, [x21, x9]\n" - "umax v8.16b, v8.16b, v19.16b\n" - "add x20, x20, #0x20\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" + "umax v8.16b, v8.16b, v16.16b\n" + "add x22, x22, #0x20\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 4 inputs tail - "umax v23.16b, v4.16b, v3.16b\n" - "umax v19.16b, v28.16b, v22.16b\n" - "umax v19.16b, v23.16b, v19.16b\n" - "umax v8.16b, v8.16b, v19.16b\n" + "umax v17.16b, v4.16b, v3.16b\n" + "umax v16.16b, v28.16b, v22.16b\n" + "umax v16.16b, v17.16b, v16.16b\n" + "umax v8.16b, v8.16b, v16.16b\n" "11:" // Single vector of channels: Loop: After loop "ands x21, %x[n_valid_cells], #0x3\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x24, [x20], #0x8\n" - "ldr q4, [x24, x9]\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" "subs x21, x21, #0x1\n" - "umax v8.16b, v8.16b, v4.16b\n" + "umax v8.16b, v8.16b, v16.16b\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End "sub %x[n_channels], %x[n_channels], #0x10\n" "cmp %x[n_channels], #0x10\n" - "str q8, [%x[outptr], x9]\n" - "add x9, x9, #0x10\n" + "str q8, [%x[outptr], x27]\n" + "add x27, x27, #0x10\n" "bge 8b\n" "cbz %x[n_channels], 43f\n" "14:" // Oddments "lsr x25, %x[n_valid_cells], #0x2\n" - "add %x[outptr], %x[outptr], x9\n" + "add %x[outptr], %x[outptr], x27\n" "movi v8.16b, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "cbz x25, 24f\n" "15:" // Oddments: 4 inputs loop - "ldp x24, x23, [x20, #0x0]\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" - "add x24, x24, x9\n" - "add x23, x23, x9\n" - "add x22, x22, x9\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "add x23, x23, x27\n" + "add x22, x22, x27\n" + "add x21, x21, x27\n" "movi v4.16b, #0x0\n" "movi v3.16b, #0x0\n" - "add x21, x21, x9\n" + "add x20, x20, x27\n" "movi v28.16b, #0x0\n" "movi v22.16b, #0x0\n" "tbz %x[n_channels], #3, 19f\n" - "ldr d4, [x24], #0x8\n" - "ldr d3, [x23], #0x8\n" - "ldr d28, [x22], #0x8\n" - "ldr d22, [x21], #0x8\n" + "ldr d4, [x23], #0x8\n" + "ldr d3, [x22], #0x8\n" + "ldr d28, [x21], #0x8\n" + "ldr d22, [x20], #0x8\n" "tbz %x[n_channels], #2, 17f\n" - "ld1 { v4.s }[2], [x24], #0x4\n" - "ld1 { v3.s }[2], [x23], #0x4\n" - "ld1 { v28.s }[2], [x22], #0x4\n" - "ld1 { v22.s }[2], [x21], #0x4\n" + "ld1 { v4.s }[2], [x23], #0x4\n" + "ld1 { v3.s }[2], [x22], #0x4\n" + "ld1 { v28.s }[2], [x21], #0x4\n" + "ld1 { v22.s }[2], [x20], #0x4\n" "tbz %x[n_channels], #1, 16f\n" - "ld1 { v4.h }[6], [x24], #0x2\n" - "ld1 { v3.h }[6], [x23], #0x2\n" - "ld1 { v28.h }[6], [x22], #0x2\n" - "ld1 { v22.h }[6], [x21], #0x2\n" + "ld1 { v4.h }[6], [x23], #0x2\n" + "ld1 { v3.h }[6], [x22], #0x2\n" + "ld1 { v28.h }[6], [x21], #0x2\n" + "ld1 { v22.h }[6], [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v4.b }[14], [x24], #0x1\n" - "ld1 { v3.b }[14], [x23], #0x1\n" - "ld1 { v28.b }[14], [x22], #0x1\n" - "ld1 { v22.b }[14], [x21], #0x1\n" + "ld1 { v4.b }[14], [x23], #0x1\n" + "ld1 { v3.b }[14], [x22], #0x1\n" + "ld1 { v28.b }[14], [x21], #0x1\n" + "ld1 { v22.b }[14], [x20], #0x1\n" "b 23f\n" "16:" // Oddments: 4 inputs loop: Load: Bit 3: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ld1 { v4.b }[12], [x24], #0x1\n" - "ld1 { v3.b }[12], [x23], #0x1\n" - "ld1 { v28.b }[12], [x22], #0x1\n" - "ld1 { v22.b }[12], [x21], #0x1\n" + "ld1 { v4.b }[12], [x23], #0x1\n" + "ld1 { v3.b }[12], [x22], #0x1\n" + "ld1 { v28.b }[12], [x21], #0x1\n" + "ld1 { v22.b }[12], [x20], #0x1\n" "b 23f\n" "17:" // Oddments: 4 inputs loop: Load: Bit 3: Bit 2: Unset "tbz %x[n_channels], #1, 18f\n" - "ld1 { v4.h }[4], [x24], #0x2\n" - "ld1 { v3.h }[4], [x23], #0x2\n" - "ld1 { v28.h }[4], [x22], #0x2\n" - "ld1 { v22.h }[4], [x21], #0x2\n" + "ld1 { v4.h }[4], [x23], #0x2\n" + "ld1 { v3.h }[4], [x22], #0x2\n" + "ld1 { v28.h }[4], [x21], #0x2\n" + "ld1 { v22.h }[4], [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v4.b }[10], [x24], #0x1\n" - "ld1 { v3.b }[10], [x23], #0x1\n" - "ld1 { v28.b }[10], [x22], #0x1\n" - "ld1 { v22.b }[10], [x21], #0x1\n" + "ld1 { v4.b }[10], [x23], #0x1\n" + "ld1 { v3.b }[10], [x22], #0x1\n" + "ld1 { v28.b }[10], [x21], #0x1\n" + "ld1 { v22.b }[10], [x20], #0x1\n" "b 23f\n" "18:" // Oddments: 4 inputs loop: Load: Bit 3: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ld1 { v4.b }[8], [x24], #0x1\n" - "ld1 { v3.b }[8], [x23], #0x1\n" - "ld1 { v28.b }[8], [x22], #0x1\n" - "ld1 { v22.b }[8], [x21], #0x1\n" + "ld1 { v4.b }[8], [x23], #0x1\n" + "ld1 { v3.b }[8], [x22], #0x1\n" + "ld1 { v28.b }[8], [x21], #0x1\n" + "ld1 { v22.b }[8], [x20], #0x1\n" "b 23f\n" "19:" // Oddments: 4 inputs loop: Load: Bit 3: Unset "tbz %x[n_channels], #2, 21f\n" - "ldr s4, [x24], #0x4\n" - "ldr s3, [x23], #0x4\n" - "ldr s28, [x22], #0x4\n" - "ldr s22, [x21], #0x4\n" + "ldr s4, [x23], #0x4\n" + "ldr s3, [x22], #0x4\n" + "ldr s28, [x21], #0x4\n" + "ldr s22, [x20], #0x4\n" "tbz %x[n_channels], #1, 20f\n" - "ld1 { v4.h }[2], [x24], #0x2\n" - "ld1 { v3.h }[2], [x23], #0x2\n" - "ld1 { v28.h }[2], [x22], #0x2\n" - "ld1 { v22.h }[2], [x21], #0x2\n" + "ld1 { v4.h }[2], [x23], #0x2\n" + "ld1 { v3.h }[2], [x22], #0x2\n" + "ld1 { v28.h }[2], [x21], #0x2\n" + "ld1 { v22.h }[2], [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v4.b }[6], [x24], #0x1\n" - "ld1 { v3.b }[6], [x23], #0x1\n" - "ld1 { v28.b }[6], [x22], #0x1\n" - "ld1 { v22.b }[6], [x21], #0x1\n" + "ld1 { v4.b }[6], [x23], #0x1\n" + "ld1 { v3.b }[6], [x22], #0x1\n" + "ld1 { v28.b }[6], [x21], #0x1\n" + "ld1 { v22.b }[6], [x20], #0x1\n" "b 23f\n" "20:" // Oddments: 4 inputs loop: Load: Bit 3: Unset: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ld1 { v4.b }[4], [x24], #0x1\n" - "ld1 { v3.b }[4], [x23], #0x1\n" - "ld1 { v28.b }[4], [x22], #0x1\n" - "ld1 { v22.b }[4], [x21], #0x1\n" + "ld1 { v4.b }[4], [x23], #0x1\n" + "ld1 { v3.b }[4], [x22], #0x1\n" + "ld1 { v28.b }[4], [x21], #0x1\n" + "ld1 { v22.b }[4], [x20], #0x1\n" "b 23f\n" "21:" // Oddments: 4 inputs loop: Load: Bit 3: Unset: Bit 2: Unset "tbz %x[n_channels], #1, 22f\n" - "ldr h4, [x24], #0x2\n" - "ldr h3, [x23], #0x2\n" - "ldr h28, [x22], #0x2\n" - "ldr h22, [x21], #0x2\n" + "ldr h4, [x23], #0x2\n" + "ldr h3, [x22], #0x2\n" + "ldr h28, [x21], #0x2\n" + "ldr h22, [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v4.b }[2], [x24], #0x1\n" - "ld1 { v3.b }[2], [x23], #0x1\n" - "ld1 { v28.b }[2], [x22], #0x1\n" - "ld1 { v22.b }[2], [x21], #0x1\n" + "ld1 { v4.b }[2], [x23], #0x1\n" + "ld1 { v3.b }[2], [x22], #0x1\n" + "ld1 { v28.b }[2], [x21], #0x1\n" + "ld1 { v22.b }[2], [x20], #0x1\n" "b 23f\n" "22:" // Oddments: 4 inputs loop: Load: Bit 3: Unset: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ldr b4, [x24], #0x1\n" - "ldr b3, [x23], #0x1\n" - "ldr b28, [x22], #0x1\n" - "ldr b22, [x21], #0x1\n" + "ldr b4, [x23], #0x1\n" + "ldr b3, [x22], #0x1\n" + "ldr b28, [x21], #0x1\n" + "ldr b22, [x20], #0x1\n" "23:" // Oddments: 4 inputs loop: Load: Bit 3: End - "umax v23.16b, v4.16b, v3.16b\n" - "umax v19.16b, v28.16b, v22.16b\n" + "umax v17.16b, v4.16b, v3.16b\n" + "umax v16.16b, v28.16b, v22.16b\n" "subs x25, x25, #0x1\n" - "umax v19.16b, v23.16b, v19.16b\n" - "umax v8.16b, v8.16b, v19.16b\n" + "umax v16.16b, v17.16b, v16.16b\n" + "umax v8.16b, v8.16b, v16.16b\n" "bgt 15b\n" "24:" // Oddments: After loop "ands x21, %x[n_valid_cells], #0x3\n" "beq 34f\n" "25:" // Oddments: Single input loop - "ldr x24, [x20], #0x8\n" - "add x24, x24, x9\n" + "ldr x23, [x24], #0x8\n" + "add x23, x23, x27\n" "movi v4.16b, #0x0\n" "tbz %x[n_channels], #3, 29f\n" - "ldr d4, [x24], #0x8\n" + "ldr d4, [x23], #0x8\n" "tbz %x[n_channels], #2, 27f\n" - "ld1 { v4.s }[2], [x24], #0x4\n" + "ld1 { v4.s }[2], [x23], #0x4\n" "tbz %x[n_channels], #1, 26f\n" - "ld1 { v4.h }[6], [x24], #0x2\n" + "ld1 { v4.h }[6], [x23], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v4.b }[14], [x24], #0x1\n" + "ld1 { v4.b }[14], [x23], #0x1\n" "b 33f\n" "26:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ld1 { v4.b }[12], [x24], #0x1\n" + "ld1 { v4.b }[12], [x23], #0x1\n" "b 33f\n" "27:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Unset "tbz %x[n_channels], #1, 28f\n" - "ld1 { v4.h }[4], [x24], #0x2\n" + "ld1 { v4.h }[4], [x23], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v4.b }[10], [x24], #0x1\n" + "ld1 { v4.b }[10], [x23], #0x1\n" "b 33f\n" "28:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ld1 { v4.b }[8], [x24], #0x1\n" + "ld1 { v4.b }[8], [x23], #0x1\n" "b 33f\n" "29:" // Oddments: Single input loop: Load: Bit 3: Unset "tbz %x[n_channels], #2, 31f\n" - "ldr s4, [x24], #0x4\n" + "ldr s4, [x23], #0x4\n" "tbz %x[n_channels], #1, 30f\n" - "ld1 { v4.h }[2], [x24], #0x2\n" + "ld1 { v4.h }[2], [x23], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v4.b }[6], [x24], #0x1\n" + "ld1 { v4.b }[6], [x23], #0x1\n" "b 33f\n" "30:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ld1 { v4.b }[4], [x24], #0x1\n" + "ld1 { v4.b }[4], [x23], #0x1\n" "b 33f\n" "31:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Unset "tbz %x[n_channels], #1, 32f\n" - "ldr h4, [x24], #0x2\n" + "ldr h4, [x23], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v4.b }[2], [x24], #0x1\n" + "ld1 { v4.b }[2], [x23], #0x1\n" "b 33f\n" "32:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ldr b4, [x24], #0x1\n" + "ldr b4, [x23], #0x1\n" "33:" // Oddments: Single input loop: Load: Bit 3: End "subs x21, x21, #0x1\n" "umax v8.16b, v8.16b, v4.16b\n" @@ -428,10 +428,11 @@ void a64_u8_nhwc_max_generic_depthfirst_impl( "43:" // End : [n_channels] "+&r" (n_channels), [outptr] "+&r" (outptr) : [inptrs] "r" (inptrs), [n_valid_cells] "r" (n_valid_cells) - : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x9", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" + : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); } } // namespace pooling } // namespace arm_conv + #endif // defined(__aarch64__) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8q_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8q_nhwc_avg_generic_depthfirst/generic.cpp index 19227d8aaa..31a3489e5c 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8q_nhwc_avg_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8q_nhwc_avg_generic_depthfirst/generic.cpp @@ -22,8 +22,6 @@ * SOFTWARE. */ -#if defined(__aarch64__) - #include "pooling.hpp" #include <cstdint> #include <cstddef> @@ -31,6 +29,8 @@ #include <cmath> +#if defined(__aarch64__) + namespace arm_conv { namespace pooling { @@ -132,7 +132,7 @@ void a64_u8q_nhwc_avg_generic_depthfirst_impl( "mov v13.16b, v15.16b\n" "mov v12.16b, v15.16b\n" "mov v11.16b, v15.16b\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "mov v10.16b, v15.16b\n" "mov v9.16b, v15.16b\n" "mov v8.16b, v15.16b\n" @@ -145,42 +145,42 @@ void a64_u8q_nhwc_avg_generic_depthfirst_impl( "mov v1.16b, v15.16b\n" "mov v0.16b, v15.16b\n" "cbz x23, 4f\n" - "ldp x22, x21, [x20, #0x0]\n" - "ldr q31, [x22, x27]\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q31, [x21, x27]\n" "subs x23, x23, #0x1\n" - "add x20, x20, #0x10\n" - "ldr q30, [x21, x27]\n" - "ldr q29, [x22, x26]\n" - "ldr q28, [x21, x26]\n" - "ldr q27, [x22, x25]\n" - "ldr q26, [x21, x25]\n" - "ldr q25, [x22, x24]\n" - "ldr q24, [x21, x24]\n" + "add x22, x22, #0x10\n" + "ldr q30, [x20, x27]\n" + "ldr q29, [x21, x26]\n" + "ldr q28, [x20, x26]\n" + "ldr q27, [x21, x25]\n" + "ldr q26, [x20, x25]\n" + "ldr q25, [x21, x24]\n" + "ldr q24, [x20, x24]\n" "beq 3f\n" "2:" // 4-vectors of channels: 2 inputs loop "uaddl v23.8h, v31.8b, v30.8b\n" "uaddl2 v22.8h, v31.16b, v30.16b\n" - "ldp x22, x21, [x20, #0x0]\n" - "ldr q31, [x22, x27]\n" - "ldr q30, [x21, x27]\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q31, [x21, x27]\n" + "ldr q30, [x20, x27]\n" "uaddl v21.8h, v29.8b, v28.8b\n" "uaddl2 v20.8h, v29.16b, v28.16b\n" - "ldr q29, [x22, x26]\n" - "ldr q28, [x21, x26]\n" + "ldr q29, [x21, x26]\n" + "ldr q28, [x20, x26]\n" "uaddl v19.8h, v27.8b, v26.8b\n" "uaddl2 v18.8h, v27.16b, v26.16b\n" - "ldr q27, [x22, x25]\n" - "ldr q26, [x21, x25]\n" + "ldr q27, [x21, x25]\n" + "ldr q26, [x20, x25]\n" + "uaddl v17.8h, v25.8b, v24.8b\n" + "uaddl2 v16.8h, v25.16b, v24.16b\n" + "ldr q25, [x21, x24]\n" + "ldr q24, [x20, x24]\n" "subs x23, x23, #0x1\n" "uaddw v15.4s, v15.4s, v23.4h\n" "uaddw2 v14.4s, v14.4s, v23.8h\n" - "uaddl v17.8h, v25.8b, v24.8b\n" - "uaddl2 v16.8h, v25.16b, v24.16b\n" - "ldr q25, [x22, x24]\n" - "add x20, x20, #0x10\n" "uaddw v13.4s, v13.4s, v22.4h\n" "uaddw2 v12.4s, v12.4s, v22.8h\n" - "ldr q24, [x21, x24]\n" + "add x22, x22, #0x10\n" "uaddw v11.4s, v11.4s, v21.4h\n" "uaddw2 v10.4s, v10.4s, v21.8h\n" "uaddw v9.4s, v9.4s, v20.4h\n" @@ -220,23 +220,23 @@ void a64_u8q_nhwc_avg_generic_depthfirst_impl( "uaddw v1.4s, v1.4s, v16.4h\n" "uaddw2 v0.4s, v0.4s, v16.8h\n" "4:" // 4-vectors of channels: After loop - "ands x21, %x[n_valid_cells], #0x1\n" + "ands x23, %x[n_valid_cells], #0x1\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x22, [x20], #0x8\n" - "ldr q31, [x22, x27]\n" - "uxtl v23.8h, v31.8b\n" - "uxtl2 v22.8h, v31.16b\n" - "ldr q29, [x22, x26]\n" - "ldr q27, [x22, x25]\n" - "uxtl v21.8h, v29.8b\n" - "uxtl2 v20.8h, v29.16b\n" - "ldr q25, [x22, x24]\n" - "uxtl v19.8h, v27.8b\n" - "uxtl2 v18.8h, v27.16b\n" - "subs x21, x21, #0x1\n" - "uxtl v17.8h, v25.8b\n" - "uxtl2 v16.8h, v25.16b\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" + "uxtl v23.8h, v16.8b\n" + "uxtl2 v22.8h, v16.16b\n" + "ldr q16, [x20, x26]\n" + "ldr q17, [x20, x25]\n" + "uxtl v21.8h, v16.8b\n" + "uxtl2 v20.8h, v16.16b\n" + "ldr q16, [x20, x24]\n" + "uxtl v19.8h, v17.8b\n" + "uxtl2 v18.8h, v17.16b\n" + "subs x23, x23, #0x1\n" + "uxtl v17.8h, v16.8b\n" + "uxtl2 v16.8h, v16.16b\n" "uaddw v15.4s, v15.4s, v23.4h\n" "uaddw2 v14.4s, v14.4s, v23.8h\n" "uaddw v13.4s, v13.4s, v22.4h\n" @@ -391,56 +391,56 @@ void a64_u8q_nhwc_avg_generic_depthfirst_impl( "mov v14.16b, v15.16b\n" "mov v13.16b, v15.16b\n" "mov v12.16b, v15.16b\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "cbz x23, 11f\n" - "ldp x22, x21, [x20, #0x0]\n" - "ldr q31, [x22, x27]\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q31, [x21, x27]\n" "subs x23, x23, #0x1\n" - "add x20, x20, #0x10\n" - "ldr q30, [x21, x27]\n" + "add x22, x22, #0x10\n" + "ldr q30, [x20, x27]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 2 inputs loop - "uaddl v23.8h, v31.8b, v30.8b\n" - "uaddl2 v22.8h, v31.16b, v30.16b\n" - "ldp x22, x21, [x20, #0x0]\n" - "ldr q31, [x22, x27]\n" - "ldr q30, [x21, x27]\n" + "uaddl v17.8h, v31.8b, v30.8b\n" + "uaddl2 v16.8h, v31.16b, v30.16b\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q31, [x21, x27]\n" + "ldr q30, [x20, x27]\n" "subs x23, x23, #0x1\n" - "uaddw v15.4s, v15.4s, v23.4h\n" - "uaddw2 v14.4s, v14.4s, v23.8h\n" - "uaddw v13.4s, v13.4s, v22.4h\n" - "uaddw2 v12.4s, v12.4s, v22.8h\n" - "add x20, x20, #0x10\n" + "uaddw v15.4s, v15.4s, v17.4h\n" + "uaddw2 v14.4s, v14.4s, v17.8h\n" + "uaddw v13.4s, v13.4s, v16.4h\n" + "uaddw2 v12.4s, v12.4s, v16.8h\n" + "add x22, x22, #0x10\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 2 inputs tail - "uaddl v23.8h, v31.8b, v30.8b\n" - "uaddl2 v22.8h, v31.16b, v30.16b\n" - "uaddw v15.4s, v15.4s, v23.4h\n" - "uaddw2 v14.4s, v14.4s, v23.8h\n" - "uaddw v13.4s, v13.4s, v22.4h\n" - "uaddw2 v12.4s, v12.4s, v22.8h\n" + "uaddl v17.8h, v31.8b, v30.8b\n" + "uaddl2 v16.8h, v31.16b, v30.16b\n" + "uaddw v15.4s, v15.4s, v17.4h\n" + "uaddw2 v14.4s, v14.4s, v17.8h\n" + "uaddw v13.4s, v13.4s, v16.4h\n" + "uaddw2 v12.4s, v12.4s, v16.8h\n" "11:" // Single vector of channels: Loop: After loop - "ands x21, %x[n_valid_cells], #0x1\n" + "ands x23, %x[n_valid_cells], #0x1\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x22, [x20], #0x8\n" - "ldr q31, [x22, x27]\n" - "uxtl v23.8h, v31.8b\n" - "uxtl2 v22.8h, v31.16b\n" - "subs x21, x21, #0x1\n" - "uaddw v15.4s, v15.4s, v23.4h\n" - "uaddw2 v14.4s, v14.4s, v23.8h\n" - "uaddw v13.4s, v13.4s, v22.4h\n" - "uaddw2 v12.4s, v12.4s, v22.8h\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" + "uxtl v17.8h, v16.8b\n" + "uxtl2 v16.8h, v16.16b\n" + "subs x23, x23, #0x1\n" + "uaddw v15.4s, v15.4s, v17.4h\n" + "uaddw2 v14.4s, v14.4s, v17.8h\n" + "uaddw v13.4s, v13.4s, v16.4h\n" + "uaddw2 v12.4s, v12.4s, v16.8h\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End - "ld1r { v19.4s }, [%x[left_shift]]\n" + "ld1r { v16.4s }, [%x[left_shift]]\n" "ld1r { v18.4s }, [%x[combined_rescale_value]]\n" - "srshl v15.4s, v15.4s, v19.4s\n" - "srshl v14.4s, v14.4s, v19.4s\n" + "srshl v15.4s, v15.4s, v16.4s\n" + "srshl v14.4s, v14.4s, v16.4s\n" "ld1r { v17.4s }, [%x[right_shift]]\n" - "srshl v13.4s, v13.4s, v19.4s\n" - "srshl v12.4s, v12.4s, v19.4s\n" + "srshl v13.4s, v13.4s, v16.4s\n" + "srshl v12.4s, v12.4s, v16.4s\n" "add x20, %x[quant_params], %[offsetof_qp_output_offset]\n" "ld1r { v16.4s }, [x20]\n" "sqrdmulh v15.4s, v15.4s, v18.4s\n" @@ -467,9 +467,9 @@ void a64_u8q_nhwc_avg_generic_depthfirst_impl( "smin v14.4s, v14.4s, v16.4s\n" "smin v13.4s, v13.4s, v16.4s\n" "smin v12.4s, v12.4s, v16.4s\n" - "uzp1 v23.16b, v15.16b, v14.16b\n" + "uzp1 v17.16b, v15.16b, v14.16b\n" "uzp1 v16.16b, v13.16b, v12.16b\n" - "uzp1 v16.16b, v23.16b, v16.16b\n" + "uzp1 v16.16b, v17.16b, v16.16b\n" "str q16, [%x[outptr], x27]\n" "add x27, x27, #0x10\n" "bge 8b\n" @@ -481,151 +481,151 @@ void a64_u8q_nhwc_avg_generic_depthfirst_impl( "mov v14.16b, v15.16b\n" "mov v13.16b, v15.16b\n" "mov v12.16b, v15.16b\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "cbz x23, 24f\n" "15:" // Oddments: 2 inputs loop - "ldp x22, x21, [x20, #0x0]\n" - "add x20, x20, #0x10\n" - "add x22, x22, x27\n" - "movi v31.16b, #0x0\n" + "ldp x21, x20, [x22, #0x0]\n" + "add x22, x22, #0x10\n" "add x21, x21, x27\n" + "movi v31.16b, #0x0\n" + "add x20, x20, x27\n" "movi v30.16b, #0x0\n" "tbz %x[n_channels], #3, 19f\n" - "ldr d31, [x22], #0x8\n" - "ldr d30, [x21], #0x8\n" + "ldr d31, [x21], #0x8\n" + "ldr d30, [x20], #0x8\n" "tbz %x[n_channels], #2, 17f\n" - "ld1 { v31.s }[2], [x22], #0x4\n" - "ld1 { v30.s }[2], [x21], #0x4\n" + "ld1 { v31.s }[2], [x21], #0x4\n" + "ld1 { v30.s }[2], [x20], #0x4\n" "tbz %x[n_channels], #1, 16f\n" - "ld1 { v31.h }[6], [x22], #0x2\n" - "ld1 { v30.h }[6], [x21], #0x2\n" + "ld1 { v31.h }[6], [x21], #0x2\n" + "ld1 { v30.h }[6], [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v31.b }[14], [x22], #0x1\n" - "ld1 { v30.b }[14], [x21], #0x1\n" + "ld1 { v31.b }[14], [x21], #0x1\n" + "ld1 { v30.b }[14], [x20], #0x1\n" "b 23f\n" "16:" // Oddments: 2 inputs loop: Load: Bit 3: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ld1 { v31.b }[12], [x22], #0x1\n" - "ld1 { v30.b }[12], [x21], #0x1\n" + "ld1 { v31.b }[12], [x21], #0x1\n" + "ld1 { v30.b }[12], [x20], #0x1\n" "b 23f\n" "17:" // Oddments: 2 inputs loop: Load: Bit 3: Bit 2: Unset "tbz %x[n_channels], #1, 18f\n" - "ld1 { v31.h }[4], [x22], #0x2\n" - "ld1 { v30.h }[4], [x21], #0x2\n" + "ld1 { v31.h }[4], [x21], #0x2\n" + "ld1 { v30.h }[4], [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v31.b }[10], [x22], #0x1\n" - "ld1 { v30.b }[10], [x21], #0x1\n" + "ld1 { v31.b }[10], [x21], #0x1\n" + "ld1 { v30.b }[10], [x20], #0x1\n" "b 23f\n" "18:" // Oddments: 2 inputs loop: Load: Bit 3: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ld1 { v31.b }[8], [x22], #0x1\n" - "ld1 { v30.b }[8], [x21], #0x1\n" + "ld1 { v31.b }[8], [x21], #0x1\n" + "ld1 { v30.b }[8], [x20], #0x1\n" "b 23f\n" "19:" // Oddments: 2 inputs loop: Load: Bit 3: Unset "tbz %x[n_channels], #2, 21f\n" - "ldr s31, [x22], #0x4\n" - "ldr s30, [x21], #0x4\n" + "ldr s31, [x21], #0x4\n" + "ldr s30, [x20], #0x4\n" "tbz %x[n_channels], #1, 20f\n" - "ld1 { v31.h }[2], [x22], #0x2\n" - "ld1 { v30.h }[2], [x21], #0x2\n" + "ld1 { v31.h }[2], [x21], #0x2\n" + "ld1 { v30.h }[2], [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v31.b }[6], [x22], #0x1\n" - "ld1 { v30.b }[6], [x21], #0x1\n" + "ld1 { v31.b }[6], [x21], #0x1\n" + "ld1 { v30.b }[6], [x20], #0x1\n" "b 23f\n" "20:" // Oddments: 2 inputs loop: Load: Bit 3: Unset: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ld1 { v31.b }[4], [x22], #0x1\n" - "ld1 { v30.b }[4], [x21], #0x1\n" + "ld1 { v31.b }[4], [x21], #0x1\n" + "ld1 { v30.b }[4], [x20], #0x1\n" "b 23f\n" "21:" // Oddments: 2 inputs loop: Load: Bit 3: Unset: Bit 2: Unset "tbz %x[n_channels], #1, 22f\n" - "ldr h31, [x22], #0x2\n" - "ldr h30, [x21], #0x2\n" + "ldr h31, [x21], #0x2\n" + "ldr h30, [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v31.b }[2], [x22], #0x1\n" - "ld1 { v30.b }[2], [x21], #0x1\n" + "ld1 { v31.b }[2], [x21], #0x1\n" + "ld1 { v30.b }[2], [x20], #0x1\n" "b 23f\n" "22:" // Oddments: 2 inputs loop: Load: Bit 3: Unset: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ldr b31, [x22], #0x1\n" - "ldr b30, [x21], #0x1\n" + "ldr b31, [x21], #0x1\n" + "ldr b30, [x20], #0x1\n" "23:" // Oddments: 2 inputs loop: Load: Bit 3: End - "uaddl v23.8h, v31.8b, v30.8b\n" - "uaddl2 v22.8h, v31.16b, v30.16b\n" + "uaddl v17.8h, v31.8b, v30.8b\n" + "uaddl2 v16.8h, v31.16b, v30.16b\n" "subs x23, x23, #0x1\n" - "uaddw v15.4s, v15.4s, v23.4h\n" - "uaddw2 v14.4s, v14.4s, v23.8h\n" - "uaddw v13.4s, v13.4s, v22.4h\n" - "uaddw2 v12.4s, v12.4s, v22.8h\n" + "uaddw v15.4s, v15.4s, v17.4h\n" + "uaddw2 v14.4s, v14.4s, v17.8h\n" + "uaddw v13.4s, v13.4s, v16.4h\n" + "uaddw2 v12.4s, v12.4s, v16.8h\n" "bgt 15b\n" "24:" // Oddments: After loop - "ands x21, %x[n_valid_cells], #0x1\n" + "ands x23, %x[n_valid_cells], #0x1\n" "beq 34f\n" "25:" // Oddments: Single input loop - "ldr x22, [x20], #0x8\n" - "add x22, x22, x27\n" + "ldr x21, [x22], #0x8\n" + "add x21, x21, x27\n" "movi v31.16b, #0x0\n" "tbz %x[n_channels], #3, 29f\n" - "ldr d31, [x22], #0x8\n" + "ldr d31, [x21], #0x8\n" "tbz %x[n_channels], #2, 27f\n" - "ld1 { v31.s }[2], [x22], #0x4\n" + "ld1 { v31.s }[2], [x21], #0x4\n" "tbz %x[n_channels], #1, 26f\n" - "ld1 { v31.h }[6], [x22], #0x2\n" + "ld1 { v31.h }[6], [x21], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v31.b }[14], [x22], #0x1\n" + "ld1 { v31.b }[14], [x21], #0x1\n" "b 33f\n" "26:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ld1 { v31.b }[12], [x22], #0x1\n" + "ld1 { v31.b }[12], [x21], #0x1\n" "b 33f\n" "27:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Unset "tbz %x[n_channels], #1, 28f\n" - "ld1 { v31.h }[4], [x22], #0x2\n" + "ld1 { v31.h }[4], [x21], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v31.b }[10], [x22], #0x1\n" + "ld1 { v31.b }[10], [x21], #0x1\n" "b 33f\n" "28:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ld1 { v31.b }[8], [x22], #0x1\n" + "ld1 { v31.b }[8], [x21], #0x1\n" "b 33f\n" "29:" // Oddments: Single input loop: Load: Bit 3: Unset "tbz %x[n_channels], #2, 31f\n" - "ldr s31, [x22], #0x4\n" + "ldr s31, [x21], #0x4\n" "tbz %x[n_channels], #1, 30f\n" - "ld1 { v31.h }[2], [x22], #0x2\n" + "ld1 { v31.h }[2], [x21], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v31.b }[6], [x22], #0x1\n" + "ld1 { v31.b }[6], [x21], #0x1\n" "b 33f\n" "30:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ld1 { v31.b }[4], [x22], #0x1\n" + "ld1 { v31.b }[4], [x21], #0x1\n" "b 33f\n" "31:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Unset "tbz %x[n_channels], #1, 32f\n" - "ldr h31, [x22], #0x2\n" + "ldr h31, [x21], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v31.b }[2], [x22], #0x1\n" + "ld1 { v31.b }[2], [x21], #0x1\n" "b 33f\n" "32:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ldr b31, [x22], #0x1\n" + "ldr b31, [x21], #0x1\n" "33:" // Oddments: Single input loop: Load: Bit 3: End - "uxtl v23.8h, v31.8b\n" - "uxtl2 v22.8h, v31.16b\n" - "subs x21, x21, #0x1\n" - "uaddw v15.4s, v15.4s, v23.4h\n" - "uaddw2 v14.4s, v14.4s, v23.8h\n" - "uaddw v13.4s, v13.4s, v22.4h\n" - "uaddw2 v12.4s, v12.4s, v22.8h\n" + "uxtl v17.8h, v31.8b\n" + "uxtl2 v16.8h, v31.16b\n" + "subs x23, x23, #0x1\n" + "uaddw v15.4s, v15.4s, v17.4h\n" + "uaddw2 v14.4s, v14.4s, v17.8h\n" + "uaddw v13.4s, v13.4s, v16.4h\n" + "uaddw2 v12.4s, v12.4s, v16.8h\n" "bgt 25b\n" "34:" // Oddments: Single input loop: End - "ld1r { v19.4s }, [%x[left_shift]]\n" + "ld1r { v16.4s }, [%x[left_shift]]\n" "ld1r { v18.4s }, [%x[combined_rescale_value]]\n" - "srshl v15.4s, v15.4s, v19.4s\n" - "srshl v14.4s, v14.4s, v19.4s\n" + "srshl v15.4s, v15.4s, v16.4s\n" + "srshl v14.4s, v14.4s, v16.4s\n" "ld1r { v17.4s }, [%x[right_shift]]\n" - "srshl v13.4s, v13.4s, v19.4s\n" - "srshl v12.4s, v12.4s, v19.4s\n" + "srshl v13.4s, v13.4s, v16.4s\n" + "srshl v12.4s, v12.4s, v16.4s\n" "add x20, %x[quant_params], %[offsetof_qp_output_offset]\n" "ld1r { v16.4s }, [x20]\n" "sqrdmulh v15.4s, v15.4s, v18.4s\n" @@ -650,9 +650,9 @@ void a64_u8q_nhwc_avg_generic_depthfirst_impl( "smin v14.4s, v14.4s, v16.4s\n" "smin v13.4s, v13.4s, v16.4s\n" "smin v12.4s, v12.4s, v16.4s\n" - "uzp1 v23.16b, v15.16b, v14.16b\n" + "uzp1 v17.16b, v15.16b, v14.16b\n" "uzp1 v16.16b, v13.16b, v12.16b\n" - "uzp1 v16.16b, v23.16b, v16.16b\n" + "uzp1 v16.16b, v17.16b, v16.16b\n" "tbz %x[n_channels], #3, 38f\n" "st1 { v16.d }[0], [%x[outptr]], #0x8\n" "tbz %x[n_channels], #2, 36f\n" @@ -707,4 +707,5 @@ void a64_u8q_nhwc_avg_generic_depthfirst_impl( } // namespace pooling } // namespace arm_conv + #endif // defined(__aarch64__) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8q_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8q_nhwc_max_generic_depthfirst/generic.cpp index 7eea14f70f..f4927c5536 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8q_nhwc_max_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8q_nhwc_max_generic_depthfirst/generic.cpp @@ -22,12 +22,12 @@ * SOFTWARE. */ -#if defined(__aarch64__) - #include "pooling.hpp" #include <cstdint> #include <cstddef> +#if defined(__aarch64__) + namespace arm_conv { namespace pooling { @@ -43,77 +43,77 @@ void a64_u8q_nhwc_max_generic_depthfirst_impl( { __asm__ __volatile__( "cmp %x[n_channels], #0x40\n" - "mov x9, #0x0\n" - "mov x28, #0x10\n" // cntb _, ALL, #1 - "mov x27, #0x20\n" // cntb _, ALL, #2 - "mov x26, #0x30\n" // cntb _, ALL, #3 + "mov x27, #0x0\n" + "mov x26, #0x10\n" // cntb _, ALL, #1 + "mov x24, #0x20\n" // cntb _, ALL, #2 + "mov x23, #0x30\n" // cntb _, ALL, #3 "blt 7f\n" "1:" // 4-vectors of channels "lsr x25, %x[n_valid_cells], #0x2\n" "movi v8.16b, #0x0\n" "movi v7.16b, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "movi v6.16b, #0x0\n" "movi v5.16b, #0x0\n" "cbz x25, 4f\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldr q4, [x24, x9]\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" "subs x25, x25, #0x1\n" - "ldr q3, [x23, x9]\n" - "ldr q2, [x24, x28]\n" - "ldr q1, [x23, x28]\n" - "ldr q0, [x24, x27]\n" - "ldr q31, [x23, x27]\n" - "ldr q30, [x24, x26]\n" - "ldr q29, [x23, x26]\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" - "ldr q28, [x22, x9]\n" - "ldr q22, [x21, x9]\n" - "ldr q27, [x22, x28]\n" - "ldr q21, [x21, x28]\n" - "ldr q26, [x22, x27]\n" - "ldr q20, [x21, x27]\n" - "ldr q25, [x22, x26]\n" - "ldr q24, [x21, x26]\n" + "ldr q3, [x20, x27]\n" + "ldr q2, [x21, x26]\n" + "ldr q1, [x20, x26]\n" + "ldr q0, [x21, x24]\n" + "ldr q31, [x20, x24]\n" + "ldr q30, [x21, x23]\n" + "ldr q29, [x20, x23]\n" + "ldp x21, x20, [x22, #0x10]\n" + "add x22, x22, #0x20\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" + "ldr q27, [x21, x26]\n" + "ldr q21, [x20, x26]\n" + "ldr q26, [x21, x24]\n" + "ldr q20, [x20, x24]\n" + "ldr q25, [x21, x23]\n" + "ldr q24, [x20, x23]\n" "beq 3f\n" "2:" // 4-vectors of channels: 4 inputs loop "umax v23.16b, v4.16b, v3.16b\n" "umax v19.16b, v28.16b, v22.16b\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldr q4, [x24, x9]\n" - "ldr q3, [x23, x9]\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "ldr q3, [x20, x27]\n" "umax v22.16b, v2.16b, v1.16b\n" - "ldr q2, [x24, x28]\n" + "ldr q2, [x21, x26]\n" "umax v18.16b, v27.16b, v21.16b\n" - "ldr q1, [x23, x28]\n" + "ldr q1, [x20, x26]\n" "umax v21.16b, v0.16b, v31.16b\n" - "ldr q0, [x24, x27]\n" + "ldr q0, [x21, x24]\n" "umax v17.16b, v26.16b, v20.16b\n" - "ldr q31, [x23, x27]\n" + "ldr q31, [x20, x24]\n" "umax v20.16b, v30.16b, v29.16b\n" - "ldr q30, [x24, x26]\n" + "ldr q30, [x21, x23]\n" "umax v16.16b, v25.16b, v24.16b\n" - "ldr q29, [x23, x26]\n" + "ldr q29, [x20, x23]\n" "umax v19.16b, v23.16b, v19.16b\n" "umax v18.16b, v22.16b, v18.16b\n" - "ldp x22, x21, [x20, #0x10]\n" - "ldr q28, [x22, x9]\n" - "ldr q22, [x21, x9]\n" + "ldp x21, x20, [x22, #0x10]\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" "umax v17.16b, v21.16b, v17.16b\n" "umax v16.16b, v20.16b, v16.16b\n" - "ldr q27, [x22, x28]\n" - "ldr q21, [x21, x28]\n" + "ldr q27, [x21, x26]\n" + "ldr q21, [x20, x26]\n" "subs x25, x25, #0x1\n" "umax v8.16b, v8.16b, v19.16b\n" - "ldr q26, [x22, x27]\n" - "ldr q20, [x21, x27]\n" + "ldr q26, [x21, x24]\n" + "ldr q20, [x20, x24]\n" "umax v7.16b, v7.16b, v18.16b\n" "umax v6.16b, v6.16b, v17.16b\n" - "ldr q25, [x22, x26]\n" - "ldr q24, [x21, x26]\n" + "ldr q25, [x21, x23]\n" + "ldr q24, [x20, x23]\n" "umax v5.16b, v5.16b, v16.16b\n" - "add x20, x20, #0x20\n" + "add x22, x22, #0x20\n" "bgt 2b\n" "3:" // 4-vectors of channels: 4 inputs tail "umax v23.16b, v4.16b, v3.16b\n" @@ -136,16 +136,16 @@ void a64_u8q_nhwc_max_generic_depthfirst_impl( "ands x21, %x[n_valid_cells], #0x3\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x24, [x20], #0x8\n" - "ldr q4, [x24, x9]\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" "subs x21, x21, #0x1\n" - "umax v8.16b, v8.16b, v4.16b\n" - "ldr q2, [x24, x28]\n" - "ldr q0, [x24, x27]\n" - "umax v7.16b, v7.16b, v2.16b\n" - "umax v6.16b, v6.16b, v0.16b\n" - "ldr q30, [x24, x26]\n" - "umax v5.16b, v5.16b, v30.16b\n" + "umax v8.16b, v8.16b, v16.16b\n" + "ldr q17, [x20, x26]\n" + "ldr q16, [x20, x24]\n" + "umax v7.16b, v7.16b, v17.16b\n" + "umax v6.16b, v6.16b, v16.16b\n" + "ldr q16, [x20, x23]\n" + "umax v5.16b, v5.16b, v16.16b\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End "add x20, %x[quant_params], %[offsetof_qp_input_offset]\n" @@ -292,17 +292,17 @@ void a64_u8q_nhwc_max_generic_depthfirst_impl( "uzp1 v19.16b, v25.16b, v19.16b\n" "uzp1 v18.16b, v24.16b, v18.16b\n" "uzp1 v16.16b, v23.16b, v16.16b\n" - "str q16, [%x[outptr], x9]\n" - "add x9, x9, #0x40\n" + "str q16, [%x[outptr], x27]\n" + "add x27, x27, #0x40\n" "uzp1 v16.16b, v22.16b, v21.16b\n" "uzp1 v17.16b, v20.16b, v17.16b\n" - "str q16, [%x[outptr], x28]\n" - "add x28, x28, #0x40\n" - "uzp1 v16.16b, v19.16b, v18.16b\n" - "str q17, [%x[outptr], x27]\n" - "add x27, x27, #0x40\n" "str q16, [%x[outptr], x26]\n" "add x26, x26, #0x40\n" + "uzp1 v16.16b, v19.16b, v18.16b\n" + "str q17, [%x[outptr], x24]\n" + "add x24, x24, #0x40\n" + "str q16, [%x[outptr], x23]\n" + "add x23, x23, #0x40\n" "bge 1b\n" "cbz %x[n_channels], 43f\n" "7:" // Single vector of channels @@ -311,314 +311,314 @@ void a64_u8q_nhwc_max_generic_depthfirst_impl( "8:" // Single vector of channels: Loop "lsr x25, %x[n_valid_cells], #0x2\n" "movi v8.16b, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "cbz x25, 11f\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldr q4, [x24, x9]\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" "subs x25, x25, #0x1\n" - "ldr q3, [x23, x9]\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" - "ldr q28, [x22, x9]\n" - "ldr q22, [x21, x9]\n" + "ldr q3, [x20, x27]\n" + "ldp x21, x20, [x22, #0x10]\n" + "add x22, x22, #0x20\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 4 inputs loop - "umax v23.16b, v4.16b, v3.16b\n" - "umax v19.16b, v28.16b, v22.16b\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldr q4, [x24, x9]\n" - "ldr q3, [x23, x9]\n" - "umax v19.16b, v23.16b, v19.16b\n" - "ldp x22, x21, [x20, #0x10]\n" + "umax v17.16b, v4.16b, v3.16b\n" + "umax v16.16b, v28.16b, v22.16b\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "ldr q3, [x20, x27]\n" + "umax v16.16b, v17.16b, v16.16b\n" + "ldp x21, x20, [x22, #0x10]\n" "subs x25, x25, #0x1\n" - "ldr q28, [x22, x9]\n" - "ldr q22, [x21, x9]\n" - "umax v8.16b, v8.16b, v19.16b\n" - "add x20, x20, #0x20\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" + "umax v8.16b, v8.16b, v16.16b\n" + "add x22, x22, #0x20\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 4 inputs tail - "umax v23.16b, v4.16b, v3.16b\n" - "umax v19.16b, v28.16b, v22.16b\n" - "umax v19.16b, v23.16b, v19.16b\n" - "umax v8.16b, v8.16b, v19.16b\n" + "umax v17.16b, v4.16b, v3.16b\n" + "umax v16.16b, v28.16b, v22.16b\n" + "umax v16.16b, v17.16b, v16.16b\n" + "umax v8.16b, v8.16b, v16.16b\n" "11:" // Single vector of channels: Loop: After loop "ands x21, %x[n_valid_cells], #0x3\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x24, [x20], #0x8\n" - "ldr q4, [x24, x9]\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" "subs x21, x21, #0x1\n" - "umax v8.16b, v8.16b, v4.16b\n" + "umax v8.16b, v8.16b, v16.16b\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End "add x20, %x[quant_params], %[offsetof_qp_input_offset]\n" - "ld1r { v4.4s }, [x20]\n" - "uxtl v23.8h, v8.8b\n" - "uxtl2 v24.8h, v8.16b\n" - "neg v4.4s, v4.4s\n" + "ld1r { v18.4s }, [x20]\n" + "uxtl v17.8h, v8.8b\n" + "uxtl2 v16.8h, v8.16b\n" + "neg v18.4s, v18.4s\n" "add x20, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n" - "ld1r { v3.4s }, [x20]\n" - "saddw v0.4s, v4.4s, v23.4h\n" - "saddw2 v23.4s, v4.4s, v23.8h\n" - "saddw v31.4s, v4.4s, v24.4h\n" + "ld1r { v23.4s }, [x20]\n" + "saddw v22.4s, v18.4s, v17.4h\n" + "saddw2 v21.4s, v18.4s, v17.8h\n" + "saddw v20.4s, v18.4s, v16.4h\n" "add x20, %x[quant_params], %[offsetof_qp_per_layer_mul]\n" - "ld1r { v2.4s }, [x20]\n" - "saddw2 v30.4s, v4.4s, v24.8h\n" - "srshl v0.4s, v0.4s, v3.4s\n" + "ld1r { v19.4s }, [x20]\n" + "saddw2 v18.4s, v18.4s, v16.8h\n" + "srshl v22.4s, v22.4s, v23.4s\n" "add x20, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n" - "ld1r { v1.4s }, [x20]\n" - "srshl v23.4s, v23.4s, v3.4s\n" - "srshl v31.4s, v31.4s, v3.4s\n" + "ld1r { v17.4s }, [x20]\n" + "srshl v21.4s, v21.4s, v23.4s\n" + "srshl v20.4s, v20.4s, v23.4s\n" "add x20, %x[quant_params], %[offsetof_qp_output_offset]\n" "ld1r { v16.4s }, [x20]\n" - "srshl v30.4s, v30.4s, v3.4s\n" - "sqrdmulh v0.4s, v0.4s, v2.4s\n" + "srshl v18.4s, v18.4s, v23.4s\n" + "sqrdmulh v22.4s, v22.4s, v19.4s\n" "sub %x[n_channels], %x[n_channels], #0x10\n" "cmp %x[n_channels], #0x10\n" - "sqrdmulh v23.4s, v23.4s, v2.4s\n" - "sqrdmulh v31.4s, v31.4s, v2.4s\n" - "sqrdmulh v30.4s, v30.4s, v2.4s\n" - "srshl v0.4s, v0.4s, v1.4s\n" - "srshl v23.4s, v23.4s, v1.4s\n" - "srshl v31.4s, v31.4s, v1.4s\n" - "srshl v30.4s, v30.4s, v1.4s\n" - "add v0.4s, v0.4s, v16.4s\n" - "add v23.4s, v23.4s, v16.4s\n" - "add v31.4s, v31.4s, v16.4s\n" - "add v30.4s, v30.4s, v16.4s\n" + "sqrdmulh v21.4s, v21.4s, v19.4s\n" + "sqrdmulh v20.4s, v20.4s, v19.4s\n" + "sqrdmulh v18.4s, v18.4s, v19.4s\n" + "srshl v22.4s, v22.4s, v17.4s\n" + "srshl v21.4s, v21.4s, v17.4s\n" + "srshl v20.4s, v20.4s, v17.4s\n" + "srshl v18.4s, v18.4s, v17.4s\n" + "add v22.4s, v22.4s, v16.4s\n" + "add v21.4s, v21.4s, v16.4s\n" + "add v20.4s, v20.4s, v16.4s\n" + "add v18.4s, v18.4s, v16.4s\n" "movi v16.4s, #0x0\n" - "smax v0.4s, v0.4s, v16.4s\n" - "smax v23.4s, v23.4s, v16.4s\n" - "smax v31.4s, v31.4s, v16.4s\n" - "smax v30.4s, v30.4s, v16.4s\n" + "smax v22.4s, v22.4s, v16.4s\n" + "smax v21.4s, v21.4s, v16.4s\n" + "smax v20.4s, v20.4s, v16.4s\n" + "smax v18.4s, v18.4s, v16.4s\n" "movi v16.4s, #0xff\n" - "smin v0.4s, v0.4s, v16.4s\n" - "smin v23.4s, v23.4s, v16.4s\n" - "smin v31.4s, v31.4s, v16.4s\n" - "smin v30.4s, v30.4s, v16.4s\n" - "uzp1 v23.16b, v0.16b, v23.16b\n" - "uzp1 v16.16b, v31.16b, v30.16b\n" - "uzp1 v16.16b, v23.16b, v16.16b\n" - "str q16, [%x[outptr], x9]\n" - "add x9, x9, #0x10\n" + "smin v22.4s, v22.4s, v16.4s\n" + "smin v21.4s, v21.4s, v16.4s\n" + "smin v20.4s, v20.4s, v16.4s\n" + "smin v18.4s, v18.4s, v16.4s\n" + "uzp1 v17.16b, v22.16b, v21.16b\n" + "uzp1 v16.16b, v20.16b, v18.16b\n" + "uzp1 v16.16b, v17.16b, v16.16b\n" + "str q16, [%x[outptr], x27]\n" + "add x27, x27, #0x10\n" "bge 8b\n" "cbz %x[n_channels], 43f\n" "14:" // Oddments "lsr x25, %x[n_valid_cells], #0x2\n" - "add %x[outptr], %x[outptr], x9\n" + "add %x[outptr], %x[outptr], x27\n" "movi v8.16b, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "cbz x25, 24f\n" "15:" // Oddments: 4 inputs loop - "ldp x24, x23, [x20, #0x0]\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" - "add x24, x24, x9\n" - "add x23, x23, x9\n" - "add x22, x22, x9\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "add x23, x23, x27\n" + "add x22, x22, x27\n" + "add x21, x21, x27\n" "movi v4.16b, #0x0\n" "movi v3.16b, #0x0\n" - "add x21, x21, x9\n" + "add x20, x20, x27\n" "movi v28.16b, #0x0\n" "movi v22.16b, #0x0\n" "tbz %x[n_channels], #3, 19f\n" - "ldr d4, [x24], #0x8\n" - "ldr d3, [x23], #0x8\n" - "ldr d28, [x22], #0x8\n" - "ldr d22, [x21], #0x8\n" + "ldr d4, [x23], #0x8\n" + "ldr d3, [x22], #0x8\n" + "ldr d28, [x21], #0x8\n" + "ldr d22, [x20], #0x8\n" "tbz %x[n_channels], #2, 17f\n" - "ld1 { v4.s }[2], [x24], #0x4\n" - "ld1 { v3.s }[2], [x23], #0x4\n" - "ld1 { v28.s }[2], [x22], #0x4\n" - "ld1 { v22.s }[2], [x21], #0x4\n" + "ld1 { v4.s }[2], [x23], #0x4\n" + "ld1 { v3.s }[2], [x22], #0x4\n" + "ld1 { v28.s }[2], [x21], #0x4\n" + "ld1 { v22.s }[2], [x20], #0x4\n" "tbz %x[n_channels], #1, 16f\n" - "ld1 { v4.h }[6], [x24], #0x2\n" - "ld1 { v3.h }[6], [x23], #0x2\n" - "ld1 { v28.h }[6], [x22], #0x2\n" - "ld1 { v22.h }[6], [x21], #0x2\n" + "ld1 { v4.h }[6], [x23], #0x2\n" + "ld1 { v3.h }[6], [x22], #0x2\n" + "ld1 { v28.h }[6], [x21], #0x2\n" + "ld1 { v22.h }[6], [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v4.b }[14], [x24], #0x1\n" - "ld1 { v3.b }[14], [x23], #0x1\n" - "ld1 { v28.b }[14], [x22], #0x1\n" - "ld1 { v22.b }[14], [x21], #0x1\n" + "ld1 { v4.b }[14], [x23], #0x1\n" + "ld1 { v3.b }[14], [x22], #0x1\n" + "ld1 { v28.b }[14], [x21], #0x1\n" + "ld1 { v22.b }[14], [x20], #0x1\n" "b 23f\n" "16:" // Oddments: 4 inputs loop: Load: Bit 3: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ld1 { v4.b }[12], [x24], #0x1\n" - "ld1 { v3.b }[12], [x23], #0x1\n" - "ld1 { v28.b }[12], [x22], #0x1\n" - "ld1 { v22.b }[12], [x21], #0x1\n" + "ld1 { v4.b }[12], [x23], #0x1\n" + "ld1 { v3.b }[12], [x22], #0x1\n" + "ld1 { v28.b }[12], [x21], #0x1\n" + "ld1 { v22.b }[12], [x20], #0x1\n" "b 23f\n" "17:" // Oddments: 4 inputs loop: Load: Bit 3: Bit 2: Unset "tbz %x[n_channels], #1, 18f\n" - "ld1 { v4.h }[4], [x24], #0x2\n" - "ld1 { v3.h }[4], [x23], #0x2\n" - "ld1 { v28.h }[4], [x22], #0x2\n" - "ld1 { v22.h }[4], [x21], #0x2\n" + "ld1 { v4.h }[4], [x23], #0x2\n" + "ld1 { v3.h }[4], [x22], #0x2\n" + "ld1 { v28.h }[4], [x21], #0x2\n" + "ld1 { v22.h }[4], [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v4.b }[10], [x24], #0x1\n" - "ld1 { v3.b }[10], [x23], #0x1\n" - "ld1 { v28.b }[10], [x22], #0x1\n" - "ld1 { v22.b }[10], [x21], #0x1\n" + "ld1 { v4.b }[10], [x23], #0x1\n" + "ld1 { v3.b }[10], [x22], #0x1\n" + "ld1 { v28.b }[10], [x21], #0x1\n" + "ld1 { v22.b }[10], [x20], #0x1\n" "b 23f\n" "18:" // Oddments: 4 inputs loop: Load: Bit 3: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ld1 { v4.b }[8], [x24], #0x1\n" - "ld1 { v3.b }[8], [x23], #0x1\n" - "ld1 { v28.b }[8], [x22], #0x1\n" - "ld1 { v22.b }[8], [x21], #0x1\n" + "ld1 { v4.b }[8], [x23], #0x1\n" + "ld1 { v3.b }[8], [x22], #0x1\n" + "ld1 { v28.b }[8], [x21], #0x1\n" + "ld1 { v22.b }[8], [x20], #0x1\n" "b 23f\n" "19:" // Oddments: 4 inputs loop: Load: Bit 3: Unset "tbz %x[n_channels], #2, 21f\n" - "ldr s4, [x24], #0x4\n" - "ldr s3, [x23], #0x4\n" - "ldr s28, [x22], #0x4\n" - "ldr s22, [x21], #0x4\n" + "ldr s4, [x23], #0x4\n" + "ldr s3, [x22], #0x4\n" + "ldr s28, [x21], #0x4\n" + "ldr s22, [x20], #0x4\n" "tbz %x[n_channels], #1, 20f\n" - "ld1 { v4.h }[2], [x24], #0x2\n" - "ld1 { v3.h }[2], [x23], #0x2\n" - "ld1 { v28.h }[2], [x22], #0x2\n" - "ld1 { v22.h }[2], [x21], #0x2\n" + "ld1 { v4.h }[2], [x23], #0x2\n" + "ld1 { v3.h }[2], [x22], #0x2\n" + "ld1 { v28.h }[2], [x21], #0x2\n" + "ld1 { v22.h }[2], [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v4.b }[6], [x24], #0x1\n" - "ld1 { v3.b }[6], [x23], #0x1\n" - "ld1 { v28.b }[6], [x22], #0x1\n" - "ld1 { v22.b }[6], [x21], #0x1\n" + "ld1 { v4.b }[6], [x23], #0x1\n" + "ld1 { v3.b }[6], [x22], #0x1\n" + "ld1 { v28.b }[6], [x21], #0x1\n" + "ld1 { v22.b }[6], [x20], #0x1\n" "b 23f\n" "20:" // Oddments: 4 inputs loop: Load: Bit 3: Unset: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ld1 { v4.b }[4], [x24], #0x1\n" - "ld1 { v3.b }[4], [x23], #0x1\n" - "ld1 { v28.b }[4], [x22], #0x1\n" - "ld1 { v22.b }[4], [x21], #0x1\n" + "ld1 { v4.b }[4], [x23], #0x1\n" + "ld1 { v3.b }[4], [x22], #0x1\n" + "ld1 { v28.b }[4], [x21], #0x1\n" + "ld1 { v22.b }[4], [x20], #0x1\n" "b 23f\n" "21:" // Oddments: 4 inputs loop: Load: Bit 3: Unset: Bit 2: Unset "tbz %x[n_channels], #1, 22f\n" - "ldr h4, [x24], #0x2\n" - "ldr h3, [x23], #0x2\n" - "ldr h28, [x22], #0x2\n" - "ldr h22, [x21], #0x2\n" + "ldr h4, [x23], #0x2\n" + "ldr h3, [x22], #0x2\n" + "ldr h28, [x21], #0x2\n" + "ldr h22, [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v4.b }[2], [x24], #0x1\n" - "ld1 { v3.b }[2], [x23], #0x1\n" - "ld1 { v28.b }[2], [x22], #0x1\n" - "ld1 { v22.b }[2], [x21], #0x1\n" + "ld1 { v4.b }[2], [x23], #0x1\n" + "ld1 { v3.b }[2], [x22], #0x1\n" + "ld1 { v28.b }[2], [x21], #0x1\n" + "ld1 { v22.b }[2], [x20], #0x1\n" "b 23f\n" "22:" // Oddments: 4 inputs loop: Load: Bit 3: Unset: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ldr b4, [x24], #0x1\n" - "ldr b3, [x23], #0x1\n" - "ldr b28, [x22], #0x1\n" - "ldr b22, [x21], #0x1\n" + "ldr b4, [x23], #0x1\n" + "ldr b3, [x22], #0x1\n" + "ldr b28, [x21], #0x1\n" + "ldr b22, [x20], #0x1\n" "23:" // Oddments: 4 inputs loop: Load: Bit 3: End - "umax v23.16b, v4.16b, v3.16b\n" - "umax v19.16b, v28.16b, v22.16b\n" + "umax v17.16b, v4.16b, v3.16b\n" + "umax v16.16b, v28.16b, v22.16b\n" "subs x25, x25, #0x1\n" - "umax v19.16b, v23.16b, v19.16b\n" - "umax v8.16b, v8.16b, v19.16b\n" + "umax v16.16b, v17.16b, v16.16b\n" + "umax v8.16b, v8.16b, v16.16b\n" "bgt 15b\n" "24:" // Oddments: After loop "ands x21, %x[n_valid_cells], #0x3\n" "beq 34f\n" "25:" // Oddments: Single input loop - "ldr x24, [x20], #0x8\n" - "add x24, x24, x9\n" + "ldr x23, [x24], #0x8\n" + "add x23, x23, x27\n" "movi v4.16b, #0x0\n" "tbz %x[n_channels], #3, 29f\n" - "ldr d4, [x24], #0x8\n" + "ldr d4, [x23], #0x8\n" "tbz %x[n_channels], #2, 27f\n" - "ld1 { v4.s }[2], [x24], #0x4\n" + "ld1 { v4.s }[2], [x23], #0x4\n" "tbz %x[n_channels], #1, 26f\n" - "ld1 { v4.h }[6], [x24], #0x2\n" + "ld1 { v4.h }[6], [x23], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v4.b }[14], [x24], #0x1\n" + "ld1 { v4.b }[14], [x23], #0x1\n" "b 33f\n" "26:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ld1 { v4.b }[12], [x24], #0x1\n" + "ld1 { v4.b }[12], [x23], #0x1\n" "b 33f\n" "27:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Unset "tbz %x[n_channels], #1, 28f\n" - "ld1 { v4.h }[4], [x24], #0x2\n" + "ld1 { v4.h }[4], [x23], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v4.b }[10], [x24], #0x1\n" + "ld1 { v4.b }[10], [x23], #0x1\n" "b 33f\n" "28:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ld1 { v4.b }[8], [x24], #0x1\n" + "ld1 { v4.b }[8], [x23], #0x1\n" "b 33f\n" "29:" // Oddments: Single input loop: Load: Bit 3: Unset "tbz %x[n_channels], #2, 31f\n" - "ldr s4, [x24], #0x4\n" + "ldr s4, [x23], #0x4\n" "tbz %x[n_channels], #1, 30f\n" - "ld1 { v4.h }[2], [x24], #0x2\n" + "ld1 { v4.h }[2], [x23], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v4.b }[6], [x24], #0x1\n" + "ld1 { v4.b }[6], [x23], #0x1\n" "b 33f\n" "30:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ld1 { v4.b }[4], [x24], #0x1\n" + "ld1 { v4.b }[4], [x23], #0x1\n" "b 33f\n" "31:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Unset "tbz %x[n_channels], #1, 32f\n" - "ldr h4, [x24], #0x2\n" + "ldr h4, [x23], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v4.b }[2], [x24], #0x1\n" + "ld1 { v4.b }[2], [x23], #0x1\n" "b 33f\n" "32:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ldr b4, [x24], #0x1\n" + "ldr b4, [x23], #0x1\n" "33:" // Oddments: Single input loop: Load: Bit 3: End "subs x21, x21, #0x1\n" "umax v8.16b, v8.16b, v4.16b\n" "bgt 25b\n" "34:" // Oddments: Single input loop: End "add x20, %x[quant_params], %[offsetof_qp_input_offset]\n" - "ld1r { v4.4s }, [x20]\n" - "uxtl v23.8h, v8.8b\n" - "uxtl2 v24.8h, v8.16b\n" - "neg v4.4s, v4.4s\n" + "ld1r { v18.4s }, [x20]\n" + "uxtl v17.8h, v8.8b\n" + "uxtl2 v16.8h, v8.16b\n" + "neg v18.4s, v18.4s\n" "add x20, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n" - "ld1r { v3.4s }, [x20]\n" - "saddw v0.4s, v4.4s, v23.4h\n" - "saddw2 v23.4s, v4.4s, v23.8h\n" - "saddw v31.4s, v4.4s, v24.4h\n" + "ld1r { v23.4s }, [x20]\n" + "saddw v22.4s, v18.4s, v17.4h\n" + "saddw2 v21.4s, v18.4s, v17.8h\n" + "saddw v20.4s, v18.4s, v16.4h\n" "add x20, %x[quant_params], %[offsetof_qp_per_layer_mul]\n" - "ld1r { v2.4s }, [x20]\n" - "saddw2 v30.4s, v4.4s, v24.8h\n" - "srshl v0.4s, v0.4s, v3.4s\n" + "ld1r { v19.4s }, [x20]\n" + "saddw2 v18.4s, v18.4s, v16.8h\n" + "srshl v22.4s, v22.4s, v23.4s\n" "add x20, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n" - "ld1r { v1.4s }, [x20]\n" - "srshl v23.4s, v23.4s, v3.4s\n" - "srshl v31.4s, v31.4s, v3.4s\n" + "ld1r { v17.4s }, [x20]\n" + "srshl v21.4s, v21.4s, v23.4s\n" + "srshl v20.4s, v20.4s, v23.4s\n" "add x20, %x[quant_params], %[offsetof_qp_output_offset]\n" "ld1r { v16.4s }, [x20]\n" - "srshl v30.4s, v30.4s, v3.4s\n" - "sqrdmulh v0.4s, v0.4s, v2.4s\n" - "sqrdmulh v23.4s, v23.4s, v2.4s\n" - "sqrdmulh v31.4s, v31.4s, v2.4s\n" - "sqrdmulh v30.4s, v30.4s, v2.4s\n" - "srshl v0.4s, v0.4s, v1.4s\n" - "srshl v23.4s, v23.4s, v1.4s\n" - "srshl v31.4s, v31.4s, v1.4s\n" - "srshl v30.4s, v30.4s, v1.4s\n" - "add v0.4s, v0.4s, v16.4s\n" - "add v23.4s, v23.4s, v16.4s\n" - "add v31.4s, v31.4s, v16.4s\n" - "add v30.4s, v30.4s, v16.4s\n" + "srshl v18.4s, v18.4s, v23.4s\n" + "sqrdmulh v22.4s, v22.4s, v19.4s\n" + "sqrdmulh v21.4s, v21.4s, v19.4s\n" + "sqrdmulh v20.4s, v20.4s, v19.4s\n" + "sqrdmulh v18.4s, v18.4s, v19.4s\n" + "srshl v22.4s, v22.4s, v17.4s\n" + "srshl v21.4s, v21.4s, v17.4s\n" + "srshl v20.4s, v20.4s, v17.4s\n" + "srshl v18.4s, v18.4s, v17.4s\n" + "add v22.4s, v22.4s, v16.4s\n" + "add v21.4s, v21.4s, v16.4s\n" + "add v20.4s, v20.4s, v16.4s\n" + "add v18.4s, v18.4s, v16.4s\n" "movi v16.4s, #0x0\n" - "smax v0.4s, v0.4s, v16.4s\n" - "smax v23.4s, v23.4s, v16.4s\n" - "smax v31.4s, v31.4s, v16.4s\n" - "smax v30.4s, v30.4s, v16.4s\n" + "smax v22.4s, v22.4s, v16.4s\n" + "smax v21.4s, v21.4s, v16.4s\n" + "smax v20.4s, v20.4s, v16.4s\n" + "smax v18.4s, v18.4s, v16.4s\n" "movi v16.4s, #0xff\n" - "smin v0.4s, v0.4s, v16.4s\n" - "smin v23.4s, v23.4s, v16.4s\n" - "smin v31.4s, v31.4s, v16.4s\n" - "smin v30.4s, v30.4s, v16.4s\n" - "uzp1 v23.16b, v0.16b, v23.16b\n" - "uzp1 v16.16b, v31.16b, v30.16b\n" - "uzp1 v16.16b, v23.16b, v16.16b\n" + "smin v22.4s, v22.4s, v16.4s\n" + "smin v21.4s, v21.4s, v16.4s\n" + "smin v20.4s, v20.4s, v16.4s\n" + "smin v18.4s, v18.4s, v16.4s\n" + "uzp1 v17.16b, v22.16b, v21.16b\n" + "uzp1 v16.16b, v20.16b, v18.16b\n" + "uzp1 v16.16b, v17.16b, v16.16b\n" "tbz %x[n_channels], #3, 38f\n" "st1 { v16.d }[0], [%x[outptr]], #0x8\n" "tbz %x[n_channels], #2, 36f\n" @@ -667,10 +667,11 @@ void a64_u8q_nhwc_max_generic_depthfirst_impl( "43:" // End : [n_channels] "+&r" (n_channels), [outptr] "+&r" (outptr) : [inptrs] "r" (inptrs), [n_valid_cells] "r" (n_valid_cells), [offsetof_qp_input_offset] "I" (offsetof(Requantize32, input_offset)), [offsetof_qp_output_offset] "I" (offsetof(Requantize32, output_offset)), [offsetof_qp_per_layer_left_shift] "I" (offsetof(Requantize32, per_layer_left_shift)), [offsetof_qp_per_layer_mul] "I" (offsetof(Requantize32, per_layer_mul)), [offsetof_qp_per_layer_right_shift] "I" (offsetof(Requantize32, per_layer_right_shift)), [quant_params] "r" (&qp) - : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x9", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" + : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); } } // namespace pooling } // namespace arm_conv -#endif // defined(__aarch64__) + +#endif // defined(__aarch64__) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/cpp_nhwc_1x1_stride_any_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/cpp_nhwc_1x1_stride_any_depthfirst/generic.cpp index 2bb22131f7..1f8f863de2 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/cpp_nhwc_1x1_stride_any_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/cpp_nhwc_1x1_stride_any_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020 Arm Limited. + * Copyright (c) 2020, 2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -24,6 +24,10 @@ #include <cstdint> #include <cstring> +#ifdef ARM_COMPUTE_ENABLE_BF16 +#include "bfloat.hpp" +using arm_gemm::bfloat16; +#endif namespace arm_conv { namespace pooling { @@ -41,9 +45,15 @@ void cpp_nhwc_1x1_stride_any_depthfirst_impl( } template void cpp_nhwc_1x1_stride_any_depthfirst_impl(uint64_t, uint64_t, uint64_t, const float *const *, float *); -#if defined(__ARM_FP16_ARGS) + +#ifdef __ARM_FP16_ARGS template void cpp_nhwc_1x1_stride_any_depthfirst_impl(uint64_t, uint64_t, uint64_t, const __fp16 *const *, __fp16 *); -#endif // defined(__ARM_FP16_ARGS) +#endif + +#ifdef ARM_COMPUTE_ENABLE_BF16 +template void cpp_nhwc_1x1_stride_any_depthfirst_impl(uint64_t, uint64_t, uint64_t, const bfloat16 *const *, bfloat16 *); +#endif + template void cpp_nhwc_1x1_stride_any_depthfirst_impl(uint64_t, uint64_t, uint64_t, const int8_t *const *, int8_t *); template void cpp_nhwc_1x1_stride_any_depthfirst_impl(uint64_t, uint64_t, uint64_t, const uint8_t *const *, uint8_t *); diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp index 250d92c051..f6682e75e2 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Arm Limited. + * Copyright (c) 2022-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -24,6 +24,8 @@ #pragma once +#if defined(ARM_COMPUTE_ENABLE_SME) && defined(__ARM_FP16_ARGS) + namespace arm_conv { namespace pooling { @@ -45,3 +47,5 @@ struct sme_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst : public DepthfirstStrategy } // namespace pooling } // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) && defined(__ARM_FP16_ARGS) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp index bce623acd1..67b07205cd 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp @@ -26,7 +26,7 @@ #include <cstddef> #include <cstdint> -#if defined(__ARM_FEATURE_SVE) && defined(__ARM_FP16_ARGS) && defined(ARM_COMPUTE_ENABLE_SME) +#if defined(ARM_COMPUTE_ENABLE_SME) && defined(__ARM_FP16_ARGS) namespace arm_conv { namespace pooling { @@ -91,34 +91,34 @@ void sme_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst_impl( "add x20, %x[args], %[offsetof_rescale]\n" "ld1rqh { z4.h }, p0/Z, [x20]\n" "ldr x5, [%x[args], %[offsetof_n_channels]]\n" - "whilelt p1.h, x3, x5\n" + "whilelt p0.h, x3, x5\n" "mov x6, #0x0\n" "ldp x7, x8, [x21, #0x0]\n" "ldp x17, x16, [x21, #0x10]\n" "ldp x15, x14, [x4, #0x0]\n" - "ld1h { z3.h }, p1/Z, [x14, x3, LSL #1]\n" + "ld1h { z3.h }, p0/Z, [x14, x3, LSL #1]\n" "ldp x13, x12, [x4, #0x10]\n" - "ld1h { z2.h }, p1/Z, [x13, x3, LSL #1]\n" + "ld1h { z2.h }, p0/Z, [x13, x3, LSL #1]\n" "ldp x11, x10, [x4, #0x20]\n" - "ld1h { z1.h }, p1/Z, [x10, x3, LSL #1]\n" + "ld1h { z1.h }, p0/Z, [x10, x3, LSL #1]\n" "ldp x9, x28, [x4, #0x30]\n" - "ld1h { z0.h }, p1/Z, [x9, x3, LSL #1]\n" + "ld1h { z0.h }, p0/Z, [x9, x3, LSL #1]\n" "ldp x27, x26, [x4, #0x40]\n" - "ld1h { z31.h }, p1/Z, [x26, x3, LSL #1]\n" + "ld1h { z31.h }, p0/Z, [x26, x3, LSL #1]\n" "ldp x25, x24, [x4, #0x50]\n" - "ld1h { z30.h }, p1/Z, [x25, x3, LSL #1]\n" + "ld1h { z30.h }, p0/Z, [x25, x3, LSL #1]\n" "ldp x23, x22, [x4, #0x60]\n" - "ld1h { z29.h }, p1/Z, [x11, x3, LSL #1]\n" + "ld1h { z29.h }, p0/Z, [x11, x3, LSL #1]\n" "ldp x21, x20, [x4, #0x70]\n" - "ld1h { z28.h }, p1/Z, [x27, x3, LSL #1]\n" - "ld1h { z27.h }, p1/Z, [x28, x3, LSL #1]\n" - "ld1h { z22.h }, p1/Z, [x24, x3, LSL #1]\n" - "ld1h { z21.h }, p1/Z, [x22, x3, LSL #1]\n" - "ld1h { z20.h }, p1/Z, [x21, x3, LSL #1]\n" - "ld1h { z26.h }, p1/Z, [x15, x3, LSL #1]\n" - "ld1h { z25.h }, p1/Z, [x12, x3, LSL #1]\n" - "ld1h { z24.h }, p1/Z, [x23, x3, LSL #1]\n" - "ld1h { z23.h }, p1/Z, [x20, x3, LSL #1]\n" + "ld1h { z28.h }, p0/Z, [x27, x3, LSL #1]\n" + "ld1h { z27.h }, p0/Z, [x28, x3, LSL #1]\n" + "ld1h { z22.h }, p0/Z, [x24, x3, LSL #1]\n" + "ld1h { z21.h }, p0/Z, [x22, x3, LSL #1]\n" + "ld1h { z20.h }, p0/Z, [x21, x3, LSL #1]\n" + "ld1h { z26.h }, p0/Z, [x15, x3, LSL #1]\n" + "ld1h { z25.h }, p0/Z, [x12, x3, LSL #1]\n" + "ld1h { z24.h }, p0/Z, [x23, x3, LSL #1]\n" + "ld1h { z23.h }, p0/Z, [x20, x3, LSL #1]\n" "incw x3\n" "whilelt p1.h, x3, x5\n" "b.none 2f\n" @@ -206,4 +206,4 @@ void sme_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst_impl( } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) && defined(__ARM_FP16_ARGS) && defined(ARM_COMPUTE_ENABLE_SME) +#endif // defined(ARM_COMPUTE_ENABLE_SME) && defined(__ARM_FP16_ARGS) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_avg_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_avg_generic_depthfirst.hpp index 117eb36007..cf09f421c4 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_avg_generic_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_avg_generic_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Arm Limited. + * Copyright (c) 2022-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -26,6 +26,8 @@ #pragma once +#if defined(ARM_COMPUTE_ENABLE_SME) && defined(__ARM_FP16_ARGS) + namespace arm_conv { namespace pooling { @@ -40,3 +42,5 @@ struct sme_fp16_nhwc_avg_generic_depthfirst : IGenericDepthfirstStrategy<__fp16, } // namespace pooling } // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) && defined(__ARM_FP16_ARGS) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_avg_generic_depthfirst/generic.cpp index c43da42d9e..60f17b7bc2 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_avg_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_avg_generic_depthfirst/generic.cpp @@ -22,9 +22,10 @@ * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SME) - #include <cstdint> +#include <cstddef> + +#if defined(ARM_COMPUTE_ENABLE_SME) && defined(__ARM_FP16_ARGS) namespace arm_conv { namespace pooling { @@ -57,68 +58,68 @@ void sme_fp16_nhwc_avg_generic_depthfirst_impl( "lsr x25, %x[n_valid_cells], #0x2\n" "mov z5.b, #0x0\n" "mov z4.b, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "mov z3.b, #0x0\n" "mov z2.b, #0x0\n" "cbz x25, 4f\n" - "ldp x24, x23, [x20, #0x0]\n" + "ldp x23, x22, [x24, #0x0]\n" "subs x25, x25, #0x1\n" - "ld1h { z1.h }, p3/Z, [x24, x9, LSL #1]\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" - "ld1h { z0.h }, p3/Z, [x23, x9, LSL #1]\n" - "ld1h { z31.h }, p3/Z, [x22, x9, LSL #1]\n" - "ld1h { z30.h }, p3/Z, [x21, x9, LSL #1]\n" - "ld1h { z29.h }, p2/Z, [x24, x28, LSL #1]\n" - "ld1h { z22.h }, p2/Z, [x23, x28, LSL #1]\n" - "ld1h { z28.h }, p2/Z, [x22, x28, LSL #1]\n" - "ld1h { z18.h }, p2/Z, [x21, x28, LSL #1]\n" - "ld1h { z27.h }, p1/Z, [x24, x27, LSL #1]\n" - "ld1h { z21.h }, p1/Z, [x23, x27, LSL #1]\n" - "ld1h { z26.h }, p1/Z, [x22, x27, LSL #1]\n" - "ld1h { z17.h }, p1/Z, [x21, x27, LSL #1]\n" - "ld1h { z25.h }, p0/Z, [x24, x26, LSL #1]\n" - "ld1h { z20.h }, p0/Z, [x23, x26, LSL #1]\n" - "ld1h { z24.h }, p0/Z, [x22, x26, LSL #1]\n" - "ld1h { z16.h }, p0/Z, [x21, x26, LSL #1]\n" + "ld1h { z1.h }, p3/Z, [x23, x9, LSL #1]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "ld1h { z0.h }, p3/Z, [x22, x9, LSL #1]\n" + "ld1h { z31.h }, p3/Z, [x21, x9, LSL #1]\n" + "ld1h { z30.h }, p3/Z, [x20, x9, LSL #1]\n" + "ld1h { z29.h }, p2/Z, [x23, x28, LSL #1]\n" + "ld1h { z22.h }, p2/Z, [x22, x28, LSL #1]\n" + "ld1h { z28.h }, p2/Z, [x21, x28, LSL #1]\n" + "ld1h { z18.h }, p2/Z, [x20, x28, LSL #1]\n" + "ld1h { z27.h }, p1/Z, [x23, x27, LSL #1]\n" + "ld1h { z21.h }, p1/Z, [x22, x27, LSL #1]\n" + "ld1h { z26.h }, p1/Z, [x21, x27, LSL #1]\n" + "ld1h { z17.h }, p1/Z, [x20, x27, LSL #1]\n" + "ld1h { z25.h }, p0/Z, [x23, x26, LSL #1]\n" + "ld1h { z20.h }, p0/Z, [x22, x26, LSL #1]\n" + "ld1h { z24.h }, p0/Z, [x21, x26, LSL #1]\n" + "ld1h { z16.h }, p0/Z, [x20, x26, LSL #1]\n" "beq 3f\n" "2:" // 4-vectors of channels: 4 inputs loop "fadd z23.h, z1.h, z0.h\n" "fadd z19.h, z31.h, z30.h\n" - "ldp x24, x23, [x20, #0x0]\n" + "ldp x23, x22, [x24, #0x0]\n" "subs x25, x25, #0x1\n" "fadd z22.h, z29.h, z22.h\n" "fadd z18.h, z28.h, z18.h\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" "fadd z21.h, z27.h, z21.h\n" "fadd z17.h, z26.h, z17.h\n" - "ld1h { z1.h }, p3/Z, [x24, x9, LSL #1]\n" + "ld1h { z1.h }, p3/Z, [x23, x9, LSL #1]\n" "fadd z20.h, z25.h, z20.h\n" "fadd z16.h, z24.h, z16.h\n" - "ld1h { z0.h }, p3/Z, [x23, x9, LSL #1]\n" + "ld1h { z0.h }, p3/Z, [x22, x9, LSL #1]\n" "fadd z19.h, z23.h, z19.h\n" "fadd z18.h, z22.h, z18.h\n" - "ld1h { z31.h }, p3/Z, [x22, x9, LSL #1]\n" + "ld1h { z31.h }, p3/Z, [x21, x9, LSL #1]\n" "fadd z17.h, z21.h, z17.h\n" "fadd z16.h, z20.h, z16.h\n" - "ld1h { z30.h }, p3/Z, [x21, x9, LSL #1]\n" + "ld1h { z30.h }, p3/Z, [x20, x9, LSL #1]\n" "fadd z5.h, z5.h, z19.h\n" "fadd z4.h, z4.h, z18.h\n" - "ld1h { z29.h }, p2/Z, [x24, x28, LSL #1]\n" + "ld1h { z29.h }, p2/Z, [x23, x28, LSL #1]\n" "fadd z3.h, z3.h, z17.h\n" "fadd z2.h, z2.h, z16.h\n" - "ld1h { z22.h }, p2/Z, [x23, x28, LSL #1]\n" - "ld1h { z28.h }, p2/Z, [x22, x28, LSL #1]\n" - "ld1h { z18.h }, p2/Z, [x21, x28, LSL #1]\n" - "ld1h { z27.h }, p1/Z, [x24, x27, LSL #1]\n" - "ld1h { z21.h }, p1/Z, [x23, x27, LSL #1]\n" - "ld1h { z26.h }, p1/Z, [x22, x27, LSL #1]\n" - "ld1h { z17.h }, p1/Z, [x21, x27, LSL #1]\n" - "ld1h { z25.h }, p0/Z, [x24, x26, LSL #1]\n" - "ld1h { z20.h }, p0/Z, [x23, x26, LSL #1]\n" - "ld1h { z24.h }, p0/Z, [x22, x26, LSL #1]\n" - "ld1h { z16.h }, p0/Z, [x21, x26, LSL #1]\n" + "ld1h { z22.h }, p2/Z, [x22, x28, LSL #1]\n" + "ld1h { z28.h }, p2/Z, [x21, x28, LSL #1]\n" + "ld1h { z18.h }, p2/Z, [x20, x28, LSL #1]\n" + "ld1h { z27.h }, p1/Z, [x23, x27, LSL #1]\n" + "ld1h { z21.h }, p1/Z, [x22, x27, LSL #1]\n" + "ld1h { z26.h }, p1/Z, [x21, x27, LSL #1]\n" + "ld1h { z17.h }, p1/Z, [x20, x27, LSL #1]\n" + "ld1h { z25.h }, p0/Z, [x23, x26, LSL #1]\n" + "ld1h { z20.h }, p0/Z, [x22, x26, LSL #1]\n" + "ld1h { z24.h }, p0/Z, [x21, x26, LSL #1]\n" + "ld1h { z16.h }, p0/Z, [x20, x26, LSL #1]\n" "bgt 2b\n" "3:" // 4-vectors of channels: 4 inputs tail "fadd z23.h, z1.h, z0.h\n" @@ -141,16 +142,16 @@ void sme_fp16_nhwc_avg_generic_depthfirst_impl( "ands x21, %x[n_valid_cells], #0x3\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x24, [x20], #0x8\n" - "ld1h { z1.h }, p3/Z, [x24, x9, LSL #1]\n" + "ldr x20, [x24], #0x8\n" + "ld1h { z16.h }, p3/Z, [x20, x9, LSL #1]\n" "subs x21, x21, #0x1\n" - "fadd z5.h, z5.h, z1.h\n" - "ld1h { z29.h }, p2/Z, [x24, x28, LSL #1]\n" - "fadd z4.h, z4.h, z29.h\n" - "ld1h { z27.h }, p1/Z, [x24, x27, LSL #1]\n" - "fadd z3.h, z3.h, z27.h\n" - "ld1h { z25.h }, p0/Z, [x24, x26, LSL #1]\n" - "fadd z2.h, z2.h, z25.h\n" + "fadd z5.h, z5.h, z16.h\n" + "ld1h { z16.h }, p2/Z, [x20, x28, LSL #1]\n" + "fadd z4.h, z4.h, z16.h\n" + "ld1h { z16.h }, p1/Z, [x20, x27, LSL #1]\n" + "fadd z3.h, z3.h, z16.h\n" + "ld1h { z16.h }, p0/Z, [x20, x26, LSL #1]\n" + "fadd z2.h, z2.h, z16.h\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End "fmul z5.h, z5.h, z6.h\n" @@ -173,44 +174,44 @@ void sme_fp16_nhwc_avg_generic_depthfirst_impl( "8:" // Single vector of channels: Loop "lsr x25, %x[n_valid_cells], #0x2\n" "mov z5.b, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "cbz x25, 11f\n" - "ldp x24, x23, [x20, #0x0]\n" + "ldp x20, x22, [x24, #0x0]\n" "subs x25, x25, #0x1\n" - "ld1h { z1.h }, p3/Z, [x24, x9, LSL #1]\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" - "ld1h { z0.h }, p3/Z, [x23, x9, LSL #1]\n" - "ld1h { z31.h }, p3/Z, [x22, x9, LSL #1]\n" - "ld1h { z30.h }, p3/Z, [x21, x9, LSL #1]\n" + "ld1h { z1.h }, p3/Z, [x20, x9, LSL #1]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "ld1h { z0.h }, p3/Z, [x22, x9, LSL #1]\n" + "ld1h { z31.h }, p3/Z, [x21, x9, LSL #1]\n" + "ld1h { z30.h }, p3/Z, [x20, x9, LSL #1]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 4 inputs loop - "fadd z23.h, z1.h, z0.h\n" - "fadd z19.h, z31.h, z30.h\n" - "ldp x24, x23, [x20, #0x0]\n" + "fadd z17.h, z1.h, z0.h\n" + "fadd z16.h, z31.h, z30.h\n" + "ldp x23, x22, [x24, #0x0]\n" "subs x25, x25, #0x1\n" - "fadd z19.h, z23.h, z19.h\n" - "ldp x22, x21, [x20, #0x10]\n" - "fadd z5.h, z5.h, z19.h\n" - "add x20, x20, #0x20\n" - "ld1h { z1.h }, p3/Z, [x24, x9, LSL #1]\n" - "ld1h { z0.h }, p3/Z, [x23, x9, LSL #1]\n" - "ld1h { z31.h }, p3/Z, [x22, x9, LSL #1]\n" - "ld1h { z30.h }, p3/Z, [x21, x9, LSL #1]\n" + "fadd z16.h, z17.h, z16.h\n" + "ldp x21, x20, [x24, #0x10]\n" + "fadd z5.h, z5.h, z16.h\n" + "add x24, x24, #0x20\n" + "ld1h { z1.h }, p3/Z, [x23, x9, LSL #1]\n" + "ld1h { z0.h }, p3/Z, [x22, x9, LSL #1]\n" + "ld1h { z31.h }, p3/Z, [x21, x9, LSL #1]\n" + "ld1h { z30.h }, p3/Z, [x20, x9, LSL #1]\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 4 inputs tail - "fadd z23.h, z1.h, z0.h\n" - "fadd z19.h, z31.h, z30.h\n" - "fadd z19.h, z23.h, z19.h\n" - "fadd z5.h, z5.h, z19.h\n" + "fadd z17.h, z1.h, z0.h\n" + "fadd z16.h, z31.h, z30.h\n" + "fadd z16.h, z17.h, z16.h\n" + "fadd z5.h, z5.h, z16.h\n" "11:" // Single vector of channels: Loop: After loop "ands x21, %x[n_valid_cells], #0x3\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x24, [x20], #0x8\n" - "ld1h { z1.h }, p3/Z, [x24, x9, LSL #1]\n" + "ldr x20, [x24], #0x8\n" + "ld1h { z16.h }, p3/Z, [x20, x9, LSL #1]\n" "subs x21, x21, #0x1\n" - "fadd z5.h, z5.h, z1.h\n" + "fadd z5.h, z5.h, z16.h\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End "fmul z5.h, z5.h, z6.h\n" @@ -229,4 +230,4 @@ void sme_fp16_nhwc_avg_generic_depthfirst_impl( } // namespace pooling } // namespace arm_conv -#endif // defined(ARM_COMPUTE_ENABLE_SME) +#endif // defined(ARM_COMPUTE_ENABLE_SME) && defined(__ARM_FP16_ARGS) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_max_2x2_s1_output2x2_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_max_2x2_s1_output2x2_depthfirst.hpp index 9489c1f8da..cd6c7449a8 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_max_2x2_s1_output2x2_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_max_2x2_s1_output2x2_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Arm Limited. + * Copyright (c) 2022-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -24,6 +24,8 @@ #pragma once +#if defined(ARM_COMPUTE_ENABLE_SME) && defined(__ARM_FP16_ARGS) + namespace arm_conv { namespace pooling { @@ -45,3 +47,5 @@ struct sme_fp16_nhwc_max_2x2_s1_output2x2_depthfirst : public DepthfirstStrategy } // namespace pooling } // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) && defined(__ARM_FP16_ARGS) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp index f71f2625b6..7fc776ed4e 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp @@ -26,7 +26,7 @@ #include <cstddef> #include <cstdint> -#if defined(__ARM_FEATURE_SVE) && defined(__ARM_FP16_ARGS) && defined(ARM_COMPUTE_ENABLE_SME) +#if defined(ARM_COMPUTE_ENABLE_SME) && defined(__ARM_FP16_ARGS) namespace arm_conv { namespace pooling { @@ -70,23 +70,23 @@ void sme_fp16_nhwc_max_2x2_s1_output2x2_depthfirst_impl( "ldr x20, [%x[args], %[offsetof_inptrs]]\n" "mov x14, #0x0\n" "ldr x13, [%x[args], %[offsetof_n_channels]]\n" - "whilelt p1.h, x15, x13\n" + "whilelt p0.h, x15, x13\n" "ldp x12, x11, [x21, #0x0]\n" "ldp x10, x9, [x21, #0x10]\n" "ldp x28, x27, [x20, #0x0]\n" - "ld1h { z30.h }, p1/Z, [x27, x15, LSL #1]\n" + "ld1h { z30.h }, p0/Z, [x27, x15, LSL #1]\n" "ldp x26, x25, [x20, #0x10]\n" - "ld1h { z29.h }, p1/Z, [x25, x15, LSL #1]\n" + "ld1h { z29.h }, p0/Z, [x25, x15, LSL #1]\n" "ldp x24, x23, [x20, #0x20]\n" - "ld1h { z28.h }, p1/Z, [x24, x15, LSL #1]\n" + "ld1h { z28.h }, p0/Z, [x24, x15, LSL #1]\n" "ldp x22, x21, [x20, #0x30]\n" - "ld1h { z27.h }, p1/Z, [x21, x15, LSL #1]\n" + "ld1h { z27.h }, p0/Z, [x21, x15, LSL #1]\n" "ldr x20, [x20, #0x40]\n" - "ld1h { z26.h }, p1/Z, [x28, x15, LSL #1]\n" - "ld1h { z25.h }, p1/Z, [x26, x15, LSL #1]\n" - "ld1h { z24.h }, p1/Z, [x23, x15, LSL #1]\n" - "ld1h { z23.h }, p1/Z, [x22, x15, LSL #1]\n" - "ld1h { z19.h }, p1/Z, [x20, x15, LSL #1]\n" + "ld1h { z26.h }, p0/Z, [x28, x15, LSL #1]\n" + "ld1h { z25.h }, p0/Z, [x26, x15, LSL #1]\n" + "ld1h { z24.h }, p0/Z, [x23, x15, LSL #1]\n" + "ld1h { z19.h }, p0/Z, [x22, x15, LSL #1]\n" + "ld1h { z23.h }, p0/Z, [x20, x15, LSL #1]\n" "incw x15\n" "whilelt p1.h, x15, x13\n" "b.none 2f\n" @@ -95,25 +95,25 @@ void sme_fp16_nhwc_max_2x2_s1_output2x2_depthfirst_impl( "movprfx z21, z28\n fmax z21.h, p2/M, z21.h, z27.h\n" "ld1h { z30.h }, p1/Z, [x27, x15, LSL #1]\n" "whilelt p0.h, x14, x13\n" - "movprfx z20, z29\n fmax z20.h, p2/M, z20.h, z26.h\n" - "movprfx z18, z25\n fmax z18.h, p2/M, z18.h, z24.h\n" + "movprfx z18, z29\n fmax z18.h, p2/M, z18.h, z26.h\n" + "movprfx z17, z25\n fmax z17.h, p2/M, z17.h, z24.h\n" "ld1h { z28.h }, p1/Z, [x24, x15, LSL #1]\n" - "movprfx z17, z29\n fmax z17.h, p2/M, z17.h, z23.h\n" - "movprfx z16, z24\n fmax z16.h, p2/M, z16.h, z19.h\n" + "movprfx z16, z29\n fmax z16.h, p2/M, z16.h, z19.h\n" + "movprfx z20, z24\n fmax z20.h, p2/M, z20.h, z23.h\n" "ld1h { z27.h }, p1/Z, [x21, x15, LSL #1]\n" "ld1h { z29.h }, p1/Z, [x25, x15, LSL #1]\n" - "movprfx z19, z22\n fmax z19.h, p2/M, z19.h, z20.h\n" - "fmax z18.h, p2/M, z18.h, z22.h\n" + "movprfx z19, z22\n fmax z19.h, p2/M, z19.h, z18.h\n" + "movprfx z18, z17\n fmax z18.h, p2/M, z18.h, z22.h\n" "ld1h { z26.h }, p1/Z, [x28, x15, LSL #1]\n" - "fmax z17.h, p2/M, z17.h, z21.h\n" - "fmax z16.h, p2/M, z16.h, z21.h\n" + "movprfx z17, z16\n fmax z17.h, p2/M, z17.h, z21.h\n" + "movprfx z16, z21\n fmax z16.h, p2/M, z16.h, z20.h\n" "ld1h { z25.h }, p1/Z, [x26, x15, LSL #1]\n" "st1h { z19.h }, p0, [x12, x14, LSL #1]\n" "ld1h { z24.h }, p1/Z, [x23, x15, LSL #1]\n" "st1h { z18.h }, p0, [x11, x14, LSL #1]\n" - "ld1h { z23.h }, p1/Z, [x22, x15, LSL #1]\n" + "ld1h { z19.h }, p1/Z, [x22, x15, LSL #1]\n" "st1h { z17.h }, p0, [x10, x14, LSL #1]\n" - "ld1h { z19.h }, p1/Z, [x20, x15, LSL #1]\n" + "ld1h { z23.h }, p1/Z, [x20, x15, LSL #1]\n" "incw x15\n" "whilelt p1.h, x15, x13\n" "st1h { z16.h }, p0, [x9, x14, LSL #1]\n" @@ -125,13 +125,13 @@ void sme_fp16_nhwc_max_2x2_s1_output2x2_depthfirst_impl( "whilelt p0.h, x14, x13\n" "movprfx z20, z29\n fmax z20.h, p2/M, z20.h, z26.h\n" "movprfx z18, z25\n fmax z18.h, p2/M, z18.h, z24.h\n" - "movprfx z17, z29\n fmax z17.h, p2/M, z17.h, z23.h\n" - "movprfx z16, z24\n fmax z16.h, p2/M, z16.h, z19.h\n" - "movprfx z19, z22\n fmax z19.h, p2/M, z19.h, z20.h\n" + "movprfx z17, z29\n fmax z17.h, p2/M, z17.h, z19.h\n" + "movprfx z19, z24\n fmax z19.h, p2/M, z19.h, z23.h\n" + "movprfx z16, z22\n fmax z16.h, p2/M, z16.h, z20.h\n" "fmax z18.h, p2/M, z18.h, z22.h\n" - "st1h { z19.h }, p0, [x12, x14, LSL #1]\n" + "st1h { z16.h }, p0, [x12, x14, LSL #1]\n" "fmax z17.h, p2/M, z17.h, z21.h\n" - "fmax z16.h, p2/M, z16.h, z21.h\n" + "movprfx z16, z21\n fmax z16.h, p2/M, z16.h, z19.h\n" "st1h { z18.h }, p0, [x11, x14, LSL #1]\n" "st1h { z17.h }, p0, [x10, x14, LSL #1]\n" "st1h { z16.h }, p0, [x9, x14, LSL #1]\n" @@ -145,4 +145,4 @@ void sme_fp16_nhwc_max_2x2_s1_output2x2_depthfirst_impl( } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) && defined(__ARM_FP16_ARGS) && defined(ARM_COMPUTE_ENABLE_SME) +#endif // defined(ARM_COMPUTE_ENABLE_SME) && defined(__ARM_FP16_ARGS) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_max_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_max_generic_depthfirst.hpp index 33ff1f2154..bfb3bf5b1a 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_max_generic_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_max_generic_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Arm Limited. + * Copyright (c) 2022-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -26,6 +26,8 @@ #pragma once +#if defined(ARM_COMPUTE_ENABLE_SME) && defined(__ARM_FP16_ARGS) + namespace arm_conv { namespace pooling { @@ -40,3 +42,5 @@ struct sme_fp16_nhwc_max_generic_depthfirst : IGenericDepthfirstStrategy<__fp16, } // namespace pooling } // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) && defined(__ARM_FP16_ARGS) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_max_generic_depthfirst/generic.cpp index c07ce97231..afa2ccbd71 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_max_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_max_generic_depthfirst/generic.cpp @@ -22,9 +22,10 @@ * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SME) - #include <cstdint> +#include <cstddef> + +#if defined(ARM_COMPUTE_ENABLE_SME) && defined(__ARM_FP16_ARGS) namespace arm_conv { namespace pooling { @@ -54,68 +55,68 @@ void sme_fp16_nhwc_max_generic_depthfirst_impl( "lsr x25, %x[n_valid_cells], #0x2\n" "mov z4.h, #0xfc00\n" "mov z3.h, #0xfc00\n" - "mov x20, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "mov z2.h, #0xfc00\n" "mov z1.h, #0xfc00\n" "cbz x25, 4f\n" - "ldp x24, x23, [x20, #0x0]\n" + "ldp x23, x22, [x24, #0x0]\n" "subs x25, x25, #0x1\n" - "ld1h { z0.h }, p4/Z, [x24, x9, LSL #1]\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" - "ld1h { z31.h }, p4/Z, [x23, x9, LSL #1]\n" - "ld1h { z23.h }, p4/Z, [x22, x9, LSL #1]\n" - "ld1h { z30.h }, p4/Z, [x21, x9, LSL #1]\n" - "ld1h { z18.h }, p3/Z, [x24, x28, LSL #1]\n" - "ld1h { z29.h }, p3/Z, [x23, x28, LSL #1]\n" - "ld1h { z22.h }, p3/Z, [x22, x28, LSL #1]\n" - "ld1h { z28.h }, p3/Z, [x21, x28, LSL #1]\n" - "ld1h { z17.h }, p2/Z, [x24, x27, LSL #1]\n" - "ld1h { z27.h }, p2/Z, [x23, x27, LSL #1]\n" - "ld1h { z21.h }, p2/Z, [x22, x27, LSL #1]\n" - "ld1h { z26.h }, p2/Z, [x21, x27, LSL #1]\n" - "ld1h { z16.h }, p1/Z, [x24, x26, LSL #1]\n" - "ld1h { z25.h }, p1/Z, [x23, x26, LSL #1]\n" - "ld1h { z20.h }, p1/Z, [x22, x26, LSL #1]\n" - "ld1h { z24.h }, p1/Z, [x21, x26, LSL #1]\n" + "ld1h { z0.h }, p4/Z, [x23, x9, LSL #1]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "ld1h { z31.h }, p4/Z, [x22, x9, LSL #1]\n" + "ld1h { z23.h }, p4/Z, [x21, x9, LSL #1]\n" + "ld1h { z30.h }, p4/Z, [x20, x9, LSL #1]\n" + "ld1h { z18.h }, p3/Z, [x23, x28, LSL #1]\n" + "ld1h { z29.h }, p3/Z, [x22, x28, LSL #1]\n" + "ld1h { z22.h }, p3/Z, [x21, x28, LSL #1]\n" + "ld1h { z28.h }, p3/Z, [x20, x28, LSL #1]\n" + "ld1h { z17.h }, p2/Z, [x23, x27, LSL #1]\n" + "ld1h { z27.h }, p2/Z, [x22, x27, LSL #1]\n" + "ld1h { z21.h }, p2/Z, [x21, x27, LSL #1]\n" + "ld1h { z26.h }, p2/Z, [x20, x27, LSL #1]\n" + "ld1h { z16.h }, p1/Z, [x23, x26, LSL #1]\n" + "ld1h { z25.h }, p1/Z, [x22, x26, LSL #1]\n" + "ld1h { z20.h }, p1/Z, [x21, x26, LSL #1]\n" + "ld1h { z24.h }, p1/Z, [x20, x26, LSL #1]\n" "beq 3f\n" "2:" // 4-vectors of channels: 4 inputs loop "movprfx z19, z0\n fmax z19.h, p0/M, z19.h, z31.h\n" "fmax z23.h, p0/M, z23.h, z30.h\n" - "ldp x24, x23, [x20, #0x0]\n" + "ldp x23, x22, [x24, #0x0]\n" "subs x25, x25, #0x1\n" "fmax z18.h, p0/M, z18.h, z29.h\n" "fmax z22.h, p0/M, z22.h, z28.h\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" "fmax z17.h, p0/M, z17.h, z27.h\n" "fmax z21.h, p0/M, z21.h, z26.h\n" - "ld1h { z0.h }, p4/Z, [x24, x9, LSL #1]\n" + "ld1h { z0.h }, p4/Z, [x23, x9, LSL #1]\n" "fmax z16.h, p0/M, z16.h, z25.h\n" "fmax z20.h, p0/M, z20.h, z24.h\n" - "ld1h { z31.h }, p4/Z, [x23, x9, LSL #1]\n" + "ld1h { z31.h }, p4/Z, [x22, x9, LSL #1]\n" "fmax z19.h, p0/M, z19.h, z23.h\n" "fmax z18.h, p0/M, z18.h, z22.h\n" - "ld1h { z23.h }, p4/Z, [x22, x9, LSL #1]\n" + "ld1h { z23.h }, p4/Z, [x21, x9, LSL #1]\n" "fmax z17.h, p0/M, z17.h, z21.h\n" "fmax z16.h, p0/M, z16.h, z20.h\n" - "ld1h { z30.h }, p4/Z, [x21, x9, LSL #1]\n" + "ld1h { z30.h }, p4/Z, [x20, x9, LSL #1]\n" "fmax z4.h, p0/M, z4.h, z19.h\n" "fmax z3.h, p0/M, z3.h, z18.h\n" - "ld1h { z18.h }, p3/Z, [x24, x28, LSL #1]\n" + "ld1h { z18.h }, p3/Z, [x23, x28, LSL #1]\n" "fmax z2.h, p0/M, z2.h, z17.h\n" "fmax z1.h, p0/M, z1.h, z16.h\n" - "ld1h { z29.h }, p3/Z, [x23, x28, LSL #1]\n" - "ld1h { z22.h }, p3/Z, [x22, x28, LSL #1]\n" - "ld1h { z28.h }, p3/Z, [x21, x28, LSL #1]\n" - "ld1h { z17.h }, p2/Z, [x24, x27, LSL #1]\n" - "ld1h { z27.h }, p2/Z, [x23, x27, LSL #1]\n" - "ld1h { z21.h }, p2/Z, [x22, x27, LSL #1]\n" - "ld1h { z26.h }, p2/Z, [x21, x27, LSL #1]\n" - "ld1h { z16.h }, p1/Z, [x24, x26, LSL #1]\n" - "ld1h { z25.h }, p1/Z, [x23, x26, LSL #1]\n" - "ld1h { z20.h }, p1/Z, [x22, x26, LSL #1]\n" - "ld1h { z24.h }, p1/Z, [x21, x26, LSL #1]\n" + "ld1h { z29.h }, p3/Z, [x22, x28, LSL #1]\n" + "ld1h { z22.h }, p3/Z, [x21, x28, LSL #1]\n" + "ld1h { z28.h }, p3/Z, [x20, x28, LSL #1]\n" + "ld1h { z17.h }, p2/Z, [x23, x27, LSL #1]\n" + "ld1h { z27.h }, p2/Z, [x22, x27, LSL #1]\n" + "ld1h { z21.h }, p2/Z, [x21, x27, LSL #1]\n" + "ld1h { z26.h }, p2/Z, [x20, x27, LSL #1]\n" + "ld1h { z16.h }, p1/Z, [x23, x26, LSL #1]\n" + "ld1h { z25.h }, p1/Z, [x22, x26, LSL #1]\n" + "ld1h { z20.h }, p1/Z, [x21, x26, LSL #1]\n" + "ld1h { z24.h }, p1/Z, [x20, x26, LSL #1]\n" "bgt 2b\n" "3:" // 4-vectors of channels: 4 inputs tail "movprfx z19, z0\n fmax z19.h, p0/M, z19.h, z31.h\n" @@ -138,15 +139,15 @@ void sme_fp16_nhwc_max_generic_depthfirst_impl( "ands x21, %x[n_valid_cells], #0x3\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x24, [x20], #0x8\n" - "ld1h { z0.h }, p4/Z, [x24, x9, LSL #1]\n" + "ldr x20, [x24], #0x8\n" + "ld1h { z16.h }, p4/Z, [x20, x9, LSL #1]\n" "subs x21, x21, #0x1\n" - "fmax z4.h, p0/M, z4.h, z0.h\n" - "ld1h { z18.h }, p3/Z, [x24, x28, LSL #1]\n" - "fmax z3.h, p0/M, z3.h, z18.h\n" - "ld1h { z17.h }, p2/Z, [x24, x27, LSL #1]\n" - "fmax z2.h, p0/M, z2.h, z17.h\n" - "ld1h { z16.h }, p1/Z, [x24, x26, LSL #1]\n" + "fmax z4.h, p0/M, z4.h, z16.h\n" + "ld1h { z16.h }, p3/Z, [x20, x28, LSL #1]\n" + "fmax z3.h, p0/M, z3.h, z16.h\n" + "ld1h { z16.h }, p2/Z, [x20, x27, LSL #1]\n" + "fmax z2.h, p0/M, z2.h, z16.h\n" + "ld1h { z16.h }, p1/Z, [x20, x26, LSL #1]\n" "fmax z1.h, p0/M, z1.h, z16.h\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End @@ -166,44 +167,44 @@ void sme_fp16_nhwc_max_generic_depthfirst_impl( "8:" // Single vector of channels: Loop "lsr x25, %x[n_valid_cells], #0x2\n" "mov z4.h, #0xfc00\n" - "mov x20, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "cbz x25, 11f\n" - "ldp x24, x23, [x20, #0x0]\n" + "ldp x20, x22, [x24, #0x0]\n" "subs x25, x25, #0x1\n" - "ld1h { z0.h }, p4/Z, [x24, x9, LSL #1]\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" - "ld1h { z31.h }, p4/Z, [x23, x9, LSL #1]\n" - "ld1h { z23.h }, p4/Z, [x22, x9, LSL #1]\n" - "ld1h { z30.h }, p4/Z, [x21, x9, LSL #1]\n" + "ld1h { z0.h }, p4/Z, [x20, x9, LSL #1]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "ld1h { z31.h }, p4/Z, [x22, x9, LSL #1]\n" + "ld1h { z23.h }, p4/Z, [x21, x9, LSL #1]\n" + "ld1h { z30.h }, p4/Z, [x20, x9, LSL #1]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 4 inputs loop - "movprfx z19, z0\n fmax z19.h, p0/M, z19.h, z31.h\n" - "fmax z23.h, p0/M, z23.h, z30.h\n" - "ldp x24, x23, [x20, #0x0]\n" + "movprfx z16, z0\n fmax z16.h, p0/M, z16.h, z31.h\n" + "movprfx z17, z23\n fmax z17.h, p0/M, z17.h, z30.h\n" + "ldp x23, x22, [x24, #0x0]\n" "subs x25, x25, #0x1\n" - "fmax z19.h, p0/M, z19.h, z23.h\n" - "ldp x22, x21, [x20, #0x10]\n" - "fmax z4.h, p0/M, z4.h, z19.h\n" - "add x20, x20, #0x20\n" - "ld1h { z0.h }, p4/Z, [x24, x9, LSL #1]\n" - "ld1h { z31.h }, p4/Z, [x23, x9, LSL #1]\n" - "ld1h { z23.h }, p4/Z, [x22, x9, LSL #1]\n" - "ld1h { z30.h }, p4/Z, [x21, x9, LSL #1]\n" + "fmax z16.h, p0/M, z16.h, z17.h\n" + "ldp x21, x20, [x24, #0x10]\n" + "fmax z4.h, p0/M, z4.h, z16.h\n" + "add x24, x24, #0x20\n" + "ld1h { z0.h }, p4/Z, [x23, x9, LSL #1]\n" + "ld1h { z31.h }, p4/Z, [x22, x9, LSL #1]\n" + "ld1h { z23.h }, p4/Z, [x21, x9, LSL #1]\n" + "ld1h { z30.h }, p4/Z, [x20, x9, LSL #1]\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 4 inputs tail - "movprfx z19, z0\n fmax z19.h, p0/M, z19.h, z31.h\n" - "fmax z23.h, p0/M, z23.h, z30.h\n" - "fmax z19.h, p0/M, z19.h, z23.h\n" - "fmax z4.h, p0/M, z4.h, z19.h\n" + "movprfx z16, z0\n fmax z16.h, p0/M, z16.h, z31.h\n" + "movprfx z17, z23\n fmax z17.h, p0/M, z17.h, z30.h\n" + "fmax z16.h, p0/M, z16.h, z17.h\n" + "fmax z4.h, p0/M, z4.h, z16.h\n" "11:" // Single vector of channels: Loop: After loop "ands x21, %x[n_valid_cells], #0x3\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x24, [x20], #0x8\n" - "ld1h { z0.h }, p4/Z, [x24, x9, LSL #1]\n" + "ldr x20, [x24], #0x8\n" + "ld1h { z16.h }, p4/Z, [x20, x9, LSL #1]\n" "subs x21, x21, #0x1\n" - "fmax z4.h, p0/M, z4.h, z0.h\n" + "fmax z4.h, p0/M, z4.h, z16.h\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End "st1h { z4.h }, p4, [%x[outptr], x9, LSL #1]\n" @@ -221,4 +222,4 @@ void sme_fp16_nhwc_max_generic_depthfirst_impl( } // namespace pooling } // namespace arm_conv -#endif // defined(ARM_COMPUTE_ENABLE_SME) +#endif // defined(ARM_COMPUTE_ENABLE_SME) && defined(__ARM_FP16_ARGS) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp index fa1b441371..23a0eee04e 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Arm Limited. + * Copyright (c) 2022-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -24,6 +24,8 @@ #pragma once +#if defined(ARM_COMPUTE_ENABLE_SME) + namespace arm_conv { namespace pooling { @@ -45,3 +47,5 @@ struct sme_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst : public DepthfirstStrategy } // namespace pooling } // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp index cf69800522..8c8532827a 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp @@ -26,7 +26,7 @@ #include <cstddef> #include <cstdint> -#if defined(__ARM_FEATURE_SVE) && defined(ARM_COMPUTE_ENABLE_SME) +#if defined(ARM_COMPUTE_ENABLE_SME) namespace arm_conv { namespace pooling { @@ -91,34 +91,34 @@ void sme_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst_impl( "add x20, %x[args], %[offsetof_rescale]\n" "ld1rqw { z4.s }, p0/Z, [x20]\n" "ldr x5, [%x[args], %[offsetof_n_channels]]\n" - "whilelt p1.s, x3, x5\n" + "whilelt p0.s, x3, x5\n" "mov x6, #0x0\n" "ldp x7, x8, [x21, #0x0]\n" "ldp x17, x16, [x21, #0x10]\n" "ldp x15, x14, [x4, #0x0]\n" - "ld1w { z3.s }, p1/Z, [x14, x3, LSL #2]\n" + "ld1w { z3.s }, p0/Z, [x14, x3, LSL #2]\n" "ldp x13, x12, [x4, #0x10]\n" - "ld1w { z2.s }, p1/Z, [x13, x3, LSL #2]\n" + "ld1w { z2.s }, p0/Z, [x13, x3, LSL #2]\n" "ldp x11, x10, [x4, #0x20]\n" - "ld1w { z1.s }, p1/Z, [x10, x3, LSL #2]\n" + "ld1w { z1.s }, p0/Z, [x10, x3, LSL #2]\n" "ldp x9, x28, [x4, #0x30]\n" - "ld1w { z0.s }, p1/Z, [x9, x3, LSL #2]\n" + "ld1w { z0.s }, p0/Z, [x9, x3, LSL #2]\n" "ldp x27, x26, [x4, #0x40]\n" - "ld1w { z31.s }, p1/Z, [x26, x3, LSL #2]\n" + "ld1w { z31.s }, p0/Z, [x26, x3, LSL #2]\n" "ldp x25, x24, [x4, #0x50]\n" - "ld1w { z30.s }, p1/Z, [x25, x3, LSL #2]\n" + "ld1w { z30.s }, p0/Z, [x25, x3, LSL #2]\n" "ldp x23, x22, [x4, #0x60]\n" - "ld1w { z29.s }, p1/Z, [x11, x3, LSL #2]\n" + "ld1w { z29.s }, p0/Z, [x11, x3, LSL #2]\n" "ldp x21, x20, [x4, #0x70]\n" - "ld1w { z28.s }, p1/Z, [x27, x3, LSL #2]\n" - "ld1w { z27.s }, p1/Z, [x28, x3, LSL #2]\n" - "ld1w { z22.s }, p1/Z, [x24, x3, LSL #2]\n" - "ld1w { z21.s }, p1/Z, [x22, x3, LSL #2]\n" - "ld1w { z20.s }, p1/Z, [x21, x3, LSL #2]\n" - "ld1w { z26.s }, p1/Z, [x15, x3, LSL #2]\n" - "ld1w { z25.s }, p1/Z, [x12, x3, LSL #2]\n" - "ld1w { z24.s }, p1/Z, [x23, x3, LSL #2]\n" - "ld1w { z23.s }, p1/Z, [x20, x3, LSL #2]\n" + "ld1w { z28.s }, p0/Z, [x27, x3, LSL #2]\n" + "ld1w { z27.s }, p0/Z, [x28, x3, LSL #2]\n" + "ld1w { z22.s }, p0/Z, [x24, x3, LSL #2]\n" + "ld1w { z21.s }, p0/Z, [x22, x3, LSL #2]\n" + "ld1w { z20.s }, p0/Z, [x21, x3, LSL #2]\n" + "ld1w { z26.s }, p0/Z, [x15, x3, LSL #2]\n" + "ld1w { z25.s }, p0/Z, [x12, x3, LSL #2]\n" + "ld1w { z24.s }, p0/Z, [x23, x3, LSL #2]\n" + "ld1w { z23.s }, p0/Z, [x20, x3, LSL #2]\n" "incw x3\n" "whilelt p1.s, x3, x5\n" "b.none 2f\n" @@ -206,4 +206,4 @@ void sme_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst_impl( } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) && defined(ARM_COMPUTE_ENABLE_SME) +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_avg_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_avg_generic_depthfirst.hpp index 814c89ca23..29bcfc5a3b 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_avg_generic_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_avg_generic_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Arm Limited. + * Copyright (c) 2022-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -26,6 +26,8 @@ #pragma once +#if defined(ARM_COMPUTE_ENABLE_SME) + namespace arm_conv { namespace pooling { @@ -40,3 +42,5 @@ struct sme_fp32_nhwc_avg_generic_depthfirst : IGenericDepthfirstStrategy<float, } // namespace pooling } // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_avg_generic_depthfirst/generic.cpp index 03ab9c0a9e..86e7f84542 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_avg_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_avg_generic_depthfirst/generic.cpp @@ -22,9 +22,10 @@ * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SME) - #include <cstdint> +#include <cstddef> + +#if defined(ARM_COMPUTE_ENABLE_SME) namespace arm_conv { namespace pooling { @@ -57,68 +58,68 @@ void sme_fp32_nhwc_avg_generic_depthfirst_impl( "lsr x25, %x[n_valid_cells], #0x2\n" "mov z5.b, #0x0\n" "mov z4.b, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "mov z3.b, #0x0\n" "mov z2.b, #0x0\n" "cbz x25, 4f\n" - "ldp x24, x23, [x20, #0x0]\n" + "ldp x23, x22, [x24, #0x0]\n" "subs x25, x25, #0x1\n" - "ld1w { z1.s }, p3/Z, [x24, x9, LSL #2]\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" - "ld1w { z0.s }, p3/Z, [x23, x9, LSL #2]\n" - "ld1w { z31.s }, p3/Z, [x22, x9, LSL #2]\n" - "ld1w { z30.s }, p3/Z, [x21, x9, LSL #2]\n" - "ld1w { z29.s }, p2/Z, [x24, x28, LSL #2]\n" - "ld1w { z22.s }, p2/Z, [x23, x28, LSL #2]\n" - "ld1w { z28.s }, p2/Z, [x22, x28, LSL #2]\n" - "ld1w { z18.s }, p2/Z, [x21, x28, LSL #2]\n" - "ld1w { z27.s }, p1/Z, [x24, x27, LSL #2]\n" - "ld1w { z21.s }, p1/Z, [x23, x27, LSL #2]\n" - "ld1w { z26.s }, p1/Z, [x22, x27, LSL #2]\n" - "ld1w { z17.s }, p1/Z, [x21, x27, LSL #2]\n" - "ld1w { z25.s }, p0/Z, [x24, x26, LSL #2]\n" - "ld1w { z20.s }, p0/Z, [x23, x26, LSL #2]\n" - "ld1w { z24.s }, p0/Z, [x22, x26, LSL #2]\n" - "ld1w { z16.s }, p0/Z, [x21, x26, LSL #2]\n" + "ld1w { z1.s }, p3/Z, [x23, x9, LSL #2]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "ld1w { z0.s }, p3/Z, [x22, x9, LSL #2]\n" + "ld1w { z31.s }, p3/Z, [x21, x9, LSL #2]\n" + "ld1w { z30.s }, p3/Z, [x20, x9, LSL #2]\n" + "ld1w { z29.s }, p2/Z, [x23, x28, LSL #2]\n" + "ld1w { z22.s }, p2/Z, [x22, x28, LSL #2]\n" + "ld1w { z28.s }, p2/Z, [x21, x28, LSL #2]\n" + "ld1w { z18.s }, p2/Z, [x20, x28, LSL #2]\n" + "ld1w { z27.s }, p1/Z, [x23, x27, LSL #2]\n" + "ld1w { z21.s }, p1/Z, [x22, x27, LSL #2]\n" + "ld1w { z26.s }, p1/Z, [x21, x27, LSL #2]\n" + "ld1w { z17.s }, p1/Z, [x20, x27, LSL #2]\n" + "ld1w { z25.s }, p0/Z, [x23, x26, LSL #2]\n" + "ld1w { z20.s }, p0/Z, [x22, x26, LSL #2]\n" + "ld1w { z24.s }, p0/Z, [x21, x26, LSL #2]\n" + "ld1w { z16.s }, p0/Z, [x20, x26, LSL #2]\n" "beq 3f\n" "2:" // 4-vectors of channels: 4 inputs loop "fadd z23.s, z1.s, z0.s\n" "fadd z19.s, z31.s, z30.s\n" - "ldp x24, x23, [x20, #0x0]\n" + "ldp x23, x22, [x24, #0x0]\n" "subs x25, x25, #0x1\n" "fadd z22.s, z29.s, z22.s\n" "fadd z18.s, z28.s, z18.s\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" "fadd z21.s, z27.s, z21.s\n" "fadd z17.s, z26.s, z17.s\n" - "ld1w { z1.s }, p3/Z, [x24, x9, LSL #2]\n" + "ld1w { z1.s }, p3/Z, [x23, x9, LSL #2]\n" "fadd z20.s, z25.s, z20.s\n" "fadd z16.s, z24.s, z16.s\n" - "ld1w { z0.s }, p3/Z, [x23, x9, LSL #2]\n" + "ld1w { z0.s }, p3/Z, [x22, x9, LSL #2]\n" "fadd z19.s, z23.s, z19.s\n" "fadd z18.s, z22.s, z18.s\n" - "ld1w { z31.s }, p3/Z, [x22, x9, LSL #2]\n" + "ld1w { z31.s }, p3/Z, [x21, x9, LSL #2]\n" "fadd z17.s, z21.s, z17.s\n" "fadd z16.s, z20.s, z16.s\n" - "ld1w { z30.s }, p3/Z, [x21, x9, LSL #2]\n" + "ld1w { z30.s }, p3/Z, [x20, x9, LSL #2]\n" "fadd z5.s, z5.s, z19.s\n" "fadd z4.s, z4.s, z18.s\n" - "ld1w { z29.s }, p2/Z, [x24, x28, LSL #2]\n" + "ld1w { z29.s }, p2/Z, [x23, x28, LSL #2]\n" "fadd z3.s, z3.s, z17.s\n" "fadd z2.s, z2.s, z16.s\n" - "ld1w { z22.s }, p2/Z, [x23, x28, LSL #2]\n" - "ld1w { z28.s }, p2/Z, [x22, x28, LSL #2]\n" - "ld1w { z18.s }, p2/Z, [x21, x28, LSL #2]\n" - "ld1w { z27.s }, p1/Z, [x24, x27, LSL #2]\n" - "ld1w { z21.s }, p1/Z, [x23, x27, LSL #2]\n" - "ld1w { z26.s }, p1/Z, [x22, x27, LSL #2]\n" - "ld1w { z17.s }, p1/Z, [x21, x27, LSL #2]\n" - "ld1w { z25.s }, p0/Z, [x24, x26, LSL #2]\n" - "ld1w { z20.s }, p0/Z, [x23, x26, LSL #2]\n" - "ld1w { z24.s }, p0/Z, [x22, x26, LSL #2]\n" - "ld1w { z16.s }, p0/Z, [x21, x26, LSL #2]\n" + "ld1w { z22.s }, p2/Z, [x22, x28, LSL #2]\n" + "ld1w { z28.s }, p2/Z, [x21, x28, LSL #2]\n" + "ld1w { z18.s }, p2/Z, [x20, x28, LSL #2]\n" + "ld1w { z27.s }, p1/Z, [x23, x27, LSL #2]\n" + "ld1w { z21.s }, p1/Z, [x22, x27, LSL #2]\n" + "ld1w { z26.s }, p1/Z, [x21, x27, LSL #2]\n" + "ld1w { z17.s }, p1/Z, [x20, x27, LSL #2]\n" + "ld1w { z25.s }, p0/Z, [x23, x26, LSL #2]\n" + "ld1w { z20.s }, p0/Z, [x22, x26, LSL #2]\n" + "ld1w { z24.s }, p0/Z, [x21, x26, LSL #2]\n" + "ld1w { z16.s }, p0/Z, [x20, x26, LSL #2]\n" "bgt 2b\n" "3:" // 4-vectors of channels: 4 inputs tail "fadd z23.s, z1.s, z0.s\n" @@ -141,16 +142,16 @@ void sme_fp32_nhwc_avg_generic_depthfirst_impl( "ands x21, %x[n_valid_cells], #0x3\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x24, [x20], #0x8\n" - "ld1w { z1.s }, p3/Z, [x24, x9, LSL #2]\n" + "ldr x20, [x24], #0x8\n" + "ld1w { z16.s }, p3/Z, [x20, x9, LSL #2]\n" "subs x21, x21, #0x1\n" - "fadd z5.s, z5.s, z1.s\n" - "ld1w { z29.s }, p2/Z, [x24, x28, LSL #2]\n" - "fadd z4.s, z4.s, z29.s\n" - "ld1w { z27.s }, p1/Z, [x24, x27, LSL #2]\n" - "fadd z3.s, z3.s, z27.s\n" - "ld1w { z25.s }, p0/Z, [x24, x26, LSL #2]\n" - "fadd z2.s, z2.s, z25.s\n" + "fadd z5.s, z5.s, z16.s\n" + "ld1w { z16.s }, p2/Z, [x20, x28, LSL #2]\n" + "fadd z4.s, z4.s, z16.s\n" + "ld1w { z16.s }, p1/Z, [x20, x27, LSL #2]\n" + "fadd z3.s, z3.s, z16.s\n" + "ld1w { z16.s }, p0/Z, [x20, x26, LSL #2]\n" + "fadd z2.s, z2.s, z16.s\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End "fmul z5.s, z5.s, z6.s\n" @@ -173,44 +174,44 @@ void sme_fp32_nhwc_avg_generic_depthfirst_impl( "8:" // Single vector of channels: Loop "lsr x25, %x[n_valid_cells], #0x2\n" "mov z5.b, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "cbz x25, 11f\n" - "ldp x24, x23, [x20, #0x0]\n" + "ldp x20, x22, [x24, #0x0]\n" "subs x25, x25, #0x1\n" - "ld1w { z1.s }, p3/Z, [x24, x9, LSL #2]\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" - "ld1w { z0.s }, p3/Z, [x23, x9, LSL #2]\n" - "ld1w { z31.s }, p3/Z, [x22, x9, LSL #2]\n" - "ld1w { z30.s }, p3/Z, [x21, x9, LSL #2]\n" + "ld1w { z1.s }, p3/Z, [x20, x9, LSL #2]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "ld1w { z0.s }, p3/Z, [x22, x9, LSL #2]\n" + "ld1w { z31.s }, p3/Z, [x21, x9, LSL #2]\n" + "ld1w { z30.s }, p3/Z, [x20, x9, LSL #2]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 4 inputs loop - "fadd z23.s, z1.s, z0.s\n" - "fadd z19.s, z31.s, z30.s\n" - "ldp x24, x23, [x20, #0x0]\n" + "fadd z17.s, z1.s, z0.s\n" + "fadd z16.s, z31.s, z30.s\n" + "ldp x23, x22, [x24, #0x0]\n" "subs x25, x25, #0x1\n" - "fadd z19.s, z23.s, z19.s\n" - "ldp x22, x21, [x20, #0x10]\n" - "fadd z5.s, z5.s, z19.s\n" - "add x20, x20, #0x20\n" - "ld1w { z1.s }, p3/Z, [x24, x9, LSL #2]\n" - "ld1w { z0.s }, p3/Z, [x23, x9, LSL #2]\n" - "ld1w { z31.s }, p3/Z, [x22, x9, LSL #2]\n" - "ld1w { z30.s }, p3/Z, [x21, x9, LSL #2]\n" + "fadd z16.s, z17.s, z16.s\n" + "ldp x21, x20, [x24, #0x10]\n" + "fadd z5.s, z5.s, z16.s\n" + "add x24, x24, #0x20\n" + "ld1w { z1.s }, p3/Z, [x23, x9, LSL #2]\n" + "ld1w { z0.s }, p3/Z, [x22, x9, LSL #2]\n" + "ld1w { z31.s }, p3/Z, [x21, x9, LSL #2]\n" + "ld1w { z30.s }, p3/Z, [x20, x9, LSL #2]\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 4 inputs tail - "fadd z23.s, z1.s, z0.s\n" - "fadd z19.s, z31.s, z30.s\n" - "fadd z19.s, z23.s, z19.s\n" - "fadd z5.s, z5.s, z19.s\n" + "fadd z17.s, z1.s, z0.s\n" + "fadd z16.s, z31.s, z30.s\n" + "fadd z16.s, z17.s, z16.s\n" + "fadd z5.s, z5.s, z16.s\n" "11:" // Single vector of channels: Loop: After loop "ands x21, %x[n_valid_cells], #0x3\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x24, [x20], #0x8\n" - "ld1w { z1.s }, p3/Z, [x24, x9, LSL #2]\n" + "ldr x20, [x24], #0x8\n" + "ld1w { z16.s }, p3/Z, [x20, x9, LSL #2]\n" "subs x21, x21, #0x1\n" - "fadd z5.s, z5.s, z1.s\n" + "fadd z5.s, z5.s, z16.s\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End "fmul z5.s, z5.s, z6.s\n" diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_max_2x2_s1_output2x2_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_max_2x2_s1_output2x2_depthfirst.hpp index 4e3cd6e228..338348231f 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_max_2x2_s1_output2x2_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_max_2x2_s1_output2x2_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Arm Limited. + * Copyright (c) 2022-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -24,6 +24,8 @@ #pragma once +#if defined(ARM_COMPUTE_ENABLE_SME) + namespace arm_conv { namespace pooling { @@ -45,3 +47,5 @@ struct sme_fp32_nhwc_max_2x2_s1_output2x2_depthfirst : public DepthfirstStrategy } // namespace pooling } // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp index 05edac6623..3c7213a498 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp @@ -26,7 +26,7 @@ #include <cstddef> #include <cstdint> -#if defined(__ARM_FEATURE_SVE) && defined(ARM_COMPUTE_ENABLE_SME) +#if defined(ARM_COMPUTE_ENABLE_SME) namespace arm_conv { namespace pooling { @@ -70,23 +70,23 @@ void sme_fp32_nhwc_max_2x2_s1_output2x2_depthfirst_impl( "ldr x20, [%x[args], %[offsetof_inptrs]]\n" "mov x14, #0x0\n" "ldr x13, [%x[args], %[offsetof_n_channels]]\n" - "whilelt p1.s, x15, x13\n" + "whilelt p0.s, x15, x13\n" "ldp x12, x11, [x21, #0x0]\n" "ldp x10, x9, [x21, #0x10]\n" "ldp x28, x27, [x20, #0x0]\n" - "ld1w { z30.s }, p1/Z, [x27, x15, LSL #2]\n" + "ld1w { z30.s }, p0/Z, [x27, x15, LSL #2]\n" "ldp x26, x25, [x20, #0x10]\n" - "ld1w { z29.s }, p1/Z, [x25, x15, LSL #2]\n" + "ld1w { z29.s }, p0/Z, [x25, x15, LSL #2]\n" "ldp x24, x23, [x20, #0x20]\n" - "ld1w { z28.s }, p1/Z, [x24, x15, LSL #2]\n" + "ld1w { z28.s }, p0/Z, [x24, x15, LSL #2]\n" "ldp x22, x21, [x20, #0x30]\n" - "ld1w { z27.s }, p1/Z, [x21, x15, LSL #2]\n" + "ld1w { z27.s }, p0/Z, [x21, x15, LSL #2]\n" "ldr x20, [x20, #0x40]\n" - "ld1w { z26.s }, p1/Z, [x28, x15, LSL #2]\n" - "ld1w { z25.s }, p1/Z, [x26, x15, LSL #2]\n" - "ld1w { z24.s }, p1/Z, [x23, x15, LSL #2]\n" - "ld1w { z23.s }, p1/Z, [x22, x15, LSL #2]\n" - "ld1w { z19.s }, p1/Z, [x20, x15, LSL #2]\n" + "ld1w { z26.s }, p0/Z, [x28, x15, LSL #2]\n" + "ld1w { z25.s }, p0/Z, [x26, x15, LSL #2]\n" + "ld1w { z24.s }, p0/Z, [x23, x15, LSL #2]\n" + "ld1w { z19.s }, p0/Z, [x22, x15, LSL #2]\n" + "ld1w { z23.s }, p0/Z, [x20, x15, LSL #2]\n" "incw x15\n" "whilelt p1.s, x15, x13\n" "b.none 2f\n" @@ -95,25 +95,25 @@ void sme_fp32_nhwc_max_2x2_s1_output2x2_depthfirst_impl( "movprfx z21, z28\n fmax z21.s, p2/M, z21.s, z27.s\n" "ld1w { z30.s }, p1/Z, [x27, x15, LSL #2]\n" "whilelt p0.s, x14, x13\n" - "movprfx z20, z29\n fmax z20.s, p2/M, z20.s, z26.s\n" - "movprfx z18, z25\n fmax z18.s, p2/M, z18.s, z24.s\n" + "movprfx z18, z29\n fmax z18.s, p2/M, z18.s, z26.s\n" + "movprfx z17, z25\n fmax z17.s, p2/M, z17.s, z24.s\n" "ld1w { z28.s }, p1/Z, [x24, x15, LSL #2]\n" - "movprfx z17, z29\n fmax z17.s, p2/M, z17.s, z23.s\n" - "movprfx z16, z24\n fmax z16.s, p2/M, z16.s, z19.s\n" + "movprfx z16, z29\n fmax z16.s, p2/M, z16.s, z19.s\n" + "movprfx z20, z24\n fmax z20.s, p2/M, z20.s, z23.s\n" "ld1w { z27.s }, p1/Z, [x21, x15, LSL #2]\n" "ld1w { z29.s }, p1/Z, [x25, x15, LSL #2]\n" - "movprfx z19, z22\n fmax z19.s, p2/M, z19.s, z20.s\n" - "fmax z18.s, p2/M, z18.s, z22.s\n" + "movprfx z19, z22\n fmax z19.s, p2/M, z19.s, z18.s\n" + "movprfx z18, z17\n fmax z18.s, p2/M, z18.s, z22.s\n" "ld1w { z26.s }, p1/Z, [x28, x15, LSL #2]\n" - "fmax z17.s, p2/M, z17.s, z21.s\n" - "fmax z16.s, p2/M, z16.s, z21.s\n" + "movprfx z17, z16\n fmax z17.s, p2/M, z17.s, z21.s\n" + "movprfx z16, z21\n fmax z16.s, p2/M, z16.s, z20.s\n" "ld1w { z25.s }, p1/Z, [x26, x15, LSL #2]\n" "st1w { z19.s }, p0, [x12, x14, LSL #2]\n" "ld1w { z24.s }, p1/Z, [x23, x15, LSL #2]\n" "st1w { z18.s }, p0, [x11, x14, LSL #2]\n" - "ld1w { z23.s }, p1/Z, [x22, x15, LSL #2]\n" + "ld1w { z19.s }, p1/Z, [x22, x15, LSL #2]\n" "st1w { z17.s }, p0, [x10, x14, LSL #2]\n" - "ld1w { z19.s }, p1/Z, [x20, x15, LSL #2]\n" + "ld1w { z23.s }, p1/Z, [x20, x15, LSL #2]\n" "incw x15\n" "whilelt p1.s, x15, x13\n" "st1w { z16.s }, p0, [x9, x14, LSL #2]\n" @@ -125,13 +125,13 @@ void sme_fp32_nhwc_max_2x2_s1_output2x2_depthfirst_impl( "whilelt p0.s, x14, x13\n" "movprfx z20, z29\n fmax z20.s, p2/M, z20.s, z26.s\n" "movprfx z18, z25\n fmax z18.s, p2/M, z18.s, z24.s\n" - "movprfx z17, z29\n fmax z17.s, p2/M, z17.s, z23.s\n" - "movprfx z16, z24\n fmax z16.s, p2/M, z16.s, z19.s\n" - "movprfx z19, z22\n fmax z19.s, p2/M, z19.s, z20.s\n" + "movprfx z17, z29\n fmax z17.s, p2/M, z17.s, z19.s\n" + "movprfx z19, z24\n fmax z19.s, p2/M, z19.s, z23.s\n" + "movprfx z16, z22\n fmax z16.s, p2/M, z16.s, z20.s\n" "fmax z18.s, p2/M, z18.s, z22.s\n" - "st1w { z19.s }, p0, [x12, x14, LSL #2]\n" + "st1w { z16.s }, p0, [x12, x14, LSL #2]\n" "fmax z17.s, p2/M, z17.s, z21.s\n" - "fmax z16.s, p2/M, z16.s, z21.s\n" + "movprfx z16, z21\n fmax z16.s, p2/M, z16.s, z19.s\n" "st1w { z18.s }, p0, [x11, x14, LSL #2]\n" "st1w { z17.s }, p0, [x10, x14, LSL #2]\n" "st1w { z16.s }, p0, [x9, x14, LSL #2]\n" @@ -145,4 +145,4 @@ void sme_fp32_nhwc_max_2x2_s1_output2x2_depthfirst_impl( } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) && defined(ARM_COMPUTE_ENABLE_SME) +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_max_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_max_generic_depthfirst.hpp index 0c0e445c7a..9bc1f11601 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_max_generic_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_max_generic_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Arm Limited. + * Copyright (c) 2022-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -26,6 +26,8 @@ #pragma once +#if defined(ARM_COMPUTE_ENABLE_SME) + namespace arm_conv { namespace pooling { @@ -40,3 +42,5 @@ struct sme_fp32_nhwc_max_generic_depthfirst : IGenericDepthfirstStrategy<float, } // namespace pooling } // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_max_generic_depthfirst/generic.cpp index 14c07724a1..0dabc2f292 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_max_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_max_generic_depthfirst/generic.cpp @@ -22,9 +22,10 @@ * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SME) - #include <cstdint> +#include <cstddef> + +#if defined(ARM_COMPUTE_ENABLE_SME) namespace arm_conv { namespace pooling { @@ -54,68 +55,68 @@ void sme_fp32_nhwc_max_generic_depthfirst_impl( "lsr x25, %x[n_valid_cells], #0x2\n" "mov z4.s, #0xff800000\n" "mov z3.s, #0xff800000\n" - "mov x20, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "mov z2.s, #0xff800000\n" "mov z1.s, #0xff800000\n" "cbz x25, 4f\n" - "ldp x24, x23, [x20, #0x0]\n" + "ldp x23, x22, [x24, #0x0]\n" "subs x25, x25, #0x1\n" - "ld1w { z0.s }, p4/Z, [x24, x9, LSL #2]\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" - "ld1w { z31.s }, p4/Z, [x23, x9, LSL #2]\n" - "ld1w { z23.s }, p4/Z, [x22, x9, LSL #2]\n" - "ld1w { z30.s }, p4/Z, [x21, x9, LSL #2]\n" - "ld1w { z18.s }, p3/Z, [x24, x28, LSL #2]\n" - "ld1w { z29.s }, p3/Z, [x23, x28, LSL #2]\n" - "ld1w { z22.s }, p3/Z, [x22, x28, LSL #2]\n" - "ld1w { z28.s }, p3/Z, [x21, x28, LSL #2]\n" - "ld1w { z17.s }, p2/Z, [x24, x27, LSL #2]\n" - "ld1w { z27.s }, p2/Z, [x23, x27, LSL #2]\n" - "ld1w { z21.s }, p2/Z, [x22, x27, LSL #2]\n" - "ld1w { z26.s }, p2/Z, [x21, x27, LSL #2]\n" - "ld1w { z16.s }, p1/Z, [x24, x26, LSL #2]\n" - "ld1w { z25.s }, p1/Z, [x23, x26, LSL #2]\n" - "ld1w { z20.s }, p1/Z, [x22, x26, LSL #2]\n" - "ld1w { z24.s }, p1/Z, [x21, x26, LSL #2]\n" + "ld1w { z0.s }, p4/Z, [x23, x9, LSL #2]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "ld1w { z31.s }, p4/Z, [x22, x9, LSL #2]\n" + "ld1w { z23.s }, p4/Z, [x21, x9, LSL #2]\n" + "ld1w { z30.s }, p4/Z, [x20, x9, LSL #2]\n" + "ld1w { z18.s }, p3/Z, [x23, x28, LSL #2]\n" + "ld1w { z29.s }, p3/Z, [x22, x28, LSL #2]\n" + "ld1w { z22.s }, p3/Z, [x21, x28, LSL #2]\n" + "ld1w { z28.s }, p3/Z, [x20, x28, LSL #2]\n" + "ld1w { z17.s }, p2/Z, [x23, x27, LSL #2]\n" + "ld1w { z27.s }, p2/Z, [x22, x27, LSL #2]\n" + "ld1w { z21.s }, p2/Z, [x21, x27, LSL #2]\n" + "ld1w { z26.s }, p2/Z, [x20, x27, LSL #2]\n" + "ld1w { z16.s }, p1/Z, [x23, x26, LSL #2]\n" + "ld1w { z25.s }, p1/Z, [x22, x26, LSL #2]\n" + "ld1w { z20.s }, p1/Z, [x21, x26, LSL #2]\n" + "ld1w { z24.s }, p1/Z, [x20, x26, LSL #2]\n" "beq 3f\n" "2:" // 4-vectors of channels: 4 inputs loop "movprfx z19, z0\n fmax z19.s, p0/M, z19.s, z31.s\n" "fmax z23.s, p0/M, z23.s, z30.s\n" - "ldp x24, x23, [x20, #0x0]\n" + "ldp x23, x22, [x24, #0x0]\n" "subs x25, x25, #0x1\n" "fmax z18.s, p0/M, z18.s, z29.s\n" "fmax z22.s, p0/M, z22.s, z28.s\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" "fmax z17.s, p0/M, z17.s, z27.s\n" "fmax z21.s, p0/M, z21.s, z26.s\n" - "ld1w { z0.s }, p4/Z, [x24, x9, LSL #2]\n" + "ld1w { z0.s }, p4/Z, [x23, x9, LSL #2]\n" "fmax z16.s, p0/M, z16.s, z25.s\n" "fmax z20.s, p0/M, z20.s, z24.s\n" - "ld1w { z31.s }, p4/Z, [x23, x9, LSL #2]\n" + "ld1w { z31.s }, p4/Z, [x22, x9, LSL #2]\n" "fmax z19.s, p0/M, z19.s, z23.s\n" "fmax z18.s, p0/M, z18.s, z22.s\n" - "ld1w { z23.s }, p4/Z, [x22, x9, LSL #2]\n" + "ld1w { z23.s }, p4/Z, [x21, x9, LSL #2]\n" "fmax z17.s, p0/M, z17.s, z21.s\n" "fmax z16.s, p0/M, z16.s, z20.s\n" - "ld1w { z30.s }, p4/Z, [x21, x9, LSL #2]\n" + "ld1w { z30.s }, p4/Z, [x20, x9, LSL #2]\n" "fmax z4.s, p0/M, z4.s, z19.s\n" "fmax z3.s, p0/M, z3.s, z18.s\n" - "ld1w { z18.s }, p3/Z, [x24, x28, LSL #2]\n" + "ld1w { z18.s }, p3/Z, [x23, x28, LSL #2]\n" "fmax z2.s, p0/M, z2.s, z17.s\n" "fmax z1.s, p0/M, z1.s, z16.s\n" - "ld1w { z29.s }, p3/Z, [x23, x28, LSL #2]\n" - "ld1w { z22.s }, p3/Z, [x22, x28, LSL #2]\n" - "ld1w { z28.s }, p3/Z, [x21, x28, LSL #2]\n" - "ld1w { z17.s }, p2/Z, [x24, x27, LSL #2]\n" - "ld1w { z27.s }, p2/Z, [x23, x27, LSL #2]\n" - "ld1w { z21.s }, p2/Z, [x22, x27, LSL #2]\n" - "ld1w { z26.s }, p2/Z, [x21, x27, LSL #2]\n" - "ld1w { z16.s }, p1/Z, [x24, x26, LSL #2]\n" - "ld1w { z25.s }, p1/Z, [x23, x26, LSL #2]\n" - "ld1w { z20.s }, p1/Z, [x22, x26, LSL #2]\n" - "ld1w { z24.s }, p1/Z, [x21, x26, LSL #2]\n" + "ld1w { z29.s }, p3/Z, [x22, x28, LSL #2]\n" + "ld1w { z22.s }, p3/Z, [x21, x28, LSL #2]\n" + "ld1w { z28.s }, p3/Z, [x20, x28, LSL #2]\n" + "ld1w { z17.s }, p2/Z, [x23, x27, LSL #2]\n" + "ld1w { z27.s }, p2/Z, [x22, x27, LSL #2]\n" + "ld1w { z21.s }, p2/Z, [x21, x27, LSL #2]\n" + "ld1w { z26.s }, p2/Z, [x20, x27, LSL #2]\n" + "ld1w { z16.s }, p1/Z, [x23, x26, LSL #2]\n" + "ld1w { z25.s }, p1/Z, [x22, x26, LSL #2]\n" + "ld1w { z20.s }, p1/Z, [x21, x26, LSL #2]\n" + "ld1w { z24.s }, p1/Z, [x20, x26, LSL #2]\n" "bgt 2b\n" "3:" // 4-vectors of channels: 4 inputs tail "movprfx z19, z0\n fmax z19.s, p0/M, z19.s, z31.s\n" @@ -138,15 +139,15 @@ void sme_fp32_nhwc_max_generic_depthfirst_impl( "ands x21, %x[n_valid_cells], #0x3\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x24, [x20], #0x8\n" - "ld1w { z0.s }, p4/Z, [x24, x9, LSL #2]\n" + "ldr x20, [x24], #0x8\n" + "ld1w { z16.s }, p4/Z, [x20, x9, LSL #2]\n" "subs x21, x21, #0x1\n" - "fmax z4.s, p0/M, z4.s, z0.s\n" - "ld1w { z18.s }, p3/Z, [x24, x28, LSL #2]\n" - "fmax z3.s, p0/M, z3.s, z18.s\n" - "ld1w { z17.s }, p2/Z, [x24, x27, LSL #2]\n" - "fmax z2.s, p0/M, z2.s, z17.s\n" - "ld1w { z16.s }, p1/Z, [x24, x26, LSL #2]\n" + "fmax z4.s, p0/M, z4.s, z16.s\n" + "ld1w { z16.s }, p3/Z, [x20, x28, LSL #2]\n" + "fmax z3.s, p0/M, z3.s, z16.s\n" + "ld1w { z16.s }, p2/Z, [x20, x27, LSL #2]\n" + "fmax z2.s, p0/M, z2.s, z16.s\n" + "ld1w { z16.s }, p1/Z, [x20, x26, LSL #2]\n" "fmax z1.s, p0/M, z1.s, z16.s\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End @@ -166,44 +167,44 @@ void sme_fp32_nhwc_max_generic_depthfirst_impl( "8:" // Single vector of channels: Loop "lsr x25, %x[n_valid_cells], #0x2\n" "mov z4.s, #0xff800000\n" - "mov x20, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "cbz x25, 11f\n" - "ldp x24, x23, [x20, #0x0]\n" + "ldp x20, x22, [x24, #0x0]\n" "subs x25, x25, #0x1\n" - "ld1w { z0.s }, p4/Z, [x24, x9, LSL #2]\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" - "ld1w { z31.s }, p4/Z, [x23, x9, LSL #2]\n" - "ld1w { z23.s }, p4/Z, [x22, x9, LSL #2]\n" - "ld1w { z30.s }, p4/Z, [x21, x9, LSL #2]\n" + "ld1w { z0.s }, p4/Z, [x20, x9, LSL #2]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "ld1w { z31.s }, p4/Z, [x22, x9, LSL #2]\n" + "ld1w { z23.s }, p4/Z, [x21, x9, LSL #2]\n" + "ld1w { z30.s }, p4/Z, [x20, x9, LSL #2]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 4 inputs loop - "movprfx z19, z0\n fmax z19.s, p0/M, z19.s, z31.s\n" - "fmax z23.s, p0/M, z23.s, z30.s\n" - "ldp x24, x23, [x20, #0x0]\n" + "movprfx z16, z0\n fmax z16.s, p0/M, z16.s, z31.s\n" + "movprfx z17, z23\n fmax z17.s, p0/M, z17.s, z30.s\n" + "ldp x23, x22, [x24, #0x0]\n" "subs x25, x25, #0x1\n" - "fmax z19.s, p0/M, z19.s, z23.s\n" - "ldp x22, x21, [x20, #0x10]\n" - "fmax z4.s, p0/M, z4.s, z19.s\n" - "add x20, x20, #0x20\n" - "ld1w { z0.s }, p4/Z, [x24, x9, LSL #2]\n" - "ld1w { z31.s }, p4/Z, [x23, x9, LSL #2]\n" - "ld1w { z23.s }, p4/Z, [x22, x9, LSL #2]\n" - "ld1w { z30.s }, p4/Z, [x21, x9, LSL #2]\n" + "fmax z16.s, p0/M, z16.s, z17.s\n" + "ldp x21, x20, [x24, #0x10]\n" + "fmax z4.s, p0/M, z4.s, z16.s\n" + "add x24, x24, #0x20\n" + "ld1w { z0.s }, p4/Z, [x23, x9, LSL #2]\n" + "ld1w { z31.s }, p4/Z, [x22, x9, LSL #2]\n" + "ld1w { z23.s }, p4/Z, [x21, x9, LSL #2]\n" + "ld1w { z30.s }, p4/Z, [x20, x9, LSL #2]\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 4 inputs tail - "movprfx z19, z0\n fmax z19.s, p0/M, z19.s, z31.s\n" - "fmax z23.s, p0/M, z23.s, z30.s\n" - "fmax z19.s, p0/M, z19.s, z23.s\n" - "fmax z4.s, p0/M, z4.s, z19.s\n" + "movprfx z16, z0\n fmax z16.s, p0/M, z16.s, z31.s\n" + "movprfx z17, z23\n fmax z17.s, p0/M, z17.s, z30.s\n" + "fmax z16.s, p0/M, z16.s, z17.s\n" + "fmax z4.s, p0/M, z4.s, z16.s\n" "11:" // Single vector of channels: Loop: After loop "ands x21, %x[n_valid_cells], #0x3\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x24, [x20], #0x8\n" - "ld1w { z0.s }, p4/Z, [x24, x9, LSL #2]\n" + "ldr x20, [x24], #0x8\n" + "ld1w { z16.s }, p4/Z, [x20, x9, LSL #2]\n" "subs x21, x21, #0x1\n" - "fmax z4.s, p0/M, z4.s, z0.s\n" + "fmax z4.s, p0/M, z4.s, z16.s\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End "st1w { z4.s }, p4, [%x[outptr], x9, LSL #2]\n" diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_avg_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_avg_generic_depthfirst.hpp index e383a4c3bd..318510e697 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_avg_generic_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_avg_generic_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Arm Limited. + * Copyright (c) 2022-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -26,6 +26,8 @@ #pragma once +#if defined(ARM_COMPUTE_ENABLE_SME) + namespace arm_conv { namespace pooling { @@ -40,3 +42,5 @@ struct sme_s8_nhwc_avg_generic_depthfirst : IGenericDepthfirstStrategy<int8_t, i } // namespace pooling } // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_avg_generic_depthfirst/generic.cpp index ded1274c13..c24e977dc6 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_avg_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_avg_generic_depthfirst/generic.cpp @@ -22,13 +22,14 @@ * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SME) - #include <cstdint> +#include <cstddef> #include <cstring> #include <cmath> +#if defined(ARM_COMPUTE_ENABLE_SME) + namespace arm_conv { namespace pooling { @@ -109,7 +110,7 @@ void sme_s8_nhwc_avg_generic_depthfirst_impl( "lsr x23, %x[n_valid_cells], #0x1\n" "mov z15.s, #0x0\n" "mov z14.s, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "mov z13.s, #0x0\n" "mov z12.s, #0x0\n" "mov z11.s, #0x0\n" @@ -125,48 +126,48 @@ void sme_s8_nhwc_avg_generic_depthfirst_impl( "mov z1.s, #0x0\n" "mov z0.s, #0x0\n" "cbz x23, 4f\n" - "ldp x22, x21, [x20, #0x0]\n" + "ldp x21, x20, [x22, #0x0]\n" "subs x23, x23, #0x1\n" - "add x20, x20, #0x10\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" - "ld1b { z30.b }, p4/Z, [x21, x27]\n" - "ld1b { z29.b }, p3/Z, [x22, x26]\n" - "ld1b { z28.b }, p3/Z, [x21, x26]\n" - "ld1b { z27.b }, p2/Z, [x22, x25]\n" - "ld1b { z26.b }, p2/Z, [x21, x25]\n" - "ld1b { z25.b }, p1/Z, [x22, x24]\n" - "ld1b { z24.b }, p1/Z, [x21, x24]\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" + "ld1b { z29.b }, p3/Z, [x21, x26]\n" + "ld1b { z28.b }, p3/Z, [x20, x26]\n" + "ld1b { z27.b }, p2/Z, [x21, x25]\n" + "ld1b { z26.b }, p2/Z, [x20, x25]\n" + "ld1b { z25.b }, p1/Z, [x21, x24]\n" + "ld1b { z24.b }, p1/Z, [x20, x24]\n" "beq 3f\n" "2:" // 4-vectors of channels: 2 inputs loop ".inst 0x455e03f7 // saddlb z23.h, z31.b, z30.b\n" ".inst 0x455e07f6 // saddlt z22.h, z31.b, z30.b\n" - "ldp x22, x21, [x20, #0x0]\n" + "ldp x21, x20, [x22, #0x0]\n" "subs x23, x23, #0x1\n" ".inst 0x455c03b5 // saddlb z21.h, z29.b, z28.b\n" ".inst 0x455c07b4 // saddlt z20.h, z29.b, z28.b\n" - "add x20, x20, #0x10\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" ".inst 0x455a0373 // saddlb z19.h, z27.b, z26.b\n" ".inst 0x455a0772 // saddlt z18.h, z27.b, z26.b\n" - "ld1b { z30.b }, p4/Z, [x21, x27]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" ".inst 0x45580331 // saddlb z17.h, z25.b, z24.b\n" ".inst 0x45580730 // saddlt z16.h, z25.b, z24.b\n" - "ld1b { z29.b }, p3/Z, [x22, x26]\n" + "ld1b { z29.b }, p3/Z, [x21, x26]\n" ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" - "ld1b { z28.b }, p3/Z, [x21, x26]\n" + "ld1b { z28.b }, p3/Z, [x20, x26]\n" ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" - "ld1b { z27.b }, p2/Z, [x22, x25]\n" + "ld1b { z27.b }, p2/Z, [x21, x25]\n" ".inst 0x4595416b // saddwb z11.s, z11.s, z21.h\n" ".inst 0x4595454a // saddwt z10.s, z10.s, z21.h\n" - "ld1b { z26.b }, p2/Z, [x21, x25]\n" + "ld1b { z26.b }, p2/Z, [x20, x25]\n" ".inst 0x45944129 // saddwb z9.s, z9.s, z20.h\n" ".inst 0x45944508 // saddwt z8.s, z8.s, z20.h\n" - "ld1b { z25.b }, p1/Z, [x22, x24]\n" + "ld1b { z25.b }, p1/Z, [x21, x24]\n" ".inst 0x459340e7 // saddwb z7.s, z7.s, z19.h\n" ".inst 0x459344c6 // saddwt z6.s, z6.s, z19.h\n" - "ld1b { z24.b }, p1/Z, [x21, x24]\n" + "ld1b { z24.b }, p1/Z, [x20, x24]\n" ".inst 0x459240a5 // saddwb z5.s, z5.s, z18.h\n" ".inst 0x45924484 // saddwt z4.s, z4.s, z18.h\n" ".inst 0x45914063 // saddwb z3.s, z3.s, z17.h\n" @@ -203,20 +204,20 @@ void sme_s8_nhwc_avg_generic_depthfirst_impl( "ands x21, %x[n_valid_cells], #0x1\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x22, [x20], #0x8\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" - ".inst 0x4508a3f7 // sshllb z23.h, z31.b, #0x0\n" - ".inst 0x4508a7f6 // sshllt z22.h, z31.b, #0x0\n" - "ld1b { z29.b }, p3/Z, [x22, x26]\n" - ".inst 0x4508a3b5 // sshllb z21.h, z29.b, #0x0\n" - ".inst 0x4508a7b4 // sshllt z20.h, z29.b, #0x0\n" + "ldr x20, [x22], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x27]\n" + ".inst 0x4508a217 // sshllb z23.h, z16.b, #0x0\n" + ".inst 0x4508a616 // sshllt z22.h, z16.b, #0x0\n" + "ld1b { z16.b }, p3/Z, [x20, x26]\n" + ".inst 0x4508a215 // sshllb z21.h, z16.b, #0x0\n" + ".inst 0x4508a614 // sshllt z20.h, z16.b, #0x0\n" "subs x21, x21, #0x1\n" - "ld1b { z27.b }, p2/Z, [x22, x25]\n" - ".inst 0x4508a373 // sshllb z19.h, z27.b, #0x0\n" - ".inst 0x4508a772 // sshllt z18.h, z27.b, #0x0\n" - "ld1b { z25.b }, p1/Z, [x22, x24]\n" - ".inst 0x4508a331 // sshllb z17.h, z25.b, #0x0\n" - ".inst 0x4508a730 // sshllt z16.h, z25.b, #0x0\n" + "ld1b { z16.b }, p2/Z, [x20, x25]\n" + ".inst 0x4508a213 // sshllb z19.h, z16.b, #0x0\n" + ".inst 0x4508a612 // sshllt z18.h, z16.b, #0x0\n" + "ld1b { z16.b }, p1/Z, [x20, x24]\n" + ".inst 0x4508a211 // sshllb z17.h, z16.b, #0x0\n" + ".inst 0x4508a610 // sshllt z16.h, z16.b, #0x0\n" ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" @@ -332,74 +333,74 @@ void sme_s8_nhwc_avg_generic_depthfirst_impl( "lsr x23, %x[n_valid_cells], #0x1\n" "mov z15.s, #0x0\n" "mov z14.s, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "mov z13.s, #0x0\n" "mov z12.s, #0x0\n" "cbz x23, 11f\n" - "ldp x22, x21, [x20, #0x0]\n" + "ldp x21, x20, [x22, #0x0]\n" "subs x23, x23, #0x1\n" - "add x20, x20, #0x10\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" - "ld1b { z30.b }, p4/Z, [x21, x27]\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 2 inputs loop - ".inst 0x455e03f7 // saddlb z23.h, z31.b, z30.b\n" - ".inst 0x455e07f6 // saddlt z22.h, z31.b, z30.b\n" - "ldp x22, x21, [x20, #0x0]\n" + ".inst 0x455e03f1 // saddlb z17.h, z31.b, z30.b\n" + ".inst 0x455e07f0 // saddlt z16.h, z31.b, z30.b\n" + "ldp x21, x20, [x22, #0x0]\n" "subs x23, x23, #0x1\n" - ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" - ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" - "add x20, x20, #0x10\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" - ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" - ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" - "ld1b { z30.b }, p4/Z, [x21, x27]\n" + ".inst 0x459141ef // saddwb z15.s, z15.s, z17.h\n" + ".inst 0x459145ce // saddwt z14.s, z14.s, z17.h\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + ".inst 0x459041ad // saddwb z13.s, z13.s, z16.h\n" + ".inst 0x4590458c // saddwt z12.s, z12.s, z16.h\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 2 inputs tail - ".inst 0x455e03f7 // saddlb z23.h, z31.b, z30.b\n" - ".inst 0x455e07f6 // saddlt z22.h, z31.b, z30.b\n" - ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" - ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" - ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" - ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" + ".inst 0x455e03f1 // saddlb z17.h, z31.b, z30.b\n" + ".inst 0x455e07f0 // saddlt z16.h, z31.b, z30.b\n" + ".inst 0x459141ef // saddwb z15.s, z15.s, z17.h\n" + ".inst 0x459145ce // saddwt z14.s, z14.s, z17.h\n" + ".inst 0x459041ad // saddwb z13.s, z13.s, z16.h\n" + ".inst 0x4590458c // saddwt z12.s, z12.s, z16.h\n" "11:" // Single vector of channels: Loop: After loop "ands x21, %x[n_valid_cells], #0x1\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x22, [x20], #0x8\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" - ".inst 0x4508a3f7 // sshllb z23.h, z31.b, #0x0\n" - ".inst 0x4508a7f6 // sshllt z22.h, z31.b, #0x0\n" + "ldr x20, [x22], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x27]\n" + ".inst 0x4508a211 // sshllb z17.h, z16.b, #0x0\n" + ".inst 0x4508a610 // sshllt z16.h, z16.b, #0x0\n" "subs x21, x21, #0x1\n" - ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" - ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" - ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" - ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" + ".inst 0x459141ef // saddwb z15.s, z15.s, z17.h\n" + ".inst 0x459145ce // saddwt z14.s, z14.s, z17.h\n" + ".inst 0x459041ad // saddwb z13.s, z13.s, z16.h\n" + ".inst 0x4590458c // saddwt z12.s, z12.s, z16.h\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End - "ld1rw { z17.s }, p0/Z, [%x[rescale_ptr]]\n" - ".inst 0x04b175ef // sqdmulh z15.s, z15.s, z17.s\n" - ".inst 0x04b175ce // sqdmulh z14.s, z14.s, z17.s\n" - ".inst 0x04b175ad // sqdmulh z13.s, z13.s, z17.s\n" - ".inst 0x04b1758c // sqdmulh z12.s, z12.s, z17.s\n" + "ld1rw { z16.s }, p0/Z, [%x[rescale_ptr]]\n" + ".inst 0x04b075ef // sqdmulh z15.s, z15.s, z16.s\n" + ".inst 0x04b075ce // sqdmulh z14.s, z14.s, z16.s\n" + ".inst 0x04b075ad // sqdmulh z13.s, z13.s, z16.s\n" + ".inst 0x04b0758c // sqdmulh z12.s, z12.s, z16.s\n" "ld1rw { z16.s }, p0/Z, [%x[shift_ptr]]\n" - "mov z19.s, #0x7f\n" + "mov z18.s, #0x7f\n" ".inst 0x4482820f // srshl z15.s, p0/M, z15.s, z16.s\n" ".inst 0x4482820e // srshl z14.s, p0/M, z14.s, z16.s\n" ".inst 0x4482820d // srshl z13.s, p0/M, z13.s, z16.s\n" ".inst 0x4482820c // srshl z12.s, p0/M, z12.s, z16.s\n" - "not z16.s, p0/M, z19.s\n" + "not z16.s, p0/M, z18.s\n" "smax z15.s, p0/M, z15.s, z16.s\n" "smax z14.s, p0/M, z14.s, z16.s\n" "smax z13.s, p0/M, z13.s, z16.s\n" "smax z12.s, p0/M, z12.s, z16.s\n" - "smin z15.s, p0/M, z15.s, z19.s\n" - "smin z14.s, p0/M, z14.s, z19.s\n" - "trn1 z23.h, z15.h, z14.h\n" - "smin z13.s, p0/M, z13.s, z19.s\n" - "smin z12.s, p0/M, z12.s, z19.s\n" + "smin z15.s, p0/M, z15.s, z18.s\n" + "smin z14.s, p0/M, z14.s, z18.s\n" + "trn1 z17.h, z15.h, z14.h\n" + "smin z13.s, p0/M, z13.s, z18.s\n" + "smin z12.s, p0/M, z12.s, z18.s\n" "trn1 z16.h, z13.h, z12.h\n" - "trn1 z16.b, z23.b, z16.b\n" + "trn1 z16.b, z17.b, z16.b\n" "st1b { z16.b }, p4, [%x[outptr], x27]\n" "incb x27\n" "whilelt p4.b, x27, %x[n_channels]\n" diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp index 1613970618..c9a80e6a5b 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Arm Limited. + * Copyright (c) 2022-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -24,6 +24,8 @@ #pragma once +#if defined(ARM_COMPUTE_ENABLE_SME) + namespace arm_conv { namespace pooling { @@ -45,3 +47,5 @@ struct sme_s8_nhwc_max_2x2_s1_output2x2_depthfirst : public DepthfirstStrategy<i } // namespace pooling } // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp index e3b9c98d80..96617566a8 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp @@ -26,7 +26,7 @@ #include <cstddef> #include <cstdint> -#if defined(__ARM_FEATURE_SVE) && defined(ARM_COMPUTE_ENABLE_SME) +#if defined(ARM_COMPUTE_ENABLE_SME) namespace arm_conv { namespace pooling { @@ -70,23 +70,23 @@ void sme_s8_nhwc_max_2x2_s1_output2x2_depthfirst_impl( "ldr x20, [%x[args], %[offsetof_inptrs]]\n" "mov x14, #0x0\n" "ldr x13, [%x[args], %[offsetof_n_channels]]\n" - "whilelt p1.b, x15, x13\n" + "whilelt p0.b, x15, x13\n" "ldp x12, x11, [x21, #0x0]\n" "ldp x10, x9, [x21, #0x10]\n" "ldp x28, x27, [x20, #0x0]\n" - "ld1b { z30.b }, p1/Z, [x27, x15]\n" + "ld1b { z30.b }, p0/Z, [x27, x15]\n" "ldp x26, x25, [x20, #0x10]\n" - "ld1b { z29.b }, p1/Z, [x25, x15]\n" + "ld1b { z29.b }, p0/Z, [x25, x15]\n" "ldp x24, x23, [x20, #0x20]\n" - "ld1b { z28.b }, p1/Z, [x24, x15]\n" + "ld1b { z28.b }, p0/Z, [x24, x15]\n" "ldp x22, x21, [x20, #0x30]\n" - "ld1b { z27.b }, p1/Z, [x21, x15]\n" + "ld1b { z27.b }, p0/Z, [x21, x15]\n" "ldr x20, [x20, #0x40]\n" - "ld1b { z26.b }, p1/Z, [x28, x15]\n" - "ld1b { z25.b }, p1/Z, [x26, x15]\n" - "ld1b { z24.b }, p1/Z, [x23, x15]\n" - "ld1b { z23.b }, p1/Z, [x22, x15]\n" - "ld1b { z19.b }, p1/Z, [x20, x15]\n" + "ld1b { z26.b }, p0/Z, [x28, x15]\n" + "ld1b { z25.b }, p0/Z, [x26, x15]\n" + "ld1b { z24.b }, p0/Z, [x23, x15]\n" + "ld1b { z19.b }, p0/Z, [x22, x15]\n" + "ld1b { z23.b }, p0/Z, [x20, x15]\n" "incw x15\n" "whilelt p1.b, x15, x13\n" "b.none 2f\n" @@ -95,25 +95,25 @@ void sme_s8_nhwc_max_2x2_s1_output2x2_depthfirst_impl( "movprfx z21, z28\n smax z21.b, p2/M, z21.b, z27.b\n" "ld1b { z30.b }, p1/Z, [x27, x15]\n" "whilelt p0.b, x14, x13\n" - "movprfx z20, z29\n smax z20.b, p2/M, z20.b, z26.b\n" - "movprfx z18, z25\n smax z18.b, p2/M, z18.b, z24.b\n" + "movprfx z18, z29\n smax z18.b, p2/M, z18.b, z26.b\n" + "movprfx z17, z25\n smax z17.b, p2/M, z17.b, z24.b\n" "ld1b { z28.b }, p1/Z, [x24, x15]\n" - "movprfx z17, z29\n smax z17.b, p2/M, z17.b, z23.b\n" - "movprfx z16, z24\n smax z16.b, p2/M, z16.b, z19.b\n" + "movprfx z16, z29\n smax z16.b, p2/M, z16.b, z19.b\n" + "movprfx z20, z24\n smax z20.b, p2/M, z20.b, z23.b\n" "ld1b { z27.b }, p1/Z, [x21, x15]\n" "ld1b { z29.b }, p1/Z, [x25, x15]\n" - "movprfx z19, z22\n smax z19.b, p2/M, z19.b, z20.b\n" - "smax z18.b, p2/M, z18.b, z22.b\n" + "movprfx z19, z22\n smax z19.b, p2/M, z19.b, z18.b\n" + "movprfx z18, z17\n smax z18.b, p2/M, z18.b, z22.b\n" "ld1b { z26.b }, p1/Z, [x28, x15]\n" - "smax z17.b, p2/M, z17.b, z21.b\n" - "smax z16.b, p2/M, z16.b, z21.b\n" + "movprfx z17, z16\n smax z17.b, p2/M, z17.b, z21.b\n" + "movprfx z16, z21\n smax z16.b, p2/M, z16.b, z20.b\n" "ld1b { z25.b }, p1/Z, [x26, x15]\n" "st1b { z19.b }, p0, [x12, x14]\n" "ld1b { z24.b }, p1/Z, [x23, x15]\n" "st1b { z18.b }, p0, [x11, x14]\n" - "ld1b { z23.b }, p1/Z, [x22, x15]\n" + "ld1b { z19.b }, p1/Z, [x22, x15]\n" "st1b { z17.b }, p0, [x10, x14]\n" - "ld1b { z19.b }, p1/Z, [x20, x15]\n" + "ld1b { z23.b }, p1/Z, [x20, x15]\n" "incw x15\n" "whilelt p1.b, x15, x13\n" "st1b { z16.b }, p0, [x9, x14]\n" @@ -125,13 +125,13 @@ void sme_s8_nhwc_max_2x2_s1_output2x2_depthfirst_impl( "whilelt p0.b, x14, x13\n" "movprfx z20, z29\n smax z20.b, p2/M, z20.b, z26.b\n" "movprfx z18, z25\n smax z18.b, p2/M, z18.b, z24.b\n" - "movprfx z17, z29\n smax z17.b, p2/M, z17.b, z23.b\n" - "movprfx z16, z24\n smax z16.b, p2/M, z16.b, z19.b\n" - "movprfx z19, z22\n smax z19.b, p2/M, z19.b, z20.b\n" + "movprfx z17, z29\n smax z17.b, p2/M, z17.b, z19.b\n" + "movprfx z19, z24\n smax z19.b, p2/M, z19.b, z23.b\n" + "movprfx z16, z22\n smax z16.b, p2/M, z16.b, z20.b\n" "smax z18.b, p2/M, z18.b, z22.b\n" - "st1b { z19.b }, p0, [x12, x14]\n" + "st1b { z16.b }, p0, [x12, x14]\n" "smax z17.b, p2/M, z17.b, z21.b\n" - "smax z16.b, p2/M, z16.b, z21.b\n" + "movprfx z16, z21\n smax z16.b, p2/M, z16.b, z19.b\n" "st1b { z18.b }, p0, [x11, x14]\n" "st1b { z17.b }, p0, [x10, x14]\n" "st1b { z16.b }, p0, [x9, x14]\n" @@ -145,4 +145,4 @@ void sme_s8_nhwc_max_2x2_s1_output2x2_depthfirst_impl( } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) && defined(ARM_COMPUTE_ENABLE_SME) +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_max_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_max_generic_depthfirst.hpp index 56aa120cfe..3e0d76c277 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_max_generic_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_max_generic_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Arm Limited. + * Copyright (c) 2022-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -26,6 +26,8 @@ #pragma once +#if defined(ARM_COMPUTE_ENABLE_SME) + namespace arm_conv { namespace pooling { @@ -40,3 +42,5 @@ struct sme_s8_nhwc_max_generic_depthfirst : IGenericDepthfirstStrategy<int8_t, i } // namespace pooling } // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_max_generic_depthfirst/generic.cpp index 4e6cad6e92..d2b45cd353 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_max_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_max_generic_depthfirst/generic.cpp @@ -22,9 +22,10 @@ * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SME) - #include <cstdint> +#include <cstddef> + +#if defined(ARM_COMPUTE_ENABLE_SME) namespace arm_conv { namespace pooling { @@ -54,68 +55,68 @@ void sme_s8_nhwc_max_generic_depthfirst_impl( "lsr x25, %x[n_valid_cells], #0x2\n" "mov z4.b, #0x80\n" "mov z3.b, #0x80\n" - "mov x20, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "mov z2.b, #0x80\n" "mov z1.b, #0x80\n" "cbz x25, 4f\n" - "ldp x24, x23, [x20, #0x0]\n" + "ldp x23, x22, [x24, #0x0]\n" "subs x25, x25, #0x1\n" - "ld1b { z0.b }, p4/Z, [x24, x9]\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" - "ld1b { z31.b }, p4/Z, [x23, x9]\n" - "ld1b { z23.b }, p4/Z, [x22, x9]\n" - "ld1b { z30.b }, p4/Z, [x21, x9]\n" - "ld1b { z18.b }, p3/Z, [x24, x28]\n" - "ld1b { z29.b }, p3/Z, [x23, x28]\n" - "ld1b { z22.b }, p3/Z, [x22, x28]\n" - "ld1b { z28.b }, p3/Z, [x21, x28]\n" - "ld1b { z17.b }, p2/Z, [x24, x27]\n" - "ld1b { z27.b }, p2/Z, [x23, x27]\n" - "ld1b { z21.b }, p2/Z, [x22, x27]\n" - "ld1b { z26.b }, p2/Z, [x21, x27]\n" - "ld1b { z16.b }, p1/Z, [x24, x26]\n" - "ld1b { z25.b }, p1/Z, [x23, x26]\n" - "ld1b { z20.b }, p1/Z, [x22, x26]\n" - "ld1b { z24.b }, p1/Z, [x21, x26]\n" + "ld1b { z0.b }, p4/Z, [x23, x9]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "ld1b { z31.b }, p4/Z, [x22, x9]\n" + "ld1b { z23.b }, p4/Z, [x21, x9]\n" + "ld1b { z30.b }, p4/Z, [x20, x9]\n" + "ld1b { z18.b }, p3/Z, [x23, x28]\n" + "ld1b { z29.b }, p3/Z, [x22, x28]\n" + "ld1b { z22.b }, p3/Z, [x21, x28]\n" + "ld1b { z28.b }, p3/Z, [x20, x28]\n" + "ld1b { z17.b }, p2/Z, [x23, x27]\n" + "ld1b { z27.b }, p2/Z, [x22, x27]\n" + "ld1b { z21.b }, p2/Z, [x21, x27]\n" + "ld1b { z26.b }, p2/Z, [x20, x27]\n" + "ld1b { z16.b }, p1/Z, [x23, x26]\n" + "ld1b { z25.b }, p1/Z, [x22, x26]\n" + "ld1b { z20.b }, p1/Z, [x21, x26]\n" + "ld1b { z24.b }, p1/Z, [x20, x26]\n" "beq 3f\n" "2:" // 4-vectors of channels: 4 inputs loop "movprfx z19, z0\n smax z19.b, p0/M, z19.b, z31.b\n" "smax z23.b, p0/M, z23.b, z30.b\n" - "ldp x24, x23, [x20, #0x0]\n" + "ldp x23, x22, [x24, #0x0]\n" "subs x25, x25, #0x1\n" "smax z18.b, p0/M, z18.b, z29.b\n" "smax z22.b, p0/M, z22.b, z28.b\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" "smax z17.b, p0/M, z17.b, z27.b\n" "smax z21.b, p0/M, z21.b, z26.b\n" - "ld1b { z0.b }, p4/Z, [x24, x9]\n" + "ld1b { z0.b }, p4/Z, [x23, x9]\n" "smax z16.b, p0/M, z16.b, z25.b\n" "smax z20.b, p0/M, z20.b, z24.b\n" - "ld1b { z31.b }, p4/Z, [x23, x9]\n" + "ld1b { z31.b }, p4/Z, [x22, x9]\n" "smax z19.b, p0/M, z19.b, z23.b\n" "smax z18.b, p0/M, z18.b, z22.b\n" - "ld1b { z23.b }, p4/Z, [x22, x9]\n" + "ld1b { z23.b }, p4/Z, [x21, x9]\n" "smax z17.b, p0/M, z17.b, z21.b\n" "smax z16.b, p0/M, z16.b, z20.b\n" - "ld1b { z30.b }, p4/Z, [x21, x9]\n" + "ld1b { z30.b }, p4/Z, [x20, x9]\n" "smax z4.b, p0/M, z4.b, z19.b\n" "smax z3.b, p0/M, z3.b, z18.b\n" - "ld1b { z18.b }, p3/Z, [x24, x28]\n" + "ld1b { z18.b }, p3/Z, [x23, x28]\n" "smax z2.b, p0/M, z2.b, z17.b\n" "smax z1.b, p0/M, z1.b, z16.b\n" - "ld1b { z29.b }, p3/Z, [x23, x28]\n" - "ld1b { z22.b }, p3/Z, [x22, x28]\n" - "ld1b { z28.b }, p3/Z, [x21, x28]\n" - "ld1b { z17.b }, p2/Z, [x24, x27]\n" - "ld1b { z27.b }, p2/Z, [x23, x27]\n" - "ld1b { z21.b }, p2/Z, [x22, x27]\n" - "ld1b { z26.b }, p2/Z, [x21, x27]\n" - "ld1b { z16.b }, p1/Z, [x24, x26]\n" - "ld1b { z25.b }, p1/Z, [x23, x26]\n" - "ld1b { z20.b }, p1/Z, [x22, x26]\n" - "ld1b { z24.b }, p1/Z, [x21, x26]\n" + "ld1b { z29.b }, p3/Z, [x22, x28]\n" + "ld1b { z22.b }, p3/Z, [x21, x28]\n" + "ld1b { z28.b }, p3/Z, [x20, x28]\n" + "ld1b { z17.b }, p2/Z, [x23, x27]\n" + "ld1b { z27.b }, p2/Z, [x22, x27]\n" + "ld1b { z21.b }, p2/Z, [x21, x27]\n" + "ld1b { z26.b }, p2/Z, [x20, x27]\n" + "ld1b { z16.b }, p1/Z, [x23, x26]\n" + "ld1b { z25.b }, p1/Z, [x22, x26]\n" + "ld1b { z20.b }, p1/Z, [x21, x26]\n" + "ld1b { z24.b }, p1/Z, [x20, x26]\n" "bgt 2b\n" "3:" // 4-vectors of channels: 4 inputs tail "movprfx z19, z0\n smax z19.b, p0/M, z19.b, z31.b\n" @@ -138,15 +139,15 @@ void sme_s8_nhwc_max_generic_depthfirst_impl( "ands x21, %x[n_valid_cells], #0x3\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x24, [x20], #0x8\n" - "ld1b { z0.b }, p4/Z, [x24, x9]\n" + "ldr x20, [x24], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x9]\n" "subs x21, x21, #0x1\n" - "smax z4.b, p0/M, z4.b, z0.b\n" - "ld1b { z18.b }, p3/Z, [x24, x28]\n" - "smax z3.b, p0/M, z3.b, z18.b\n" - "ld1b { z17.b }, p2/Z, [x24, x27]\n" - "smax z2.b, p0/M, z2.b, z17.b\n" - "ld1b { z16.b }, p1/Z, [x24, x26]\n" + "smax z4.b, p0/M, z4.b, z16.b\n" + "ld1b { z16.b }, p3/Z, [x20, x28]\n" + "smax z3.b, p0/M, z3.b, z16.b\n" + "ld1b { z16.b }, p2/Z, [x20, x27]\n" + "smax z2.b, p0/M, z2.b, z16.b\n" + "ld1b { z16.b }, p1/Z, [x20, x26]\n" "smax z1.b, p0/M, z1.b, z16.b\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End @@ -166,44 +167,44 @@ void sme_s8_nhwc_max_generic_depthfirst_impl( "8:" // Single vector of channels: Loop "lsr x25, %x[n_valid_cells], #0x2\n" "mov z4.b, #0x80\n" - "mov x20, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "cbz x25, 11f\n" - "ldp x24, x23, [x20, #0x0]\n" + "ldp x20, x22, [x24, #0x0]\n" "subs x25, x25, #0x1\n" - "ld1b { z0.b }, p4/Z, [x24, x9]\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" - "ld1b { z31.b }, p4/Z, [x23, x9]\n" - "ld1b { z23.b }, p4/Z, [x22, x9]\n" - "ld1b { z30.b }, p4/Z, [x21, x9]\n" + "ld1b { z0.b }, p4/Z, [x20, x9]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "ld1b { z31.b }, p4/Z, [x22, x9]\n" + "ld1b { z23.b }, p4/Z, [x21, x9]\n" + "ld1b { z30.b }, p4/Z, [x20, x9]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 4 inputs loop - "movprfx z19, z0\n smax z19.b, p0/M, z19.b, z31.b\n" - "smax z23.b, p0/M, z23.b, z30.b\n" - "ldp x24, x23, [x20, #0x0]\n" + "movprfx z16, z0\n smax z16.b, p0/M, z16.b, z31.b\n" + "movprfx z17, z23\n smax z17.b, p0/M, z17.b, z30.b\n" + "ldp x23, x22, [x24, #0x0]\n" "subs x25, x25, #0x1\n" - "smax z19.b, p0/M, z19.b, z23.b\n" - "ldp x22, x21, [x20, #0x10]\n" - "smax z4.b, p0/M, z4.b, z19.b\n" - "add x20, x20, #0x20\n" - "ld1b { z0.b }, p4/Z, [x24, x9]\n" - "ld1b { z31.b }, p4/Z, [x23, x9]\n" - "ld1b { z23.b }, p4/Z, [x22, x9]\n" - "ld1b { z30.b }, p4/Z, [x21, x9]\n" + "smax z16.b, p0/M, z16.b, z17.b\n" + "ldp x21, x20, [x24, #0x10]\n" + "smax z4.b, p0/M, z4.b, z16.b\n" + "add x24, x24, #0x20\n" + "ld1b { z0.b }, p4/Z, [x23, x9]\n" + "ld1b { z31.b }, p4/Z, [x22, x9]\n" + "ld1b { z23.b }, p4/Z, [x21, x9]\n" + "ld1b { z30.b }, p4/Z, [x20, x9]\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 4 inputs tail - "movprfx z19, z0\n smax z19.b, p0/M, z19.b, z31.b\n" - "smax z23.b, p0/M, z23.b, z30.b\n" - "smax z19.b, p0/M, z19.b, z23.b\n" - "smax z4.b, p0/M, z4.b, z19.b\n" + "movprfx z16, z0\n smax z16.b, p0/M, z16.b, z31.b\n" + "movprfx z17, z23\n smax z17.b, p0/M, z17.b, z30.b\n" + "smax z16.b, p0/M, z16.b, z17.b\n" + "smax z4.b, p0/M, z4.b, z16.b\n" "11:" // Single vector of channels: Loop: After loop "ands x21, %x[n_valid_cells], #0x3\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x24, [x20], #0x8\n" - "ld1b { z0.b }, p4/Z, [x24, x9]\n" + "ldr x20, [x24], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x9]\n" "subs x21, x21, #0x1\n" - "smax z4.b, p0/M, z4.b, z0.b\n" + "smax z4.b, p0/M, z4.b, z16.b\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End "st1b { z4.b }, p4, [%x[outptr], x9]\n" diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8q_nhwc_avg_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8q_nhwc_avg_generic_depthfirst.hpp index ee02c60bc1..c6263f5dbc 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8q_nhwc_avg_generic_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8q_nhwc_avg_generic_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Arm Limited. + * Copyright (c) 2022-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -26,6 +26,8 @@ #pragma once +#if defined(ARM_COMPUTE_ENABLE_SME) + namespace arm_conv { namespace pooling { @@ -40,3 +42,5 @@ struct sme_s8q_nhwc_avg_generic_depthfirst : IGenericDepthfirstStrategy<int8_t, } // namespace pooling } // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8q_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8q_nhwc_avg_generic_depthfirst/generic.cpp index cc58d3e9e2..91f2f7ab31 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8q_nhwc_avg_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8q_nhwc_avg_generic_depthfirst/generic.cpp @@ -22,14 +22,15 @@ * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SME) - -#include "src/core/NEON/kernels/assembly/pooling.hpp" +#include "pooling.hpp" #include <cstdint> +#include <cstddef> #include <cstring> #include <cmath> +#if defined(ARM_COMPUTE_ENABLE_SME) + namespace arm_conv { namespace pooling { @@ -128,7 +129,7 @@ void sme_s8q_nhwc_avg_generic_depthfirst_impl( "lsr x23, %x[n_valid_cells], #0x1\n" "mov z15.s, #0x0\n" "mov z14.s, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "mov z13.s, #0x0\n" "mov z12.s, #0x0\n" "mov z11.s, #0x0\n" @@ -144,48 +145,48 @@ void sme_s8q_nhwc_avg_generic_depthfirst_impl( "mov z1.s, #0x0\n" "mov z0.s, #0x0\n" "cbz x23, 4f\n" - "ldp x22, x21, [x20, #0x0]\n" + "ldp x21, x20, [x22, #0x0]\n" "subs x23, x23, #0x1\n" - "add x20, x20, #0x10\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" - "ld1b { z30.b }, p4/Z, [x21, x27]\n" - "ld1b { z29.b }, p3/Z, [x22, x26]\n" - "ld1b { z28.b }, p3/Z, [x21, x26]\n" - "ld1b { z27.b }, p2/Z, [x22, x25]\n" - "ld1b { z26.b }, p2/Z, [x21, x25]\n" - "ld1b { z25.b }, p1/Z, [x22, x24]\n" - "ld1b { z24.b }, p1/Z, [x21, x24]\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" + "ld1b { z29.b }, p3/Z, [x21, x26]\n" + "ld1b { z28.b }, p3/Z, [x20, x26]\n" + "ld1b { z27.b }, p2/Z, [x21, x25]\n" + "ld1b { z26.b }, p2/Z, [x20, x25]\n" + "ld1b { z25.b }, p1/Z, [x21, x24]\n" + "ld1b { z24.b }, p1/Z, [x20, x24]\n" "beq 3f\n" "2:" // 4-vectors of channels: 2 inputs loop ".inst 0x455e03f7 // saddlb z23.h, z31.b, z30.b\n" ".inst 0x455e07f6 // saddlt z22.h, z31.b, z30.b\n" - "ldp x22, x21, [x20, #0x0]\n" + "ldp x21, x20, [x22, #0x0]\n" "subs x23, x23, #0x1\n" ".inst 0x455c03b5 // saddlb z21.h, z29.b, z28.b\n" ".inst 0x455c07b4 // saddlt z20.h, z29.b, z28.b\n" - "add x20, x20, #0x10\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" ".inst 0x455a0373 // saddlb z19.h, z27.b, z26.b\n" ".inst 0x455a0772 // saddlt z18.h, z27.b, z26.b\n" - "ld1b { z30.b }, p4/Z, [x21, x27]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" ".inst 0x45580331 // saddlb z17.h, z25.b, z24.b\n" ".inst 0x45580730 // saddlt z16.h, z25.b, z24.b\n" - "ld1b { z29.b }, p3/Z, [x22, x26]\n" + "ld1b { z29.b }, p3/Z, [x21, x26]\n" ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" - "ld1b { z28.b }, p3/Z, [x21, x26]\n" + "ld1b { z28.b }, p3/Z, [x20, x26]\n" ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" - "ld1b { z27.b }, p2/Z, [x22, x25]\n" + "ld1b { z27.b }, p2/Z, [x21, x25]\n" ".inst 0x4595416b // saddwb z11.s, z11.s, z21.h\n" ".inst 0x4595454a // saddwt z10.s, z10.s, z21.h\n" - "ld1b { z26.b }, p2/Z, [x21, x25]\n" + "ld1b { z26.b }, p2/Z, [x20, x25]\n" ".inst 0x45944129 // saddwb z9.s, z9.s, z20.h\n" ".inst 0x45944508 // saddwt z8.s, z8.s, z20.h\n" - "ld1b { z25.b }, p1/Z, [x22, x24]\n" + "ld1b { z25.b }, p1/Z, [x21, x24]\n" ".inst 0x459340e7 // saddwb z7.s, z7.s, z19.h\n" ".inst 0x459344c6 // saddwt z6.s, z6.s, z19.h\n" - "ld1b { z24.b }, p1/Z, [x21, x24]\n" + "ld1b { z24.b }, p1/Z, [x20, x24]\n" ".inst 0x459240a5 // saddwb z5.s, z5.s, z18.h\n" ".inst 0x45924484 // saddwt z4.s, z4.s, z18.h\n" ".inst 0x45914063 // saddwb z3.s, z3.s, z17.h\n" @@ -222,20 +223,20 @@ void sme_s8q_nhwc_avg_generic_depthfirst_impl( "ands x21, %x[n_valid_cells], #0x1\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x22, [x20], #0x8\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" - ".inst 0x4508a3f7 // sshllb z23.h, z31.b, #0x0\n" - ".inst 0x4508a7f6 // sshllt z22.h, z31.b, #0x0\n" - "ld1b { z29.b }, p3/Z, [x22, x26]\n" - ".inst 0x4508a3b5 // sshllb z21.h, z29.b, #0x0\n" - ".inst 0x4508a7b4 // sshllt z20.h, z29.b, #0x0\n" + "ldr x20, [x22], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x27]\n" + ".inst 0x4508a217 // sshllb z23.h, z16.b, #0x0\n" + ".inst 0x4508a616 // sshllt z22.h, z16.b, #0x0\n" + "ld1b { z16.b }, p3/Z, [x20, x26]\n" + ".inst 0x4508a215 // sshllb z21.h, z16.b, #0x0\n" + ".inst 0x4508a614 // sshllt z20.h, z16.b, #0x0\n" "subs x21, x21, #0x1\n" - "ld1b { z27.b }, p2/Z, [x22, x25]\n" - ".inst 0x4508a373 // sshllb z19.h, z27.b, #0x0\n" - ".inst 0x4508a772 // sshllt z18.h, z27.b, #0x0\n" - "ld1b { z25.b }, p1/Z, [x22, x24]\n" - ".inst 0x4508a331 // sshllb z17.h, z25.b, #0x0\n" - ".inst 0x4508a730 // sshllt z16.h, z25.b, #0x0\n" + "ld1b { z16.b }, p2/Z, [x20, x25]\n" + ".inst 0x4508a213 // sshllb z19.h, z16.b, #0x0\n" + ".inst 0x4508a612 // sshllt z18.h, z16.b, #0x0\n" + "ld1b { z16.b }, p1/Z, [x20, x24]\n" + ".inst 0x4508a211 // sshllb z17.h, z16.b, #0x0\n" + ".inst 0x4508a610 // sshllt z16.h, z16.b, #0x0\n" ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" @@ -368,79 +369,79 @@ void sme_s8q_nhwc_avg_generic_depthfirst_impl( "lsr x23, %x[n_valid_cells], #0x1\n" "mov z15.s, #0x0\n" "mov z14.s, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "mov z13.s, #0x0\n" "mov z12.s, #0x0\n" "cbz x23, 11f\n" - "ldp x22, x21, [x20, #0x0]\n" + "ldp x21, x20, [x22, #0x0]\n" "subs x23, x23, #0x1\n" - "add x20, x20, #0x10\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" - "ld1b { z30.b }, p4/Z, [x21, x27]\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 2 inputs loop - ".inst 0x455e03f7 // saddlb z23.h, z31.b, z30.b\n" - ".inst 0x455e07f6 // saddlt z22.h, z31.b, z30.b\n" - "ldp x22, x21, [x20, #0x0]\n" + ".inst 0x455e03f1 // saddlb z17.h, z31.b, z30.b\n" + ".inst 0x455e07f0 // saddlt z16.h, z31.b, z30.b\n" + "ldp x21, x20, [x22, #0x0]\n" "subs x23, x23, #0x1\n" - ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" - ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" - "add x20, x20, #0x10\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" - ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" - ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" - "ld1b { z30.b }, p4/Z, [x21, x27]\n" + ".inst 0x459141ef // saddwb z15.s, z15.s, z17.h\n" + ".inst 0x459145ce // saddwt z14.s, z14.s, z17.h\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + ".inst 0x459041ad // saddwb z13.s, z13.s, z16.h\n" + ".inst 0x4590458c // saddwt z12.s, z12.s, z16.h\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 2 inputs tail - ".inst 0x455e03f7 // saddlb z23.h, z31.b, z30.b\n" - ".inst 0x455e07f6 // saddlt z22.h, z31.b, z30.b\n" - ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" - ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" - ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" - ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" + ".inst 0x455e03f1 // saddlb z17.h, z31.b, z30.b\n" + ".inst 0x455e07f0 // saddlt z16.h, z31.b, z30.b\n" + ".inst 0x459141ef // saddwb z15.s, z15.s, z17.h\n" + ".inst 0x459145ce // saddwt z14.s, z14.s, z17.h\n" + ".inst 0x459041ad // saddwb z13.s, z13.s, z16.h\n" + ".inst 0x4590458c // saddwt z12.s, z12.s, z16.h\n" "11:" // Single vector of channels: Loop: After loop "ands x21, %x[n_valid_cells], #0x1\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x22, [x20], #0x8\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" - ".inst 0x4508a3f7 // sshllb z23.h, z31.b, #0x0\n" - ".inst 0x4508a7f6 // sshllt z22.h, z31.b, #0x0\n" + "ldr x20, [x22], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x27]\n" + ".inst 0x4508a211 // sshllb z17.h, z16.b, #0x0\n" + ".inst 0x4508a610 // sshllt z16.h, z16.b, #0x0\n" "subs x21, x21, #0x1\n" - ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" - ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" - ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" - ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" + ".inst 0x459141ef // saddwb z15.s, z15.s, z17.h\n" + ".inst 0x459145ce // saddwt z14.s, z14.s, z17.h\n" + ".inst 0x459041ad // saddwb z13.s, z13.s, z16.h\n" + ".inst 0x4590458c // saddwt z12.s, z12.s, z16.h\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End - "ld1rw { z18.s }, p0/Z, [%x[left_shift]]\n" - ".inst 0x4482824f // srshl z15.s, p0/M, z15.s, z18.s\n" - ".inst 0x4482824e // srshl z14.s, p0/M, z14.s, z18.s\n" - ".inst 0x4482824d // srshl z13.s, p0/M, z13.s, z18.s\n" - ".inst 0x4482824c // srshl z12.s, p0/M, z12.s, z18.s\n" + "ld1rw { z16.s }, p0/Z, [%x[left_shift]]\n" + ".inst 0x4482820f // srshl z15.s, p0/M, z15.s, z16.s\n" + ".inst 0x4482820e // srshl z14.s, p0/M, z14.s, z16.s\n" + ".inst 0x4482820d // srshl z13.s, p0/M, z13.s, z16.s\n" + ".inst 0x4482820c // srshl z12.s, p0/M, z12.s, z16.s\n" "ld1rw { z17.s }, p0/Z, [%x[combined_rescale_value]]\n" ".inst 0x04b175ef // sqrdmulh z15.s, z15.s, z17.s\n" ".inst 0x04b175ce // sqrdmulh z14.s, z14.s, z17.s\n" "ld1rw { z16.s }, p0/Z, [%x[right_shift]]\n" ".inst 0x04b175ad // sqrdmulh z13.s, z13.s, z17.s\n" ".inst 0x04b1758c // sqrdmulh z12.s, z12.s, z17.s\n" - "mov z19.s, #0x7f\n" + "mov z18.s, #0x7f\n" ".inst 0x4482820f // srshl z15.s, p0/M, z15.s, z16.s\n" ".inst 0x4482820e // srshl z14.s, p0/M, z14.s, z16.s\n" ".inst 0x4482820d // srshl z13.s, p0/M, z13.s, z16.s\n" ".inst 0x4482820c // srshl z12.s, p0/M, z12.s, z16.s\n" - "not z16.s, p0/M, z19.s\n" + "not z16.s, p0/M, z18.s\n" "smax z15.s, p0/M, z15.s, z16.s\n" "smax z14.s, p0/M, z14.s, z16.s\n" "smax z13.s, p0/M, z13.s, z16.s\n" "smax z12.s, p0/M, z12.s, z16.s\n" - "smin z15.s, p0/M, z15.s, z19.s\n" - "smin z14.s, p0/M, z14.s, z19.s\n" - "trn1 z23.h, z15.h, z14.h\n" - "smin z13.s, p0/M, z13.s, z19.s\n" - "smin z12.s, p0/M, z12.s, z19.s\n" + "smin z15.s, p0/M, z15.s, z18.s\n" + "smin z14.s, p0/M, z14.s, z18.s\n" + "trn1 z17.h, z15.h, z14.h\n" + "smin z13.s, p0/M, z13.s, z18.s\n" + "smin z12.s, p0/M, z12.s, z18.s\n" "trn1 z16.h, z13.h, z12.h\n" - "trn1 z16.b, z23.b, z16.b\n" + "trn1 z16.b, z17.b, z16.b\n" "st1b { z16.b }, p4, [%x[outptr], x27]\n" "incb x27\n" "whilelt p4.b, x27, %x[n_channels]\n" @@ -456,4 +457,4 @@ void sme_s8q_nhwc_avg_generic_depthfirst_impl( } // namespace pooling } // namespace arm_conv -#endif // defined(ARM_COMPUTE_ENABLE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8q_nhwc_max_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8q_nhwc_max_generic_depthfirst.hpp index 050aff397e..9667d37954 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8q_nhwc_max_generic_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8q_nhwc_max_generic_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Arm Limited. + * Copyright (c) 2022-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -26,6 +26,8 @@ #pragma once +#if defined(ARM_COMPUTE_ENABLE_SME) + namespace arm_conv { namespace pooling { @@ -40,3 +42,5 @@ struct sme_s8q_nhwc_max_generic_depthfirst : IGenericDepthfirstStrategy<int8_t, } // namespace pooling } // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8q_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8q_nhwc_max_generic_depthfirst/generic.cpp index 3850ebf464..e9b586f4ce 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8q_nhwc_max_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8q_nhwc_max_generic_depthfirst/generic.cpp @@ -22,10 +22,11 @@ * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SME) - -#include "src/core/NEON/kernels/assembly/pooling.hpp" +#include "pooling.hpp" #include <cstdint> +#include <cstddef> + +#if defined(ARM_COMPUTE_ENABLE_SME) namespace arm_conv { namespace pooling { @@ -56,68 +57,68 @@ void sme_s8q_nhwc_max_generic_depthfirst_impl( "lsr x25, %x[n_valid_cells], #0x2\n" "mov z4.b, #0x80\n" "mov z3.b, #0x80\n" - "mov x20, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "mov z2.b, #0x80\n" "mov z1.b, #0x80\n" "cbz x25, 4f\n" - "ldp x24, x23, [x20, #0x0]\n" + "ldp x23, x22, [x24, #0x0]\n" "subs x25, x25, #0x1\n" - "ld1b { z0.b }, p4/Z, [x24, x9]\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" - "ld1b { z31.b }, p4/Z, [x23, x9]\n" - "ld1b { z23.b }, p4/Z, [x22, x9]\n" - "ld1b { z30.b }, p4/Z, [x21, x9]\n" - "ld1b { z18.b }, p3/Z, [x24, x28]\n" - "ld1b { z29.b }, p3/Z, [x23, x28]\n" - "ld1b { z22.b }, p3/Z, [x22, x28]\n" - "ld1b { z28.b }, p3/Z, [x21, x28]\n" - "ld1b { z17.b }, p2/Z, [x24, x27]\n" - "ld1b { z27.b }, p2/Z, [x23, x27]\n" - "ld1b { z21.b }, p2/Z, [x22, x27]\n" - "ld1b { z26.b }, p2/Z, [x21, x27]\n" - "ld1b { z16.b }, p1/Z, [x24, x26]\n" - "ld1b { z25.b }, p1/Z, [x23, x26]\n" - "ld1b { z20.b }, p1/Z, [x22, x26]\n" - "ld1b { z24.b }, p1/Z, [x21, x26]\n" + "ld1b { z0.b }, p4/Z, [x23, x9]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "ld1b { z31.b }, p4/Z, [x22, x9]\n" + "ld1b { z23.b }, p4/Z, [x21, x9]\n" + "ld1b { z30.b }, p4/Z, [x20, x9]\n" + "ld1b { z18.b }, p3/Z, [x23, x28]\n" + "ld1b { z29.b }, p3/Z, [x22, x28]\n" + "ld1b { z22.b }, p3/Z, [x21, x28]\n" + "ld1b { z28.b }, p3/Z, [x20, x28]\n" + "ld1b { z17.b }, p2/Z, [x23, x27]\n" + "ld1b { z27.b }, p2/Z, [x22, x27]\n" + "ld1b { z21.b }, p2/Z, [x21, x27]\n" + "ld1b { z26.b }, p2/Z, [x20, x27]\n" + "ld1b { z16.b }, p1/Z, [x23, x26]\n" + "ld1b { z25.b }, p1/Z, [x22, x26]\n" + "ld1b { z20.b }, p1/Z, [x21, x26]\n" + "ld1b { z24.b }, p1/Z, [x20, x26]\n" "beq 3f\n" "2:" // 4-vectors of channels: 4 inputs loop "movprfx z19, z0\n smax z19.b, p0/M, z19.b, z31.b\n" "smax z23.b, p0/M, z23.b, z30.b\n" - "ldp x24, x23, [x20, #0x0]\n" + "ldp x23, x22, [x24, #0x0]\n" "subs x25, x25, #0x1\n" "smax z18.b, p0/M, z18.b, z29.b\n" "smax z22.b, p0/M, z22.b, z28.b\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" "smax z17.b, p0/M, z17.b, z27.b\n" "smax z21.b, p0/M, z21.b, z26.b\n" - "ld1b { z0.b }, p4/Z, [x24, x9]\n" + "ld1b { z0.b }, p4/Z, [x23, x9]\n" "smax z16.b, p0/M, z16.b, z25.b\n" "smax z20.b, p0/M, z20.b, z24.b\n" - "ld1b { z31.b }, p4/Z, [x23, x9]\n" + "ld1b { z31.b }, p4/Z, [x22, x9]\n" "smax z19.b, p0/M, z19.b, z23.b\n" "smax z18.b, p0/M, z18.b, z22.b\n" - "ld1b { z23.b }, p4/Z, [x22, x9]\n" + "ld1b { z23.b }, p4/Z, [x21, x9]\n" "smax z17.b, p0/M, z17.b, z21.b\n" "smax z16.b, p0/M, z16.b, z20.b\n" - "ld1b { z30.b }, p4/Z, [x21, x9]\n" + "ld1b { z30.b }, p4/Z, [x20, x9]\n" "smax z4.b, p0/M, z4.b, z19.b\n" "smax z3.b, p0/M, z3.b, z18.b\n" - "ld1b { z18.b }, p3/Z, [x24, x28]\n" + "ld1b { z18.b }, p3/Z, [x23, x28]\n" "smax z2.b, p0/M, z2.b, z17.b\n" "smax z1.b, p0/M, z1.b, z16.b\n" - "ld1b { z29.b }, p3/Z, [x23, x28]\n" - "ld1b { z22.b }, p3/Z, [x22, x28]\n" - "ld1b { z28.b }, p3/Z, [x21, x28]\n" - "ld1b { z17.b }, p2/Z, [x24, x27]\n" - "ld1b { z27.b }, p2/Z, [x23, x27]\n" - "ld1b { z21.b }, p2/Z, [x22, x27]\n" - "ld1b { z26.b }, p2/Z, [x21, x27]\n" - "ld1b { z16.b }, p1/Z, [x24, x26]\n" - "ld1b { z25.b }, p1/Z, [x23, x26]\n" - "ld1b { z20.b }, p1/Z, [x22, x26]\n" - "ld1b { z24.b }, p1/Z, [x21, x26]\n" + "ld1b { z29.b }, p3/Z, [x22, x28]\n" + "ld1b { z22.b }, p3/Z, [x21, x28]\n" + "ld1b { z28.b }, p3/Z, [x20, x28]\n" + "ld1b { z17.b }, p2/Z, [x23, x27]\n" + "ld1b { z27.b }, p2/Z, [x22, x27]\n" + "ld1b { z21.b }, p2/Z, [x21, x27]\n" + "ld1b { z26.b }, p2/Z, [x20, x27]\n" + "ld1b { z16.b }, p1/Z, [x23, x26]\n" + "ld1b { z25.b }, p1/Z, [x22, x26]\n" + "ld1b { z20.b }, p1/Z, [x21, x26]\n" + "ld1b { z24.b }, p1/Z, [x20, x26]\n" "bgt 2b\n" "3:" // 4-vectors of channels: 4 inputs tail "movprfx z19, z0\n smax z19.b, p0/M, z19.b, z31.b\n" @@ -140,15 +141,15 @@ void sme_s8q_nhwc_max_generic_depthfirst_impl( "ands x21, %x[n_valid_cells], #0x3\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x24, [x20], #0x8\n" - "ld1b { z0.b }, p4/Z, [x24, x9]\n" + "ldr x20, [x24], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x9]\n" "subs x21, x21, #0x1\n" - "smax z4.b, p0/M, z4.b, z0.b\n" - "ld1b { z18.b }, p3/Z, [x24, x28]\n" - "smax z3.b, p0/M, z3.b, z18.b\n" - "ld1b { z17.b }, p2/Z, [x24, x27]\n" - "smax z2.b, p0/M, z2.b, z17.b\n" - "ld1b { z16.b }, p1/Z, [x24, x26]\n" + "smax z4.b, p0/M, z4.b, z16.b\n" + "ld1b { z16.b }, p3/Z, [x20, x28]\n" + "smax z3.b, p0/M, z3.b, z16.b\n" + "ld1b { z16.b }, p2/Z, [x20, x27]\n" + "smax z2.b, p0/M, z2.b, z16.b\n" + "ld1b { z16.b }, p1/Z, [x20, x26]\n" "smax z1.b, p0/M, z1.b, z16.b\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End @@ -292,83 +293,83 @@ void sme_s8q_nhwc_max_generic_depthfirst_impl( "8:" // Single vector of channels: Loop "lsr x25, %x[n_valid_cells], #0x2\n" "mov z4.b, #0x80\n" - "mov x20, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "cbz x25, 11f\n" - "ldp x24, x23, [x20, #0x0]\n" + "ldp x20, x22, [x24, #0x0]\n" "subs x25, x25, #0x1\n" - "ld1b { z0.b }, p4/Z, [x24, x9]\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" - "ld1b { z31.b }, p4/Z, [x23, x9]\n" - "ld1b { z23.b }, p4/Z, [x22, x9]\n" - "ld1b { z30.b }, p4/Z, [x21, x9]\n" + "ld1b { z0.b }, p4/Z, [x20, x9]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "ld1b { z31.b }, p4/Z, [x22, x9]\n" + "ld1b { z23.b }, p4/Z, [x21, x9]\n" + "ld1b { z30.b }, p4/Z, [x20, x9]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 4 inputs loop - "movprfx z19, z0\n smax z19.b, p0/M, z19.b, z31.b\n" - "smax z23.b, p0/M, z23.b, z30.b\n" - "ldp x24, x23, [x20, #0x0]\n" + "movprfx z16, z0\n smax z16.b, p0/M, z16.b, z31.b\n" + "movprfx z17, z23\n smax z17.b, p0/M, z17.b, z30.b\n" + "ldp x23, x22, [x24, #0x0]\n" "subs x25, x25, #0x1\n" - "smax z19.b, p0/M, z19.b, z23.b\n" - "ldp x22, x21, [x20, #0x10]\n" - "smax z4.b, p0/M, z4.b, z19.b\n" - "add x20, x20, #0x20\n" - "ld1b { z0.b }, p4/Z, [x24, x9]\n" - "ld1b { z31.b }, p4/Z, [x23, x9]\n" - "ld1b { z23.b }, p4/Z, [x22, x9]\n" - "ld1b { z30.b }, p4/Z, [x21, x9]\n" + "smax z16.b, p0/M, z16.b, z17.b\n" + "ldp x21, x20, [x24, #0x10]\n" + "smax z4.b, p0/M, z4.b, z16.b\n" + "add x24, x24, #0x20\n" + "ld1b { z0.b }, p4/Z, [x23, x9]\n" + "ld1b { z31.b }, p4/Z, [x22, x9]\n" + "ld1b { z23.b }, p4/Z, [x21, x9]\n" + "ld1b { z30.b }, p4/Z, [x20, x9]\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 4 inputs tail - "movprfx z19, z0\n smax z19.b, p0/M, z19.b, z31.b\n" - "smax z23.b, p0/M, z23.b, z30.b\n" - "smax z19.b, p0/M, z19.b, z23.b\n" - "smax z4.b, p0/M, z4.b, z19.b\n" + "movprfx z16, z0\n smax z16.b, p0/M, z16.b, z31.b\n" + "movprfx z17, z23\n smax z17.b, p0/M, z17.b, z30.b\n" + "smax z16.b, p0/M, z16.b, z17.b\n" + "smax z4.b, p0/M, z4.b, z16.b\n" "11:" // Single vector of channels: Loop: After loop "ands x21, %x[n_valid_cells], #0x3\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x24, [x20], #0x8\n" - "ld1b { z0.b }, p4/Z, [x24, x9]\n" + "ldr x20, [x24], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x9]\n" "subs x21, x21, #0x1\n" - "smax z4.b, p0/M, z4.b, z0.b\n" + "smax z4.b, p0/M, z4.b, z16.b\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End - ".inst 0x4508a097 // sshllb z23.h, z4.b, #0x0\n" - ".inst 0x4508a496 // sshllt z22.h, z4.b, #0x0\n" + ".inst 0x4508a091 // sshllb z17.h, z4.b, #0x0\n" + ".inst 0x4508a490 // sshllt z16.h, z4.b, #0x0\n" "add x20, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n" - "ld1rw { z4.s }, p0/Z, [x20]\n" - ".inst 0x4510a2e1 // sshllb z1.s, z23.h, #0x0\n" - ".inst 0x4510a6f7 // sshllt z23.s, z23.h, #0x0\n" + "ld1rw { z18.s }, p0/Z, [x20]\n" + ".inst 0x4510a236 // sshllb z22.s, z17.h, #0x0\n" + ".inst 0x4510a635 // sshllt z21.s, z17.h, #0x0\n" "add x20, %x[quant_params], %[offsetof_qp_per_layer_mul]\n" - "ld1rw { z3.s }, p0/Z, [x20]\n" - ".inst 0x4510a2c0 // sshllb z0.s, z22.h, #0x0\n" - ".inst 0x4510a6df // sshllt z31.s, z22.h, #0x0\n" + "ld1rw { z17.s }, p0/Z, [x20]\n" + ".inst 0x4510a214 // sshllb z20.s, z16.h, #0x0\n" + ".inst 0x4510a613 // sshllt z19.s, z16.h, #0x0\n" "add x20, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n" - "ld1rw { z2.s }, p0/Z, [x20]\n" - ".inst 0x44828081 // srshl z1.s, p0/M, z1.s, z4.s\n" - ".inst 0x44828097 // srshl z23.s, p0/M, z23.s, z4.s\n" - ".inst 0x44828080 // srshl z0.s, p0/M, z0.s, z4.s\n" - ".inst 0x4482809f // srshl z31.s, p0/M, z31.s, z4.s\n" - ".inst 0x04a37421 // sqrdmulh z1.s, z1.s, z3.s\n" - ".inst 0x04a376f7 // sqrdmulh z23.s, z23.s, z3.s\n" - ".inst 0x04a37400 // sqrdmulh z0.s, z0.s, z3.s\n" - ".inst 0x04a377ff // sqrdmulh z31.s, z31.s, z3.s\n" - "mov z19.s, #0x7f\n" - ".inst 0x44828041 // srshl z1.s, p0/M, z1.s, z2.s\n" - ".inst 0x44828057 // srshl z23.s, p0/M, z23.s, z2.s\n" - ".inst 0x44828040 // srshl z0.s, p0/M, z0.s, z2.s\n" - ".inst 0x4482805f // srshl z31.s, p0/M, z31.s, z2.s\n" - "not z16.s, p0/M, z19.s\n" - "smax z1.s, p0/M, z1.s, z16.s\n" - "smax z23.s, p0/M, z23.s, z16.s\n" - "smax z0.s, p0/M, z0.s, z16.s\n" - "smax z31.s, p0/M, z31.s, z16.s\n" - "smin z1.s, p0/M, z1.s, z19.s\n" - "smin z23.s, p0/M, z23.s, z19.s\n" - "trn1 z23.h, z1.h, z23.h\n" - "smin z0.s, p0/M, z0.s, z19.s\n" - "smin z31.s, p0/M, z31.s, z19.s\n" - "trn1 z16.h, z0.h, z31.h\n" - "trn1 z16.b, z23.b, z16.b\n" + "ld1rw { z16.s }, p0/Z, [x20]\n" + ".inst 0x44828256 // srshl z22.s, p0/M, z22.s, z18.s\n" + ".inst 0x44828255 // srshl z21.s, p0/M, z21.s, z18.s\n" + ".inst 0x44828254 // srshl z20.s, p0/M, z20.s, z18.s\n" + ".inst 0x44828253 // srshl z19.s, p0/M, z19.s, z18.s\n" + ".inst 0x04b176d6 // sqrdmulh z22.s, z22.s, z17.s\n" + ".inst 0x04b176b5 // sqrdmulh z21.s, z21.s, z17.s\n" + ".inst 0x04b17694 // sqrdmulh z20.s, z20.s, z17.s\n" + ".inst 0x04b17673 // sqrdmulh z19.s, z19.s, z17.s\n" + "mov z18.s, #0x7f\n" + ".inst 0x44828216 // srshl z22.s, p0/M, z22.s, z16.s\n" + ".inst 0x44828215 // srshl z21.s, p0/M, z21.s, z16.s\n" + ".inst 0x44828214 // srshl z20.s, p0/M, z20.s, z16.s\n" + ".inst 0x44828213 // srshl z19.s, p0/M, z19.s, z16.s\n" + "not z16.s, p0/M, z18.s\n" + "smax z22.s, p0/M, z22.s, z16.s\n" + "smax z21.s, p0/M, z21.s, z16.s\n" + "smax z20.s, p0/M, z20.s, z16.s\n" + "smax z19.s, p0/M, z19.s, z16.s\n" + "smin z22.s, p0/M, z22.s, z18.s\n" + "smin z21.s, p0/M, z21.s, z18.s\n" + "trn1 z17.h, z22.h, z21.h\n" + "smin z20.s, p0/M, z20.s, z18.s\n" + "smin z19.s, p0/M, z19.s, z18.s\n" + "trn1 z16.h, z20.h, z19.h\n" + "trn1 z16.b, z17.b, z16.b\n" "st1b { z16.b }, p4, [%x[outptr], x9]\n" "incb x9\n" "whilelt p4.b, x9, %x[n_channels]\n" diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_avg_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_avg_generic_depthfirst.hpp index 2cdb2883c2..29a03ec509 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_avg_generic_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_avg_generic_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Arm Limited. + * Copyright (c) 2022-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -26,6 +26,8 @@ #pragma once +#if defined(ARM_COMPUTE_ENABLE_SME) + namespace arm_conv { namespace pooling { @@ -40,3 +42,5 @@ struct sme_u8_nhwc_avg_generic_depthfirst : IGenericDepthfirstStrategy<uint8_t, } // namespace pooling } // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_avg_generic_depthfirst/generic.cpp index a637654908..f0e7bbf5cc 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_avg_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_avg_generic_depthfirst/generic.cpp @@ -22,13 +22,14 @@ * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SME) - #include <cstdint> +#include <cstddef> #include <cstring> #include <cmath> +#if defined(ARM_COMPUTE_ENABLE_SME) + namespace arm_conv { namespace pooling { @@ -109,7 +110,7 @@ void sme_u8_nhwc_avg_generic_depthfirst_impl( "lsr x23, %x[n_valid_cells], #0x1\n" "mov z15.s, #0x0\n" "mov z14.s, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "mov z13.s, #0x0\n" "mov z12.s, #0x0\n" "mov z11.s, #0x0\n" @@ -125,48 +126,48 @@ void sme_u8_nhwc_avg_generic_depthfirst_impl( "mov z1.s, #0x0\n" "mov z0.s, #0x0\n" "cbz x23, 4f\n" - "ldp x22, x21, [x20, #0x0]\n" + "ldp x21, x20, [x22, #0x0]\n" "subs x23, x23, #0x1\n" - "add x20, x20, #0x10\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" - "ld1b { z30.b }, p4/Z, [x21, x27]\n" - "ld1b { z29.b }, p3/Z, [x22, x26]\n" - "ld1b { z28.b }, p3/Z, [x21, x26]\n" - "ld1b { z27.b }, p2/Z, [x22, x25]\n" - "ld1b { z26.b }, p2/Z, [x21, x25]\n" - "ld1b { z25.b }, p1/Z, [x22, x24]\n" - "ld1b { z24.b }, p1/Z, [x21, x24]\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" + "ld1b { z29.b }, p3/Z, [x21, x26]\n" + "ld1b { z28.b }, p3/Z, [x20, x26]\n" + "ld1b { z27.b }, p2/Z, [x21, x25]\n" + "ld1b { z26.b }, p2/Z, [x20, x25]\n" + "ld1b { z25.b }, p1/Z, [x21, x24]\n" + "ld1b { z24.b }, p1/Z, [x20, x24]\n" "beq 3f\n" "2:" // 4-vectors of channels: 2 inputs loop ".inst 0x455e0bf7 // uaddlb z23.h, z31.b, z30.b\n" ".inst 0x455e0ff6 // uaddlt z22.h, z31.b, z30.b\n" - "ldp x22, x21, [x20, #0x0]\n" + "ldp x21, x20, [x22, #0x0]\n" "subs x23, x23, #0x1\n" ".inst 0x455c0bb5 // uaddlb z21.h, z29.b, z28.b\n" ".inst 0x455c0fb4 // uaddlt z20.h, z29.b, z28.b\n" - "add x20, x20, #0x10\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" ".inst 0x455a0b73 // uaddlb z19.h, z27.b, z26.b\n" ".inst 0x455a0f72 // uaddlt z18.h, z27.b, z26.b\n" - "ld1b { z30.b }, p4/Z, [x21, x27]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" ".inst 0x45580b31 // uaddlb z17.h, z25.b, z24.b\n" ".inst 0x45580f30 // uaddlt z16.h, z25.b, z24.b\n" - "ld1b { z29.b }, p3/Z, [x22, x26]\n" + "ld1b { z29.b }, p3/Z, [x21, x26]\n" ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" - "ld1b { z28.b }, p3/Z, [x21, x26]\n" + "ld1b { z28.b }, p3/Z, [x20, x26]\n" ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" - "ld1b { z27.b }, p2/Z, [x22, x25]\n" + "ld1b { z27.b }, p2/Z, [x21, x25]\n" ".inst 0x4595496b // uaddwb z11.s, z11.s, z21.h\n" ".inst 0x45954d4a // uaddwt z10.s, z10.s, z21.h\n" - "ld1b { z26.b }, p2/Z, [x21, x25]\n" + "ld1b { z26.b }, p2/Z, [x20, x25]\n" ".inst 0x45944929 // uaddwb z9.s, z9.s, z20.h\n" ".inst 0x45944d08 // uaddwt z8.s, z8.s, z20.h\n" - "ld1b { z25.b }, p1/Z, [x22, x24]\n" + "ld1b { z25.b }, p1/Z, [x21, x24]\n" ".inst 0x459348e7 // uaddwb z7.s, z7.s, z19.h\n" ".inst 0x45934cc6 // uaddwt z6.s, z6.s, z19.h\n" - "ld1b { z24.b }, p1/Z, [x21, x24]\n" + "ld1b { z24.b }, p1/Z, [x20, x24]\n" ".inst 0x459248a5 // uaddwb z5.s, z5.s, z18.h\n" ".inst 0x45924c84 // uaddwt z4.s, z4.s, z18.h\n" ".inst 0x45914863 // uaddwb z3.s, z3.s, z17.h\n" @@ -203,20 +204,20 @@ void sme_u8_nhwc_avg_generic_depthfirst_impl( "ands x21, %x[n_valid_cells], #0x1\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x22, [x20], #0x8\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" - ".inst 0x4508abf7 // ushllb z23.h, z31.b, #0x0\n" - ".inst 0x4508aff6 // ushllt z22.h, z31.b, #0x0\n" - "ld1b { z29.b }, p3/Z, [x22, x26]\n" - ".inst 0x4508abb5 // ushllb z21.h, z29.b, #0x0\n" - ".inst 0x4508afb4 // ushllt z20.h, z29.b, #0x0\n" + "ldr x20, [x22], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x27]\n" + ".inst 0x4508aa17 // ushllb z23.h, z16.b, #0x0\n" + ".inst 0x4508ae16 // ushllt z22.h, z16.b, #0x0\n" + "ld1b { z16.b }, p3/Z, [x20, x26]\n" + ".inst 0x4508aa15 // ushllb z21.h, z16.b, #0x0\n" + ".inst 0x4508ae14 // ushllt z20.h, z16.b, #0x0\n" "subs x21, x21, #0x1\n" - "ld1b { z27.b }, p2/Z, [x22, x25]\n" - ".inst 0x4508ab73 // ushllb z19.h, z27.b, #0x0\n" - ".inst 0x4508af72 // ushllt z18.h, z27.b, #0x0\n" - "ld1b { z25.b }, p1/Z, [x22, x24]\n" - ".inst 0x4508ab31 // ushllb z17.h, z25.b, #0x0\n" - ".inst 0x4508af30 // ushllt z16.h, z25.b, #0x0\n" + "ld1b { z16.b }, p2/Z, [x20, x25]\n" + ".inst 0x4508aa13 // ushllb z19.h, z16.b, #0x0\n" + ".inst 0x4508ae12 // ushllt z18.h, z16.b, #0x0\n" + "ld1b { z16.b }, p1/Z, [x20, x24]\n" + ".inst 0x4508aa11 // ushllb z17.h, z16.b, #0x0\n" + ".inst 0x4508ae10 // ushllt z16.h, z16.b, #0x0\n" ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" @@ -332,74 +333,74 @@ void sme_u8_nhwc_avg_generic_depthfirst_impl( "lsr x23, %x[n_valid_cells], #0x1\n" "mov z15.s, #0x0\n" "mov z14.s, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "mov z13.s, #0x0\n" "mov z12.s, #0x0\n" "cbz x23, 11f\n" - "ldp x22, x21, [x20, #0x0]\n" + "ldp x21, x20, [x22, #0x0]\n" "subs x23, x23, #0x1\n" - "add x20, x20, #0x10\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" - "ld1b { z30.b }, p4/Z, [x21, x27]\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 2 inputs loop - ".inst 0x455e0bf7 // uaddlb z23.h, z31.b, z30.b\n" - ".inst 0x455e0ff6 // uaddlt z22.h, z31.b, z30.b\n" - "ldp x22, x21, [x20, #0x0]\n" + ".inst 0x455e0bf1 // uaddlb z17.h, z31.b, z30.b\n" + ".inst 0x455e0ff0 // uaddlt z16.h, z31.b, z30.b\n" + "ldp x21, x20, [x22, #0x0]\n" "subs x23, x23, #0x1\n" - ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" - ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" - "add x20, x20, #0x10\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" - ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" - ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" - "ld1b { z30.b }, p4/Z, [x21, x27]\n" + ".inst 0x459149ef // uaddwb z15.s, z15.s, z17.h\n" + ".inst 0x45914dce // uaddwt z14.s, z14.s, z17.h\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + ".inst 0x459049ad // uaddwb z13.s, z13.s, z16.h\n" + ".inst 0x45904d8c // uaddwt z12.s, z12.s, z16.h\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 2 inputs tail - ".inst 0x455e0bf7 // uaddlb z23.h, z31.b, z30.b\n" - ".inst 0x455e0ff6 // uaddlt z22.h, z31.b, z30.b\n" - ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" - ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" - ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" - ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" + ".inst 0x455e0bf1 // uaddlb z17.h, z31.b, z30.b\n" + ".inst 0x455e0ff0 // uaddlt z16.h, z31.b, z30.b\n" + ".inst 0x459149ef // uaddwb z15.s, z15.s, z17.h\n" + ".inst 0x45914dce // uaddwt z14.s, z14.s, z17.h\n" + ".inst 0x459049ad // uaddwb z13.s, z13.s, z16.h\n" + ".inst 0x45904d8c // uaddwt z12.s, z12.s, z16.h\n" "11:" // Single vector of channels: Loop: After loop "ands x21, %x[n_valid_cells], #0x1\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x22, [x20], #0x8\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" - ".inst 0x4508abf7 // ushllb z23.h, z31.b, #0x0\n" - ".inst 0x4508aff6 // ushllt z22.h, z31.b, #0x0\n" + "ldr x20, [x22], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x27]\n" + ".inst 0x4508aa11 // ushllb z17.h, z16.b, #0x0\n" + ".inst 0x4508ae10 // ushllt z16.h, z16.b, #0x0\n" "subs x21, x21, #0x1\n" - ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" - ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" - ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" - ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" + ".inst 0x459149ef // uaddwb z15.s, z15.s, z17.h\n" + ".inst 0x45914dce // uaddwt z14.s, z14.s, z17.h\n" + ".inst 0x459049ad // uaddwb z13.s, z13.s, z16.h\n" + ".inst 0x45904d8c // uaddwt z12.s, z12.s, z16.h\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End - "ld1rw { z17.s }, p0/Z, [%x[rescale_ptr]]\n" - ".inst 0x04b175ef // sqdmulh z15.s, z15.s, z17.s\n" - ".inst 0x04b175ce // sqdmulh z14.s, z14.s, z17.s\n" - ".inst 0x04b175ad // sqdmulh z13.s, z13.s, z17.s\n" - ".inst 0x04b1758c // sqdmulh z12.s, z12.s, z17.s\n" + "ld1rw { z16.s }, p0/Z, [%x[rescale_ptr]]\n" + ".inst 0x04b075ef // sqdmulh z15.s, z15.s, z16.s\n" + ".inst 0x04b075ce // sqdmulh z14.s, z14.s, z16.s\n" + ".inst 0x04b075ad // sqdmulh z13.s, z13.s, z16.s\n" + ".inst 0x04b0758c // sqdmulh z12.s, z12.s, z16.s\n" "ld1rw { z16.s }, p0/Z, [%x[shift_ptr]]\n" ".inst 0x4482820f // srshl z15.s, p0/M, z15.s, z16.s\n" ".inst 0x4482820e // srshl z14.s, p0/M, z14.s, z16.s\n" ".inst 0x4482820d // srshl z13.s, p0/M, z13.s, z16.s\n" ".inst 0x4482820c // srshl z12.s, p0/M, z12.s, z16.s\n" - "mov z16.s, #0x0\n" - "mov z19.s, #0xff\n" - "smax z15.s, p0/M, z15.s, z16.s\n" - "smax z14.s, p0/M, z14.s, z16.s\n" - "smax z13.s, p0/M, z13.s, z16.s\n" - "smax z12.s, p0/M, z12.s, z16.s\n" - "smin z15.s, p0/M, z15.s, z19.s\n" - "smin z14.s, p0/M, z14.s, z19.s\n" - "trn1 z23.h, z15.h, z14.h\n" - "smin z13.s, p0/M, z13.s, z19.s\n" - "smin z12.s, p0/M, z12.s, z19.s\n" + "mov z17.s, #0x0\n" + "mov z16.s, #0xff\n" + "smax z15.s, p0/M, z15.s, z17.s\n" + "smax z14.s, p0/M, z14.s, z17.s\n" + "smax z13.s, p0/M, z13.s, z17.s\n" + "smax z12.s, p0/M, z12.s, z17.s\n" + "smin z15.s, p0/M, z15.s, z16.s\n" + "smin z14.s, p0/M, z14.s, z16.s\n" + "trn1 z17.h, z15.h, z14.h\n" + "smin z13.s, p0/M, z13.s, z16.s\n" + "smin z12.s, p0/M, z12.s, z16.s\n" "trn1 z16.h, z13.h, z12.h\n" - "trn1 z16.b, z23.b, z16.b\n" + "trn1 z16.b, z17.b, z16.b\n" "st1b { z16.b }, p4, [%x[outptr], x27]\n" "incb x27\n" "whilelt p4.b, x27, %x[n_channels]\n" diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp index 6d5f53d7a5..3df4e4efb8 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Arm Limited. + * Copyright (c) 2022-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -24,6 +24,8 @@ #pragma once +#if defined(ARM_COMPUTE_ENABLE_SME) + namespace arm_conv { namespace pooling { @@ -45,3 +47,5 @@ struct sme_u8_nhwc_max_2x2_s1_output2x2_depthfirst : public DepthfirstStrategy<u } // namespace pooling } // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp index 9f267d76ea..9088cbde89 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp @@ -26,7 +26,7 @@ #include <cstddef> #include <cstdint> -#if defined(__ARM_FEATURE_SVE) && defined(ARM_COMPUTE_ENABLE_SME) +#if defined(ARM_COMPUTE_ENABLE_SME) namespace arm_conv { namespace pooling { @@ -70,23 +70,23 @@ void sme_u8_nhwc_max_2x2_s1_output2x2_depthfirst_impl( "ldr x20, [%x[args], %[offsetof_inptrs]]\n" "mov x14, #0x0\n" "ldr x13, [%x[args], %[offsetof_n_channels]]\n" - "whilelt p1.b, x15, x13\n" + "whilelt p0.b, x15, x13\n" "ldp x12, x11, [x21, #0x0]\n" "ldp x10, x9, [x21, #0x10]\n" "ldp x28, x27, [x20, #0x0]\n" - "ld1b { z30.b }, p1/Z, [x27, x15]\n" + "ld1b { z30.b }, p0/Z, [x27, x15]\n" "ldp x26, x25, [x20, #0x10]\n" - "ld1b { z29.b }, p1/Z, [x25, x15]\n" + "ld1b { z29.b }, p0/Z, [x25, x15]\n" "ldp x24, x23, [x20, #0x20]\n" - "ld1b { z28.b }, p1/Z, [x24, x15]\n" + "ld1b { z28.b }, p0/Z, [x24, x15]\n" "ldp x22, x21, [x20, #0x30]\n" - "ld1b { z27.b }, p1/Z, [x21, x15]\n" + "ld1b { z27.b }, p0/Z, [x21, x15]\n" "ldr x20, [x20, #0x40]\n" - "ld1b { z26.b }, p1/Z, [x28, x15]\n" - "ld1b { z25.b }, p1/Z, [x26, x15]\n" - "ld1b { z24.b }, p1/Z, [x23, x15]\n" - "ld1b { z23.b }, p1/Z, [x22, x15]\n" - "ld1b { z19.b }, p1/Z, [x20, x15]\n" + "ld1b { z26.b }, p0/Z, [x28, x15]\n" + "ld1b { z25.b }, p0/Z, [x26, x15]\n" + "ld1b { z24.b }, p0/Z, [x23, x15]\n" + "ld1b { z19.b }, p0/Z, [x22, x15]\n" + "ld1b { z23.b }, p0/Z, [x20, x15]\n" "incw x15\n" "whilelt p1.b, x15, x13\n" "b.none 2f\n" @@ -95,25 +95,25 @@ void sme_u8_nhwc_max_2x2_s1_output2x2_depthfirst_impl( "movprfx z21, z28\n umax z21.b, p2/M, z21.b, z27.b\n" "ld1b { z30.b }, p1/Z, [x27, x15]\n" "whilelt p0.b, x14, x13\n" - "movprfx z20, z29\n umax z20.b, p2/M, z20.b, z26.b\n" - "movprfx z18, z25\n umax z18.b, p2/M, z18.b, z24.b\n" + "movprfx z18, z29\n umax z18.b, p2/M, z18.b, z26.b\n" + "movprfx z17, z25\n umax z17.b, p2/M, z17.b, z24.b\n" "ld1b { z28.b }, p1/Z, [x24, x15]\n" - "movprfx z17, z29\n umax z17.b, p2/M, z17.b, z23.b\n" - "movprfx z16, z24\n umax z16.b, p2/M, z16.b, z19.b\n" + "movprfx z16, z29\n umax z16.b, p2/M, z16.b, z19.b\n" + "movprfx z20, z24\n umax z20.b, p2/M, z20.b, z23.b\n" "ld1b { z27.b }, p1/Z, [x21, x15]\n" "ld1b { z29.b }, p1/Z, [x25, x15]\n" - "movprfx z19, z22\n umax z19.b, p2/M, z19.b, z20.b\n" - "umax z18.b, p2/M, z18.b, z22.b\n" + "movprfx z19, z22\n umax z19.b, p2/M, z19.b, z18.b\n" + "movprfx z18, z17\n umax z18.b, p2/M, z18.b, z22.b\n" "ld1b { z26.b }, p1/Z, [x28, x15]\n" - "umax z17.b, p2/M, z17.b, z21.b\n" - "umax z16.b, p2/M, z16.b, z21.b\n" + "movprfx z17, z16\n umax z17.b, p2/M, z17.b, z21.b\n" + "movprfx z16, z21\n umax z16.b, p2/M, z16.b, z20.b\n" "ld1b { z25.b }, p1/Z, [x26, x15]\n" "st1b { z19.b }, p0, [x12, x14]\n" "ld1b { z24.b }, p1/Z, [x23, x15]\n" "st1b { z18.b }, p0, [x11, x14]\n" - "ld1b { z23.b }, p1/Z, [x22, x15]\n" + "ld1b { z19.b }, p1/Z, [x22, x15]\n" "st1b { z17.b }, p0, [x10, x14]\n" - "ld1b { z19.b }, p1/Z, [x20, x15]\n" + "ld1b { z23.b }, p1/Z, [x20, x15]\n" "incw x15\n" "whilelt p1.b, x15, x13\n" "st1b { z16.b }, p0, [x9, x14]\n" @@ -125,13 +125,13 @@ void sme_u8_nhwc_max_2x2_s1_output2x2_depthfirst_impl( "whilelt p0.b, x14, x13\n" "movprfx z20, z29\n umax z20.b, p2/M, z20.b, z26.b\n" "movprfx z18, z25\n umax z18.b, p2/M, z18.b, z24.b\n" - "movprfx z17, z29\n umax z17.b, p2/M, z17.b, z23.b\n" - "movprfx z16, z24\n umax z16.b, p2/M, z16.b, z19.b\n" - "movprfx z19, z22\n umax z19.b, p2/M, z19.b, z20.b\n" + "movprfx z17, z29\n umax z17.b, p2/M, z17.b, z19.b\n" + "movprfx z19, z24\n umax z19.b, p2/M, z19.b, z23.b\n" + "movprfx z16, z22\n umax z16.b, p2/M, z16.b, z20.b\n" "umax z18.b, p2/M, z18.b, z22.b\n" - "st1b { z19.b }, p0, [x12, x14]\n" + "st1b { z16.b }, p0, [x12, x14]\n" "umax z17.b, p2/M, z17.b, z21.b\n" - "umax z16.b, p2/M, z16.b, z21.b\n" + "movprfx z16, z21\n umax z16.b, p2/M, z16.b, z19.b\n" "st1b { z18.b }, p0, [x11, x14]\n" "st1b { z17.b }, p0, [x10, x14]\n" "st1b { z16.b }, p0, [x9, x14]\n" @@ -145,4 +145,4 @@ void sme_u8_nhwc_max_2x2_s1_output2x2_depthfirst_impl( } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) && defined(ARM_COMPUTE_ENABLE_SME) +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_max_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_max_generic_depthfirst.hpp index 5c637ec3c3..077c8ed2f7 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_max_generic_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_max_generic_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Arm Limited. + * Copyright (c) 2022-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -26,6 +26,8 @@ #pragma once +#if defined(ARM_COMPUTE_ENABLE_SME) + namespace arm_conv { namespace pooling { @@ -40,3 +42,5 @@ struct sme_u8_nhwc_max_generic_depthfirst : IGenericDepthfirstStrategy<uint8_t, } // namespace pooling } // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_max_generic_depthfirst/generic.cpp index 9a13deafda..06f13e8111 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_max_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_max_generic_depthfirst/generic.cpp @@ -22,9 +22,10 @@ * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SME) - #include <cstdint> +#include <cstddef> + +#if defined(ARM_COMPUTE_ENABLE_SME) namespace arm_conv { namespace pooling { @@ -54,68 +55,68 @@ void sme_u8_nhwc_max_generic_depthfirst_impl( "lsr x25, %x[n_valid_cells], #0x2\n" "mov z4.b, #0x0\n" "mov z3.b, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "mov z2.b, #0x0\n" "mov z1.b, #0x0\n" "cbz x25, 4f\n" - "ldp x24, x23, [x20, #0x0]\n" + "ldp x23, x22, [x24, #0x0]\n" "subs x25, x25, #0x1\n" - "ld1b { z0.b }, p4/Z, [x24, x9]\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" - "ld1b { z31.b }, p4/Z, [x23, x9]\n" - "ld1b { z23.b }, p4/Z, [x22, x9]\n" - "ld1b { z30.b }, p4/Z, [x21, x9]\n" - "ld1b { z18.b }, p3/Z, [x24, x28]\n" - "ld1b { z29.b }, p3/Z, [x23, x28]\n" - "ld1b { z22.b }, p3/Z, [x22, x28]\n" - "ld1b { z28.b }, p3/Z, [x21, x28]\n" - "ld1b { z17.b }, p2/Z, [x24, x27]\n" - "ld1b { z27.b }, p2/Z, [x23, x27]\n" - "ld1b { z21.b }, p2/Z, [x22, x27]\n" - "ld1b { z26.b }, p2/Z, [x21, x27]\n" - "ld1b { z16.b }, p1/Z, [x24, x26]\n" - "ld1b { z25.b }, p1/Z, [x23, x26]\n" - "ld1b { z20.b }, p1/Z, [x22, x26]\n" - "ld1b { z24.b }, p1/Z, [x21, x26]\n" + "ld1b { z0.b }, p4/Z, [x23, x9]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "ld1b { z31.b }, p4/Z, [x22, x9]\n" + "ld1b { z23.b }, p4/Z, [x21, x9]\n" + "ld1b { z30.b }, p4/Z, [x20, x9]\n" + "ld1b { z18.b }, p3/Z, [x23, x28]\n" + "ld1b { z29.b }, p3/Z, [x22, x28]\n" + "ld1b { z22.b }, p3/Z, [x21, x28]\n" + "ld1b { z28.b }, p3/Z, [x20, x28]\n" + "ld1b { z17.b }, p2/Z, [x23, x27]\n" + "ld1b { z27.b }, p2/Z, [x22, x27]\n" + "ld1b { z21.b }, p2/Z, [x21, x27]\n" + "ld1b { z26.b }, p2/Z, [x20, x27]\n" + "ld1b { z16.b }, p1/Z, [x23, x26]\n" + "ld1b { z25.b }, p1/Z, [x22, x26]\n" + "ld1b { z20.b }, p1/Z, [x21, x26]\n" + "ld1b { z24.b }, p1/Z, [x20, x26]\n" "beq 3f\n" "2:" // 4-vectors of channels: 4 inputs loop "movprfx z19, z0\n umax z19.b, p0/M, z19.b, z31.b\n" "umax z23.b, p0/M, z23.b, z30.b\n" - "ldp x24, x23, [x20, #0x0]\n" + "ldp x23, x22, [x24, #0x0]\n" "subs x25, x25, #0x1\n" "umax z18.b, p0/M, z18.b, z29.b\n" "umax z22.b, p0/M, z22.b, z28.b\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" "umax z17.b, p0/M, z17.b, z27.b\n" "umax z21.b, p0/M, z21.b, z26.b\n" - "ld1b { z0.b }, p4/Z, [x24, x9]\n" + "ld1b { z0.b }, p4/Z, [x23, x9]\n" "umax z16.b, p0/M, z16.b, z25.b\n" "umax z20.b, p0/M, z20.b, z24.b\n" - "ld1b { z31.b }, p4/Z, [x23, x9]\n" + "ld1b { z31.b }, p4/Z, [x22, x9]\n" "umax z19.b, p0/M, z19.b, z23.b\n" "umax z18.b, p0/M, z18.b, z22.b\n" - "ld1b { z23.b }, p4/Z, [x22, x9]\n" + "ld1b { z23.b }, p4/Z, [x21, x9]\n" "umax z17.b, p0/M, z17.b, z21.b\n" "umax z16.b, p0/M, z16.b, z20.b\n" - "ld1b { z30.b }, p4/Z, [x21, x9]\n" + "ld1b { z30.b }, p4/Z, [x20, x9]\n" "umax z4.b, p0/M, z4.b, z19.b\n" "umax z3.b, p0/M, z3.b, z18.b\n" - "ld1b { z18.b }, p3/Z, [x24, x28]\n" + "ld1b { z18.b }, p3/Z, [x23, x28]\n" "umax z2.b, p0/M, z2.b, z17.b\n" "umax z1.b, p0/M, z1.b, z16.b\n" - "ld1b { z29.b }, p3/Z, [x23, x28]\n" - "ld1b { z22.b }, p3/Z, [x22, x28]\n" - "ld1b { z28.b }, p3/Z, [x21, x28]\n" - "ld1b { z17.b }, p2/Z, [x24, x27]\n" - "ld1b { z27.b }, p2/Z, [x23, x27]\n" - "ld1b { z21.b }, p2/Z, [x22, x27]\n" - "ld1b { z26.b }, p2/Z, [x21, x27]\n" - "ld1b { z16.b }, p1/Z, [x24, x26]\n" - "ld1b { z25.b }, p1/Z, [x23, x26]\n" - "ld1b { z20.b }, p1/Z, [x22, x26]\n" - "ld1b { z24.b }, p1/Z, [x21, x26]\n" + "ld1b { z29.b }, p3/Z, [x22, x28]\n" + "ld1b { z22.b }, p3/Z, [x21, x28]\n" + "ld1b { z28.b }, p3/Z, [x20, x28]\n" + "ld1b { z17.b }, p2/Z, [x23, x27]\n" + "ld1b { z27.b }, p2/Z, [x22, x27]\n" + "ld1b { z21.b }, p2/Z, [x21, x27]\n" + "ld1b { z26.b }, p2/Z, [x20, x27]\n" + "ld1b { z16.b }, p1/Z, [x23, x26]\n" + "ld1b { z25.b }, p1/Z, [x22, x26]\n" + "ld1b { z20.b }, p1/Z, [x21, x26]\n" + "ld1b { z24.b }, p1/Z, [x20, x26]\n" "bgt 2b\n" "3:" // 4-vectors of channels: 4 inputs tail "movprfx z19, z0\n umax z19.b, p0/M, z19.b, z31.b\n" @@ -138,15 +139,15 @@ void sme_u8_nhwc_max_generic_depthfirst_impl( "ands x21, %x[n_valid_cells], #0x3\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x24, [x20], #0x8\n" - "ld1b { z0.b }, p4/Z, [x24, x9]\n" + "ldr x20, [x24], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x9]\n" "subs x21, x21, #0x1\n" - "umax z4.b, p0/M, z4.b, z0.b\n" - "ld1b { z18.b }, p3/Z, [x24, x28]\n" - "umax z3.b, p0/M, z3.b, z18.b\n" - "ld1b { z17.b }, p2/Z, [x24, x27]\n" - "umax z2.b, p0/M, z2.b, z17.b\n" - "ld1b { z16.b }, p1/Z, [x24, x26]\n" + "umax z4.b, p0/M, z4.b, z16.b\n" + "ld1b { z16.b }, p3/Z, [x20, x28]\n" + "umax z3.b, p0/M, z3.b, z16.b\n" + "ld1b { z16.b }, p2/Z, [x20, x27]\n" + "umax z2.b, p0/M, z2.b, z16.b\n" + "ld1b { z16.b }, p1/Z, [x20, x26]\n" "umax z1.b, p0/M, z1.b, z16.b\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End @@ -166,44 +167,44 @@ void sme_u8_nhwc_max_generic_depthfirst_impl( "8:" // Single vector of channels: Loop "lsr x25, %x[n_valid_cells], #0x2\n" "mov z4.b, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "cbz x25, 11f\n" - "ldp x24, x23, [x20, #0x0]\n" + "ldp x20, x22, [x24, #0x0]\n" "subs x25, x25, #0x1\n" - "ld1b { z0.b }, p4/Z, [x24, x9]\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" - "ld1b { z31.b }, p4/Z, [x23, x9]\n" - "ld1b { z23.b }, p4/Z, [x22, x9]\n" - "ld1b { z30.b }, p4/Z, [x21, x9]\n" + "ld1b { z0.b }, p4/Z, [x20, x9]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "ld1b { z31.b }, p4/Z, [x22, x9]\n" + "ld1b { z23.b }, p4/Z, [x21, x9]\n" + "ld1b { z30.b }, p4/Z, [x20, x9]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 4 inputs loop - "movprfx z19, z0\n umax z19.b, p0/M, z19.b, z31.b\n" - "umax z23.b, p0/M, z23.b, z30.b\n" - "ldp x24, x23, [x20, #0x0]\n" + "movprfx z16, z0\n umax z16.b, p0/M, z16.b, z31.b\n" + "movprfx z17, z23\n umax z17.b, p0/M, z17.b, z30.b\n" + "ldp x23, x22, [x24, #0x0]\n" "subs x25, x25, #0x1\n" - "umax z19.b, p0/M, z19.b, z23.b\n" - "ldp x22, x21, [x20, #0x10]\n" - "umax z4.b, p0/M, z4.b, z19.b\n" - "add x20, x20, #0x20\n" - "ld1b { z0.b }, p4/Z, [x24, x9]\n" - "ld1b { z31.b }, p4/Z, [x23, x9]\n" - "ld1b { z23.b }, p4/Z, [x22, x9]\n" - "ld1b { z30.b }, p4/Z, [x21, x9]\n" + "umax z16.b, p0/M, z16.b, z17.b\n" + "ldp x21, x20, [x24, #0x10]\n" + "umax z4.b, p0/M, z4.b, z16.b\n" + "add x24, x24, #0x20\n" + "ld1b { z0.b }, p4/Z, [x23, x9]\n" + "ld1b { z31.b }, p4/Z, [x22, x9]\n" + "ld1b { z23.b }, p4/Z, [x21, x9]\n" + "ld1b { z30.b }, p4/Z, [x20, x9]\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 4 inputs tail - "movprfx z19, z0\n umax z19.b, p0/M, z19.b, z31.b\n" - "umax z23.b, p0/M, z23.b, z30.b\n" - "umax z19.b, p0/M, z19.b, z23.b\n" - "umax z4.b, p0/M, z4.b, z19.b\n" + "movprfx z16, z0\n umax z16.b, p0/M, z16.b, z31.b\n" + "movprfx z17, z23\n umax z17.b, p0/M, z17.b, z30.b\n" + "umax z16.b, p0/M, z16.b, z17.b\n" + "umax z4.b, p0/M, z4.b, z16.b\n" "11:" // Single vector of channels: Loop: After loop "ands x21, %x[n_valid_cells], #0x3\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x24, [x20], #0x8\n" - "ld1b { z0.b }, p4/Z, [x24, x9]\n" + "ldr x20, [x24], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x9]\n" "subs x21, x21, #0x1\n" - "umax z4.b, p0/M, z4.b, z0.b\n" + "umax z4.b, p0/M, z4.b, z16.b\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End "st1b { z4.b }, p4, [%x[outptr], x9]\n" diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8q_nhwc_avg_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8q_nhwc_avg_generic_depthfirst.hpp index 2930993800..bd30a32828 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8q_nhwc_avg_generic_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8q_nhwc_avg_generic_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Arm Limited. + * Copyright (c) 2022-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -26,6 +26,8 @@ #pragma once +#if defined(ARM_COMPUTE_ENABLE_SME) + namespace arm_conv { namespace pooling { @@ -40,3 +42,5 @@ struct sme_u8q_nhwc_avg_generic_depthfirst : IGenericDepthfirstStrategy<uint8_t, } // namespace pooling } // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8q_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8q_nhwc_avg_generic_depthfirst/generic.cpp index a2fe7a301d..52c52ccdb9 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8q_nhwc_avg_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8q_nhwc_avg_generic_depthfirst/generic.cpp @@ -22,14 +22,15 @@ * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SME) - -#include "src/core/NEON/kernels/assembly/pooling.hpp" +#include "pooling.hpp" #include <cstdint> +#include <cstddef> #include <cstring> #include <cmath> +#if defined(ARM_COMPUTE_ENABLE_SME) + namespace arm_conv { namespace pooling { @@ -136,7 +137,7 @@ void sme_u8q_nhwc_avg_generic_depthfirst_impl( "mov z13.d, z15.d\n" "mov z12.d, z15.d\n" "mov z11.d, z15.d\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "mov z10.d, z15.d\n" "mov z9.d, z15.d\n" "mov z8.d, z15.d\n" @@ -149,48 +150,48 @@ void sme_u8q_nhwc_avg_generic_depthfirst_impl( "mov z1.d, z15.d\n" "mov z0.d, z15.d\n" "cbz x23, 4f\n" - "ldp x22, x21, [x20, #0x0]\n" + "ldp x21, x20, [x22, #0x0]\n" "subs x23, x23, #0x1\n" - "add x20, x20, #0x10\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" - "ld1b { z30.b }, p4/Z, [x21, x27]\n" - "ld1b { z29.b }, p3/Z, [x22, x26]\n" - "ld1b { z28.b }, p3/Z, [x21, x26]\n" - "ld1b { z27.b }, p2/Z, [x22, x25]\n" - "ld1b { z26.b }, p2/Z, [x21, x25]\n" - "ld1b { z25.b }, p1/Z, [x22, x24]\n" - "ld1b { z24.b }, p1/Z, [x21, x24]\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" + "ld1b { z29.b }, p3/Z, [x21, x26]\n" + "ld1b { z28.b }, p3/Z, [x20, x26]\n" + "ld1b { z27.b }, p2/Z, [x21, x25]\n" + "ld1b { z26.b }, p2/Z, [x20, x25]\n" + "ld1b { z25.b }, p1/Z, [x21, x24]\n" + "ld1b { z24.b }, p1/Z, [x20, x24]\n" "beq 3f\n" "2:" // 4-vectors of channels: 2 inputs loop ".inst 0x455e0bf7 // uaddlb z23.h, z31.b, z30.b\n" ".inst 0x455e0ff6 // uaddlt z22.h, z31.b, z30.b\n" - "ldp x22, x21, [x20, #0x0]\n" + "ldp x21, x20, [x22, #0x0]\n" "subs x23, x23, #0x1\n" ".inst 0x455c0bb5 // uaddlb z21.h, z29.b, z28.b\n" ".inst 0x455c0fb4 // uaddlt z20.h, z29.b, z28.b\n" - "add x20, x20, #0x10\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" ".inst 0x455a0b73 // uaddlb z19.h, z27.b, z26.b\n" ".inst 0x455a0f72 // uaddlt z18.h, z27.b, z26.b\n" - "ld1b { z30.b }, p4/Z, [x21, x27]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" ".inst 0x45580b31 // uaddlb z17.h, z25.b, z24.b\n" ".inst 0x45580f30 // uaddlt z16.h, z25.b, z24.b\n" - "ld1b { z29.b }, p3/Z, [x22, x26]\n" + "ld1b { z29.b }, p3/Z, [x21, x26]\n" ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" - "ld1b { z28.b }, p3/Z, [x21, x26]\n" + "ld1b { z28.b }, p3/Z, [x20, x26]\n" ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" - "ld1b { z27.b }, p2/Z, [x22, x25]\n" + "ld1b { z27.b }, p2/Z, [x21, x25]\n" ".inst 0x4595496b // uaddwb z11.s, z11.s, z21.h\n" ".inst 0x45954d4a // uaddwt z10.s, z10.s, z21.h\n" - "ld1b { z26.b }, p2/Z, [x21, x25]\n" + "ld1b { z26.b }, p2/Z, [x20, x25]\n" ".inst 0x45944929 // uaddwb z9.s, z9.s, z20.h\n" ".inst 0x45944d08 // uaddwt z8.s, z8.s, z20.h\n" - "ld1b { z25.b }, p1/Z, [x22, x24]\n" + "ld1b { z25.b }, p1/Z, [x21, x24]\n" ".inst 0x459348e7 // uaddwb z7.s, z7.s, z19.h\n" ".inst 0x45934cc6 // uaddwt z6.s, z6.s, z19.h\n" - "ld1b { z24.b }, p1/Z, [x21, x24]\n" + "ld1b { z24.b }, p1/Z, [x20, x24]\n" ".inst 0x459248a5 // uaddwb z5.s, z5.s, z18.h\n" ".inst 0x45924c84 // uaddwt z4.s, z4.s, z18.h\n" ".inst 0x45914863 // uaddwb z3.s, z3.s, z17.h\n" @@ -227,20 +228,20 @@ void sme_u8q_nhwc_avg_generic_depthfirst_impl( "ands x21, %x[n_valid_cells], #0x1\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x22, [x20], #0x8\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" - ".inst 0x4508abf7 // ushllb z23.h, z31.b, #0x0\n" - ".inst 0x4508aff6 // ushllt z22.h, z31.b, #0x0\n" - "ld1b { z29.b }, p3/Z, [x22, x26]\n" - ".inst 0x4508abb5 // ushllb z21.h, z29.b, #0x0\n" - ".inst 0x4508afb4 // ushllt z20.h, z29.b, #0x0\n" + "ldr x20, [x22], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x27]\n" + ".inst 0x4508aa17 // ushllb z23.h, z16.b, #0x0\n" + ".inst 0x4508ae16 // ushllt z22.h, z16.b, #0x0\n" + "ld1b { z16.b }, p3/Z, [x20, x26]\n" + ".inst 0x4508aa15 // ushllb z21.h, z16.b, #0x0\n" + ".inst 0x4508ae14 // ushllt z20.h, z16.b, #0x0\n" "subs x21, x21, #0x1\n" - "ld1b { z27.b }, p2/Z, [x22, x25]\n" - ".inst 0x4508ab73 // ushllb z19.h, z27.b, #0x0\n" - ".inst 0x4508af72 // ushllt z18.h, z27.b, #0x0\n" - "ld1b { z25.b }, p1/Z, [x22, x24]\n" - ".inst 0x4508ab31 // ushllb z17.h, z25.b, #0x0\n" - ".inst 0x4508af30 // ushllt z16.h, z25.b, #0x0\n" + "ld1b { z16.b }, p2/Z, [x20, x25]\n" + ".inst 0x4508aa13 // ushllb z19.h, z16.b, #0x0\n" + ".inst 0x4508ae12 // ushllt z18.h, z16.b, #0x0\n" + "ld1b { z16.b }, p1/Z, [x20, x24]\n" + ".inst 0x4508aa11 // ushllb z17.h, z16.b, #0x0\n" + ".inst 0x4508ae10 // ushllt z16.h, z16.b, #0x0\n" ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" @@ -393,61 +394,61 @@ void sme_u8q_nhwc_avg_generic_depthfirst_impl( "mov z14.d, z15.d\n" "mov z13.d, z15.d\n" "mov z12.d, z15.d\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "cbz x23, 11f\n" - "ldp x22, x21, [x20, #0x0]\n" + "ldp x21, x20, [x22, #0x0]\n" "subs x23, x23, #0x1\n" - "add x20, x20, #0x10\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" - "ld1b { z30.b }, p4/Z, [x21, x27]\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 2 inputs loop - ".inst 0x455e0bf7 // uaddlb z23.h, z31.b, z30.b\n" - ".inst 0x455e0ff6 // uaddlt z22.h, z31.b, z30.b\n" - "ldp x22, x21, [x20, #0x0]\n" + ".inst 0x455e0bf1 // uaddlb z17.h, z31.b, z30.b\n" + ".inst 0x455e0ff0 // uaddlt z16.h, z31.b, z30.b\n" + "ldp x21, x20, [x22, #0x0]\n" "subs x23, x23, #0x1\n" - ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" - ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" - "add x20, x20, #0x10\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" - ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" - ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" - "ld1b { z30.b }, p4/Z, [x21, x27]\n" + ".inst 0x459149ef // uaddwb z15.s, z15.s, z17.h\n" + ".inst 0x45914dce // uaddwt z14.s, z14.s, z17.h\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + ".inst 0x459049ad // uaddwb z13.s, z13.s, z16.h\n" + ".inst 0x45904d8c // uaddwt z12.s, z12.s, z16.h\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 2 inputs tail - ".inst 0x455e0bf7 // uaddlb z23.h, z31.b, z30.b\n" - ".inst 0x455e0ff6 // uaddlt z22.h, z31.b, z30.b\n" - ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" - ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" - ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" - ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" + ".inst 0x455e0bf1 // uaddlb z17.h, z31.b, z30.b\n" + ".inst 0x455e0ff0 // uaddlt z16.h, z31.b, z30.b\n" + ".inst 0x459149ef // uaddwb z15.s, z15.s, z17.h\n" + ".inst 0x45914dce // uaddwt z14.s, z14.s, z17.h\n" + ".inst 0x459049ad // uaddwb z13.s, z13.s, z16.h\n" + ".inst 0x45904d8c // uaddwt z12.s, z12.s, z16.h\n" "11:" // Single vector of channels: Loop: After loop "ands x21, %x[n_valid_cells], #0x1\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x22, [x20], #0x8\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" - ".inst 0x4508abf7 // ushllb z23.h, z31.b, #0x0\n" - ".inst 0x4508aff6 // ushllt z22.h, z31.b, #0x0\n" + "ldr x20, [x22], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x27]\n" + ".inst 0x4508aa11 // ushllb z17.h, z16.b, #0x0\n" + ".inst 0x4508ae10 // ushllt z16.h, z16.b, #0x0\n" "subs x21, x21, #0x1\n" - ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" - ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" - ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" - ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" + ".inst 0x459149ef // uaddwb z15.s, z15.s, z17.h\n" + ".inst 0x45914dce // uaddwt z14.s, z14.s, z17.h\n" + ".inst 0x459049ad // uaddwb z13.s, z13.s, z16.h\n" + ".inst 0x45904d8c // uaddwt z12.s, z12.s, z16.h\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End - "ld1rw { z19.s }, p0/Z, [%x[left_shift]]\n" - ".inst 0x4482826f // srshl z15.s, p0/M, z15.s, z19.s\n" - ".inst 0x4482826e // srshl z14.s, p0/M, z14.s, z19.s\n" + "ld1rw { z16.s }, p0/Z, [%x[left_shift]]\n" + ".inst 0x4482820f // srshl z15.s, p0/M, z15.s, z16.s\n" + ".inst 0x4482820e // srshl z14.s, p0/M, z14.s, z16.s\n" "add x20, %x[quant_params], %[offsetof_qp_output_offset]\n" - ".inst 0x4482826d // srshl z13.s, p0/M, z13.s, z19.s\n" - ".inst 0x4482826c // srshl z12.s, p0/M, z12.s, z19.s\n" - "ld1rw { z18.s }, p0/Z, [%x[combined_rescale_value]]\n" - ".inst 0x04b275ef // sqrdmulh z15.s, z15.s, z18.s\n" - ".inst 0x04b275ce // sqrdmulh z14.s, z14.s, z18.s\n" + ".inst 0x4482820d // srshl z13.s, p0/M, z13.s, z16.s\n" + ".inst 0x4482820c // srshl z12.s, p0/M, z12.s, z16.s\n" + "ld1rw { z16.s }, p0/Z, [%x[combined_rescale_value]]\n" + ".inst 0x04b075ef // sqrdmulh z15.s, z15.s, z16.s\n" + ".inst 0x04b075ce // sqrdmulh z14.s, z14.s, z16.s\n" "ld1rw { z17.s }, p0/Z, [%x[right_shift]]\n" - ".inst 0x04b275ad // sqrdmulh z13.s, z13.s, z18.s\n" - ".inst 0x04b2758c // sqrdmulh z12.s, z12.s, z18.s\n" + ".inst 0x04b075ad // sqrdmulh z13.s, z13.s, z16.s\n" + ".inst 0x04b0758c // sqrdmulh z12.s, z12.s, z16.s\n" "ld1rw { z16.s }, p0/Z, [x20]\n" ".inst 0x4482822f // srshl z15.s, p0/M, z15.s, z17.s\n" ".inst 0x4482822e // srshl z14.s, p0/M, z14.s, z17.s\n" @@ -457,19 +458,19 @@ void sme_u8q_nhwc_avg_generic_depthfirst_impl( "add z14.s, z14.s, z16.s\n" "add z13.s, z13.s, z16.s\n" "add z12.s, z12.s, z16.s\n" - "mov z16.s, #0x0\n" - "mov z19.s, #0xff\n" - "smax z15.s, p0/M, z15.s, z16.s\n" - "smax z14.s, p0/M, z14.s, z16.s\n" - "smax z13.s, p0/M, z13.s, z16.s\n" - "smax z12.s, p0/M, z12.s, z16.s\n" - "smin z15.s, p0/M, z15.s, z19.s\n" - "smin z14.s, p0/M, z14.s, z19.s\n" - "trn1 z23.h, z15.h, z14.h\n" - "smin z13.s, p0/M, z13.s, z19.s\n" - "smin z12.s, p0/M, z12.s, z19.s\n" + "mov z17.s, #0x0\n" + "mov z16.s, #0xff\n" + "smax z15.s, p0/M, z15.s, z17.s\n" + "smax z14.s, p0/M, z14.s, z17.s\n" + "smax z13.s, p0/M, z13.s, z17.s\n" + "smax z12.s, p0/M, z12.s, z17.s\n" + "smin z15.s, p0/M, z15.s, z16.s\n" + "smin z14.s, p0/M, z14.s, z16.s\n" + "trn1 z17.h, z15.h, z14.h\n" + "smin z13.s, p0/M, z13.s, z16.s\n" + "smin z12.s, p0/M, z12.s, z16.s\n" "trn1 z16.h, z13.h, z12.h\n" - "trn1 z16.b, z23.b, z16.b\n" + "trn1 z16.b, z17.b, z16.b\n" "st1b { z16.b }, p4, [%x[outptr], x27]\n" "incb x27\n" "whilelt p4.b, x27, %x[n_channels]\n" diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8q_nhwc_max_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8q_nhwc_max_generic_depthfirst.hpp index d7bf6cbd08..69d627c047 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8q_nhwc_max_generic_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8q_nhwc_max_generic_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Arm Limited. + * Copyright (c) 2022-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -26,6 +26,8 @@ #pragma once +#if defined(ARM_COMPUTE_ENABLE_SME) + namespace arm_conv { namespace pooling { @@ -40,3 +42,5 @@ struct sme_u8q_nhwc_max_generic_depthfirst : IGenericDepthfirstStrategy<uint8_t, } // namespace pooling } // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8q_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8q_nhwc_max_generic_depthfirst/generic.cpp index d050cd014f..c8e8e7d399 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8q_nhwc_max_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8q_nhwc_max_generic_depthfirst/generic.cpp @@ -22,10 +22,11 @@ * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SME) - -#include "src/core/NEON/kernels/assembly/pooling.hpp" +#include "pooling.hpp" #include <cstdint> +#include <cstddef> + +#if defined(ARM_COMPUTE_ENABLE_SME) namespace arm_conv { namespace pooling { @@ -56,68 +57,68 @@ void sme_u8q_nhwc_max_generic_depthfirst_impl( "lsr x25, %x[n_valid_cells], #0x2\n" "mov z5.b, #0x0\n" "mov z3.b, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "mov z2.b, #0x0\n" "mov z1.b, #0x0\n" "cbz x25, 4f\n" - "ldp x24, x23, [x20, #0x0]\n" + "ldp x23, x22, [x24, #0x0]\n" "subs x25, x25, #0x1\n" - "ld1b { z0.b }, p4/Z, [x24, x9]\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" - "ld1b { z31.b }, p4/Z, [x23, x9]\n" - "ld1b { z23.b }, p4/Z, [x22, x9]\n" - "ld1b { z30.b }, p4/Z, [x21, x9]\n" - "ld1b { z18.b }, p3/Z, [x24, x28]\n" - "ld1b { z29.b }, p3/Z, [x23, x28]\n" - "ld1b { z22.b }, p3/Z, [x22, x28]\n" - "ld1b { z28.b }, p3/Z, [x21, x28]\n" - "ld1b { z17.b }, p2/Z, [x24, x27]\n" - "ld1b { z27.b }, p2/Z, [x23, x27]\n" - "ld1b { z21.b }, p2/Z, [x22, x27]\n" - "ld1b { z26.b }, p2/Z, [x21, x27]\n" - "ld1b { z16.b }, p1/Z, [x24, x26]\n" - "ld1b { z25.b }, p1/Z, [x23, x26]\n" - "ld1b { z20.b }, p1/Z, [x22, x26]\n" - "ld1b { z24.b }, p1/Z, [x21, x26]\n" + "ld1b { z0.b }, p4/Z, [x23, x9]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "ld1b { z31.b }, p4/Z, [x22, x9]\n" + "ld1b { z23.b }, p4/Z, [x21, x9]\n" + "ld1b { z30.b }, p4/Z, [x20, x9]\n" + "ld1b { z18.b }, p3/Z, [x23, x28]\n" + "ld1b { z29.b }, p3/Z, [x22, x28]\n" + "ld1b { z22.b }, p3/Z, [x21, x28]\n" + "ld1b { z28.b }, p3/Z, [x20, x28]\n" + "ld1b { z17.b }, p2/Z, [x23, x27]\n" + "ld1b { z27.b }, p2/Z, [x22, x27]\n" + "ld1b { z21.b }, p2/Z, [x21, x27]\n" + "ld1b { z26.b }, p2/Z, [x20, x27]\n" + "ld1b { z16.b }, p1/Z, [x23, x26]\n" + "ld1b { z25.b }, p1/Z, [x22, x26]\n" + "ld1b { z20.b }, p1/Z, [x21, x26]\n" + "ld1b { z24.b }, p1/Z, [x20, x26]\n" "beq 3f\n" "2:" // 4-vectors of channels: 4 inputs loop "movprfx z19, z0\n umax z19.b, p0/M, z19.b, z31.b\n" "umax z23.b, p0/M, z23.b, z30.b\n" - "ldp x24, x23, [x20, #0x0]\n" + "ldp x23, x22, [x24, #0x0]\n" "subs x25, x25, #0x1\n" "umax z18.b, p0/M, z18.b, z29.b\n" "umax z22.b, p0/M, z22.b, z28.b\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" "umax z17.b, p0/M, z17.b, z27.b\n" "umax z21.b, p0/M, z21.b, z26.b\n" - "ld1b { z0.b }, p4/Z, [x24, x9]\n" + "ld1b { z0.b }, p4/Z, [x23, x9]\n" "umax z16.b, p0/M, z16.b, z25.b\n" "umax z20.b, p0/M, z20.b, z24.b\n" - "ld1b { z31.b }, p4/Z, [x23, x9]\n" + "ld1b { z31.b }, p4/Z, [x22, x9]\n" "umax z19.b, p0/M, z19.b, z23.b\n" "umax z18.b, p0/M, z18.b, z22.b\n" - "ld1b { z23.b }, p4/Z, [x22, x9]\n" + "ld1b { z23.b }, p4/Z, [x21, x9]\n" "umax z17.b, p0/M, z17.b, z21.b\n" "umax z16.b, p0/M, z16.b, z20.b\n" - "ld1b { z30.b }, p4/Z, [x21, x9]\n" + "ld1b { z30.b }, p4/Z, [x20, x9]\n" "umax z5.b, p0/M, z5.b, z19.b\n" "umax z3.b, p0/M, z3.b, z18.b\n" - "ld1b { z18.b }, p3/Z, [x24, x28]\n" + "ld1b { z18.b }, p3/Z, [x23, x28]\n" "umax z2.b, p0/M, z2.b, z17.b\n" "umax z1.b, p0/M, z1.b, z16.b\n" - "ld1b { z29.b }, p3/Z, [x23, x28]\n" - "ld1b { z22.b }, p3/Z, [x22, x28]\n" - "ld1b { z28.b }, p3/Z, [x21, x28]\n" - "ld1b { z17.b }, p2/Z, [x24, x27]\n" - "ld1b { z27.b }, p2/Z, [x23, x27]\n" - "ld1b { z21.b }, p2/Z, [x22, x27]\n" - "ld1b { z26.b }, p2/Z, [x21, x27]\n" - "ld1b { z16.b }, p1/Z, [x24, x26]\n" - "ld1b { z25.b }, p1/Z, [x23, x26]\n" - "ld1b { z20.b }, p1/Z, [x22, x26]\n" - "ld1b { z24.b }, p1/Z, [x21, x26]\n" + "ld1b { z29.b }, p3/Z, [x22, x28]\n" + "ld1b { z22.b }, p3/Z, [x21, x28]\n" + "ld1b { z28.b }, p3/Z, [x20, x28]\n" + "ld1b { z17.b }, p2/Z, [x23, x27]\n" + "ld1b { z27.b }, p2/Z, [x22, x27]\n" + "ld1b { z21.b }, p2/Z, [x21, x27]\n" + "ld1b { z26.b }, p2/Z, [x20, x27]\n" + "ld1b { z16.b }, p1/Z, [x23, x26]\n" + "ld1b { z25.b }, p1/Z, [x22, x26]\n" + "ld1b { z20.b }, p1/Z, [x21, x26]\n" + "ld1b { z24.b }, p1/Z, [x20, x26]\n" "bgt 2b\n" "3:" // 4-vectors of channels: 4 inputs tail "movprfx z19, z0\n umax z19.b, p0/M, z19.b, z31.b\n" @@ -140,15 +141,15 @@ void sme_u8q_nhwc_max_generic_depthfirst_impl( "ands x21, %x[n_valid_cells], #0x3\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x24, [x20], #0x8\n" - "ld1b { z0.b }, p4/Z, [x24, x9]\n" + "ldr x20, [x24], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x9]\n" "subs x21, x21, #0x1\n" - "umax z5.b, p0/M, z5.b, z0.b\n" - "ld1b { z18.b }, p3/Z, [x24, x28]\n" - "umax z3.b, p0/M, z3.b, z18.b\n" - "ld1b { z17.b }, p2/Z, [x24, x27]\n" - "umax z2.b, p0/M, z2.b, z17.b\n" - "ld1b { z16.b }, p1/Z, [x24, x26]\n" + "umax z5.b, p0/M, z5.b, z16.b\n" + "ld1b { z16.b }, p3/Z, [x20, x28]\n" + "umax z3.b, p0/M, z3.b, z16.b\n" + "ld1b { z16.b }, p2/Z, [x20, x27]\n" + "umax z2.b, p0/M, z2.b, z16.b\n" + "ld1b { z16.b }, p1/Z, [x20, x26]\n" "umax z1.b, p0/M, z1.b, z16.b\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End @@ -313,92 +314,92 @@ void sme_u8q_nhwc_max_generic_depthfirst_impl( "8:" // Single vector of channels: Loop "lsr x25, %x[n_valid_cells], #0x2\n" "mov z5.b, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "cbz x25, 11f\n" - "ldp x24, x23, [x20, #0x0]\n" + "ldp x20, x22, [x24, #0x0]\n" "subs x25, x25, #0x1\n" - "ld1b { z0.b }, p4/Z, [x24, x9]\n" - "ldp x22, x21, [x20, #0x10]\n" - "add x20, x20, #0x20\n" - "ld1b { z31.b }, p4/Z, [x23, x9]\n" - "ld1b { z23.b }, p4/Z, [x22, x9]\n" - "ld1b { z30.b }, p4/Z, [x21, x9]\n" + "ld1b { z0.b }, p4/Z, [x20, x9]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "ld1b { z31.b }, p4/Z, [x22, x9]\n" + "ld1b { z23.b }, p4/Z, [x21, x9]\n" + "ld1b { z30.b }, p4/Z, [x20, x9]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 4 inputs loop - "movprfx z19, z0\n umax z19.b, p0/M, z19.b, z31.b\n" - "umax z23.b, p0/M, z23.b, z30.b\n" - "ldp x24, x23, [x20, #0x0]\n" + "movprfx z16, z0\n umax z16.b, p0/M, z16.b, z31.b\n" + "movprfx z17, z23\n umax z17.b, p0/M, z17.b, z30.b\n" + "ldp x23, x22, [x24, #0x0]\n" "subs x25, x25, #0x1\n" - "umax z19.b, p0/M, z19.b, z23.b\n" - "ldp x22, x21, [x20, #0x10]\n" - "umax z5.b, p0/M, z5.b, z19.b\n" - "add x20, x20, #0x20\n" - "ld1b { z0.b }, p4/Z, [x24, x9]\n" - "ld1b { z31.b }, p4/Z, [x23, x9]\n" - "ld1b { z23.b }, p4/Z, [x22, x9]\n" - "ld1b { z30.b }, p4/Z, [x21, x9]\n" + "umax z16.b, p0/M, z16.b, z17.b\n" + "ldp x21, x20, [x24, #0x10]\n" + "umax z5.b, p0/M, z5.b, z16.b\n" + "add x24, x24, #0x20\n" + "ld1b { z0.b }, p4/Z, [x23, x9]\n" + "ld1b { z31.b }, p4/Z, [x22, x9]\n" + "ld1b { z23.b }, p4/Z, [x21, x9]\n" + "ld1b { z30.b }, p4/Z, [x20, x9]\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 4 inputs tail - "movprfx z19, z0\n umax z19.b, p0/M, z19.b, z31.b\n" - "umax z23.b, p0/M, z23.b, z30.b\n" - "umax z19.b, p0/M, z19.b, z23.b\n" - "umax z5.b, p0/M, z5.b, z19.b\n" + "movprfx z16, z0\n umax z16.b, p0/M, z16.b, z31.b\n" + "movprfx z17, z23\n umax z17.b, p0/M, z17.b, z30.b\n" + "umax z16.b, p0/M, z16.b, z17.b\n" + "umax z5.b, p0/M, z5.b, z16.b\n" "11:" // Single vector of channels: Loop: After loop "ands x21, %x[n_valid_cells], #0x3\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x24, [x20], #0x8\n" - "ld1b { z0.b }, p4/Z, [x24, x9]\n" + "ldr x20, [x24], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x9]\n" "subs x21, x21, #0x1\n" - "umax z5.b, p0/M, z5.b, z0.b\n" + "umax z5.b, p0/M, z5.b, z16.b\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End "add x20, %x[quant_params], %[offsetof_qp_input_offset]\n" - "ld1rw { z4.s }, p0/Z, [x20]\n" - ".inst 0x4508a8b7 // ushllb z23.h, z5.b, #0x0\n" - ".inst 0x4508acb9 // ushllt z25.h, z5.b, #0x0\n" - "neg z4.s, p0/M, z4.s\n" - ".inst 0x45974081 // saddwb z1.s, z4.s, z23.h\n" + "ld1rw { z18.s }, p0/Z, [x20]\n" + ".inst 0x4508a8b1 // ushllb z17.h, z5.b, #0x0\n" + ".inst 0x4508acb0 // ushllt z16.h, z5.b, #0x0\n" + "neg z18.s, p0/M, z18.s\n" + ".inst 0x45914257 // saddwb z23.s, z18.s, z17.h\n" "add x20, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n" - "ld1rw { z3.s }, p0/Z, [x20]\n" - ".inst 0x45974497 // saddwt z23.s, z4.s, z23.h\n" - ".inst 0x45994080 // saddwb z0.s, z4.s, z25.h\n" + "ld1rw { z22.s }, p0/Z, [x20]\n" + ".inst 0x45914655 // saddwt z21.s, z18.s, z17.h\n" + ".inst 0x45904254 // saddwb z20.s, z18.s, z16.h\n" "add x20, %x[quant_params], %[offsetof_qp_per_layer_mul]\n" - "ld1rw { z2.s }, p0/Z, [x20]\n" - ".inst 0x4599449f // saddwt z31.s, z4.s, z25.h\n" - ".inst 0x44828061 // srshl z1.s, p0/M, z1.s, z3.s\n" - "add x20, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n" "ld1rw { z19.s }, p0/Z, [x20]\n" - ".inst 0x44828077 // srshl z23.s, p0/M, z23.s, z3.s\n" - ".inst 0x44828060 // srshl z0.s, p0/M, z0.s, z3.s\n" + ".inst 0x45904652 // saddwt z18.s, z18.s, z16.h\n" + ".inst 0x448282d7 // srshl z23.s, p0/M, z23.s, z22.s\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n" + "ld1rw { z17.s }, p0/Z, [x20]\n" + ".inst 0x448282d5 // srshl z21.s, p0/M, z21.s, z22.s\n" + ".inst 0x448282d4 // srshl z20.s, p0/M, z20.s, z22.s\n" "add x20, %x[quant_params], %[offsetof_qp_output_offset]\n" "ld1rw { z16.s }, p0/Z, [x20]\n" - ".inst 0x4482807f // srshl z31.s, p0/M, z31.s, z3.s\n" - ".inst 0x04a27421 // sqrdmulh z1.s, z1.s, z2.s\n" - ".inst 0x04a276f7 // sqrdmulh z23.s, z23.s, z2.s\n" - ".inst 0x04a27400 // sqrdmulh z0.s, z0.s, z2.s\n" - ".inst 0x04a277ff // sqrdmulh z31.s, z31.s, z2.s\n" - ".inst 0x44828261 // srshl z1.s, p0/M, z1.s, z19.s\n" - ".inst 0x44828277 // srshl z23.s, p0/M, z23.s, z19.s\n" - ".inst 0x44828260 // srshl z0.s, p0/M, z0.s, z19.s\n" - ".inst 0x4482827f // srshl z31.s, p0/M, z31.s, z19.s\n" - "add z1.s, z1.s, z16.s\n" + ".inst 0x448282d2 // srshl z18.s, p0/M, z18.s, z22.s\n" + ".inst 0x04b376f7 // sqrdmulh z23.s, z23.s, z19.s\n" + ".inst 0x04b376b5 // sqrdmulh z21.s, z21.s, z19.s\n" + ".inst 0x04b37694 // sqrdmulh z20.s, z20.s, z19.s\n" + ".inst 0x04b37652 // sqrdmulh z18.s, z18.s, z19.s\n" + ".inst 0x44828237 // srshl z23.s, p0/M, z23.s, z17.s\n" + ".inst 0x44828235 // srshl z21.s, p0/M, z21.s, z17.s\n" + ".inst 0x44828234 // srshl z20.s, p0/M, z20.s, z17.s\n" + ".inst 0x44828232 // srshl z18.s, p0/M, z18.s, z17.s\n" "add z23.s, z23.s, z16.s\n" - "add z0.s, z0.s, z16.s\n" - "add z31.s, z31.s, z16.s\n" - "mov z16.s, #0x0\n" - "mov z19.s, #0xff\n" - "smax z1.s, p0/M, z1.s, z16.s\n" - "smax z23.s, p0/M, z23.s, z16.s\n" - "smax z0.s, p0/M, z0.s, z16.s\n" - "smax z31.s, p0/M, z31.s, z16.s\n" - "smin z1.s, p0/M, z1.s, z19.s\n" - "smin z23.s, p0/M, z23.s, z19.s\n" - "smin z0.s, p0/M, z0.s, z19.s\n" - "trn1 z23.h, z1.h, z23.h\n" - "smin z31.s, p0/M, z31.s, z19.s\n" - "trn1 z16.h, z0.h, z31.h\n" - "trn1 z16.b, z23.b, z16.b\n" + "add z21.s, z21.s, z16.s\n" + "add z20.s, z20.s, z16.s\n" + "add z18.s, z18.s, z16.s\n" + "mov z17.s, #0x0\n" + "mov z16.s, #0xff\n" + "smax z23.s, p0/M, z23.s, z17.s\n" + "smax z21.s, p0/M, z21.s, z17.s\n" + "smax z20.s, p0/M, z20.s, z17.s\n" + "smax z18.s, p0/M, z18.s, z17.s\n" + "smin z23.s, p0/M, z23.s, z16.s\n" + "smin z21.s, p0/M, z21.s, z16.s\n" + "smin z20.s, p0/M, z20.s, z16.s\n" + "trn1 z17.h, z23.h, z21.h\n" + "smin z18.s, p0/M, z18.s, z16.s\n" + "trn1 z16.h, z20.h, z18.h\n" + "trn1 z16.b, z17.b, z16.b\n" "st1b { z16.b }, p4, [%x[outptr], x9]\n" "incb x9\n" "whilelt p4.b, x9, %x[n_channels]\n" diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp index 593fb58445..1ba78f3fba 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp @@ -88,8 +88,8 @@ void sve_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst_impl( "mov x20, #0x4\n" "ldr x4, [%x[args], %[offsetof_inptrs]]\n" "ldp x5, x6, [x21, #0x0]\n" - "whilelt p0.h, XZR, x20\n" - "whilelt p1.h, x3, x2\n" + "whilelt p2.h, XZR, x20\n" + "whilelt p0.h, x3, x2\n" "ldp x7, x8, [x21, #0x10]\n" "ldp x17, x16, [x4, #0x0]\n" "add x15, %x[args], %[offsetof_rescale]\n" @@ -101,25 +101,25 @@ void sve_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst_impl( "ldp x25, x24, [x4, #0x50]\n" "ldp x23, x22, [x4, #0x60]\n" "ldp x21, x20, [x4, #0x70]\n" - "ld1h { z7.h }, p1/Z, [x10, x3, LSL #1]\n" - "ld1h { z6.h }, p1/Z, [x9, x3, LSL #1]\n" - "ld1h { z5.h }, p1/Z, [x26, x3, LSL #1]\n" - "ld1h { z4.h }, p1/Z, [x25, x3, LSL #1]\n" - "ld1h { z3.h }, p1/Z, [x16, x3, LSL #1]\n" - "ld1h { z2.h }, p1/Z, [x13, x3, LSL #1]\n" - "ld1h { z1.h }, p1/Z, [x11, x3, LSL #1]\n" - "ld1h { z31.h }, p1/Z, [x27, x3, LSL #1]\n" - "ld1h { z30.h }, p1/Z, [x28, x3, LSL #1]\n" - "ld1h { z29.h }, p1/Z, [x24, x3, LSL #1]\n" - "ld1h { z28.h }, p1/Z, [x22, x3, LSL #1]\n" - "ld1h { z27.h }, p1/Z, [x21, x3, LSL #1]\n" - "ld1h { z26.h }, p1/Z, [x17, x3, LSL #1]\n" - "ld1h { z25.h }, p1/Z, [x12, x3, LSL #1]\n" - "ld1h { z24.h }, p1/Z, [x23, x3, LSL #1]\n" - "ld1h { z23.h }, p1/Z, [x20, x3, LSL #1]\n" + "ld1h { z7.h }, p0/Z, [x10, x3, LSL #1]\n" + "ld1h { z6.h }, p0/Z, [x9, x3, LSL #1]\n" + "ld1h { z5.h }, p0/Z, [x26, x3, LSL #1]\n" + "ld1h { z4.h }, p0/Z, [x25, x3, LSL #1]\n" + "ld1h { z3.h }, p0/Z, [x16, x3, LSL #1]\n" + "ld1h { z2.h }, p0/Z, [x13, x3, LSL #1]\n" + "ld1h { z1.h }, p0/Z, [x11, x3, LSL #1]\n" + "ld1h { z31.h }, p0/Z, [x27, x3, LSL #1]\n" + "ld1h { z30.h }, p0/Z, [x28, x3, LSL #1]\n" + "ld1h { z29.h }, p0/Z, [x24, x3, LSL #1]\n" + "ld1h { z28.h }, p0/Z, [x22, x3, LSL #1]\n" + "ld1h { z27.h }, p0/Z, [x21, x3, LSL #1]\n" + "ld1h { z26.h }, p0/Z, [x17, x3, LSL #1]\n" + "ld1h { z25.h }, p0/Z, [x12, x3, LSL #1]\n" + "ld1h { z24.h }, p0/Z, [x23, x3, LSL #1]\n" + "ld1h { z23.h }, p0/Z, [x20, x3, LSL #1]\n" "incw x3\n" "whilelt p1.h, x3, x2\n" - "ld1rqh { z0.h }, p0/Z, [x15]\n" + "ld1rqh { z0.h }, p2/Z, [x15]\n" "b.none 2f\n" "1:" // Vector: Loop "fadd z17.h, z7.h, z6.h\n" @@ -172,32 +172,32 @@ void sve_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst_impl( "fadd z17.h, z7.h, z6.h\n" "fadd z16.h, z5.h, z4.h\n" "whilelt p0.h, x14, x2\n" - "fadd z19.h, z17.h, z16.h\n" + "fadd z20.h, z17.h, z16.h\n" "fadd z18.h, z3.h, z2.h\n" "fadd z17.h, z1.h, z31.h\n" - "fadd z22.h, z30.h, z29.h\n" + "fadd z19.h, z30.h, z29.h\n" "fadd z16.h, z28.h, z27.h\n" - "fadd z21.h, z18.h, z19.h\n" - "fadd z20.h, z16.h, z19.h\n" - "fadd z19.h, z26.h, z17.h\n" - "fadd z18.h, z25.h, z22.h\n" + "fadd z21.h, z18.h, z20.h\n" + "fadd z20.h, z16.h, z20.h\n" + "fadd z16.h, z26.h, z17.h\n" + "fadd z18.h, z25.h, z19.h\n" "fadd z17.h, z24.h, z17.h\n" - "fadd z16.h, z23.h, z22.h\n" - "fadd z19.h, z21.h, z19.h\n" - "fmul z19.h, z19.h, z0.h[0]\n" - "st1h { z19.h }, p0, [x5, x14, LSL #1]\n" + "fadd z19.h, z23.h, z19.h\n" + "fadd z16.h, z21.h, z16.h\n" + "fmul z16.h, z16.h, z0.h[0]\n" + "st1h { z16.h }, p0, [x5, x14, LSL #1]\n" "fadd z18.h, z21.h, z18.h\n" "fadd z17.h, z17.h, z20.h\n" "fmul z18.h, z18.h, z0.h[1]\n" "fmul z17.h, z17.h, z0.h[2]\n" - "fadd z16.h, z16.h, z20.h\n" + "fadd z16.h, z19.h, z20.h\n" "fmul z16.h, z16.h, z0.h[3]\n" "st1h { z18.h }, p0, [x6, x14, LSL #1]\n" "st1h { z17.h }, p0, [x7, x14, LSL #1]\n" "st1h { z16.h }, p0, [x8, x14, LSL #1]\n" : : [args] "r" (&args), [offsetof_inptrs] "I" (offsetof(KernelArgs, inptrs)), [offsetof_n_channels] "I" (offsetof(KernelArgs, n_channels)), [offsetof_outptrs] "I" (offsetof(KernelArgs, outptrs)), [offsetof_rescale] "I" (offsetof(KernelArgs, rescale_vals)) - : "cc", "memory", "p0", "p1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + : "cc", "memory", "p0", "p1", "p2", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" ); } diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_avg_generic_depthfirst/generic.cpp index 594c65e18d..2bef44ea5c 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_avg_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_avg_generic_depthfirst/generic.cpp @@ -57,68 +57,68 @@ void sve_fp16_nhwc_avg_generic_depthfirst_impl( "lsr x25, %x[n_valid_cells], #0x2\n" "mov z6.b, #0x0\n" "mov z5.b, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "mov z4.b, #0x0\n" "mov z3.b, #0x0\n" "cbz x25, 4f\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldp x22, x21, [x20, #0x10]\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" "subs x25, x25, #0x1\n" - "add x20, x20, #0x20\n" - "ld1h { z2.h }, p3/Z, [x24, x9, LSL #1]\n" - "ld1h { z1.h }, p3/Z, [x23, x9, LSL #1]\n" - "ld1h { z0.h }, p3/Z, [x22, x9, LSL #1]\n" - "ld1h { z31.h }, p3/Z, [x21, x9, LSL #1]\n" - "ld1h { z30.h }, p2/Z, [x24, x28, LSL #1]\n" - "ld1h { z22.h }, p2/Z, [x23, x28, LSL #1]\n" - "ld1h { z29.h }, p2/Z, [x22, x28, LSL #1]\n" - "ld1h { z28.h }, p2/Z, [x21, x28, LSL #1]\n" - "ld1h { z27.h }, p1/Z, [x24, x27, LSL #1]\n" - "ld1h { z21.h }, p1/Z, [x23, x27, LSL #1]\n" - "ld1h { z26.h }, p1/Z, [x22, x27, LSL #1]\n" - "ld1h { z17.h }, p1/Z, [x21, x27, LSL #1]\n" - "ld1h { z25.h }, p0/Z, [x24, x26, LSL #1]\n" - "ld1h { z20.h }, p0/Z, [x23, x26, LSL #1]\n" - "ld1h { z24.h }, p0/Z, [x22, x26, LSL #1]\n" - "ld1h { z16.h }, p0/Z, [x21, x26, LSL #1]\n" + "add x24, x24, #0x20\n" + "ld1h { z2.h }, p3/Z, [x23, x9, LSL #1]\n" + "ld1h { z1.h }, p3/Z, [x22, x9, LSL #1]\n" + "ld1h { z0.h }, p3/Z, [x21, x9, LSL #1]\n" + "ld1h { z31.h }, p3/Z, [x20, x9, LSL #1]\n" + "ld1h { z30.h }, p2/Z, [x23, x28, LSL #1]\n" + "ld1h { z22.h }, p2/Z, [x22, x28, LSL #1]\n" + "ld1h { z29.h }, p2/Z, [x21, x28, LSL #1]\n" + "ld1h { z28.h }, p2/Z, [x20, x28, LSL #1]\n" + "ld1h { z27.h }, p1/Z, [x23, x27, LSL #1]\n" + "ld1h { z21.h }, p1/Z, [x22, x27, LSL #1]\n" + "ld1h { z26.h }, p1/Z, [x21, x27, LSL #1]\n" + "ld1h { z17.h }, p1/Z, [x20, x27, LSL #1]\n" + "ld1h { z25.h }, p0/Z, [x23, x26, LSL #1]\n" + "ld1h { z20.h }, p0/Z, [x22, x26, LSL #1]\n" + "ld1h { z24.h }, p0/Z, [x21, x26, LSL #1]\n" + "ld1h { z16.h }, p0/Z, [x20, x26, LSL #1]\n" "beq 3f\n" "2:" // 4-vectors of channels: 4 inputs loop "fadd z23.h, z2.h, z1.h\n" "fadd z19.h, z0.h, z31.h\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldp x22, x21, [x20, #0x10]\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" "fadd z22.h, z30.h, z22.h\n" "fadd z18.h, z29.h, z28.h\n" "subs x25, x25, #0x1\n" - "add x20, x20, #0x20\n" + "add x24, x24, #0x20\n" "fadd z21.h, z27.h, z21.h\n" "fadd z17.h, z26.h, z17.h\n" - "ld1h { z2.h }, p3/Z, [x24, x9, LSL #1]\n" - "ld1h { z1.h }, p3/Z, [x23, x9, LSL #1]\n" + "ld1h { z2.h }, p3/Z, [x23, x9, LSL #1]\n" + "ld1h { z1.h }, p3/Z, [x22, x9, LSL #1]\n" "fadd z20.h, z25.h, z20.h\n" "fadd z16.h, z24.h, z16.h\n" - "ld1h { z0.h }, p3/Z, [x22, x9, LSL #1]\n" - "ld1h { z31.h }, p3/Z, [x21, x9, LSL #1]\n" + "ld1h { z0.h }, p3/Z, [x21, x9, LSL #1]\n" + "ld1h { z31.h }, p3/Z, [x20, x9, LSL #1]\n" "fadd z19.h, z23.h, z19.h\n" "fadd z18.h, z22.h, z18.h\n" - "ld1h { z30.h }, p2/Z, [x24, x28, LSL #1]\n" - "ld1h { z22.h }, p2/Z, [x23, x28, LSL #1]\n" + "ld1h { z30.h }, p2/Z, [x23, x28, LSL #1]\n" + "ld1h { z22.h }, p2/Z, [x22, x28, LSL #1]\n" "fadd z17.h, z21.h, z17.h\n" "fadd z16.h, z20.h, z16.h\n" - "ld1h { z29.h }, p2/Z, [x22, x28, LSL #1]\n" - "ld1h { z28.h }, p2/Z, [x21, x28, LSL #1]\n" + "ld1h { z29.h }, p2/Z, [x21, x28, LSL #1]\n" + "ld1h { z28.h }, p2/Z, [x20, x28, LSL #1]\n" "fadd z6.h, z6.h, z19.h\n" "fadd z5.h, z5.h, z18.h\n" - "ld1h { z27.h }, p1/Z, [x24, x27, LSL #1]\n" - "ld1h { z21.h }, p1/Z, [x23, x27, LSL #1]\n" + "ld1h { z27.h }, p1/Z, [x23, x27, LSL #1]\n" + "ld1h { z21.h }, p1/Z, [x22, x27, LSL #1]\n" "fadd z4.h, z4.h, z17.h\n" "fadd z3.h, z3.h, z16.h\n" - "ld1h { z26.h }, p1/Z, [x22, x27, LSL #1]\n" - "ld1h { z17.h }, p1/Z, [x21, x27, LSL #1]\n" - "ld1h { z25.h }, p0/Z, [x24, x26, LSL #1]\n" - "ld1h { z20.h }, p0/Z, [x23, x26, LSL #1]\n" - "ld1h { z24.h }, p0/Z, [x22, x26, LSL #1]\n" - "ld1h { z16.h }, p0/Z, [x21, x26, LSL #1]\n" + "ld1h { z26.h }, p1/Z, [x21, x27, LSL #1]\n" + "ld1h { z17.h }, p1/Z, [x20, x27, LSL #1]\n" + "ld1h { z25.h }, p0/Z, [x23, x26, LSL #1]\n" + "ld1h { z20.h }, p0/Z, [x22, x26, LSL #1]\n" + "ld1h { z24.h }, p0/Z, [x21, x26, LSL #1]\n" + "ld1h { z16.h }, p0/Z, [x20, x26, LSL #1]\n" "bgt 2b\n" "3:" // 4-vectors of channels: 4 inputs tail "fadd z23.h, z2.h, z1.h\n" @@ -141,16 +141,16 @@ void sve_fp16_nhwc_avg_generic_depthfirst_impl( "ands x21, %x[n_valid_cells], #0x3\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x24, [x20], #0x8\n" - "ld1h { z2.h }, p3/Z, [x24, x9, LSL #1]\n" + "ldr x20, [x24], #0x8\n" + "ld1h { z16.h }, p3/Z, [x20, x9, LSL #1]\n" "subs x21, x21, #0x1\n" - "fadd z6.h, z6.h, z2.h\n" - "ld1h { z30.h }, p2/Z, [x24, x28, LSL #1]\n" - "ld1h { z27.h }, p1/Z, [x24, x27, LSL #1]\n" - "fadd z5.h, z5.h, z30.h\n" - "fadd z4.h, z4.h, z27.h\n" - "ld1h { z25.h }, p0/Z, [x24, x26, LSL #1]\n" - "fadd z3.h, z3.h, z25.h\n" + "fadd z6.h, z6.h, z16.h\n" + "ld1h { z17.h }, p2/Z, [x20, x28, LSL #1]\n" + "ld1h { z16.h }, p1/Z, [x20, x27, LSL #1]\n" + "fadd z5.h, z5.h, z17.h\n" + "fadd z4.h, z4.h, z16.h\n" + "ld1h { z16.h }, p0/Z, [x20, x26, LSL #1]\n" + "fadd z3.h, z3.h, z16.h\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End "fmul z6.h, z6.h, z7.h\n" @@ -173,44 +173,44 @@ void sve_fp16_nhwc_avg_generic_depthfirst_impl( "8:" // Single vector of channels: Loop "lsr x25, %x[n_valid_cells], #0x2\n" "mov z6.b, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "cbz x25, 11f\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldp x22, x21, [x20, #0x10]\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" "subs x25, x25, #0x1\n" - "add x20, x20, #0x20\n" - "ld1h { z2.h }, p3/Z, [x24, x9, LSL #1]\n" - "ld1h { z1.h }, p3/Z, [x23, x9, LSL #1]\n" - "ld1h { z0.h }, p3/Z, [x22, x9, LSL #1]\n" - "ld1h { z31.h }, p3/Z, [x21, x9, LSL #1]\n" + "add x24, x24, #0x20\n" + "ld1h { z2.h }, p3/Z, [x23, x9, LSL #1]\n" + "ld1h { z1.h }, p3/Z, [x22, x9, LSL #1]\n" + "ld1h { z0.h }, p3/Z, [x21, x9, LSL #1]\n" + "ld1h { z31.h }, p3/Z, [x20, x9, LSL #1]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 4 inputs loop - "fadd z23.h, z2.h, z1.h\n" - "fadd z19.h, z0.h, z31.h\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldp x22, x21, [x20, #0x10]\n" - "fadd z19.h, z23.h, z19.h\n" + "fadd z17.h, z2.h, z1.h\n" + "fadd z16.h, z0.h, z31.h\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "fadd z16.h, z17.h, z16.h\n" "subs x25, x25, #0x1\n" - "fadd z6.h, z6.h, z19.h\n" - "add x20, x20, #0x20\n" - "ld1h { z2.h }, p3/Z, [x24, x9, LSL #1]\n" - "ld1h { z1.h }, p3/Z, [x23, x9, LSL #1]\n" - "ld1h { z0.h }, p3/Z, [x22, x9, LSL #1]\n" - "ld1h { z31.h }, p3/Z, [x21, x9, LSL #1]\n" + "fadd z6.h, z6.h, z16.h\n" + "add x24, x24, #0x20\n" + "ld1h { z2.h }, p3/Z, [x23, x9, LSL #1]\n" + "ld1h { z1.h }, p3/Z, [x22, x9, LSL #1]\n" + "ld1h { z0.h }, p3/Z, [x21, x9, LSL #1]\n" + "ld1h { z31.h }, p3/Z, [x20, x9, LSL #1]\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 4 inputs tail - "fadd z23.h, z2.h, z1.h\n" - "fadd z19.h, z0.h, z31.h\n" - "fadd z19.h, z23.h, z19.h\n" - "fadd z6.h, z6.h, z19.h\n" + "fadd z17.h, z2.h, z1.h\n" + "fadd z16.h, z0.h, z31.h\n" + "fadd z16.h, z17.h, z16.h\n" + "fadd z6.h, z6.h, z16.h\n" "11:" // Single vector of channels: Loop: After loop "ands x21, %x[n_valid_cells], #0x3\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x24, [x20], #0x8\n" - "ld1h { z2.h }, p3/Z, [x24, x9, LSL #1]\n" + "ldr x20, [x24], #0x8\n" + "ld1h { z16.h }, p3/Z, [x20, x9, LSL #1]\n" "subs x21, x21, #0x1\n" - "fadd z6.h, z6.h, z2.h\n" + "fadd z6.h, z6.h, z16.h\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End "fmul z6.h, z6.h, z7.h\n" diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp index 838cd3406c..31bbfd085e 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp @@ -66,10 +66,10 @@ void sve_fp16_nhwc_max_2x2_s1_output2x2_depthfirst_impl( "ldr x15, [%x[args], %[offsetof_n_channels]]\n" "ldr x21, [%x[args], %[offsetof_outptrs]]\n" "mov x14, #0x0\n" - "whilelt p2.h, x14, x15\n" + "whilelt p0.h, x14, x15\n" "ldr x20, [%x[args], %[offsetof_inptrs]]\n" "ldp x13, x12, [x21, #0x0]\n" - "ptrue p1.b\n" + "ptrue p2.b\n" "mov x11, #0x0\n" "ldp x10, x9, [x21, #0x10]\n" "ldp x28, x27, [x20, #0x0]\n" @@ -77,61 +77,61 @@ void sve_fp16_nhwc_max_2x2_s1_output2x2_depthfirst_impl( "ldp x24, x23, [x20, #0x20]\n" "ldp x22, x21, [x20, #0x30]\n" "ldr x20, [x20, #0x40]\n" - "ld1h { z31.h }, p2/Z, [x27, x14, LSL #1]\n" - "ld1h { z30.h }, p2/Z, [x24, x14, LSL #1]\n" - "ld1h { z29.h }, p2/Z, [x21, x14, LSL #1]\n" - "ld1h { z28.h }, p2/Z, [x25, x14, LSL #1]\n" - "ld1h { z27.h }, p2/Z, [x28, x14, LSL #1]\n" - "ld1h { z26.h }, p2/Z, [x26, x14, LSL #1]\n" - "ld1h { z25.h }, p2/Z, [x23, x14, LSL #1]\n" - "ld1h { z24.h }, p2/Z, [x22, x14, LSL #1]\n" - "ld1h { z23.h }, p2/Z, [x20, x14, LSL #1]\n" + "ld1h { z31.h }, p0/Z, [x27, x14, LSL #1]\n" + "ld1h { z30.h }, p0/Z, [x24, x14, LSL #1]\n" + "ld1h { z29.h }, p0/Z, [x21, x14, LSL #1]\n" + "ld1h { z28.h }, p0/Z, [x25, x14, LSL #1]\n" + "ld1h { z27.h }, p0/Z, [x28, x14, LSL #1]\n" + "ld1h { z26.h }, p0/Z, [x26, x14, LSL #1]\n" + "ld1h { z25.h }, p0/Z, [x23, x14, LSL #1]\n" + "ld1h { z24.h }, p0/Z, [x22, x14, LSL #1]\n" + "ld1h { z23.h }, p0/Z, [x20, x14, LSL #1]\n" "incw x14\n" - "whilelt p2.h, x14, x15\n" + "whilelt p1.h, x14, x15\n" "b.none 2f\n" "1:" // Vector: Loop - "movprfx z22, z31\n fmax z22.h, p1/M, z22.h, z30.h\n" - "movprfx z21, z30\n fmax z21.h, p1/M, z21.h, z29.h\n" - "ld1h { z31.h }, p2/Z, [x27, x14, LSL #1]\n" - "ld1h { z30.h }, p2/Z, [x24, x14, LSL #1]\n" - "movprfx z20, z28\n fmax z20.h, p1/M, z20.h, z27.h\n" - "movprfx z19, z26\n fmax z19.h, p1/M, z19.h, z25.h\n" - "ld1h { z29.h }, p2/Z, [x21, x14, LSL #1]\n" - "ld1h { z27.h }, p2/Z, [x28, x14, LSL #1]\n" - "movprfx z17, z28\n fmax z17.h, p1/M, z17.h, z24.h\n" - "movprfx z18, z25\n fmax z18.h, p1/M, z18.h, z23.h\n" - "ld1h { z28.h }, p2/Z, [x25, x14, LSL #1]\n" - "ld1h { z26.h }, p2/Z, [x26, x14, LSL #1]\n" - "ld1h { z25.h }, p2/Z, [x23, x14, LSL #1]\n" - "ld1h { z24.h }, p2/Z, [x22, x14, LSL #1]\n" + "movprfx z22, z31\n fmax z22.h, p2/M, z22.h, z30.h\n" + "movprfx z21, z30\n fmax z21.h, p2/M, z21.h, z29.h\n" + "ld1h { z31.h }, p1/Z, [x27, x14, LSL #1]\n" + "ld1h { z30.h }, p1/Z, [x24, x14, LSL #1]\n" + "movprfx z20, z28\n fmax z20.h, p2/M, z20.h, z27.h\n" + "movprfx z19, z26\n fmax z19.h, p2/M, z19.h, z25.h\n" + "ld1h { z29.h }, p1/Z, [x21, x14, LSL #1]\n" + "ld1h { z27.h }, p1/Z, [x28, x14, LSL #1]\n" + "movprfx z17, z28\n fmax z17.h, p2/M, z17.h, z24.h\n" + "movprfx z18, z25\n fmax z18.h, p2/M, z18.h, z23.h\n" + "ld1h { z28.h }, p1/Z, [x25, x14, LSL #1]\n" + "ld1h { z26.h }, p1/Z, [x26, x14, LSL #1]\n" + "ld1h { z25.h }, p1/Z, [x23, x14, LSL #1]\n" + "ld1h { z24.h }, p1/Z, [x22, x14, LSL #1]\n" "whilelt p0.h, x11, x15\n" - "movprfx z16, z22\n fmax z16.h, p1/M, z16.h, z20.h\n" - "ld1h { z23.h }, p2/Z, [x20, x14, LSL #1]\n" + "movprfx z16, z22\n fmax z16.h, p2/M, z16.h, z20.h\n" + "ld1h { z23.h }, p1/Z, [x20, x14, LSL #1]\n" "incw x14\n" - "whilelt p2.h, x14, x15\n" + "whilelt p1.h, x14, x15\n" "st1h { z16.h }, p0, [x13, x11, LSL #1]\n" - "movprfx z16, z19\n fmax z16.h, p1/M, z16.h, z22.h\n" - "fmax z17.h, p1/M, z17.h, z21.h\n" + "movprfx z16, z19\n fmax z16.h, p2/M, z16.h, z22.h\n" + "fmax z17.h, p2/M, z17.h, z21.h\n" "st1h { z16.h }, p0, [x12, x11, LSL #1]\n" - "movprfx z16, z18\n fmax z16.h, p1/M, z16.h, z21.h\n" + "movprfx z16, z21\n fmax z16.h, p2/M, z16.h, z18.h\n" "st1h { z17.h }, p0, [x10, x11, LSL #1]\n" "st1h { z16.h }, p0, [x9, x11, LSL #1]\n" "incw x11\n" "b.any 1b\n" "2:" // Vector: Tail - "movprfx z22, z31\n fmax z22.h, p1/M, z22.h, z30.h\n" - "movprfx z21, z30\n fmax z21.h, p1/M, z21.h, z29.h\n" - "movprfx z20, z28\n fmax z20.h, p1/M, z20.h, z27.h\n" - "movprfx z19, z26\n fmax z19.h, p1/M, z19.h, z25.h\n" - "movprfx z17, z28\n fmax z17.h, p1/M, z17.h, z24.h\n" - "movprfx z18, z25\n fmax z18.h, p1/M, z18.h, z23.h\n" + "movprfx z22, z31\n fmax z22.h, p2/M, z22.h, z30.h\n" + "movprfx z21, z30\n fmax z21.h, p2/M, z21.h, z29.h\n" + "movprfx z20, z28\n fmax z20.h, p2/M, z20.h, z27.h\n" + "movprfx z19, z26\n fmax z19.h, p2/M, z19.h, z25.h\n" + "movprfx z17, z28\n fmax z17.h, p2/M, z17.h, z24.h\n" + "movprfx z18, z25\n fmax z18.h, p2/M, z18.h, z23.h\n" "whilelt p0.h, x11, x15\n" - "movprfx z16, z22\n fmax z16.h, p1/M, z16.h, z20.h\n" + "movprfx z16, z22\n fmax z16.h, p2/M, z16.h, z20.h\n" "st1h { z16.h }, p0, [x13, x11, LSL #1]\n" - "movprfx z16, z19\n fmax z16.h, p1/M, z16.h, z22.h\n" - "fmax z17.h, p1/M, z17.h, z21.h\n" + "movprfx z16, z19\n fmax z16.h, p2/M, z16.h, z22.h\n" + "fmax z17.h, p2/M, z17.h, z21.h\n" "st1h { z16.h }, p0, [x12, x11, LSL #1]\n" - "movprfx z16, z18\n fmax z16.h, p1/M, z16.h, z21.h\n" + "movprfx z16, z21\n fmax z16.h, p2/M, z16.h, z18.h\n" "st1h { z17.h }, p0, [x10, x11, LSL #1]\n" "st1h { z16.h }, p0, [x9, x11, LSL #1]\n" : diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_max_generic_depthfirst/generic.cpp index 9f1f9e7377..1a01412836 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_max_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_max_generic_depthfirst/generic.cpp @@ -54,68 +54,68 @@ void sve_fp16_nhwc_max_generic_depthfirst_impl( "lsr x25, %x[n_valid_cells], #0x2\n" "mov z8.h, #0xfc00\n" "mov z7.h, #0xfc00\n" - "mov x20, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "mov z6.h, #0xfc00\n" "mov z5.h, #0xfc00\n" "cbz x25, 4f\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldp x22, x21, [x20, #0x10]\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" "subs x25, x25, #0x1\n" - "add x20, x20, #0x20\n" - "ld1h { z4.h }, p4/Z, [x24, x9, LSL #1]\n" - "ld1h { z3.h }, p4/Z, [x23, x9, LSL #1]\n" - "ld1h { z2.h }, p4/Z, [x22, x9, LSL #1]\n" - "ld1h { z1.h }, p4/Z, [x21, x9, LSL #1]\n" - "ld1h { z0.h }, p3/Z, [x24, x28, LSL #1]\n" - "ld1h { z31.h }, p3/Z, [x23, x28, LSL #1]\n" - "ld1h { z22.h }, p3/Z, [x22, x28, LSL #1]\n" - "ld1h { z30.h }, p3/Z, [x21, x28, LSL #1]\n" - "ld1h { z29.h }, p2/Z, [x24, x27, LSL #1]\n" - "ld1h { z28.h }, p2/Z, [x23, x27, LSL #1]\n" - "ld1h { z21.h }, p2/Z, [x22, x27, LSL #1]\n" - "ld1h { z27.h }, p2/Z, [x21, x27, LSL #1]\n" - "ld1h { z26.h }, p1/Z, [x24, x26, LSL #1]\n" - "ld1h { z25.h }, p1/Z, [x23, x26, LSL #1]\n" - "ld1h { z20.h }, p1/Z, [x22, x26, LSL #1]\n" - "ld1h { z24.h }, p1/Z, [x21, x26, LSL #1]\n" + "add x24, x24, #0x20\n" + "ld1h { z4.h }, p4/Z, [x23, x9, LSL #1]\n" + "ld1h { z3.h }, p4/Z, [x22, x9, LSL #1]\n" + "ld1h { z2.h }, p4/Z, [x21, x9, LSL #1]\n" + "ld1h { z1.h }, p4/Z, [x20, x9, LSL #1]\n" + "ld1h { z0.h }, p3/Z, [x23, x28, LSL #1]\n" + "ld1h { z31.h }, p3/Z, [x22, x28, LSL #1]\n" + "ld1h { z22.h }, p3/Z, [x21, x28, LSL #1]\n" + "ld1h { z30.h }, p3/Z, [x20, x28, LSL #1]\n" + "ld1h { z29.h }, p2/Z, [x23, x27, LSL #1]\n" + "ld1h { z28.h }, p2/Z, [x22, x27, LSL #1]\n" + "ld1h { z21.h }, p2/Z, [x21, x27, LSL #1]\n" + "ld1h { z27.h }, p2/Z, [x20, x27, LSL #1]\n" + "ld1h { z26.h }, p1/Z, [x23, x26, LSL #1]\n" + "ld1h { z25.h }, p1/Z, [x22, x26, LSL #1]\n" + "ld1h { z20.h }, p1/Z, [x21, x26, LSL #1]\n" + "ld1h { z24.h }, p1/Z, [x20, x26, LSL #1]\n" "beq 3f\n" "2:" // 4-vectors of channels: 4 inputs loop "movprfx z19, z4\n fmax z19.h, p0/M, z19.h, z3.h\n" "movprfx z23, z2\n fmax z23.h, p0/M, z23.h, z1.h\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldp x22, x21, [x20, #0x10]\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" "movprfx z18, z0\n fmax z18.h, p0/M, z18.h, z31.h\n" "fmax z22.h, p0/M, z22.h, z30.h\n" - "ld1h { z4.h }, p4/Z, [x24, x9, LSL #1]\n" - "ld1h { z3.h }, p4/Z, [x23, x9, LSL #1]\n" + "ld1h { z4.h }, p4/Z, [x23, x9, LSL #1]\n" + "ld1h { z3.h }, p4/Z, [x22, x9, LSL #1]\n" "movprfx z17, z29\n fmax z17.h, p0/M, z17.h, z28.h\n" "fmax z21.h, p0/M, z21.h, z27.h\n" - "ld1h { z2.h }, p4/Z, [x22, x9, LSL #1]\n" - "ld1h { z1.h }, p4/Z, [x21, x9, LSL #1]\n" + "ld1h { z2.h }, p4/Z, [x21, x9, LSL #1]\n" + "ld1h { z1.h }, p4/Z, [x20, x9, LSL #1]\n" "movprfx z16, z26\n fmax z16.h, p0/M, z16.h, z25.h\n" "fmax z20.h, p0/M, z20.h, z24.h\n" - "ld1h { z0.h }, p3/Z, [x24, x28, LSL #1]\n" - "ld1h { z31.h }, p3/Z, [x23, x28, LSL #1]\n" + "ld1h { z0.h }, p3/Z, [x23, x28, LSL #1]\n" + "ld1h { z31.h }, p3/Z, [x22, x28, LSL #1]\n" "fmax z19.h, p0/M, z19.h, z23.h\n" "fmax z18.h, p0/M, z18.h, z22.h\n" - "ld1h { z22.h }, p3/Z, [x22, x28, LSL #1]\n" - "ld1h { z30.h }, p3/Z, [x21, x28, LSL #1]\n" + "ld1h { z22.h }, p3/Z, [x21, x28, LSL #1]\n" + "ld1h { z30.h }, p3/Z, [x20, x28, LSL #1]\n" "fmax z17.h, p0/M, z17.h, z21.h\n" "fmax z16.h, p0/M, z16.h, z20.h\n" - "ld1h { z29.h }, p2/Z, [x24, x27, LSL #1]\n" - "ld1h { z28.h }, p2/Z, [x23, x27, LSL #1]\n" + "ld1h { z29.h }, p2/Z, [x23, x27, LSL #1]\n" + "ld1h { z28.h }, p2/Z, [x22, x27, LSL #1]\n" "subs x25, x25, #0x1\n" "fmax z8.h, p0/M, z8.h, z19.h\n" - "ld1h { z21.h }, p2/Z, [x22, x27, LSL #1]\n" - "ld1h { z27.h }, p2/Z, [x21, x27, LSL #1]\n" + "ld1h { z21.h }, p2/Z, [x21, x27, LSL #1]\n" + "ld1h { z27.h }, p2/Z, [x20, x27, LSL #1]\n" "fmax z7.h, p0/M, z7.h, z18.h\n" "fmax z6.h, p0/M, z6.h, z17.h\n" - "ld1h { z26.h }, p1/Z, [x24, x26, LSL #1]\n" - "ld1h { z25.h }, p1/Z, [x23, x26, LSL #1]\n" + "ld1h { z26.h }, p1/Z, [x23, x26, LSL #1]\n" + "ld1h { z25.h }, p1/Z, [x22, x26, LSL #1]\n" "fmax z5.h, p0/M, z5.h, z16.h\n" - "add x20, x20, #0x20\n" - "ld1h { z20.h }, p1/Z, [x22, x26, LSL #1]\n" - "ld1h { z24.h }, p1/Z, [x21, x26, LSL #1]\n" + "add x24, x24, #0x20\n" + "ld1h { z20.h }, p1/Z, [x21, x26, LSL #1]\n" + "ld1h { z24.h }, p1/Z, [x20, x26, LSL #1]\n" "bgt 2b\n" "3:" // 4-vectors of channels: 4 inputs tail "movprfx z19, z4\n fmax z19.h, p0/M, z19.h, z3.h\n" @@ -138,16 +138,16 @@ void sve_fp16_nhwc_max_generic_depthfirst_impl( "ands x21, %x[n_valid_cells], #0x3\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x24, [x20], #0x8\n" - "ld1h { z4.h }, p4/Z, [x24, x9, LSL #1]\n" + "ldr x20, [x24], #0x8\n" + "ld1h { z16.h }, p4/Z, [x20, x9, LSL #1]\n" "subs x21, x21, #0x1\n" - "fmax z8.h, p0/M, z8.h, z4.h\n" - "ld1h { z0.h }, p3/Z, [x24, x28, LSL #1]\n" - "ld1h { z29.h }, p2/Z, [x24, x27, LSL #1]\n" - "fmax z7.h, p0/M, z7.h, z0.h\n" - "fmax z6.h, p0/M, z6.h, z29.h\n" - "ld1h { z26.h }, p1/Z, [x24, x26, LSL #1]\n" - "fmax z5.h, p0/M, z5.h, z26.h\n" + "fmax z8.h, p0/M, z8.h, z16.h\n" + "ld1h { z17.h }, p3/Z, [x20, x28, LSL #1]\n" + "ld1h { z16.h }, p2/Z, [x20, x27, LSL #1]\n" + "fmax z7.h, p0/M, z7.h, z17.h\n" + "fmax z6.h, p0/M, z6.h, z16.h\n" + "ld1h { z16.h }, p1/Z, [x20, x26, LSL #1]\n" + "fmax z5.h, p0/M, z5.h, z16.h\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End "st1h { z8.h }, p4, [%x[outptr], x9, LSL #1]\n" @@ -166,44 +166,44 @@ void sve_fp16_nhwc_max_generic_depthfirst_impl( "8:" // Single vector of channels: Loop "lsr x25, %x[n_valid_cells], #0x2\n" "mov z8.h, #0xfc00\n" - "mov x20, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "cbz x25, 11f\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldp x22, x21, [x20, #0x10]\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" "subs x25, x25, #0x1\n" - "add x20, x20, #0x20\n" - "ld1h { z4.h }, p4/Z, [x24, x9, LSL #1]\n" - "ld1h { z3.h }, p4/Z, [x23, x9, LSL #1]\n" - "ld1h { z2.h }, p4/Z, [x22, x9, LSL #1]\n" - "ld1h { z1.h }, p4/Z, [x21, x9, LSL #1]\n" + "add x24, x24, #0x20\n" + "ld1h { z4.h }, p4/Z, [x23, x9, LSL #1]\n" + "ld1h { z3.h }, p4/Z, [x22, x9, LSL #1]\n" + "ld1h { z2.h }, p4/Z, [x21, x9, LSL #1]\n" + "ld1h { z1.h }, p4/Z, [x20, x9, LSL #1]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 4 inputs loop - "movprfx z19, z4\n fmax z19.h, p0/M, z19.h, z3.h\n" - "movprfx z23, z2\n fmax z23.h, p0/M, z23.h, z1.h\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldp x22, x21, [x20, #0x10]\n" - "fmax z19.h, p0/M, z19.h, z23.h\n" + "movprfx z16, z4\n fmax z16.h, p0/M, z16.h, z3.h\n" + "movprfx z17, z2\n fmax z17.h, p0/M, z17.h, z1.h\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "fmax z16.h, p0/M, z16.h, z17.h\n" "subs x25, x25, #0x1\n" - "ld1h { z4.h }, p4/Z, [x24, x9, LSL #1]\n" - "ld1h { z3.h }, p4/Z, [x23, x9, LSL #1]\n" - "fmax z8.h, p0/M, z8.h, z19.h\n" - "add x20, x20, #0x20\n" - "ld1h { z2.h }, p4/Z, [x22, x9, LSL #1]\n" - "ld1h { z1.h }, p4/Z, [x21, x9, LSL #1]\n" + "ld1h { z4.h }, p4/Z, [x23, x9, LSL #1]\n" + "ld1h { z3.h }, p4/Z, [x22, x9, LSL #1]\n" + "fmax z8.h, p0/M, z8.h, z16.h\n" + "add x24, x24, #0x20\n" + "ld1h { z2.h }, p4/Z, [x21, x9, LSL #1]\n" + "ld1h { z1.h }, p4/Z, [x20, x9, LSL #1]\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 4 inputs tail - "movprfx z19, z4\n fmax z19.h, p0/M, z19.h, z3.h\n" - "movprfx z23, z2\n fmax z23.h, p0/M, z23.h, z1.h\n" - "fmax z19.h, p0/M, z19.h, z23.h\n" - "fmax z8.h, p0/M, z8.h, z19.h\n" + "movprfx z16, z4\n fmax z16.h, p0/M, z16.h, z3.h\n" + "movprfx z17, z2\n fmax z17.h, p0/M, z17.h, z1.h\n" + "fmax z16.h, p0/M, z16.h, z17.h\n" + "fmax z8.h, p0/M, z8.h, z16.h\n" "11:" // Single vector of channels: Loop: After loop "ands x21, %x[n_valid_cells], #0x3\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x24, [x20], #0x8\n" - "ld1h { z4.h }, p4/Z, [x24, x9, LSL #1]\n" + "ldr x20, [x24], #0x8\n" + "ld1h { z16.h }, p4/Z, [x20, x9, LSL #1]\n" "subs x21, x21, #0x1\n" - "fmax z8.h, p0/M, z8.h, z4.h\n" + "fmax z8.h, p0/M, z8.h, z16.h\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End "st1h { z8.h }, p4, [%x[outptr], x9, LSL #1]\n" diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp index 39197aa04d..c5ea5adea0 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp @@ -88,8 +88,8 @@ void sve_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst_impl( "mov x20, #0x4\n" "ldr x4, [%x[args], %[offsetof_inptrs]]\n" "ldp x5, x6, [x21, #0x0]\n" - "whilelt p0.s, XZR, x20\n" - "whilelt p1.s, x3, x2\n" + "whilelt p2.s, XZR, x20\n" + "whilelt p0.s, x3, x2\n" "ldp x7, x8, [x21, #0x10]\n" "ldp x17, x16, [x4, #0x0]\n" "add x15, %x[args], %[offsetof_rescale]\n" @@ -101,25 +101,25 @@ void sve_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst_impl( "ldp x25, x24, [x4, #0x50]\n" "ldp x23, x22, [x4, #0x60]\n" "ldp x21, x20, [x4, #0x70]\n" - "ld1w { z7.s }, p1/Z, [x10, x3, LSL #2]\n" - "ld1w { z6.s }, p1/Z, [x9, x3, LSL #2]\n" - "ld1w { z5.s }, p1/Z, [x26, x3, LSL #2]\n" - "ld1w { z4.s }, p1/Z, [x25, x3, LSL #2]\n" - "ld1w { z3.s }, p1/Z, [x16, x3, LSL #2]\n" - "ld1w { z2.s }, p1/Z, [x13, x3, LSL #2]\n" - "ld1w { z1.s }, p1/Z, [x11, x3, LSL #2]\n" - "ld1w { z31.s }, p1/Z, [x27, x3, LSL #2]\n" - "ld1w { z30.s }, p1/Z, [x28, x3, LSL #2]\n" - "ld1w { z29.s }, p1/Z, [x24, x3, LSL #2]\n" - "ld1w { z28.s }, p1/Z, [x22, x3, LSL #2]\n" - "ld1w { z27.s }, p1/Z, [x21, x3, LSL #2]\n" - "ld1w { z26.s }, p1/Z, [x17, x3, LSL #2]\n" - "ld1w { z25.s }, p1/Z, [x12, x3, LSL #2]\n" - "ld1w { z24.s }, p1/Z, [x23, x3, LSL #2]\n" - "ld1w { z23.s }, p1/Z, [x20, x3, LSL #2]\n" + "ld1w { z7.s }, p0/Z, [x10, x3, LSL #2]\n" + "ld1w { z6.s }, p0/Z, [x9, x3, LSL #2]\n" + "ld1w { z5.s }, p0/Z, [x26, x3, LSL #2]\n" + "ld1w { z4.s }, p0/Z, [x25, x3, LSL #2]\n" + "ld1w { z3.s }, p0/Z, [x16, x3, LSL #2]\n" + "ld1w { z2.s }, p0/Z, [x13, x3, LSL #2]\n" + "ld1w { z1.s }, p0/Z, [x11, x3, LSL #2]\n" + "ld1w { z31.s }, p0/Z, [x27, x3, LSL #2]\n" + "ld1w { z30.s }, p0/Z, [x28, x3, LSL #2]\n" + "ld1w { z29.s }, p0/Z, [x24, x3, LSL #2]\n" + "ld1w { z28.s }, p0/Z, [x22, x3, LSL #2]\n" + "ld1w { z27.s }, p0/Z, [x21, x3, LSL #2]\n" + "ld1w { z26.s }, p0/Z, [x17, x3, LSL #2]\n" + "ld1w { z25.s }, p0/Z, [x12, x3, LSL #2]\n" + "ld1w { z24.s }, p0/Z, [x23, x3, LSL #2]\n" + "ld1w { z23.s }, p0/Z, [x20, x3, LSL #2]\n" "incw x3\n" "whilelt p1.s, x3, x2\n" - "ld1rqw { z0.s }, p0/Z, [x15]\n" + "ld1rqw { z0.s }, p2/Z, [x15]\n" "b.none 2f\n" "1:" // Vector: Loop "fadd z17.s, z7.s, z6.s\n" @@ -172,32 +172,32 @@ void sve_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst_impl( "fadd z17.s, z7.s, z6.s\n" "fadd z16.s, z5.s, z4.s\n" "whilelt p0.s, x14, x2\n" - "fadd z19.s, z17.s, z16.s\n" + "fadd z20.s, z17.s, z16.s\n" "fadd z18.s, z3.s, z2.s\n" "fadd z17.s, z1.s, z31.s\n" - "fadd z22.s, z30.s, z29.s\n" + "fadd z19.s, z30.s, z29.s\n" "fadd z16.s, z28.s, z27.s\n" - "fadd z21.s, z18.s, z19.s\n" - "fadd z20.s, z16.s, z19.s\n" - "fadd z19.s, z26.s, z17.s\n" - "fadd z18.s, z25.s, z22.s\n" + "fadd z21.s, z18.s, z20.s\n" + "fadd z20.s, z16.s, z20.s\n" + "fadd z16.s, z26.s, z17.s\n" + "fadd z18.s, z25.s, z19.s\n" "fadd z17.s, z24.s, z17.s\n" - "fadd z16.s, z23.s, z22.s\n" - "fadd z19.s, z21.s, z19.s\n" - "fmul z19.s, z19.s, z0.s[0]\n" - "st1w { z19.s }, p0, [x5, x14, LSL #2]\n" + "fadd z19.s, z23.s, z19.s\n" + "fadd z16.s, z21.s, z16.s\n" + "fmul z16.s, z16.s, z0.s[0]\n" + "st1w { z16.s }, p0, [x5, x14, LSL #2]\n" "fadd z18.s, z21.s, z18.s\n" "fadd z17.s, z17.s, z20.s\n" "fmul z18.s, z18.s, z0.s[1]\n" "fmul z17.s, z17.s, z0.s[2]\n" - "fadd z16.s, z16.s, z20.s\n" + "fadd z16.s, z19.s, z20.s\n" "fmul z16.s, z16.s, z0.s[3]\n" "st1w { z18.s }, p0, [x6, x14, LSL #2]\n" "st1w { z17.s }, p0, [x7, x14, LSL #2]\n" "st1w { z16.s }, p0, [x8, x14, LSL #2]\n" : : [args] "r" (&args), [offsetof_inptrs] "I" (offsetof(KernelArgs, inptrs)), [offsetof_n_channels] "I" (offsetof(KernelArgs, n_channels)), [offsetof_outptrs] "I" (offsetof(KernelArgs, outptrs)), [offsetof_rescale] "I" (offsetof(KernelArgs, rescale_vals)) - : "cc", "memory", "p0", "p1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + : "cc", "memory", "p0", "p1", "p2", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" ); } diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_avg_generic_depthfirst/generic.cpp index c1a3e5de84..7c94894892 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_avg_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_avg_generic_depthfirst/generic.cpp @@ -57,68 +57,68 @@ void sve_fp32_nhwc_avg_generic_depthfirst_impl( "lsr x25, %x[n_valid_cells], #0x2\n" "mov z6.b, #0x0\n" "mov z5.b, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "mov z4.b, #0x0\n" "mov z3.b, #0x0\n" "cbz x25, 4f\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldp x22, x21, [x20, #0x10]\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" "subs x25, x25, #0x1\n" - "add x20, x20, #0x20\n" - "ld1w { z2.s }, p3/Z, [x24, x9, LSL #2]\n" - "ld1w { z1.s }, p3/Z, [x23, x9, LSL #2]\n" - "ld1w { z0.s }, p3/Z, [x22, x9, LSL #2]\n" - "ld1w { z31.s }, p3/Z, [x21, x9, LSL #2]\n" - "ld1w { z30.s }, p2/Z, [x24, x28, LSL #2]\n" - "ld1w { z22.s }, p2/Z, [x23, x28, LSL #2]\n" - "ld1w { z29.s }, p2/Z, [x22, x28, LSL #2]\n" - "ld1w { z28.s }, p2/Z, [x21, x28, LSL #2]\n" - "ld1w { z27.s }, p1/Z, [x24, x27, LSL #2]\n" - "ld1w { z21.s }, p1/Z, [x23, x27, LSL #2]\n" - "ld1w { z26.s }, p1/Z, [x22, x27, LSL #2]\n" - "ld1w { z17.s }, p1/Z, [x21, x27, LSL #2]\n" - "ld1w { z25.s }, p0/Z, [x24, x26, LSL #2]\n" - "ld1w { z20.s }, p0/Z, [x23, x26, LSL #2]\n" - "ld1w { z24.s }, p0/Z, [x22, x26, LSL #2]\n" - "ld1w { z16.s }, p0/Z, [x21, x26, LSL #2]\n" + "add x24, x24, #0x20\n" + "ld1w { z2.s }, p3/Z, [x23, x9, LSL #2]\n" + "ld1w { z1.s }, p3/Z, [x22, x9, LSL #2]\n" + "ld1w { z0.s }, p3/Z, [x21, x9, LSL #2]\n" + "ld1w { z31.s }, p3/Z, [x20, x9, LSL #2]\n" + "ld1w { z30.s }, p2/Z, [x23, x28, LSL #2]\n" + "ld1w { z22.s }, p2/Z, [x22, x28, LSL #2]\n" + "ld1w { z29.s }, p2/Z, [x21, x28, LSL #2]\n" + "ld1w { z28.s }, p2/Z, [x20, x28, LSL #2]\n" + "ld1w { z27.s }, p1/Z, [x23, x27, LSL #2]\n" + "ld1w { z21.s }, p1/Z, [x22, x27, LSL #2]\n" + "ld1w { z26.s }, p1/Z, [x21, x27, LSL #2]\n" + "ld1w { z17.s }, p1/Z, [x20, x27, LSL #2]\n" + "ld1w { z25.s }, p0/Z, [x23, x26, LSL #2]\n" + "ld1w { z20.s }, p0/Z, [x22, x26, LSL #2]\n" + "ld1w { z24.s }, p0/Z, [x21, x26, LSL #2]\n" + "ld1w { z16.s }, p0/Z, [x20, x26, LSL #2]\n" "beq 3f\n" "2:" // 4-vectors of channels: 4 inputs loop "fadd z23.s, z2.s, z1.s\n" "fadd z19.s, z0.s, z31.s\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldp x22, x21, [x20, #0x10]\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" "fadd z22.s, z30.s, z22.s\n" "fadd z18.s, z29.s, z28.s\n" "subs x25, x25, #0x1\n" - "add x20, x20, #0x20\n" + "add x24, x24, #0x20\n" "fadd z21.s, z27.s, z21.s\n" "fadd z17.s, z26.s, z17.s\n" - "ld1w { z2.s }, p3/Z, [x24, x9, LSL #2]\n" - "ld1w { z1.s }, p3/Z, [x23, x9, LSL #2]\n" + "ld1w { z2.s }, p3/Z, [x23, x9, LSL #2]\n" + "ld1w { z1.s }, p3/Z, [x22, x9, LSL #2]\n" "fadd z20.s, z25.s, z20.s\n" "fadd z16.s, z24.s, z16.s\n" - "ld1w { z0.s }, p3/Z, [x22, x9, LSL #2]\n" - "ld1w { z31.s }, p3/Z, [x21, x9, LSL #2]\n" + "ld1w { z0.s }, p3/Z, [x21, x9, LSL #2]\n" + "ld1w { z31.s }, p3/Z, [x20, x9, LSL #2]\n" "fadd z19.s, z23.s, z19.s\n" "fadd z18.s, z22.s, z18.s\n" - "ld1w { z30.s }, p2/Z, [x24, x28, LSL #2]\n" - "ld1w { z22.s }, p2/Z, [x23, x28, LSL #2]\n" + "ld1w { z30.s }, p2/Z, [x23, x28, LSL #2]\n" + "ld1w { z22.s }, p2/Z, [x22, x28, LSL #2]\n" "fadd z17.s, z21.s, z17.s\n" "fadd z16.s, z20.s, z16.s\n" - "ld1w { z29.s }, p2/Z, [x22, x28, LSL #2]\n" - "ld1w { z28.s }, p2/Z, [x21, x28, LSL #2]\n" + "ld1w { z29.s }, p2/Z, [x21, x28, LSL #2]\n" + "ld1w { z28.s }, p2/Z, [x20, x28, LSL #2]\n" "fadd z6.s, z6.s, z19.s\n" "fadd z5.s, z5.s, z18.s\n" - "ld1w { z27.s }, p1/Z, [x24, x27, LSL #2]\n" - "ld1w { z21.s }, p1/Z, [x23, x27, LSL #2]\n" + "ld1w { z27.s }, p1/Z, [x23, x27, LSL #2]\n" + "ld1w { z21.s }, p1/Z, [x22, x27, LSL #2]\n" "fadd z4.s, z4.s, z17.s\n" "fadd z3.s, z3.s, z16.s\n" - "ld1w { z26.s }, p1/Z, [x22, x27, LSL #2]\n" - "ld1w { z17.s }, p1/Z, [x21, x27, LSL #2]\n" - "ld1w { z25.s }, p0/Z, [x24, x26, LSL #2]\n" - "ld1w { z20.s }, p0/Z, [x23, x26, LSL #2]\n" - "ld1w { z24.s }, p0/Z, [x22, x26, LSL #2]\n" - "ld1w { z16.s }, p0/Z, [x21, x26, LSL #2]\n" + "ld1w { z26.s }, p1/Z, [x21, x27, LSL #2]\n" + "ld1w { z17.s }, p1/Z, [x20, x27, LSL #2]\n" + "ld1w { z25.s }, p0/Z, [x23, x26, LSL #2]\n" + "ld1w { z20.s }, p0/Z, [x22, x26, LSL #2]\n" + "ld1w { z24.s }, p0/Z, [x21, x26, LSL #2]\n" + "ld1w { z16.s }, p0/Z, [x20, x26, LSL #2]\n" "bgt 2b\n" "3:" // 4-vectors of channels: 4 inputs tail "fadd z23.s, z2.s, z1.s\n" @@ -141,16 +141,16 @@ void sve_fp32_nhwc_avg_generic_depthfirst_impl( "ands x21, %x[n_valid_cells], #0x3\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x24, [x20], #0x8\n" - "ld1w { z2.s }, p3/Z, [x24, x9, LSL #2]\n" + "ldr x20, [x24], #0x8\n" + "ld1w { z16.s }, p3/Z, [x20, x9, LSL #2]\n" "subs x21, x21, #0x1\n" - "fadd z6.s, z6.s, z2.s\n" - "ld1w { z30.s }, p2/Z, [x24, x28, LSL #2]\n" - "ld1w { z27.s }, p1/Z, [x24, x27, LSL #2]\n" - "fadd z5.s, z5.s, z30.s\n" - "fadd z4.s, z4.s, z27.s\n" - "ld1w { z25.s }, p0/Z, [x24, x26, LSL #2]\n" - "fadd z3.s, z3.s, z25.s\n" + "fadd z6.s, z6.s, z16.s\n" + "ld1w { z17.s }, p2/Z, [x20, x28, LSL #2]\n" + "ld1w { z16.s }, p1/Z, [x20, x27, LSL #2]\n" + "fadd z5.s, z5.s, z17.s\n" + "fadd z4.s, z4.s, z16.s\n" + "ld1w { z16.s }, p0/Z, [x20, x26, LSL #2]\n" + "fadd z3.s, z3.s, z16.s\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End "fmul z6.s, z6.s, z7.s\n" @@ -173,44 +173,44 @@ void sve_fp32_nhwc_avg_generic_depthfirst_impl( "8:" // Single vector of channels: Loop "lsr x25, %x[n_valid_cells], #0x2\n" "mov z6.b, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "cbz x25, 11f\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldp x22, x21, [x20, #0x10]\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" "subs x25, x25, #0x1\n" - "add x20, x20, #0x20\n" - "ld1w { z2.s }, p3/Z, [x24, x9, LSL #2]\n" - "ld1w { z1.s }, p3/Z, [x23, x9, LSL #2]\n" - "ld1w { z0.s }, p3/Z, [x22, x9, LSL #2]\n" - "ld1w { z31.s }, p3/Z, [x21, x9, LSL #2]\n" + "add x24, x24, #0x20\n" + "ld1w { z2.s }, p3/Z, [x23, x9, LSL #2]\n" + "ld1w { z1.s }, p3/Z, [x22, x9, LSL #2]\n" + "ld1w { z0.s }, p3/Z, [x21, x9, LSL #2]\n" + "ld1w { z31.s }, p3/Z, [x20, x9, LSL #2]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 4 inputs loop - "fadd z23.s, z2.s, z1.s\n" - "fadd z19.s, z0.s, z31.s\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldp x22, x21, [x20, #0x10]\n" - "fadd z19.s, z23.s, z19.s\n" + "fadd z17.s, z2.s, z1.s\n" + "fadd z16.s, z0.s, z31.s\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "fadd z16.s, z17.s, z16.s\n" "subs x25, x25, #0x1\n" - "fadd z6.s, z6.s, z19.s\n" - "add x20, x20, #0x20\n" - "ld1w { z2.s }, p3/Z, [x24, x9, LSL #2]\n" - "ld1w { z1.s }, p3/Z, [x23, x9, LSL #2]\n" - "ld1w { z0.s }, p3/Z, [x22, x9, LSL #2]\n" - "ld1w { z31.s }, p3/Z, [x21, x9, LSL #2]\n" + "fadd z6.s, z6.s, z16.s\n" + "add x24, x24, #0x20\n" + "ld1w { z2.s }, p3/Z, [x23, x9, LSL #2]\n" + "ld1w { z1.s }, p3/Z, [x22, x9, LSL #2]\n" + "ld1w { z0.s }, p3/Z, [x21, x9, LSL #2]\n" + "ld1w { z31.s }, p3/Z, [x20, x9, LSL #2]\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 4 inputs tail - "fadd z23.s, z2.s, z1.s\n" - "fadd z19.s, z0.s, z31.s\n" - "fadd z19.s, z23.s, z19.s\n" - "fadd z6.s, z6.s, z19.s\n" + "fadd z17.s, z2.s, z1.s\n" + "fadd z16.s, z0.s, z31.s\n" + "fadd z16.s, z17.s, z16.s\n" + "fadd z6.s, z6.s, z16.s\n" "11:" // Single vector of channels: Loop: After loop "ands x21, %x[n_valid_cells], #0x3\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x24, [x20], #0x8\n" - "ld1w { z2.s }, p3/Z, [x24, x9, LSL #2]\n" + "ldr x20, [x24], #0x8\n" + "ld1w { z16.s }, p3/Z, [x20, x9, LSL #2]\n" "subs x21, x21, #0x1\n" - "fadd z6.s, z6.s, z2.s\n" + "fadd z6.s, z6.s, z16.s\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End "fmul z6.s, z6.s, z7.s\n" diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp index da0239cea8..d9cebd1363 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp @@ -66,10 +66,10 @@ void sve_fp32_nhwc_max_2x2_s1_output2x2_depthfirst_impl( "ldr x15, [%x[args], %[offsetof_n_channels]]\n" "ldr x21, [%x[args], %[offsetof_outptrs]]\n" "mov x14, #0x0\n" - "whilelt p2.s, x14, x15\n" + "whilelt p0.s, x14, x15\n" "ldr x20, [%x[args], %[offsetof_inptrs]]\n" "ldp x13, x12, [x21, #0x0]\n" - "ptrue p1.b\n" + "ptrue p2.b\n" "mov x11, #0x0\n" "ldp x10, x9, [x21, #0x10]\n" "ldp x28, x27, [x20, #0x0]\n" @@ -77,61 +77,61 @@ void sve_fp32_nhwc_max_2x2_s1_output2x2_depthfirst_impl( "ldp x24, x23, [x20, #0x20]\n" "ldp x22, x21, [x20, #0x30]\n" "ldr x20, [x20, #0x40]\n" - "ld1w { z31.s }, p2/Z, [x27, x14, LSL #2]\n" - "ld1w { z30.s }, p2/Z, [x24, x14, LSL #2]\n" - "ld1w { z29.s }, p2/Z, [x21, x14, LSL #2]\n" - "ld1w { z28.s }, p2/Z, [x25, x14, LSL #2]\n" - "ld1w { z27.s }, p2/Z, [x28, x14, LSL #2]\n" - "ld1w { z26.s }, p2/Z, [x26, x14, LSL #2]\n" - "ld1w { z25.s }, p2/Z, [x23, x14, LSL #2]\n" - "ld1w { z24.s }, p2/Z, [x22, x14, LSL #2]\n" - "ld1w { z23.s }, p2/Z, [x20, x14, LSL #2]\n" + "ld1w { z31.s }, p0/Z, [x27, x14, LSL #2]\n" + "ld1w { z30.s }, p0/Z, [x24, x14, LSL #2]\n" + "ld1w { z29.s }, p0/Z, [x21, x14, LSL #2]\n" + "ld1w { z28.s }, p0/Z, [x25, x14, LSL #2]\n" + "ld1w { z27.s }, p0/Z, [x28, x14, LSL #2]\n" + "ld1w { z26.s }, p0/Z, [x26, x14, LSL #2]\n" + "ld1w { z25.s }, p0/Z, [x23, x14, LSL #2]\n" + "ld1w { z24.s }, p0/Z, [x22, x14, LSL #2]\n" + "ld1w { z23.s }, p0/Z, [x20, x14, LSL #2]\n" "incw x14\n" - "whilelt p2.s, x14, x15\n" + "whilelt p1.s, x14, x15\n" "b.none 2f\n" "1:" // Vector: Loop - "movprfx z22, z31\n fmax z22.s, p1/M, z22.s, z30.s\n" - "movprfx z21, z30\n fmax z21.s, p1/M, z21.s, z29.s\n" - "ld1w { z31.s }, p2/Z, [x27, x14, LSL #2]\n" - "ld1w { z30.s }, p2/Z, [x24, x14, LSL #2]\n" - "movprfx z20, z28\n fmax z20.s, p1/M, z20.s, z27.s\n" - "movprfx z19, z26\n fmax z19.s, p1/M, z19.s, z25.s\n" - "ld1w { z29.s }, p2/Z, [x21, x14, LSL #2]\n" - "ld1w { z27.s }, p2/Z, [x28, x14, LSL #2]\n" - "movprfx z17, z28\n fmax z17.s, p1/M, z17.s, z24.s\n" - "movprfx z18, z25\n fmax z18.s, p1/M, z18.s, z23.s\n" - "ld1w { z28.s }, p2/Z, [x25, x14, LSL #2]\n" - "ld1w { z26.s }, p2/Z, [x26, x14, LSL #2]\n" - "ld1w { z25.s }, p2/Z, [x23, x14, LSL #2]\n" - "ld1w { z24.s }, p2/Z, [x22, x14, LSL #2]\n" + "movprfx z22, z31\n fmax z22.s, p2/M, z22.s, z30.s\n" + "movprfx z21, z30\n fmax z21.s, p2/M, z21.s, z29.s\n" + "ld1w { z31.s }, p1/Z, [x27, x14, LSL #2]\n" + "ld1w { z30.s }, p1/Z, [x24, x14, LSL #2]\n" + "movprfx z20, z28\n fmax z20.s, p2/M, z20.s, z27.s\n" + "movprfx z19, z26\n fmax z19.s, p2/M, z19.s, z25.s\n" + "ld1w { z29.s }, p1/Z, [x21, x14, LSL #2]\n" + "ld1w { z27.s }, p1/Z, [x28, x14, LSL #2]\n" + "movprfx z17, z28\n fmax z17.s, p2/M, z17.s, z24.s\n" + "movprfx z18, z25\n fmax z18.s, p2/M, z18.s, z23.s\n" + "ld1w { z28.s }, p1/Z, [x25, x14, LSL #2]\n" + "ld1w { z26.s }, p1/Z, [x26, x14, LSL #2]\n" + "ld1w { z25.s }, p1/Z, [x23, x14, LSL #2]\n" + "ld1w { z24.s }, p1/Z, [x22, x14, LSL #2]\n" "whilelt p0.s, x11, x15\n" - "movprfx z16, z22\n fmax z16.s, p1/M, z16.s, z20.s\n" - "ld1w { z23.s }, p2/Z, [x20, x14, LSL #2]\n" + "movprfx z16, z22\n fmax z16.s, p2/M, z16.s, z20.s\n" + "ld1w { z23.s }, p1/Z, [x20, x14, LSL #2]\n" "incw x14\n" - "whilelt p2.s, x14, x15\n" + "whilelt p1.s, x14, x15\n" "st1w { z16.s }, p0, [x13, x11, LSL #2]\n" - "movprfx z16, z19\n fmax z16.s, p1/M, z16.s, z22.s\n" - "fmax z17.s, p1/M, z17.s, z21.s\n" + "movprfx z16, z19\n fmax z16.s, p2/M, z16.s, z22.s\n" + "fmax z17.s, p2/M, z17.s, z21.s\n" "st1w { z16.s }, p0, [x12, x11, LSL #2]\n" - "movprfx z16, z18\n fmax z16.s, p1/M, z16.s, z21.s\n" + "movprfx z16, z21\n fmax z16.s, p2/M, z16.s, z18.s\n" "st1w { z17.s }, p0, [x10, x11, LSL #2]\n" "st1w { z16.s }, p0, [x9, x11, LSL #2]\n" "incw x11\n" "b.any 1b\n" "2:" // Vector: Tail - "movprfx z22, z31\n fmax z22.s, p1/M, z22.s, z30.s\n" - "movprfx z21, z30\n fmax z21.s, p1/M, z21.s, z29.s\n" - "movprfx z20, z28\n fmax z20.s, p1/M, z20.s, z27.s\n" - "movprfx z19, z26\n fmax z19.s, p1/M, z19.s, z25.s\n" - "movprfx z17, z28\n fmax z17.s, p1/M, z17.s, z24.s\n" - "movprfx z18, z25\n fmax z18.s, p1/M, z18.s, z23.s\n" + "movprfx z22, z31\n fmax z22.s, p2/M, z22.s, z30.s\n" + "movprfx z21, z30\n fmax z21.s, p2/M, z21.s, z29.s\n" + "movprfx z20, z28\n fmax z20.s, p2/M, z20.s, z27.s\n" + "movprfx z19, z26\n fmax z19.s, p2/M, z19.s, z25.s\n" + "movprfx z17, z28\n fmax z17.s, p2/M, z17.s, z24.s\n" + "movprfx z18, z25\n fmax z18.s, p2/M, z18.s, z23.s\n" "whilelt p0.s, x11, x15\n" - "movprfx z16, z22\n fmax z16.s, p1/M, z16.s, z20.s\n" + "movprfx z16, z22\n fmax z16.s, p2/M, z16.s, z20.s\n" "st1w { z16.s }, p0, [x13, x11, LSL #2]\n" - "movprfx z16, z19\n fmax z16.s, p1/M, z16.s, z22.s\n" - "fmax z17.s, p1/M, z17.s, z21.s\n" + "movprfx z16, z19\n fmax z16.s, p2/M, z16.s, z22.s\n" + "fmax z17.s, p2/M, z17.s, z21.s\n" "st1w { z16.s }, p0, [x12, x11, LSL #2]\n" - "movprfx z16, z18\n fmax z16.s, p1/M, z16.s, z21.s\n" + "movprfx z16, z21\n fmax z16.s, p2/M, z16.s, z18.s\n" "st1w { z17.s }, p0, [x10, x11, LSL #2]\n" "st1w { z16.s }, p0, [x9, x11, LSL #2]\n" : diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_max_generic_depthfirst/generic.cpp index ddce2be62c..87fc75adda 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_max_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_max_generic_depthfirst/generic.cpp @@ -54,68 +54,68 @@ void sve_fp32_nhwc_max_generic_depthfirst_impl( "lsr x25, %x[n_valid_cells], #0x2\n" "mov z8.s, #0xff800000\n" "mov z7.s, #0xff800000\n" - "mov x20, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "mov z6.s, #0xff800000\n" "mov z5.s, #0xff800000\n" "cbz x25, 4f\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldp x22, x21, [x20, #0x10]\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" "subs x25, x25, #0x1\n" - "add x20, x20, #0x20\n" - "ld1w { z4.s }, p4/Z, [x24, x9, LSL #2]\n" - "ld1w { z3.s }, p4/Z, [x23, x9, LSL #2]\n" - "ld1w { z2.s }, p4/Z, [x22, x9, LSL #2]\n" - "ld1w { z1.s }, p4/Z, [x21, x9, LSL #2]\n" - "ld1w { z0.s }, p3/Z, [x24, x28, LSL #2]\n" - "ld1w { z31.s }, p3/Z, [x23, x28, LSL #2]\n" - "ld1w { z22.s }, p3/Z, [x22, x28, LSL #2]\n" - "ld1w { z30.s }, p3/Z, [x21, x28, LSL #2]\n" - "ld1w { z29.s }, p2/Z, [x24, x27, LSL #2]\n" - "ld1w { z28.s }, p2/Z, [x23, x27, LSL #2]\n" - "ld1w { z21.s }, p2/Z, [x22, x27, LSL #2]\n" - "ld1w { z27.s }, p2/Z, [x21, x27, LSL #2]\n" - "ld1w { z26.s }, p1/Z, [x24, x26, LSL #2]\n" - "ld1w { z25.s }, p1/Z, [x23, x26, LSL #2]\n" - "ld1w { z20.s }, p1/Z, [x22, x26, LSL #2]\n" - "ld1w { z24.s }, p1/Z, [x21, x26, LSL #2]\n" + "add x24, x24, #0x20\n" + "ld1w { z4.s }, p4/Z, [x23, x9, LSL #2]\n" + "ld1w { z3.s }, p4/Z, [x22, x9, LSL #2]\n" + "ld1w { z2.s }, p4/Z, [x21, x9, LSL #2]\n" + "ld1w { z1.s }, p4/Z, [x20, x9, LSL #2]\n" + "ld1w { z0.s }, p3/Z, [x23, x28, LSL #2]\n" + "ld1w { z31.s }, p3/Z, [x22, x28, LSL #2]\n" + "ld1w { z22.s }, p3/Z, [x21, x28, LSL #2]\n" + "ld1w { z30.s }, p3/Z, [x20, x28, LSL #2]\n" + "ld1w { z29.s }, p2/Z, [x23, x27, LSL #2]\n" + "ld1w { z28.s }, p2/Z, [x22, x27, LSL #2]\n" + "ld1w { z21.s }, p2/Z, [x21, x27, LSL #2]\n" + "ld1w { z27.s }, p2/Z, [x20, x27, LSL #2]\n" + "ld1w { z26.s }, p1/Z, [x23, x26, LSL #2]\n" + "ld1w { z25.s }, p1/Z, [x22, x26, LSL #2]\n" + "ld1w { z20.s }, p1/Z, [x21, x26, LSL #2]\n" + "ld1w { z24.s }, p1/Z, [x20, x26, LSL #2]\n" "beq 3f\n" "2:" // 4-vectors of channels: 4 inputs loop "movprfx z19, z4\n fmax z19.s, p0/M, z19.s, z3.s\n" "movprfx z23, z2\n fmax z23.s, p0/M, z23.s, z1.s\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldp x22, x21, [x20, #0x10]\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" "movprfx z18, z0\n fmax z18.s, p0/M, z18.s, z31.s\n" "fmax z22.s, p0/M, z22.s, z30.s\n" - "ld1w { z4.s }, p4/Z, [x24, x9, LSL #2]\n" - "ld1w { z3.s }, p4/Z, [x23, x9, LSL #2]\n" + "ld1w { z4.s }, p4/Z, [x23, x9, LSL #2]\n" + "ld1w { z3.s }, p4/Z, [x22, x9, LSL #2]\n" "movprfx z17, z29\n fmax z17.s, p0/M, z17.s, z28.s\n" "fmax z21.s, p0/M, z21.s, z27.s\n" - "ld1w { z2.s }, p4/Z, [x22, x9, LSL #2]\n" - "ld1w { z1.s }, p4/Z, [x21, x9, LSL #2]\n" + "ld1w { z2.s }, p4/Z, [x21, x9, LSL #2]\n" + "ld1w { z1.s }, p4/Z, [x20, x9, LSL #2]\n" "movprfx z16, z26\n fmax z16.s, p0/M, z16.s, z25.s\n" "fmax z20.s, p0/M, z20.s, z24.s\n" - "ld1w { z0.s }, p3/Z, [x24, x28, LSL #2]\n" - "ld1w { z31.s }, p3/Z, [x23, x28, LSL #2]\n" + "ld1w { z0.s }, p3/Z, [x23, x28, LSL #2]\n" + "ld1w { z31.s }, p3/Z, [x22, x28, LSL #2]\n" "fmax z19.s, p0/M, z19.s, z23.s\n" "fmax z18.s, p0/M, z18.s, z22.s\n" - "ld1w { z22.s }, p3/Z, [x22, x28, LSL #2]\n" - "ld1w { z30.s }, p3/Z, [x21, x28, LSL #2]\n" + "ld1w { z22.s }, p3/Z, [x21, x28, LSL #2]\n" + "ld1w { z30.s }, p3/Z, [x20, x28, LSL #2]\n" "fmax z17.s, p0/M, z17.s, z21.s\n" "fmax z16.s, p0/M, z16.s, z20.s\n" - "ld1w { z29.s }, p2/Z, [x24, x27, LSL #2]\n" - "ld1w { z28.s }, p2/Z, [x23, x27, LSL #2]\n" + "ld1w { z29.s }, p2/Z, [x23, x27, LSL #2]\n" + "ld1w { z28.s }, p2/Z, [x22, x27, LSL #2]\n" "subs x25, x25, #0x1\n" "fmax z8.s, p0/M, z8.s, z19.s\n" - "ld1w { z21.s }, p2/Z, [x22, x27, LSL #2]\n" - "ld1w { z27.s }, p2/Z, [x21, x27, LSL #2]\n" + "ld1w { z21.s }, p2/Z, [x21, x27, LSL #2]\n" + "ld1w { z27.s }, p2/Z, [x20, x27, LSL #2]\n" "fmax z7.s, p0/M, z7.s, z18.s\n" "fmax z6.s, p0/M, z6.s, z17.s\n" - "ld1w { z26.s }, p1/Z, [x24, x26, LSL #2]\n" - "ld1w { z25.s }, p1/Z, [x23, x26, LSL #2]\n" + "ld1w { z26.s }, p1/Z, [x23, x26, LSL #2]\n" + "ld1w { z25.s }, p1/Z, [x22, x26, LSL #2]\n" "fmax z5.s, p0/M, z5.s, z16.s\n" - "add x20, x20, #0x20\n" - "ld1w { z20.s }, p1/Z, [x22, x26, LSL #2]\n" - "ld1w { z24.s }, p1/Z, [x21, x26, LSL #2]\n" + "add x24, x24, #0x20\n" + "ld1w { z20.s }, p1/Z, [x21, x26, LSL #2]\n" + "ld1w { z24.s }, p1/Z, [x20, x26, LSL #2]\n" "bgt 2b\n" "3:" // 4-vectors of channels: 4 inputs tail "movprfx z19, z4\n fmax z19.s, p0/M, z19.s, z3.s\n" @@ -138,16 +138,16 @@ void sve_fp32_nhwc_max_generic_depthfirst_impl( "ands x21, %x[n_valid_cells], #0x3\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x24, [x20], #0x8\n" - "ld1w { z4.s }, p4/Z, [x24, x9, LSL #2]\n" + "ldr x20, [x24], #0x8\n" + "ld1w { z16.s }, p4/Z, [x20, x9, LSL #2]\n" "subs x21, x21, #0x1\n" - "fmax z8.s, p0/M, z8.s, z4.s\n" - "ld1w { z0.s }, p3/Z, [x24, x28, LSL #2]\n" - "ld1w { z29.s }, p2/Z, [x24, x27, LSL #2]\n" - "fmax z7.s, p0/M, z7.s, z0.s\n" - "fmax z6.s, p0/M, z6.s, z29.s\n" - "ld1w { z26.s }, p1/Z, [x24, x26, LSL #2]\n" - "fmax z5.s, p0/M, z5.s, z26.s\n" + "fmax z8.s, p0/M, z8.s, z16.s\n" + "ld1w { z17.s }, p3/Z, [x20, x28, LSL #2]\n" + "ld1w { z16.s }, p2/Z, [x20, x27, LSL #2]\n" + "fmax z7.s, p0/M, z7.s, z17.s\n" + "fmax z6.s, p0/M, z6.s, z16.s\n" + "ld1w { z16.s }, p1/Z, [x20, x26, LSL #2]\n" + "fmax z5.s, p0/M, z5.s, z16.s\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End "st1w { z8.s }, p4, [%x[outptr], x9, LSL #2]\n" @@ -166,44 +166,44 @@ void sve_fp32_nhwc_max_generic_depthfirst_impl( "8:" // Single vector of channels: Loop "lsr x25, %x[n_valid_cells], #0x2\n" "mov z8.s, #0xff800000\n" - "mov x20, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "cbz x25, 11f\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldp x22, x21, [x20, #0x10]\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" "subs x25, x25, #0x1\n" - "add x20, x20, #0x20\n" - "ld1w { z4.s }, p4/Z, [x24, x9, LSL #2]\n" - "ld1w { z3.s }, p4/Z, [x23, x9, LSL #2]\n" - "ld1w { z2.s }, p4/Z, [x22, x9, LSL #2]\n" - "ld1w { z1.s }, p4/Z, [x21, x9, LSL #2]\n" + "add x24, x24, #0x20\n" + "ld1w { z4.s }, p4/Z, [x23, x9, LSL #2]\n" + "ld1w { z3.s }, p4/Z, [x22, x9, LSL #2]\n" + "ld1w { z2.s }, p4/Z, [x21, x9, LSL #2]\n" + "ld1w { z1.s }, p4/Z, [x20, x9, LSL #2]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 4 inputs loop - "movprfx z19, z4\n fmax z19.s, p0/M, z19.s, z3.s\n" - "movprfx z23, z2\n fmax z23.s, p0/M, z23.s, z1.s\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldp x22, x21, [x20, #0x10]\n" - "fmax z19.s, p0/M, z19.s, z23.s\n" + "movprfx z16, z4\n fmax z16.s, p0/M, z16.s, z3.s\n" + "movprfx z17, z2\n fmax z17.s, p0/M, z17.s, z1.s\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "fmax z16.s, p0/M, z16.s, z17.s\n" "subs x25, x25, #0x1\n" - "ld1w { z4.s }, p4/Z, [x24, x9, LSL #2]\n" - "ld1w { z3.s }, p4/Z, [x23, x9, LSL #2]\n" - "fmax z8.s, p0/M, z8.s, z19.s\n" - "add x20, x20, #0x20\n" - "ld1w { z2.s }, p4/Z, [x22, x9, LSL #2]\n" - "ld1w { z1.s }, p4/Z, [x21, x9, LSL #2]\n" + "ld1w { z4.s }, p4/Z, [x23, x9, LSL #2]\n" + "ld1w { z3.s }, p4/Z, [x22, x9, LSL #2]\n" + "fmax z8.s, p0/M, z8.s, z16.s\n" + "add x24, x24, #0x20\n" + "ld1w { z2.s }, p4/Z, [x21, x9, LSL #2]\n" + "ld1w { z1.s }, p4/Z, [x20, x9, LSL #2]\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 4 inputs tail - "movprfx z19, z4\n fmax z19.s, p0/M, z19.s, z3.s\n" - "movprfx z23, z2\n fmax z23.s, p0/M, z23.s, z1.s\n" - "fmax z19.s, p0/M, z19.s, z23.s\n" - "fmax z8.s, p0/M, z8.s, z19.s\n" + "movprfx z16, z4\n fmax z16.s, p0/M, z16.s, z3.s\n" + "movprfx z17, z2\n fmax z17.s, p0/M, z17.s, z1.s\n" + "fmax z16.s, p0/M, z16.s, z17.s\n" + "fmax z8.s, p0/M, z8.s, z16.s\n" "11:" // Single vector of channels: Loop: After loop "ands x21, %x[n_valid_cells], #0x3\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x24, [x20], #0x8\n" - "ld1w { z4.s }, p4/Z, [x24, x9, LSL #2]\n" + "ldr x20, [x24], #0x8\n" + "ld1w { z16.s }, p4/Z, [x20, x9, LSL #2]\n" "subs x21, x21, #0x1\n" - "fmax z8.s, p0/M, z8.s, z4.s\n" + "fmax z8.s, p0/M, z8.s, z16.s\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End "st1w { z8.s }, p4, [%x[outptr], x9, LSL #2]\n" diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8_nhwc_avg_generic_depthfirst/generic.cpp index 68bd831d63..7925905e64 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8_nhwc_avg_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8_nhwc_avg_generic_depthfirst/generic.cpp @@ -109,7 +109,7 @@ void sve_s8_nhwc_avg_generic_depthfirst_impl( "lsr x23, %x[n_valid_cells], #0x1\n" "mov z15.s, #0x0\n" "mov z14.s, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "mov z13.s, #0x0\n" "mov z12.s, #0x0\n" "mov z11.s, #0x0\n" @@ -125,42 +125,42 @@ void sve_s8_nhwc_avg_generic_depthfirst_impl( "mov z1.s, #0x0\n" "mov z0.s, #0x0\n" "cbz x23, 4f\n" - "ldp x22, x21, [x20, #0x0]\n" + "ldp x21, x20, [x22, #0x0]\n" "subs x23, x23, #0x1\n" - "add x20, x20, #0x10\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" - "ld1b { z30.b }, p4/Z, [x21, x27]\n" - "ld1b { z29.b }, p3/Z, [x22, x26]\n" - "ld1b { z28.b }, p3/Z, [x21, x26]\n" - "ld1b { z27.b }, p2/Z, [x22, x25]\n" - "ld1b { z26.b }, p2/Z, [x21, x25]\n" - "ld1b { z25.b }, p1/Z, [x22, x24]\n" - "ld1b { z24.b }, p1/Z, [x21, x24]\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" + "ld1b { z29.b }, p3/Z, [x21, x26]\n" + "ld1b { z28.b }, p3/Z, [x20, x26]\n" + "ld1b { z27.b }, p2/Z, [x21, x25]\n" + "ld1b { z26.b }, p2/Z, [x20, x25]\n" + "ld1b { z25.b }, p1/Z, [x21, x24]\n" + "ld1b { z24.b }, p1/Z, [x20, x24]\n" "beq 3f\n" "2:" // 4-vectors of channels: 2 inputs loop ".inst 0x455e03f7 // saddlb z23.h, z31.b, z30.b\n" ".inst 0x455e07f6 // saddlt z22.h, z31.b, z30.b\n" - "ldp x22, x21, [x20, #0x0]\n" + "ldp x21, x20, [x22, #0x0]\n" "subs x23, x23, #0x1\n" ".inst 0x455c03b5 // saddlb z21.h, z29.b, z28.b\n" ".inst 0x455c07b4 // saddlt z20.h, z29.b, z28.b\n" - "add x20, x20, #0x10\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" ".inst 0x455a0373 // saddlb z19.h, z27.b, z26.b\n" ".inst 0x455a0772 // saddlt z18.h, z27.b, z26.b\n" - "ld1b { z30.b }, p4/Z, [x21, x27]\n" - "ld1b { z29.b }, p3/Z, [x22, x26]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" + "ld1b { z29.b }, p3/Z, [x21, x26]\n" ".inst 0x45580331 // saddlb z17.h, z25.b, z24.b\n" ".inst 0x45580730 // saddlt z16.h, z25.b, z24.b\n" - "ld1b { z28.b }, p3/Z, [x21, x26]\n" - "ld1b { z27.b }, p2/Z, [x22, x25]\n" + "ld1b { z28.b }, p3/Z, [x20, x26]\n" + "ld1b { z27.b }, p2/Z, [x21, x25]\n" ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" - "ld1b { z26.b }, p2/Z, [x21, x25]\n" - "ld1b { z25.b }, p1/Z, [x22, x24]\n" + "ld1b { z26.b }, p2/Z, [x20, x25]\n" + "ld1b { z25.b }, p1/Z, [x21, x24]\n" ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" - "ld1b { z24.b }, p1/Z, [x21, x24]\n" + "ld1b { z24.b }, p1/Z, [x20, x24]\n" ".inst 0x4595416b // saddwb z11.s, z11.s, z21.h\n" ".inst 0x4595454a // saddwt z10.s, z10.s, z21.h\n" ".inst 0x45944129 // saddwb z9.s, z9.s, z20.h\n" @@ -203,20 +203,20 @@ void sve_s8_nhwc_avg_generic_depthfirst_impl( "ands x21, %x[n_valid_cells], #0x1\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x22, [x20], #0x8\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" - ".inst 0x4508a3f7 // sshllb z23.h, z31.b, #0x0\n" - ".inst 0x4508a7f6 // sshllt z22.h, z31.b, #0x0\n" - "ld1b { z29.b }, p3/Z, [x22, x26]\n" - "ld1b { z27.b }, p2/Z, [x22, x25]\n" - ".inst 0x4508a3b5 // sshllb z21.h, z29.b, #0x0\n" - ".inst 0x4508a7b4 // sshllt z20.h, z29.b, #0x0\n" - "ld1b { z25.b }, p1/Z, [x22, x24]\n" - ".inst 0x4508a373 // sshllb z19.h, z27.b, #0x0\n" - ".inst 0x4508a772 // sshllt z18.h, z27.b, #0x0\n" + "ldr x20, [x22], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x27]\n" + ".inst 0x4508a217 // sshllb z23.h, z16.b, #0x0\n" + ".inst 0x4508a616 // sshllt z22.h, z16.b, #0x0\n" + "ld1b { z16.b }, p3/Z, [x20, x26]\n" + "ld1b { z17.b }, p2/Z, [x20, x25]\n" + ".inst 0x4508a215 // sshllb z21.h, z16.b, #0x0\n" + ".inst 0x4508a614 // sshllt z20.h, z16.b, #0x0\n" + "ld1b { z16.b }, p1/Z, [x20, x24]\n" + ".inst 0x4508a233 // sshllb z19.h, z17.b, #0x0\n" + ".inst 0x4508a632 // sshllt z18.h, z17.b, #0x0\n" "subs x21, x21, #0x1\n" - ".inst 0x4508a331 // sshllb z17.h, z25.b, #0x0\n" - ".inst 0x4508a730 // sshllt z16.h, z25.b, #0x0\n" + ".inst 0x4508a211 // sshllb z17.h, z16.b, #0x0\n" + ".inst 0x4508a610 // sshllt z16.h, z16.b, #0x0\n" ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" @@ -332,49 +332,49 @@ void sve_s8_nhwc_avg_generic_depthfirst_impl( "lsr x23, %x[n_valid_cells], #0x1\n" "mov z15.s, #0x0\n" "mov z14.s, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "mov z13.s, #0x0\n" "mov z12.s, #0x0\n" "cbz x23, 11f\n" - "ldp x22, x21, [x20, #0x0]\n" + "ldp x21, x20, [x22, #0x0]\n" "subs x23, x23, #0x1\n" - "add x20, x20, #0x10\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" - "ld1b { z30.b }, p4/Z, [x21, x27]\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 2 inputs loop - ".inst 0x455e03f7 // saddlb z23.h, z31.b, z30.b\n" - ".inst 0x455e07f6 // saddlt z22.h, z31.b, z30.b\n" - "ldp x22, x21, [x20, #0x0]\n" + ".inst 0x455e03f1 // saddlb z17.h, z31.b, z30.b\n" + ".inst 0x455e07f0 // saddlt z16.h, z31.b, z30.b\n" + "ldp x21, x20, [x22, #0x0]\n" "subs x23, x23, #0x1\n" - ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" - ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" - "add x20, x20, #0x10\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" - ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" - ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" - "ld1b { z30.b }, p4/Z, [x21, x27]\n" + ".inst 0x459141ef // saddwb z15.s, z15.s, z17.h\n" + ".inst 0x459145ce // saddwt z14.s, z14.s, z17.h\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + ".inst 0x459041ad // saddwb z13.s, z13.s, z16.h\n" + ".inst 0x4590458c // saddwt z12.s, z12.s, z16.h\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 2 inputs tail - ".inst 0x455e03f7 // saddlb z23.h, z31.b, z30.b\n" - ".inst 0x455e07f6 // saddlt z22.h, z31.b, z30.b\n" - ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" - ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" - ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" - ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" + ".inst 0x455e03f1 // saddlb z17.h, z31.b, z30.b\n" + ".inst 0x455e07f0 // saddlt z16.h, z31.b, z30.b\n" + ".inst 0x459141ef // saddwb z15.s, z15.s, z17.h\n" + ".inst 0x459145ce // saddwt z14.s, z14.s, z17.h\n" + ".inst 0x459041ad // saddwb z13.s, z13.s, z16.h\n" + ".inst 0x4590458c // saddwt z12.s, z12.s, z16.h\n" "11:" // Single vector of channels: Loop: After loop "ands x21, %x[n_valid_cells], #0x1\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x22, [x20], #0x8\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" - ".inst 0x4508a3f7 // sshllb z23.h, z31.b, #0x0\n" - ".inst 0x4508a7f6 // sshllt z22.h, z31.b, #0x0\n" + "ldr x20, [x22], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x27]\n" + ".inst 0x4508a211 // sshllb z17.h, z16.b, #0x0\n" + ".inst 0x4508a610 // sshllt z16.h, z16.b, #0x0\n" "subs x21, x21, #0x1\n" - ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" - ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" - ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" - ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" + ".inst 0x459141ef // saddwb z15.s, z15.s, z17.h\n" + ".inst 0x459145ce // saddwt z14.s, z14.s, z17.h\n" + ".inst 0x459041ad // saddwb z13.s, z13.s, z16.h\n" + ".inst 0x4590458c // saddwt z12.s, z12.s, z16.h\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End "ld1rw { z17.s }, p0/Z, [%x[rescale_ptr]]\n" diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp index 96e20c752e..5681cc1f3d 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp @@ -66,10 +66,10 @@ void sve_s8_nhwc_max_2x2_s1_output2x2_depthfirst_impl( "ldr x15, [%x[args], %[offsetof_n_channels]]\n" "ldr x21, [%x[args], %[offsetof_outptrs]]\n" "mov x14, #0x0\n" - "whilelt p2.b, x14, x15\n" + "whilelt p0.b, x14, x15\n" "ldr x20, [%x[args], %[offsetof_inptrs]]\n" "ldp x13, x12, [x21, #0x0]\n" - "ptrue p1.b\n" + "ptrue p2.b\n" "mov x11, #0x0\n" "ldp x10, x9, [x21, #0x10]\n" "ldp x28, x27, [x20, #0x0]\n" @@ -77,61 +77,61 @@ void sve_s8_nhwc_max_2x2_s1_output2x2_depthfirst_impl( "ldp x24, x23, [x20, #0x20]\n" "ldp x22, x21, [x20, #0x30]\n" "ldr x20, [x20, #0x40]\n" - "ld1b { z31.b }, p2/Z, [x27, x14]\n" - "ld1b { z30.b }, p2/Z, [x24, x14]\n" - "ld1b { z29.b }, p2/Z, [x21, x14]\n" - "ld1b { z28.b }, p2/Z, [x25, x14]\n" - "ld1b { z27.b }, p2/Z, [x28, x14]\n" - "ld1b { z26.b }, p2/Z, [x26, x14]\n" - "ld1b { z25.b }, p2/Z, [x23, x14]\n" - "ld1b { z24.b }, p2/Z, [x22, x14]\n" - "ld1b { z23.b }, p2/Z, [x20, x14]\n" + "ld1b { z31.b }, p0/Z, [x27, x14]\n" + "ld1b { z30.b }, p0/Z, [x24, x14]\n" + "ld1b { z29.b }, p0/Z, [x21, x14]\n" + "ld1b { z28.b }, p0/Z, [x25, x14]\n" + "ld1b { z27.b }, p0/Z, [x28, x14]\n" + "ld1b { z26.b }, p0/Z, [x26, x14]\n" + "ld1b { z25.b }, p0/Z, [x23, x14]\n" + "ld1b { z24.b }, p0/Z, [x22, x14]\n" + "ld1b { z23.b }, p0/Z, [x20, x14]\n" "incw x14\n" - "whilelt p2.b, x14, x15\n" + "whilelt p1.b, x14, x15\n" "b.none 2f\n" "1:" // Vector: Loop - "movprfx z22, z31\n smax z22.b, p1/M, z22.b, z30.b\n" - "movprfx z21, z30\n smax z21.b, p1/M, z21.b, z29.b\n" - "ld1b { z31.b }, p2/Z, [x27, x14]\n" - "ld1b { z30.b }, p2/Z, [x24, x14]\n" - "movprfx z20, z28\n smax z20.b, p1/M, z20.b, z27.b\n" - "movprfx z19, z26\n smax z19.b, p1/M, z19.b, z25.b\n" - "ld1b { z29.b }, p2/Z, [x21, x14]\n" - "ld1b { z27.b }, p2/Z, [x28, x14]\n" - "movprfx z17, z28\n smax z17.b, p1/M, z17.b, z24.b\n" - "movprfx z18, z25\n smax z18.b, p1/M, z18.b, z23.b\n" - "ld1b { z28.b }, p2/Z, [x25, x14]\n" - "ld1b { z26.b }, p2/Z, [x26, x14]\n" - "ld1b { z25.b }, p2/Z, [x23, x14]\n" - "ld1b { z24.b }, p2/Z, [x22, x14]\n" + "movprfx z22, z31\n smax z22.b, p2/M, z22.b, z30.b\n" + "movprfx z21, z30\n smax z21.b, p2/M, z21.b, z29.b\n" + "ld1b { z31.b }, p1/Z, [x27, x14]\n" + "ld1b { z30.b }, p1/Z, [x24, x14]\n" + "movprfx z20, z28\n smax z20.b, p2/M, z20.b, z27.b\n" + "movprfx z19, z26\n smax z19.b, p2/M, z19.b, z25.b\n" + "ld1b { z29.b }, p1/Z, [x21, x14]\n" + "ld1b { z27.b }, p1/Z, [x28, x14]\n" + "movprfx z17, z28\n smax z17.b, p2/M, z17.b, z24.b\n" + "movprfx z18, z25\n smax z18.b, p2/M, z18.b, z23.b\n" + "ld1b { z28.b }, p1/Z, [x25, x14]\n" + "ld1b { z26.b }, p1/Z, [x26, x14]\n" + "ld1b { z25.b }, p1/Z, [x23, x14]\n" + "ld1b { z24.b }, p1/Z, [x22, x14]\n" "whilelt p0.b, x11, x15\n" - "movprfx z16, z22\n smax z16.b, p1/M, z16.b, z20.b\n" - "ld1b { z23.b }, p2/Z, [x20, x14]\n" + "movprfx z16, z22\n smax z16.b, p2/M, z16.b, z20.b\n" + "ld1b { z23.b }, p1/Z, [x20, x14]\n" "incw x14\n" - "whilelt p2.b, x14, x15\n" + "whilelt p1.b, x14, x15\n" "st1b { z16.b }, p0, [x13, x11]\n" - "movprfx z16, z19\n smax z16.b, p1/M, z16.b, z22.b\n" - "smax z17.b, p1/M, z17.b, z21.b\n" + "movprfx z16, z19\n smax z16.b, p2/M, z16.b, z22.b\n" + "smax z17.b, p2/M, z17.b, z21.b\n" "st1b { z16.b }, p0, [x12, x11]\n" - "movprfx z16, z18\n smax z16.b, p1/M, z16.b, z21.b\n" + "movprfx z16, z21\n smax z16.b, p2/M, z16.b, z18.b\n" "st1b { z17.b }, p0, [x10, x11]\n" "st1b { z16.b }, p0, [x9, x11]\n" "incw x11\n" "b.any 1b\n" "2:" // Vector: Tail - "movprfx z22, z31\n smax z22.b, p1/M, z22.b, z30.b\n" - "movprfx z21, z30\n smax z21.b, p1/M, z21.b, z29.b\n" - "movprfx z20, z28\n smax z20.b, p1/M, z20.b, z27.b\n" - "movprfx z19, z26\n smax z19.b, p1/M, z19.b, z25.b\n" - "movprfx z17, z28\n smax z17.b, p1/M, z17.b, z24.b\n" - "movprfx z18, z25\n smax z18.b, p1/M, z18.b, z23.b\n" + "movprfx z22, z31\n smax z22.b, p2/M, z22.b, z30.b\n" + "movprfx z21, z30\n smax z21.b, p2/M, z21.b, z29.b\n" + "movprfx z20, z28\n smax z20.b, p2/M, z20.b, z27.b\n" + "movprfx z19, z26\n smax z19.b, p2/M, z19.b, z25.b\n" + "movprfx z17, z28\n smax z17.b, p2/M, z17.b, z24.b\n" + "movprfx z18, z25\n smax z18.b, p2/M, z18.b, z23.b\n" "whilelt p0.b, x11, x15\n" - "movprfx z16, z22\n smax z16.b, p1/M, z16.b, z20.b\n" + "movprfx z16, z22\n smax z16.b, p2/M, z16.b, z20.b\n" "st1b { z16.b }, p0, [x13, x11]\n" - "movprfx z16, z19\n smax z16.b, p1/M, z16.b, z22.b\n" - "smax z17.b, p1/M, z17.b, z21.b\n" + "movprfx z16, z19\n smax z16.b, p2/M, z16.b, z22.b\n" + "smax z17.b, p2/M, z17.b, z21.b\n" "st1b { z16.b }, p0, [x12, x11]\n" - "movprfx z16, z18\n smax z16.b, p1/M, z16.b, z21.b\n" + "movprfx z16, z21\n smax z16.b, p2/M, z16.b, z18.b\n" "st1b { z17.b }, p0, [x10, x11]\n" "st1b { z16.b }, p0, [x9, x11]\n" : diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8_nhwc_max_generic_depthfirst/generic.cpp index 7d14edddeb..da9e1408f9 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8_nhwc_max_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8_nhwc_max_generic_depthfirst/generic.cpp @@ -54,68 +54,68 @@ void sve_s8_nhwc_max_generic_depthfirst_impl( "lsr x25, %x[n_valid_cells], #0x2\n" "mov z8.b, #0x80\n" "mov z7.b, #0x80\n" - "mov x20, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "mov z6.b, #0x80\n" "mov z5.b, #0x80\n" "cbz x25, 4f\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldp x22, x21, [x20, #0x10]\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" "subs x25, x25, #0x1\n" - "add x20, x20, #0x20\n" - "ld1b { z4.b }, p4/Z, [x24, x9]\n" - "ld1b { z3.b }, p4/Z, [x23, x9]\n" - "ld1b { z2.b }, p4/Z, [x22, x9]\n" - "ld1b { z1.b }, p4/Z, [x21, x9]\n" - "ld1b { z0.b }, p3/Z, [x24, x28]\n" - "ld1b { z31.b }, p3/Z, [x23, x28]\n" - "ld1b { z22.b }, p3/Z, [x22, x28]\n" - "ld1b { z30.b }, p3/Z, [x21, x28]\n" - "ld1b { z29.b }, p2/Z, [x24, x27]\n" - "ld1b { z28.b }, p2/Z, [x23, x27]\n" - "ld1b { z21.b }, p2/Z, [x22, x27]\n" - "ld1b { z27.b }, p2/Z, [x21, x27]\n" - "ld1b { z26.b }, p1/Z, [x24, x26]\n" - "ld1b { z25.b }, p1/Z, [x23, x26]\n" - "ld1b { z20.b }, p1/Z, [x22, x26]\n" - "ld1b { z24.b }, p1/Z, [x21, x26]\n" + "add x24, x24, #0x20\n" + "ld1b { z4.b }, p4/Z, [x23, x9]\n" + "ld1b { z3.b }, p4/Z, [x22, x9]\n" + "ld1b { z2.b }, p4/Z, [x21, x9]\n" + "ld1b { z1.b }, p4/Z, [x20, x9]\n" + "ld1b { z0.b }, p3/Z, [x23, x28]\n" + "ld1b { z31.b }, p3/Z, [x22, x28]\n" + "ld1b { z22.b }, p3/Z, [x21, x28]\n" + "ld1b { z30.b }, p3/Z, [x20, x28]\n" + "ld1b { z29.b }, p2/Z, [x23, x27]\n" + "ld1b { z28.b }, p2/Z, [x22, x27]\n" + "ld1b { z21.b }, p2/Z, [x21, x27]\n" + "ld1b { z27.b }, p2/Z, [x20, x27]\n" + "ld1b { z26.b }, p1/Z, [x23, x26]\n" + "ld1b { z25.b }, p1/Z, [x22, x26]\n" + "ld1b { z20.b }, p1/Z, [x21, x26]\n" + "ld1b { z24.b }, p1/Z, [x20, x26]\n" "beq 3f\n" "2:" // 4-vectors of channels: 4 inputs loop "movprfx z19, z4\n smax z19.b, p0/M, z19.b, z3.b\n" "movprfx z23, z2\n smax z23.b, p0/M, z23.b, z1.b\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldp x22, x21, [x20, #0x10]\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" "movprfx z18, z0\n smax z18.b, p0/M, z18.b, z31.b\n" "smax z22.b, p0/M, z22.b, z30.b\n" - "ld1b { z4.b }, p4/Z, [x24, x9]\n" - "ld1b { z3.b }, p4/Z, [x23, x9]\n" + "ld1b { z4.b }, p4/Z, [x23, x9]\n" + "ld1b { z3.b }, p4/Z, [x22, x9]\n" "movprfx z17, z29\n smax z17.b, p0/M, z17.b, z28.b\n" "smax z21.b, p0/M, z21.b, z27.b\n" - "ld1b { z2.b }, p4/Z, [x22, x9]\n" - "ld1b { z1.b }, p4/Z, [x21, x9]\n" + "ld1b { z2.b }, p4/Z, [x21, x9]\n" + "ld1b { z1.b }, p4/Z, [x20, x9]\n" "movprfx z16, z26\n smax z16.b, p0/M, z16.b, z25.b\n" "smax z20.b, p0/M, z20.b, z24.b\n" - "ld1b { z0.b }, p3/Z, [x24, x28]\n" - "ld1b { z31.b }, p3/Z, [x23, x28]\n" + "ld1b { z0.b }, p3/Z, [x23, x28]\n" + "ld1b { z31.b }, p3/Z, [x22, x28]\n" "smax z19.b, p0/M, z19.b, z23.b\n" "smax z18.b, p0/M, z18.b, z22.b\n" - "ld1b { z22.b }, p3/Z, [x22, x28]\n" - "ld1b { z30.b }, p3/Z, [x21, x28]\n" + "ld1b { z22.b }, p3/Z, [x21, x28]\n" + "ld1b { z30.b }, p3/Z, [x20, x28]\n" "smax z17.b, p0/M, z17.b, z21.b\n" "smax z16.b, p0/M, z16.b, z20.b\n" - "ld1b { z29.b }, p2/Z, [x24, x27]\n" - "ld1b { z28.b }, p2/Z, [x23, x27]\n" + "ld1b { z29.b }, p2/Z, [x23, x27]\n" + "ld1b { z28.b }, p2/Z, [x22, x27]\n" "subs x25, x25, #0x1\n" "smax z8.b, p0/M, z8.b, z19.b\n" - "ld1b { z21.b }, p2/Z, [x22, x27]\n" - "ld1b { z27.b }, p2/Z, [x21, x27]\n" + "ld1b { z21.b }, p2/Z, [x21, x27]\n" + "ld1b { z27.b }, p2/Z, [x20, x27]\n" "smax z7.b, p0/M, z7.b, z18.b\n" "smax z6.b, p0/M, z6.b, z17.b\n" - "ld1b { z26.b }, p1/Z, [x24, x26]\n" - "ld1b { z25.b }, p1/Z, [x23, x26]\n" + "ld1b { z26.b }, p1/Z, [x23, x26]\n" + "ld1b { z25.b }, p1/Z, [x22, x26]\n" "smax z5.b, p0/M, z5.b, z16.b\n" - "add x20, x20, #0x20\n" - "ld1b { z20.b }, p1/Z, [x22, x26]\n" - "ld1b { z24.b }, p1/Z, [x21, x26]\n" + "add x24, x24, #0x20\n" + "ld1b { z20.b }, p1/Z, [x21, x26]\n" + "ld1b { z24.b }, p1/Z, [x20, x26]\n" "bgt 2b\n" "3:" // 4-vectors of channels: 4 inputs tail "movprfx z19, z4\n smax z19.b, p0/M, z19.b, z3.b\n" @@ -138,16 +138,16 @@ void sve_s8_nhwc_max_generic_depthfirst_impl( "ands x21, %x[n_valid_cells], #0x3\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x24, [x20], #0x8\n" - "ld1b { z4.b }, p4/Z, [x24, x9]\n" + "ldr x20, [x24], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x9]\n" "subs x21, x21, #0x1\n" - "smax z8.b, p0/M, z8.b, z4.b\n" - "ld1b { z0.b }, p3/Z, [x24, x28]\n" - "ld1b { z29.b }, p2/Z, [x24, x27]\n" - "smax z7.b, p0/M, z7.b, z0.b\n" - "smax z6.b, p0/M, z6.b, z29.b\n" - "ld1b { z26.b }, p1/Z, [x24, x26]\n" - "smax z5.b, p0/M, z5.b, z26.b\n" + "smax z8.b, p0/M, z8.b, z16.b\n" + "ld1b { z17.b }, p3/Z, [x20, x28]\n" + "ld1b { z16.b }, p2/Z, [x20, x27]\n" + "smax z7.b, p0/M, z7.b, z17.b\n" + "smax z6.b, p0/M, z6.b, z16.b\n" + "ld1b { z16.b }, p1/Z, [x20, x26]\n" + "smax z5.b, p0/M, z5.b, z16.b\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End "st1b { z8.b }, p4, [%x[outptr], x9]\n" @@ -166,44 +166,44 @@ void sve_s8_nhwc_max_generic_depthfirst_impl( "8:" // Single vector of channels: Loop "lsr x25, %x[n_valid_cells], #0x2\n" "mov z8.b, #0x80\n" - "mov x20, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "cbz x25, 11f\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldp x22, x21, [x20, #0x10]\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" "subs x25, x25, #0x1\n" - "add x20, x20, #0x20\n" - "ld1b { z4.b }, p4/Z, [x24, x9]\n" - "ld1b { z3.b }, p4/Z, [x23, x9]\n" - "ld1b { z2.b }, p4/Z, [x22, x9]\n" - "ld1b { z1.b }, p4/Z, [x21, x9]\n" + "add x24, x24, #0x20\n" + "ld1b { z4.b }, p4/Z, [x23, x9]\n" + "ld1b { z3.b }, p4/Z, [x22, x9]\n" + "ld1b { z2.b }, p4/Z, [x21, x9]\n" + "ld1b { z1.b }, p4/Z, [x20, x9]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 4 inputs loop - "movprfx z19, z4\n smax z19.b, p0/M, z19.b, z3.b\n" - "movprfx z23, z2\n smax z23.b, p0/M, z23.b, z1.b\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldp x22, x21, [x20, #0x10]\n" - "smax z19.b, p0/M, z19.b, z23.b\n" + "movprfx z16, z4\n smax z16.b, p0/M, z16.b, z3.b\n" + "movprfx z17, z2\n smax z17.b, p0/M, z17.b, z1.b\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "smax z16.b, p0/M, z16.b, z17.b\n" "subs x25, x25, #0x1\n" - "ld1b { z4.b }, p4/Z, [x24, x9]\n" - "ld1b { z3.b }, p4/Z, [x23, x9]\n" - "smax z8.b, p0/M, z8.b, z19.b\n" - "add x20, x20, #0x20\n" - "ld1b { z2.b }, p4/Z, [x22, x9]\n" - "ld1b { z1.b }, p4/Z, [x21, x9]\n" + "ld1b { z4.b }, p4/Z, [x23, x9]\n" + "ld1b { z3.b }, p4/Z, [x22, x9]\n" + "smax z8.b, p0/M, z8.b, z16.b\n" + "add x24, x24, #0x20\n" + "ld1b { z2.b }, p4/Z, [x21, x9]\n" + "ld1b { z1.b }, p4/Z, [x20, x9]\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 4 inputs tail - "movprfx z19, z4\n smax z19.b, p0/M, z19.b, z3.b\n" - "movprfx z23, z2\n smax z23.b, p0/M, z23.b, z1.b\n" - "smax z19.b, p0/M, z19.b, z23.b\n" - "smax z8.b, p0/M, z8.b, z19.b\n" + "movprfx z16, z4\n smax z16.b, p0/M, z16.b, z3.b\n" + "movprfx z17, z2\n smax z17.b, p0/M, z17.b, z1.b\n" + "smax z16.b, p0/M, z16.b, z17.b\n" + "smax z8.b, p0/M, z8.b, z16.b\n" "11:" // Single vector of channels: Loop: After loop "ands x21, %x[n_valid_cells], #0x3\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x24, [x20], #0x8\n" - "ld1b { z4.b }, p4/Z, [x24, x9]\n" + "ldr x20, [x24], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x9]\n" "subs x21, x21, #0x1\n" - "smax z8.b, p0/M, z8.b, z4.b\n" + "smax z8.b, p0/M, z8.b, z16.b\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End "st1b { z8.b }, p4, [%x[outptr], x9]\n" diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8q_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8q_nhwc_avg_generic_depthfirst/generic.cpp index 7161c4f389..19a3b112ad 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8q_nhwc_avg_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8q_nhwc_avg_generic_depthfirst/generic.cpp @@ -128,7 +128,7 @@ void sve_s8q_nhwc_avg_generic_depthfirst_impl( "lsr x23, %x[n_valid_cells], #0x1\n" "mov z15.s, #0x0\n" "mov z14.s, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "mov z13.s, #0x0\n" "mov z12.s, #0x0\n" "mov z11.s, #0x0\n" @@ -144,42 +144,42 @@ void sve_s8q_nhwc_avg_generic_depthfirst_impl( "mov z1.s, #0x0\n" "mov z0.s, #0x0\n" "cbz x23, 4f\n" - "ldp x22, x21, [x20, #0x0]\n" + "ldp x21, x20, [x22, #0x0]\n" "subs x23, x23, #0x1\n" - "add x20, x20, #0x10\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" - "ld1b { z30.b }, p4/Z, [x21, x27]\n" - "ld1b { z29.b }, p3/Z, [x22, x26]\n" - "ld1b { z28.b }, p3/Z, [x21, x26]\n" - "ld1b { z27.b }, p2/Z, [x22, x25]\n" - "ld1b { z26.b }, p2/Z, [x21, x25]\n" - "ld1b { z25.b }, p1/Z, [x22, x24]\n" - "ld1b { z24.b }, p1/Z, [x21, x24]\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" + "ld1b { z29.b }, p3/Z, [x21, x26]\n" + "ld1b { z28.b }, p3/Z, [x20, x26]\n" + "ld1b { z27.b }, p2/Z, [x21, x25]\n" + "ld1b { z26.b }, p2/Z, [x20, x25]\n" + "ld1b { z25.b }, p1/Z, [x21, x24]\n" + "ld1b { z24.b }, p1/Z, [x20, x24]\n" "beq 3f\n" "2:" // 4-vectors of channels: 2 inputs loop ".inst 0x455e03f7 // saddlb z23.h, z31.b, z30.b\n" ".inst 0x455e07f6 // saddlt z22.h, z31.b, z30.b\n" - "ldp x22, x21, [x20, #0x0]\n" + "ldp x21, x20, [x22, #0x0]\n" "subs x23, x23, #0x1\n" ".inst 0x455c03b5 // saddlb z21.h, z29.b, z28.b\n" ".inst 0x455c07b4 // saddlt z20.h, z29.b, z28.b\n" - "add x20, x20, #0x10\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" ".inst 0x455a0373 // saddlb z19.h, z27.b, z26.b\n" ".inst 0x455a0772 // saddlt z18.h, z27.b, z26.b\n" - "ld1b { z30.b }, p4/Z, [x21, x27]\n" - "ld1b { z29.b }, p3/Z, [x22, x26]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" + "ld1b { z29.b }, p3/Z, [x21, x26]\n" ".inst 0x45580331 // saddlb z17.h, z25.b, z24.b\n" ".inst 0x45580730 // saddlt z16.h, z25.b, z24.b\n" - "ld1b { z28.b }, p3/Z, [x21, x26]\n" - "ld1b { z27.b }, p2/Z, [x22, x25]\n" + "ld1b { z28.b }, p3/Z, [x20, x26]\n" + "ld1b { z27.b }, p2/Z, [x21, x25]\n" ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" - "ld1b { z26.b }, p2/Z, [x21, x25]\n" - "ld1b { z25.b }, p1/Z, [x22, x24]\n" + "ld1b { z26.b }, p2/Z, [x20, x25]\n" + "ld1b { z25.b }, p1/Z, [x21, x24]\n" ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" - "ld1b { z24.b }, p1/Z, [x21, x24]\n" + "ld1b { z24.b }, p1/Z, [x20, x24]\n" ".inst 0x4595416b // saddwb z11.s, z11.s, z21.h\n" ".inst 0x4595454a // saddwt z10.s, z10.s, z21.h\n" ".inst 0x45944129 // saddwb z9.s, z9.s, z20.h\n" @@ -222,20 +222,20 @@ void sve_s8q_nhwc_avg_generic_depthfirst_impl( "ands x21, %x[n_valid_cells], #0x1\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x22, [x20], #0x8\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" - ".inst 0x4508a3f7 // sshllb z23.h, z31.b, #0x0\n" - ".inst 0x4508a7f6 // sshllt z22.h, z31.b, #0x0\n" - "ld1b { z29.b }, p3/Z, [x22, x26]\n" - "ld1b { z27.b }, p2/Z, [x22, x25]\n" - ".inst 0x4508a3b5 // sshllb z21.h, z29.b, #0x0\n" - ".inst 0x4508a7b4 // sshllt z20.h, z29.b, #0x0\n" - "ld1b { z25.b }, p1/Z, [x22, x24]\n" - ".inst 0x4508a373 // sshllb z19.h, z27.b, #0x0\n" - ".inst 0x4508a772 // sshllt z18.h, z27.b, #0x0\n" + "ldr x20, [x22], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x27]\n" + ".inst 0x4508a217 // sshllb z23.h, z16.b, #0x0\n" + ".inst 0x4508a616 // sshllt z22.h, z16.b, #0x0\n" + "ld1b { z16.b }, p3/Z, [x20, x26]\n" + "ld1b { z17.b }, p2/Z, [x20, x25]\n" + ".inst 0x4508a215 // sshllb z21.h, z16.b, #0x0\n" + ".inst 0x4508a614 // sshllt z20.h, z16.b, #0x0\n" + "ld1b { z16.b }, p1/Z, [x20, x24]\n" + ".inst 0x4508a233 // sshllb z19.h, z17.b, #0x0\n" + ".inst 0x4508a632 // sshllt z18.h, z17.b, #0x0\n" "subs x21, x21, #0x1\n" - ".inst 0x4508a331 // sshllb z17.h, z25.b, #0x0\n" - ".inst 0x4508a730 // sshllt z16.h, z25.b, #0x0\n" + ".inst 0x4508a211 // sshllb z17.h, z16.b, #0x0\n" + ".inst 0x4508a610 // sshllt z16.h, z16.b, #0x0\n" ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" @@ -368,57 +368,57 @@ void sve_s8q_nhwc_avg_generic_depthfirst_impl( "lsr x23, %x[n_valid_cells], #0x1\n" "mov z15.s, #0x0\n" "mov z14.s, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "mov z13.s, #0x0\n" "mov z12.s, #0x0\n" "cbz x23, 11f\n" - "ldp x22, x21, [x20, #0x0]\n" + "ldp x21, x20, [x22, #0x0]\n" "subs x23, x23, #0x1\n" - "add x20, x20, #0x10\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" - "ld1b { z30.b }, p4/Z, [x21, x27]\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 2 inputs loop - ".inst 0x455e03f7 // saddlb z23.h, z31.b, z30.b\n" - ".inst 0x455e07f6 // saddlt z22.h, z31.b, z30.b\n" - "ldp x22, x21, [x20, #0x0]\n" + ".inst 0x455e03f1 // saddlb z17.h, z31.b, z30.b\n" + ".inst 0x455e07f0 // saddlt z16.h, z31.b, z30.b\n" + "ldp x21, x20, [x22, #0x0]\n" "subs x23, x23, #0x1\n" - ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" - ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" - "add x20, x20, #0x10\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" - ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" - ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" - "ld1b { z30.b }, p4/Z, [x21, x27]\n" + ".inst 0x459141ef // saddwb z15.s, z15.s, z17.h\n" + ".inst 0x459145ce // saddwt z14.s, z14.s, z17.h\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + ".inst 0x459041ad // saddwb z13.s, z13.s, z16.h\n" + ".inst 0x4590458c // saddwt z12.s, z12.s, z16.h\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 2 inputs tail - ".inst 0x455e03f7 // saddlb z23.h, z31.b, z30.b\n" - ".inst 0x455e07f6 // saddlt z22.h, z31.b, z30.b\n" - ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" - ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" - ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" - ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" + ".inst 0x455e03f1 // saddlb z17.h, z31.b, z30.b\n" + ".inst 0x455e07f0 // saddlt z16.h, z31.b, z30.b\n" + ".inst 0x459141ef // saddwb z15.s, z15.s, z17.h\n" + ".inst 0x459145ce // saddwt z14.s, z14.s, z17.h\n" + ".inst 0x459041ad // saddwb z13.s, z13.s, z16.h\n" + ".inst 0x4590458c // saddwt z12.s, z12.s, z16.h\n" "11:" // Single vector of channels: Loop: After loop "ands x21, %x[n_valid_cells], #0x1\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x22, [x20], #0x8\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" - ".inst 0x4508a3f7 // sshllb z23.h, z31.b, #0x0\n" - ".inst 0x4508a7f6 // sshllt z22.h, z31.b, #0x0\n" + "ldr x20, [x22], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x27]\n" + ".inst 0x4508a211 // sshllb z17.h, z16.b, #0x0\n" + ".inst 0x4508a610 // sshllt z16.h, z16.b, #0x0\n" "subs x21, x21, #0x1\n" - ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" - ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" - ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" - ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" + ".inst 0x459141ef // saddwb z15.s, z15.s, z17.h\n" + ".inst 0x459145ce // saddwt z14.s, z14.s, z17.h\n" + ".inst 0x459041ad // saddwb z13.s, z13.s, z16.h\n" + ".inst 0x4590458c // saddwt z12.s, z12.s, z16.h\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End - "ld1rw { z18.s }, p0/Z, [%x[left_shift]]\n" + "ld1rw { z16.s }, p0/Z, [%x[left_shift]]\n" "ld1rw { z17.s }, p0/Z, [%x[combined_rescale_value]]\n" - ".inst 0x4482824f // srshl z15.s, p0/M, z15.s, z18.s\n" - ".inst 0x4482824e // srshl z14.s, p0/M, z14.s, z18.s\n" - ".inst 0x4482824d // srshl z13.s, p0/M, z13.s, z18.s\n" - ".inst 0x4482824c // srshl z12.s, p0/M, z12.s, z18.s\n" + ".inst 0x4482820f // srshl z15.s, p0/M, z15.s, z16.s\n" + ".inst 0x4482820e // srshl z14.s, p0/M, z14.s, z16.s\n" + ".inst 0x4482820d // srshl z13.s, p0/M, z13.s, z16.s\n" + ".inst 0x4482820c // srshl z12.s, p0/M, z12.s, z16.s\n" "ld1rw { z16.s }, p0/Z, [%x[right_shift]]\n" ".inst 0x04b175ef // sqrdmulh z15.s, z15.s, z17.s\n" ".inst 0x04b175ce // sqrdmulh z14.s, z14.s, z17.s\n" diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8q_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8q_nhwc_max_generic_depthfirst/generic.cpp index 19209811d8..4fc1532d5a 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8q_nhwc_max_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8q_nhwc_max_generic_depthfirst/generic.cpp @@ -56,68 +56,68 @@ void sve_s8q_nhwc_max_generic_depthfirst_impl( "lsr x25, %x[n_valid_cells], #0x2\n" "mov z8.b, #0x80\n" "mov z7.b, #0x80\n" - "mov x20, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "mov z6.b, #0x80\n" "mov z5.b, #0x80\n" "cbz x25, 4f\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldp x22, x21, [x20, #0x10]\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" "subs x25, x25, #0x1\n" - "add x20, x20, #0x20\n" - "ld1b { z4.b }, p4/Z, [x24, x9]\n" - "ld1b { z3.b }, p4/Z, [x23, x9]\n" - "ld1b { z2.b }, p4/Z, [x22, x9]\n" - "ld1b { z1.b }, p4/Z, [x21, x9]\n" - "ld1b { z0.b }, p3/Z, [x24, x28]\n" - "ld1b { z31.b }, p3/Z, [x23, x28]\n" - "ld1b { z22.b }, p3/Z, [x22, x28]\n" - "ld1b { z30.b }, p3/Z, [x21, x28]\n" - "ld1b { z29.b }, p2/Z, [x24, x27]\n" - "ld1b { z28.b }, p2/Z, [x23, x27]\n" - "ld1b { z21.b }, p2/Z, [x22, x27]\n" - "ld1b { z27.b }, p2/Z, [x21, x27]\n" - "ld1b { z26.b }, p1/Z, [x24, x26]\n" - "ld1b { z25.b }, p1/Z, [x23, x26]\n" - "ld1b { z20.b }, p1/Z, [x22, x26]\n" - "ld1b { z24.b }, p1/Z, [x21, x26]\n" + "add x24, x24, #0x20\n" + "ld1b { z4.b }, p4/Z, [x23, x9]\n" + "ld1b { z3.b }, p4/Z, [x22, x9]\n" + "ld1b { z2.b }, p4/Z, [x21, x9]\n" + "ld1b { z1.b }, p4/Z, [x20, x9]\n" + "ld1b { z0.b }, p3/Z, [x23, x28]\n" + "ld1b { z31.b }, p3/Z, [x22, x28]\n" + "ld1b { z22.b }, p3/Z, [x21, x28]\n" + "ld1b { z30.b }, p3/Z, [x20, x28]\n" + "ld1b { z29.b }, p2/Z, [x23, x27]\n" + "ld1b { z28.b }, p2/Z, [x22, x27]\n" + "ld1b { z21.b }, p2/Z, [x21, x27]\n" + "ld1b { z27.b }, p2/Z, [x20, x27]\n" + "ld1b { z26.b }, p1/Z, [x23, x26]\n" + "ld1b { z25.b }, p1/Z, [x22, x26]\n" + "ld1b { z20.b }, p1/Z, [x21, x26]\n" + "ld1b { z24.b }, p1/Z, [x20, x26]\n" "beq 3f\n" "2:" // 4-vectors of channels: 4 inputs loop "movprfx z19, z4\n smax z19.b, p0/M, z19.b, z3.b\n" "movprfx z23, z2\n smax z23.b, p0/M, z23.b, z1.b\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldp x22, x21, [x20, #0x10]\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" "movprfx z18, z0\n smax z18.b, p0/M, z18.b, z31.b\n" "smax z22.b, p0/M, z22.b, z30.b\n" - "ld1b { z4.b }, p4/Z, [x24, x9]\n" - "ld1b { z3.b }, p4/Z, [x23, x9]\n" + "ld1b { z4.b }, p4/Z, [x23, x9]\n" + "ld1b { z3.b }, p4/Z, [x22, x9]\n" "movprfx z17, z29\n smax z17.b, p0/M, z17.b, z28.b\n" "smax z21.b, p0/M, z21.b, z27.b\n" - "ld1b { z2.b }, p4/Z, [x22, x9]\n" - "ld1b { z1.b }, p4/Z, [x21, x9]\n" + "ld1b { z2.b }, p4/Z, [x21, x9]\n" + "ld1b { z1.b }, p4/Z, [x20, x9]\n" "movprfx z16, z26\n smax z16.b, p0/M, z16.b, z25.b\n" "smax z20.b, p0/M, z20.b, z24.b\n" - "ld1b { z0.b }, p3/Z, [x24, x28]\n" - "ld1b { z31.b }, p3/Z, [x23, x28]\n" + "ld1b { z0.b }, p3/Z, [x23, x28]\n" + "ld1b { z31.b }, p3/Z, [x22, x28]\n" "smax z19.b, p0/M, z19.b, z23.b\n" "smax z18.b, p0/M, z18.b, z22.b\n" - "ld1b { z22.b }, p3/Z, [x22, x28]\n" - "ld1b { z30.b }, p3/Z, [x21, x28]\n" + "ld1b { z22.b }, p3/Z, [x21, x28]\n" + "ld1b { z30.b }, p3/Z, [x20, x28]\n" "smax z17.b, p0/M, z17.b, z21.b\n" "smax z16.b, p0/M, z16.b, z20.b\n" - "ld1b { z29.b }, p2/Z, [x24, x27]\n" - "ld1b { z28.b }, p2/Z, [x23, x27]\n" + "ld1b { z29.b }, p2/Z, [x23, x27]\n" + "ld1b { z28.b }, p2/Z, [x22, x27]\n" "subs x25, x25, #0x1\n" "smax z8.b, p0/M, z8.b, z19.b\n" - "ld1b { z21.b }, p2/Z, [x22, x27]\n" - "ld1b { z27.b }, p2/Z, [x21, x27]\n" + "ld1b { z21.b }, p2/Z, [x21, x27]\n" + "ld1b { z27.b }, p2/Z, [x20, x27]\n" "smax z7.b, p0/M, z7.b, z18.b\n" "smax z6.b, p0/M, z6.b, z17.b\n" - "ld1b { z26.b }, p1/Z, [x24, x26]\n" - "ld1b { z25.b }, p1/Z, [x23, x26]\n" + "ld1b { z26.b }, p1/Z, [x23, x26]\n" + "ld1b { z25.b }, p1/Z, [x22, x26]\n" "smax z5.b, p0/M, z5.b, z16.b\n" - "add x20, x20, #0x20\n" - "ld1b { z20.b }, p1/Z, [x22, x26]\n" - "ld1b { z24.b }, p1/Z, [x21, x26]\n" + "add x24, x24, #0x20\n" + "ld1b { z20.b }, p1/Z, [x21, x26]\n" + "ld1b { z24.b }, p1/Z, [x20, x26]\n" "bgt 2b\n" "3:" // 4-vectors of channels: 4 inputs tail "movprfx z19, z4\n smax z19.b, p0/M, z19.b, z3.b\n" @@ -140,16 +140,16 @@ void sve_s8q_nhwc_max_generic_depthfirst_impl( "ands x21, %x[n_valid_cells], #0x3\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x24, [x20], #0x8\n" - "ld1b { z4.b }, p4/Z, [x24, x9]\n" + "ldr x20, [x24], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x9]\n" "subs x21, x21, #0x1\n" - "smax z8.b, p0/M, z8.b, z4.b\n" - "ld1b { z0.b }, p3/Z, [x24, x28]\n" - "ld1b { z29.b }, p2/Z, [x24, x27]\n" - "smax z7.b, p0/M, z7.b, z0.b\n" - "smax z6.b, p0/M, z6.b, z29.b\n" - "ld1b { z26.b }, p1/Z, [x24, x26]\n" - "smax z5.b, p0/M, z5.b, z26.b\n" + "smax z8.b, p0/M, z8.b, z16.b\n" + "ld1b { z17.b }, p3/Z, [x20, x28]\n" + "ld1b { z16.b }, p2/Z, [x20, x27]\n" + "smax z7.b, p0/M, z7.b, z17.b\n" + "smax z6.b, p0/M, z6.b, z16.b\n" + "ld1b { z16.b }, p1/Z, [x20, x26]\n" + "smax z5.b, p0/M, z5.b, z16.b\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End ".inst 0x4508a111 // sshllb z17.h, z8.b, #0x0\n" @@ -292,82 +292,82 @@ void sve_s8q_nhwc_max_generic_depthfirst_impl( "8:" // Single vector of channels: Loop "lsr x25, %x[n_valid_cells], #0x2\n" "mov z8.b, #0x80\n" - "mov x20, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "cbz x25, 11f\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldp x22, x21, [x20, #0x10]\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" "subs x25, x25, #0x1\n" - "add x20, x20, #0x20\n" - "ld1b { z4.b }, p4/Z, [x24, x9]\n" - "ld1b { z3.b }, p4/Z, [x23, x9]\n" - "ld1b { z2.b }, p4/Z, [x22, x9]\n" - "ld1b { z1.b }, p4/Z, [x21, x9]\n" + "add x24, x24, #0x20\n" + "ld1b { z4.b }, p4/Z, [x23, x9]\n" + "ld1b { z3.b }, p4/Z, [x22, x9]\n" + "ld1b { z2.b }, p4/Z, [x21, x9]\n" + "ld1b { z1.b }, p4/Z, [x20, x9]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 4 inputs loop - "movprfx z19, z4\n smax z19.b, p0/M, z19.b, z3.b\n" - "movprfx z23, z2\n smax z23.b, p0/M, z23.b, z1.b\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldp x22, x21, [x20, #0x10]\n" - "smax z19.b, p0/M, z19.b, z23.b\n" + "movprfx z16, z4\n smax z16.b, p0/M, z16.b, z3.b\n" + "movprfx z17, z2\n smax z17.b, p0/M, z17.b, z1.b\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "smax z16.b, p0/M, z16.b, z17.b\n" "subs x25, x25, #0x1\n" - "ld1b { z4.b }, p4/Z, [x24, x9]\n" - "ld1b { z3.b }, p4/Z, [x23, x9]\n" - "smax z8.b, p0/M, z8.b, z19.b\n" - "add x20, x20, #0x20\n" - "ld1b { z2.b }, p4/Z, [x22, x9]\n" - "ld1b { z1.b }, p4/Z, [x21, x9]\n" + "ld1b { z4.b }, p4/Z, [x23, x9]\n" + "ld1b { z3.b }, p4/Z, [x22, x9]\n" + "smax z8.b, p0/M, z8.b, z16.b\n" + "add x24, x24, #0x20\n" + "ld1b { z2.b }, p4/Z, [x21, x9]\n" + "ld1b { z1.b }, p4/Z, [x20, x9]\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 4 inputs tail - "movprfx z19, z4\n smax z19.b, p0/M, z19.b, z3.b\n" - "movprfx z23, z2\n smax z23.b, p0/M, z23.b, z1.b\n" - "smax z19.b, p0/M, z19.b, z23.b\n" - "smax z8.b, p0/M, z8.b, z19.b\n" + "movprfx z16, z4\n smax z16.b, p0/M, z16.b, z3.b\n" + "movprfx z17, z2\n smax z17.b, p0/M, z17.b, z1.b\n" + "smax z16.b, p0/M, z16.b, z17.b\n" + "smax z8.b, p0/M, z8.b, z16.b\n" "11:" // Single vector of channels: Loop: After loop "ands x21, %x[n_valid_cells], #0x3\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x24, [x20], #0x8\n" - "ld1b { z4.b }, p4/Z, [x24, x9]\n" + "ldr x20, [x24], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x9]\n" "subs x21, x21, #0x1\n" - "smax z8.b, p0/M, z8.b, z4.b\n" + "smax z8.b, p0/M, z8.b, z16.b\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End ".inst 0x4508a111 // sshllb z17.h, z8.b, #0x0\n" - ".inst 0x4508a517 // sshllt z23.h, z8.b, #0x0\n" + ".inst 0x4508a512 // sshllt z18.h, z8.b, #0x0\n" "add x20, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n" - "ld1rw { z4.s }, p0/Z, [x20]\n" - ".inst 0x4510a221 // sshllb z1.s, z17.h, #0x0\n" - ".inst 0x4510a631 // sshllt z17.s, z17.h, #0x0\n" + "ld1rw { z16.s }, p0/Z, [x20]\n" + ".inst 0x4510a236 // sshllb z22.s, z17.h, #0x0\n" + ".inst 0x4510a635 // sshllt z21.s, z17.h, #0x0\n" "add x20, %x[quant_params], %[offsetof_qp_per_layer_mul]\n" - "ld1rw { z3.s }, p0/Z, [x20]\n" - ".inst 0x4510a2e0 // sshllb z0.s, z23.h, #0x0\n" - ".inst 0x4510a6ff // sshllt z31.s, z23.h, #0x0\n" - ".inst 0x44828081 // srshl z1.s, p0/M, z1.s, z4.s\n" - ".inst 0x44828091 // srshl z17.s, p0/M, z17.s, z4.s\n" - ".inst 0x44828080 // srshl z0.s, p0/M, z0.s, z4.s\n" - ".inst 0x4482809f // srshl z31.s, p0/M, z31.s, z4.s\n" - ".inst 0x04a37421 // sqrdmulh z1.s, z1.s, z3.s\n" - ".inst 0x04a37631 // sqrdmulh z17.s, z17.s, z3.s\n" + "ld1rw { z17.s }, p0/Z, [x20]\n" + ".inst 0x4510a254 // sshllb z20.s, z18.h, #0x0\n" + ".inst 0x4510a653 // sshllt z19.s, z18.h, #0x0\n" + ".inst 0x44828216 // srshl z22.s, p0/M, z22.s, z16.s\n" + ".inst 0x44828215 // srshl z21.s, p0/M, z21.s, z16.s\n" + ".inst 0x44828214 // srshl z20.s, p0/M, z20.s, z16.s\n" + ".inst 0x44828213 // srshl z19.s, p0/M, z19.s, z16.s\n" + ".inst 0x04b176d6 // sqrdmulh z22.s, z22.s, z17.s\n" + ".inst 0x04b176b5 // sqrdmulh z21.s, z21.s, z17.s\n" "add x20, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n" - "ld1rw { z2.s }, p0/Z, [x20]\n" - ".inst 0x04a37400 // sqrdmulh z0.s, z0.s, z3.s\n" - ".inst 0x04a377ff // sqrdmulh z31.s, z31.s, z3.s\n" + "ld1rw { z16.s }, p0/Z, [x20]\n" + ".inst 0x04b17694 // sqrdmulh z20.s, z20.s, z17.s\n" + ".inst 0x04b17673 // sqrdmulh z19.s, z19.s, z17.s\n" "mov z18.s, #0x7f\n" - ".inst 0x44828041 // srshl z1.s, p0/M, z1.s, z2.s\n" - ".inst 0x44828051 // srshl z17.s, p0/M, z17.s, z2.s\n" - ".inst 0x44828040 // srshl z0.s, p0/M, z0.s, z2.s\n" - ".inst 0x4482805f // srshl z31.s, p0/M, z31.s, z2.s\n" + ".inst 0x44828216 // srshl z22.s, p0/M, z22.s, z16.s\n" + ".inst 0x44828215 // srshl z21.s, p0/M, z21.s, z16.s\n" + ".inst 0x44828214 // srshl z20.s, p0/M, z20.s, z16.s\n" + ".inst 0x44828213 // srshl z19.s, p0/M, z19.s, z16.s\n" "not z16.s, p0/M, z18.s\n" - "smax z1.s, p0/M, z1.s, z16.s\n" - "smax z17.s, p0/M, z17.s, z16.s\n" - "smax z0.s, p0/M, z0.s, z16.s\n" - "smax z31.s, p0/M, z31.s, z16.s\n" - "smin z1.s, p0/M, z1.s, z18.s\n" - "smin z17.s, p0/M, z17.s, z18.s\n" - "smin z0.s, p0/M, z0.s, z18.s\n" - "trn1 z17.h, z1.h, z17.h\n" - "smin z31.s, p0/M, z31.s, z18.s\n" - "trn1 z16.h, z0.h, z31.h\n" + "smax z22.s, p0/M, z22.s, z16.s\n" + "smax z21.s, p0/M, z21.s, z16.s\n" + "smax z20.s, p0/M, z20.s, z16.s\n" + "smax z19.s, p0/M, z19.s, z16.s\n" + "smin z22.s, p0/M, z22.s, z18.s\n" + "smin z21.s, p0/M, z21.s, z18.s\n" + "smin z20.s, p0/M, z20.s, z18.s\n" + "trn1 z17.h, z22.h, z21.h\n" + "smin z19.s, p0/M, z19.s, z18.s\n" + "trn1 z16.h, z20.h, z19.h\n" "trn1 z16.b, z17.b, z16.b\n" "st1b { z16.b }, p4, [%x[outptr], x9]\n" "incb x9\n" diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8_nhwc_avg_generic_depthfirst/generic.cpp index f888038a2a..f3f4950a1f 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8_nhwc_avg_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8_nhwc_avg_generic_depthfirst/generic.cpp @@ -109,7 +109,7 @@ void sve_u8_nhwc_avg_generic_depthfirst_impl( "lsr x23, %x[n_valid_cells], #0x1\n" "mov z15.s, #0x0\n" "mov z14.s, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "mov z13.s, #0x0\n" "mov z12.s, #0x0\n" "mov z11.s, #0x0\n" @@ -125,42 +125,42 @@ void sve_u8_nhwc_avg_generic_depthfirst_impl( "mov z1.s, #0x0\n" "mov z0.s, #0x0\n" "cbz x23, 4f\n" - "ldp x22, x21, [x20, #0x0]\n" + "ldp x21, x20, [x22, #0x0]\n" "subs x23, x23, #0x1\n" - "add x20, x20, #0x10\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" - "ld1b { z30.b }, p4/Z, [x21, x27]\n" - "ld1b { z29.b }, p3/Z, [x22, x26]\n" - "ld1b { z28.b }, p3/Z, [x21, x26]\n" - "ld1b { z27.b }, p2/Z, [x22, x25]\n" - "ld1b { z26.b }, p2/Z, [x21, x25]\n" - "ld1b { z25.b }, p1/Z, [x22, x24]\n" - "ld1b { z24.b }, p1/Z, [x21, x24]\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" + "ld1b { z29.b }, p3/Z, [x21, x26]\n" + "ld1b { z28.b }, p3/Z, [x20, x26]\n" + "ld1b { z27.b }, p2/Z, [x21, x25]\n" + "ld1b { z26.b }, p2/Z, [x20, x25]\n" + "ld1b { z25.b }, p1/Z, [x21, x24]\n" + "ld1b { z24.b }, p1/Z, [x20, x24]\n" "beq 3f\n" "2:" // 4-vectors of channels: 2 inputs loop ".inst 0x455e0bf7 // uaddlb z23.h, z31.b, z30.b\n" ".inst 0x455e0ff6 // uaddlt z22.h, z31.b, z30.b\n" - "ldp x22, x21, [x20, #0x0]\n" + "ldp x21, x20, [x22, #0x0]\n" "subs x23, x23, #0x1\n" ".inst 0x455c0bb5 // uaddlb z21.h, z29.b, z28.b\n" ".inst 0x455c0fb4 // uaddlt z20.h, z29.b, z28.b\n" - "add x20, x20, #0x10\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" ".inst 0x455a0b73 // uaddlb z19.h, z27.b, z26.b\n" ".inst 0x455a0f72 // uaddlt z18.h, z27.b, z26.b\n" - "ld1b { z30.b }, p4/Z, [x21, x27]\n" - "ld1b { z29.b }, p3/Z, [x22, x26]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" + "ld1b { z29.b }, p3/Z, [x21, x26]\n" ".inst 0x45580b31 // uaddlb z17.h, z25.b, z24.b\n" ".inst 0x45580f30 // uaddlt z16.h, z25.b, z24.b\n" - "ld1b { z28.b }, p3/Z, [x21, x26]\n" - "ld1b { z27.b }, p2/Z, [x22, x25]\n" + "ld1b { z28.b }, p3/Z, [x20, x26]\n" + "ld1b { z27.b }, p2/Z, [x21, x25]\n" ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" - "ld1b { z26.b }, p2/Z, [x21, x25]\n" - "ld1b { z25.b }, p1/Z, [x22, x24]\n" + "ld1b { z26.b }, p2/Z, [x20, x25]\n" + "ld1b { z25.b }, p1/Z, [x21, x24]\n" ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" - "ld1b { z24.b }, p1/Z, [x21, x24]\n" + "ld1b { z24.b }, p1/Z, [x20, x24]\n" ".inst 0x4595496b // uaddwb z11.s, z11.s, z21.h\n" ".inst 0x45954d4a // uaddwt z10.s, z10.s, z21.h\n" ".inst 0x45944929 // uaddwb z9.s, z9.s, z20.h\n" @@ -203,20 +203,20 @@ void sve_u8_nhwc_avg_generic_depthfirst_impl( "ands x21, %x[n_valid_cells], #0x1\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x22, [x20], #0x8\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" - ".inst 0x4508abf7 // ushllb z23.h, z31.b, #0x0\n" - ".inst 0x4508aff6 // ushllt z22.h, z31.b, #0x0\n" - "ld1b { z29.b }, p3/Z, [x22, x26]\n" - "ld1b { z27.b }, p2/Z, [x22, x25]\n" - ".inst 0x4508abb5 // ushllb z21.h, z29.b, #0x0\n" - ".inst 0x4508afb4 // ushllt z20.h, z29.b, #0x0\n" - "ld1b { z25.b }, p1/Z, [x22, x24]\n" - ".inst 0x4508ab73 // ushllb z19.h, z27.b, #0x0\n" - ".inst 0x4508af72 // ushllt z18.h, z27.b, #0x0\n" + "ldr x20, [x22], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x27]\n" + ".inst 0x4508aa17 // ushllb z23.h, z16.b, #0x0\n" + ".inst 0x4508ae16 // ushllt z22.h, z16.b, #0x0\n" + "ld1b { z16.b }, p3/Z, [x20, x26]\n" + "ld1b { z17.b }, p2/Z, [x20, x25]\n" + ".inst 0x4508aa15 // ushllb z21.h, z16.b, #0x0\n" + ".inst 0x4508ae14 // ushllt z20.h, z16.b, #0x0\n" + "ld1b { z16.b }, p1/Z, [x20, x24]\n" + ".inst 0x4508aa33 // ushllb z19.h, z17.b, #0x0\n" + ".inst 0x4508ae32 // ushllt z18.h, z17.b, #0x0\n" "subs x21, x21, #0x1\n" - ".inst 0x4508ab31 // ushllb z17.h, z25.b, #0x0\n" - ".inst 0x4508af30 // ushllt z16.h, z25.b, #0x0\n" + ".inst 0x4508aa11 // ushllb z17.h, z16.b, #0x0\n" + ".inst 0x4508ae10 // ushllt z16.h, z16.b, #0x0\n" ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" @@ -332,49 +332,49 @@ void sve_u8_nhwc_avg_generic_depthfirst_impl( "lsr x23, %x[n_valid_cells], #0x1\n" "mov z15.s, #0x0\n" "mov z14.s, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "mov z13.s, #0x0\n" "mov z12.s, #0x0\n" "cbz x23, 11f\n" - "ldp x22, x21, [x20, #0x0]\n" + "ldp x21, x20, [x22, #0x0]\n" "subs x23, x23, #0x1\n" - "add x20, x20, #0x10\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" - "ld1b { z30.b }, p4/Z, [x21, x27]\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 2 inputs loop - ".inst 0x455e0bf7 // uaddlb z23.h, z31.b, z30.b\n" - ".inst 0x455e0ff6 // uaddlt z22.h, z31.b, z30.b\n" - "ldp x22, x21, [x20, #0x0]\n" + ".inst 0x455e0bf1 // uaddlb z17.h, z31.b, z30.b\n" + ".inst 0x455e0ff0 // uaddlt z16.h, z31.b, z30.b\n" + "ldp x21, x20, [x22, #0x0]\n" "subs x23, x23, #0x1\n" - ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" - ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" - "add x20, x20, #0x10\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" - ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" - ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" - "ld1b { z30.b }, p4/Z, [x21, x27]\n" + ".inst 0x459149ef // uaddwb z15.s, z15.s, z17.h\n" + ".inst 0x45914dce // uaddwt z14.s, z14.s, z17.h\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + ".inst 0x459049ad // uaddwb z13.s, z13.s, z16.h\n" + ".inst 0x45904d8c // uaddwt z12.s, z12.s, z16.h\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 2 inputs tail - ".inst 0x455e0bf7 // uaddlb z23.h, z31.b, z30.b\n" - ".inst 0x455e0ff6 // uaddlt z22.h, z31.b, z30.b\n" - ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" - ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" - ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" - ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" + ".inst 0x455e0bf1 // uaddlb z17.h, z31.b, z30.b\n" + ".inst 0x455e0ff0 // uaddlt z16.h, z31.b, z30.b\n" + ".inst 0x459149ef // uaddwb z15.s, z15.s, z17.h\n" + ".inst 0x45914dce // uaddwt z14.s, z14.s, z17.h\n" + ".inst 0x459049ad // uaddwb z13.s, z13.s, z16.h\n" + ".inst 0x45904d8c // uaddwt z12.s, z12.s, z16.h\n" "11:" // Single vector of channels: Loop: After loop "ands x21, %x[n_valid_cells], #0x1\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x22, [x20], #0x8\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" - ".inst 0x4508abf7 // ushllb z23.h, z31.b, #0x0\n" - ".inst 0x4508aff6 // ushllt z22.h, z31.b, #0x0\n" + "ldr x20, [x22], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x27]\n" + ".inst 0x4508aa11 // ushllb z17.h, z16.b, #0x0\n" + ".inst 0x4508ae10 // ushllt z16.h, z16.b, #0x0\n" "subs x21, x21, #0x1\n" - ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" - ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" - ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" - ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" + ".inst 0x459149ef // uaddwb z15.s, z15.s, z17.h\n" + ".inst 0x45914dce // uaddwt z14.s, z14.s, z17.h\n" + ".inst 0x459049ad // uaddwb z13.s, z13.s, z16.h\n" + ".inst 0x45904d8c // uaddwt z12.s, z12.s, z16.h\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End "ld1rw { z17.s }, p0/Z, [%x[rescale_ptr]]\n" @@ -387,17 +387,17 @@ void sve_u8_nhwc_avg_generic_depthfirst_impl( ".inst 0x4482820e // srshl z14.s, p0/M, z14.s, z16.s\n" ".inst 0x4482820d // srshl z13.s, p0/M, z13.s, z16.s\n" ".inst 0x4482820c // srshl z12.s, p0/M, z12.s, z16.s\n" - "mov z16.s, #0x0\n" - "mov z18.s, #0xff\n" - "smax z15.s, p0/M, z15.s, z16.s\n" - "smax z14.s, p0/M, z14.s, z16.s\n" - "smax z13.s, p0/M, z13.s, z16.s\n" - "smax z12.s, p0/M, z12.s, z16.s\n" - "smin z15.s, p0/M, z15.s, z18.s\n" - "smin z14.s, p0/M, z14.s, z18.s\n" + "mov z17.s, #0x0\n" + "mov z16.s, #0xff\n" + "smax z15.s, p0/M, z15.s, z17.s\n" + "smax z14.s, p0/M, z14.s, z17.s\n" + "smax z13.s, p0/M, z13.s, z17.s\n" + "smax z12.s, p0/M, z12.s, z17.s\n" + "smin z15.s, p0/M, z15.s, z16.s\n" + "smin z14.s, p0/M, z14.s, z16.s\n" "trn1 z17.h, z15.h, z14.h\n" - "smin z13.s, p0/M, z13.s, z18.s\n" - "smin z12.s, p0/M, z12.s, z18.s\n" + "smin z13.s, p0/M, z13.s, z16.s\n" + "smin z12.s, p0/M, z12.s, z16.s\n" "trn1 z16.h, z13.h, z12.h\n" "trn1 z16.b, z17.b, z16.b\n" "st1b { z16.b }, p4, [%x[outptr], x27]\n" diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp index 70d308a585..8612555bfb 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp @@ -66,10 +66,10 @@ void sve_u8_nhwc_max_2x2_s1_output2x2_depthfirst_impl( "ldr x15, [%x[args], %[offsetof_n_channels]]\n" "ldr x21, [%x[args], %[offsetof_outptrs]]\n" "mov x14, #0x0\n" - "whilelt p2.b, x14, x15\n" + "whilelt p0.b, x14, x15\n" "ldr x20, [%x[args], %[offsetof_inptrs]]\n" "ldp x13, x12, [x21, #0x0]\n" - "ptrue p1.b\n" + "ptrue p2.b\n" "mov x11, #0x0\n" "ldp x10, x9, [x21, #0x10]\n" "ldp x28, x27, [x20, #0x0]\n" @@ -77,61 +77,61 @@ void sve_u8_nhwc_max_2x2_s1_output2x2_depthfirst_impl( "ldp x24, x23, [x20, #0x20]\n" "ldp x22, x21, [x20, #0x30]\n" "ldr x20, [x20, #0x40]\n" - "ld1b { z31.b }, p2/Z, [x27, x14]\n" - "ld1b { z30.b }, p2/Z, [x24, x14]\n" - "ld1b { z29.b }, p2/Z, [x21, x14]\n" - "ld1b { z28.b }, p2/Z, [x25, x14]\n" - "ld1b { z27.b }, p2/Z, [x28, x14]\n" - "ld1b { z26.b }, p2/Z, [x26, x14]\n" - "ld1b { z25.b }, p2/Z, [x23, x14]\n" - "ld1b { z24.b }, p2/Z, [x22, x14]\n" - "ld1b { z23.b }, p2/Z, [x20, x14]\n" + "ld1b { z31.b }, p0/Z, [x27, x14]\n" + "ld1b { z30.b }, p0/Z, [x24, x14]\n" + "ld1b { z29.b }, p0/Z, [x21, x14]\n" + "ld1b { z28.b }, p0/Z, [x25, x14]\n" + "ld1b { z27.b }, p0/Z, [x28, x14]\n" + "ld1b { z26.b }, p0/Z, [x26, x14]\n" + "ld1b { z25.b }, p0/Z, [x23, x14]\n" + "ld1b { z24.b }, p0/Z, [x22, x14]\n" + "ld1b { z23.b }, p0/Z, [x20, x14]\n" "incw x14\n" - "whilelt p2.b, x14, x15\n" + "whilelt p1.b, x14, x15\n" "b.none 2f\n" "1:" // Vector: Loop - "movprfx z22, z31\n umax z22.b, p1/M, z22.b, z30.b\n" - "movprfx z21, z30\n umax z21.b, p1/M, z21.b, z29.b\n" - "ld1b { z31.b }, p2/Z, [x27, x14]\n" - "ld1b { z30.b }, p2/Z, [x24, x14]\n" - "movprfx z20, z28\n umax z20.b, p1/M, z20.b, z27.b\n" - "movprfx z19, z26\n umax z19.b, p1/M, z19.b, z25.b\n" - "ld1b { z29.b }, p2/Z, [x21, x14]\n" - "ld1b { z27.b }, p2/Z, [x28, x14]\n" - "movprfx z17, z28\n umax z17.b, p1/M, z17.b, z24.b\n" - "movprfx z18, z25\n umax z18.b, p1/M, z18.b, z23.b\n" - "ld1b { z28.b }, p2/Z, [x25, x14]\n" - "ld1b { z26.b }, p2/Z, [x26, x14]\n" - "ld1b { z25.b }, p2/Z, [x23, x14]\n" - "ld1b { z24.b }, p2/Z, [x22, x14]\n" + "movprfx z22, z31\n umax z22.b, p2/M, z22.b, z30.b\n" + "movprfx z21, z30\n umax z21.b, p2/M, z21.b, z29.b\n" + "ld1b { z31.b }, p1/Z, [x27, x14]\n" + "ld1b { z30.b }, p1/Z, [x24, x14]\n" + "movprfx z20, z28\n umax z20.b, p2/M, z20.b, z27.b\n" + "movprfx z19, z26\n umax z19.b, p2/M, z19.b, z25.b\n" + "ld1b { z29.b }, p1/Z, [x21, x14]\n" + "ld1b { z27.b }, p1/Z, [x28, x14]\n" + "movprfx z17, z28\n umax z17.b, p2/M, z17.b, z24.b\n" + "movprfx z18, z25\n umax z18.b, p2/M, z18.b, z23.b\n" + "ld1b { z28.b }, p1/Z, [x25, x14]\n" + "ld1b { z26.b }, p1/Z, [x26, x14]\n" + "ld1b { z25.b }, p1/Z, [x23, x14]\n" + "ld1b { z24.b }, p1/Z, [x22, x14]\n" "whilelt p0.b, x11, x15\n" - "movprfx z16, z22\n umax z16.b, p1/M, z16.b, z20.b\n" - "ld1b { z23.b }, p2/Z, [x20, x14]\n" + "movprfx z16, z22\n umax z16.b, p2/M, z16.b, z20.b\n" + "ld1b { z23.b }, p1/Z, [x20, x14]\n" "incw x14\n" - "whilelt p2.b, x14, x15\n" + "whilelt p1.b, x14, x15\n" "st1b { z16.b }, p0, [x13, x11]\n" - "movprfx z16, z19\n umax z16.b, p1/M, z16.b, z22.b\n" - "umax z17.b, p1/M, z17.b, z21.b\n" + "movprfx z16, z19\n umax z16.b, p2/M, z16.b, z22.b\n" + "umax z17.b, p2/M, z17.b, z21.b\n" "st1b { z16.b }, p0, [x12, x11]\n" - "movprfx z16, z18\n umax z16.b, p1/M, z16.b, z21.b\n" + "movprfx z16, z21\n umax z16.b, p2/M, z16.b, z18.b\n" "st1b { z17.b }, p0, [x10, x11]\n" "st1b { z16.b }, p0, [x9, x11]\n" "incw x11\n" "b.any 1b\n" "2:" // Vector: Tail - "movprfx z22, z31\n umax z22.b, p1/M, z22.b, z30.b\n" - "movprfx z21, z30\n umax z21.b, p1/M, z21.b, z29.b\n" - "movprfx z20, z28\n umax z20.b, p1/M, z20.b, z27.b\n" - "movprfx z19, z26\n umax z19.b, p1/M, z19.b, z25.b\n" - "movprfx z17, z28\n umax z17.b, p1/M, z17.b, z24.b\n" - "movprfx z18, z25\n umax z18.b, p1/M, z18.b, z23.b\n" + "movprfx z22, z31\n umax z22.b, p2/M, z22.b, z30.b\n" + "movprfx z21, z30\n umax z21.b, p2/M, z21.b, z29.b\n" + "movprfx z20, z28\n umax z20.b, p2/M, z20.b, z27.b\n" + "movprfx z19, z26\n umax z19.b, p2/M, z19.b, z25.b\n" + "movprfx z17, z28\n umax z17.b, p2/M, z17.b, z24.b\n" + "movprfx z18, z25\n umax z18.b, p2/M, z18.b, z23.b\n" "whilelt p0.b, x11, x15\n" - "movprfx z16, z22\n umax z16.b, p1/M, z16.b, z20.b\n" + "movprfx z16, z22\n umax z16.b, p2/M, z16.b, z20.b\n" "st1b { z16.b }, p0, [x13, x11]\n" - "movprfx z16, z19\n umax z16.b, p1/M, z16.b, z22.b\n" - "umax z17.b, p1/M, z17.b, z21.b\n" + "movprfx z16, z19\n umax z16.b, p2/M, z16.b, z22.b\n" + "umax z17.b, p2/M, z17.b, z21.b\n" "st1b { z16.b }, p0, [x12, x11]\n" - "movprfx z16, z18\n umax z16.b, p1/M, z16.b, z21.b\n" + "movprfx z16, z21\n umax z16.b, p2/M, z16.b, z18.b\n" "st1b { z17.b }, p0, [x10, x11]\n" "st1b { z16.b }, p0, [x9, x11]\n" : diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8_nhwc_max_generic_depthfirst/generic.cpp index 34aa5a3dd6..be0eb398ae 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8_nhwc_max_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8_nhwc_max_generic_depthfirst/generic.cpp @@ -54,68 +54,68 @@ void sve_u8_nhwc_max_generic_depthfirst_impl( "lsr x25, %x[n_valid_cells], #0x2\n" "mov z8.b, #0x0\n" "mov z7.b, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "mov z6.b, #0x0\n" "mov z5.b, #0x0\n" "cbz x25, 4f\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldp x22, x21, [x20, #0x10]\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" "subs x25, x25, #0x1\n" - "add x20, x20, #0x20\n" - "ld1b { z4.b }, p4/Z, [x24, x9]\n" - "ld1b { z3.b }, p4/Z, [x23, x9]\n" - "ld1b { z2.b }, p4/Z, [x22, x9]\n" - "ld1b { z1.b }, p4/Z, [x21, x9]\n" - "ld1b { z0.b }, p3/Z, [x24, x28]\n" - "ld1b { z31.b }, p3/Z, [x23, x28]\n" - "ld1b { z22.b }, p3/Z, [x22, x28]\n" - "ld1b { z30.b }, p3/Z, [x21, x28]\n" - "ld1b { z29.b }, p2/Z, [x24, x27]\n" - "ld1b { z28.b }, p2/Z, [x23, x27]\n" - "ld1b { z21.b }, p2/Z, [x22, x27]\n" - "ld1b { z27.b }, p2/Z, [x21, x27]\n" - "ld1b { z26.b }, p1/Z, [x24, x26]\n" - "ld1b { z25.b }, p1/Z, [x23, x26]\n" - "ld1b { z20.b }, p1/Z, [x22, x26]\n" - "ld1b { z24.b }, p1/Z, [x21, x26]\n" + "add x24, x24, #0x20\n" + "ld1b { z4.b }, p4/Z, [x23, x9]\n" + "ld1b { z3.b }, p4/Z, [x22, x9]\n" + "ld1b { z2.b }, p4/Z, [x21, x9]\n" + "ld1b { z1.b }, p4/Z, [x20, x9]\n" + "ld1b { z0.b }, p3/Z, [x23, x28]\n" + "ld1b { z31.b }, p3/Z, [x22, x28]\n" + "ld1b { z22.b }, p3/Z, [x21, x28]\n" + "ld1b { z30.b }, p3/Z, [x20, x28]\n" + "ld1b { z29.b }, p2/Z, [x23, x27]\n" + "ld1b { z28.b }, p2/Z, [x22, x27]\n" + "ld1b { z21.b }, p2/Z, [x21, x27]\n" + "ld1b { z27.b }, p2/Z, [x20, x27]\n" + "ld1b { z26.b }, p1/Z, [x23, x26]\n" + "ld1b { z25.b }, p1/Z, [x22, x26]\n" + "ld1b { z20.b }, p1/Z, [x21, x26]\n" + "ld1b { z24.b }, p1/Z, [x20, x26]\n" "beq 3f\n" "2:" // 4-vectors of channels: 4 inputs loop "movprfx z19, z4\n umax z19.b, p0/M, z19.b, z3.b\n" "movprfx z23, z2\n umax z23.b, p0/M, z23.b, z1.b\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldp x22, x21, [x20, #0x10]\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" "movprfx z18, z0\n umax z18.b, p0/M, z18.b, z31.b\n" "umax z22.b, p0/M, z22.b, z30.b\n" - "ld1b { z4.b }, p4/Z, [x24, x9]\n" - "ld1b { z3.b }, p4/Z, [x23, x9]\n" + "ld1b { z4.b }, p4/Z, [x23, x9]\n" + "ld1b { z3.b }, p4/Z, [x22, x9]\n" "movprfx z17, z29\n umax z17.b, p0/M, z17.b, z28.b\n" "umax z21.b, p0/M, z21.b, z27.b\n" - "ld1b { z2.b }, p4/Z, [x22, x9]\n" - "ld1b { z1.b }, p4/Z, [x21, x9]\n" + "ld1b { z2.b }, p4/Z, [x21, x9]\n" + "ld1b { z1.b }, p4/Z, [x20, x9]\n" "movprfx z16, z26\n umax z16.b, p0/M, z16.b, z25.b\n" "umax z20.b, p0/M, z20.b, z24.b\n" - "ld1b { z0.b }, p3/Z, [x24, x28]\n" - "ld1b { z31.b }, p3/Z, [x23, x28]\n" + "ld1b { z0.b }, p3/Z, [x23, x28]\n" + "ld1b { z31.b }, p3/Z, [x22, x28]\n" "umax z19.b, p0/M, z19.b, z23.b\n" "umax z18.b, p0/M, z18.b, z22.b\n" - "ld1b { z22.b }, p3/Z, [x22, x28]\n" - "ld1b { z30.b }, p3/Z, [x21, x28]\n" + "ld1b { z22.b }, p3/Z, [x21, x28]\n" + "ld1b { z30.b }, p3/Z, [x20, x28]\n" "umax z17.b, p0/M, z17.b, z21.b\n" "umax z16.b, p0/M, z16.b, z20.b\n" - "ld1b { z29.b }, p2/Z, [x24, x27]\n" - "ld1b { z28.b }, p2/Z, [x23, x27]\n" + "ld1b { z29.b }, p2/Z, [x23, x27]\n" + "ld1b { z28.b }, p2/Z, [x22, x27]\n" "subs x25, x25, #0x1\n" "umax z8.b, p0/M, z8.b, z19.b\n" - "ld1b { z21.b }, p2/Z, [x22, x27]\n" - "ld1b { z27.b }, p2/Z, [x21, x27]\n" + "ld1b { z21.b }, p2/Z, [x21, x27]\n" + "ld1b { z27.b }, p2/Z, [x20, x27]\n" "umax z7.b, p0/M, z7.b, z18.b\n" "umax z6.b, p0/M, z6.b, z17.b\n" - "ld1b { z26.b }, p1/Z, [x24, x26]\n" - "ld1b { z25.b }, p1/Z, [x23, x26]\n" + "ld1b { z26.b }, p1/Z, [x23, x26]\n" + "ld1b { z25.b }, p1/Z, [x22, x26]\n" "umax z5.b, p0/M, z5.b, z16.b\n" - "add x20, x20, #0x20\n" - "ld1b { z20.b }, p1/Z, [x22, x26]\n" - "ld1b { z24.b }, p1/Z, [x21, x26]\n" + "add x24, x24, #0x20\n" + "ld1b { z20.b }, p1/Z, [x21, x26]\n" + "ld1b { z24.b }, p1/Z, [x20, x26]\n" "bgt 2b\n" "3:" // 4-vectors of channels: 4 inputs tail "movprfx z19, z4\n umax z19.b, p0/M, z19.b, z3.b\n" @@ -138,16 +138,16 @@ void sve_u8_nhwc_max_generic_depthfirst_impl( "ands x21, %x[n_valid_cells], #0x3\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x24, [x20], #0x8\n" - "ld1b { z4.b }, p4/Z, [x24, x9]\n" + "ldr x20, [x24], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x9]\n" "subs x21, x21, #0x1\n" - "umax z8.b, p0/M, z8.b, z4.b\n" - "ld1b { z0.b }, p3/Z, [x24, x28]\n" - "ld1b { z29.b }, p2/Z, [x24, x27]\n" - "umax z7.b, p0/M, z7.b, z0.b\n" - "umax z6.b, p0/M, z6.b, z29.b\n" - "ld1b { z26.b }, p1/Z, [x24, x26]\n" - "umax z5.b, p0/M, z5.b, z26.b\n" + "umax z8.b, p0/M, z8.b, z16.b\n" + "ld1b { z17.b }, p3/Z, [x20, x28]\n" + "ld1b { z16.b }, p2/Z, [x20, x27]\n" + "umax z7.b, p0/M, z7.b, z17.b\n" + "umax z6.b, p0/M, z6.b, z16.b\n" + "ld1b { z16.b }, p1/Z, [x20, x26]\n" + "umax z5.b, p0/M, z5.b, z16.b\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End "st1b { z8.b }, p4, [%x[outptr], x9]\n" @@ -166,44 +166,44 @@ void sve_u8_nhwc_max_generic_depthfirst_impl( "8:" // Single vector of channels: Loop "lsr x25, %x[n_valid_cells], #0x2\n" "mov z8.b, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "cbz x25, 11f\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldp x22, x21, [x20, #0x10]\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" "subs x25, x25, #0x1\n" - "add x20, x20, #0x20\n" - "ld1b { z4.b }, p4/Z, [x24, x9]\n" - "ld1b { z3.b }, p4/Z, [x23, x9]\n" - "ld1b { z2.b }, p4/Z, [x22, x9]\n" - "ld1b { z1.b }, p4/Z, [x21, x9]\n" + "add x24, x24, #0x20\n" + "ld1b { z4.b }, p4/Z, [x23, x9]\n" + "ld1b { z3.b }, p4/Z, [x22, x9]\n" + "ld1b { z2.b }, p4/Z, [x21, x9]\n" + "ld1b { z1.b }, p4/Z, [x20, x9]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 4 inputs loop - "movprfx z19, z4\n umax z19.b, p0/M, z19.b, z3.b\n" - "movprfx z23, z2\n umax z23.b, p0/M, z23.b, z1.b\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldp x22, x21, [x20, #0x10]\n" - "umax z19.b, p0/M, z19.b, z23.b\n" + "movprfx z16, z4\n umax z16.b, p0/M, z16.b, z3.b\n" + "movprfx z17, z2\n umax z17.b, p0/M, z17.b, z1.b\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "umax z16.b, p0/M, z16.b, z17.b\n" "subs x25, x25, #0x1\n" - "ld1b { z4.b }, p4/Z, [x24, x9]\n" - "ld1b { z3.b }, p4/Z, [x23, x9]\n" - "umax z8.b, p0/M, z8.b, z19.b\n" - "add x20, x20, #0x20\n" - "ld1b { z2.b }, p4/Z, [x22, x9]\n" - "ld1b { z1.b }, p4/Z, [x21, x9]\n" + "ld1b { z4.b }, p4/Z, [x23, x9]\n" + "ld1b { z3.b }, p4/Z, [x22, x9]\n" + "umax z8.b, p0/M, z8.b, z16.b\n" + "add x24, x24, #0x20\n" + "ld1b { z2.b }, p4/Z, [x21, x9]\n" + "ld1b { z1.b }, p4/Z, [x20, x9]\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 4 inputs tail - "movprfx z19, z4\n umax z19.b, p0/M, z19.b, z3.b\n" - "movprfx z23, z2\n umax z23.b, p0/M, z23.b, z1.b\n" - "umax z19.b, p0/M, z19.b, z23.b\n" - "umax z8.b, p0/M, z8.b, z19.b\n" + "movprfx z16, z4\n umax z16.b, p0/M, z16.b, z3.b\n" + "movprfx z17, z2\n umax z17.b, p0/M, z17.b, z1.b\n" + "umax z16.b, p0/M, z16.b, z17.b\n" + "umax z8.b, p0/M, z8.b, z16.b\n" "11:" // Single vector of channels: Loop: After loop "ands x21, %x[n_valid_cells], #0x3\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x24, [x20], #0x8\n" - "ld1b { z4.b }, p4/Z, [x24, x9]\n" + "ldr x20, [x24], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x9]\n" "subs x21, x21, #0x1\n" - "umax z8.b, p0/M, z8.b, z4.b\n" + "umax z8.b, p0/M, z8.b, z16.b\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End "st1b { z8.b }, p4, [%x[outptr], x9]\n" diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8q_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8q_nhwc_avg_generic_depthfirst/generic.cpp index 36ac381004..e8339a2cd9 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8q_nhwc_avg_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8q_nhwc_avg_generic_depthfirst/generic.cpp @@ -136,7 +136,7 @@ void sve_u8q_nhwc_avg_generic_depthfirst_impl( "mov z13.d, z15.d\n" "mov z12.d, z15.d\n" "mov z11.d, z15.d\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "mov z10.d, z15.d\n" "mov z9.d, z15.d\n" "mov z8.d, z15.d\n" @@ -149,42 +149,42 @@ void sve_u8q_nhwc_avg_generic_depthfirst_impl( "mov z1.d, z15.d\n" "mov z0.d, z15.d\n" "cbz x23, 4f\n" - "ldp x22, x21, [x20, #0x0]\n" + "ldp x21, x20, [x22, #0x0]\n" "subs x23, x23, #0x1\n" - "add x20, x20, #0x10\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" - "ld1b { z30.b }, p4/Z, [x21, x27]\n" - "ld1b { z29.b }, p3/Z, [x22, x26]\n" - "ld1b { z28.b }, p3/Z, [x21, x26]\n" - "ld1b { z27.b }, p2/Z, [x22, x25]\n" - "ld1b { z26.b }, p2/Z, [x21, x25]\n" - "ld1b { z25.b }, p1/Z, [x22, x24]\n" - "ld1b { z24.b }, p1/Z, [x21, x24]\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" + "ld1b { z29.b }, p3/Z, [x21, x26]\n" + "ld1b { z28.b }, p3/Z, [x20, x26]\n" + "ld1b { z27.b }, p2/Z, [x21, x25]\n" + "ld1b { z26.b }, p2/Z, [x20, x25]\n" + "ld1b { z25.b }, p1/Z, [x21, x24]\n" + "ld1b { z24.b }, p1/Z, [x20, x24]\n" "beq 3f\n" "2:" // 4-vectors of channels: 2 inputs loop ".inst 0x455e0bf7 // uaddlb z23.h, z31.b, z30.b\n" ".inst 0x455e0ff6 // uaddlt z22.h, z31.b, z30.b\n" - "ldp x22, x21, [x20, #0x0]\n" + "ldp x21, x20, [x22, #0x0]\n" "subs x23, x23, #0x1\n" ".inst 0x455c0bb5 // uaddlb z21.h, z29.b, z28.b\n" ".inst 0x455c0fb4 // uaddlt z20.h, z29.b, z28.b\n" - "add x20, x20, #0x10\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" ".inst 0x455a0b73 // uaddlb z19.h, z27.b, z26.b\n" ".inst 0x455a0f72 // uaddlt z18.h, z27.b, z26.b\n" - "ld1b { z30.b }, p4/Z, [x21, x27]\n" - "ld1b { z29.b }, p3/Z, [x22, x26]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" + "ld1b { z29.b }, p3/Z, [x21, x26]\n" ".inst 0x45580b31 // uaddlb z17.h, z25.b, z24.b\n" ".inst 0x45580f30 // uaddlt z16.h, z25.b, z24.b\n" - "ld1b { z28.b }, p3/Z, [x21, x26]\n" - "ld1b { z27.b }, p2/Z, [x22, x25]\n" + "ld1b { z28.b }, p3/Z, [x20, x26]\n" + "ld1b { z27.b }, p2/Z, [x21, x25]\n" ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" - "ld1b { z26.b }, p2/Z, [x21, x25]\n" - "ld1b { z25.b }, p1/Z, [x22, x24]\n" + "ld1b { z26.b }, p2/Z, [x20, x25]\n" + "ld1b { z25.b }, p1/Z, [x21, x24]\n" ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" - "ld1b { z24.b }, p1/Z, [x21, x24]\n" + "ld1b { z24.b }, p1/Z, [x20, x24]\n" ".inst 0x4595496b // uaddwb z11.s, z11.s, z21.h\n" ".inst 0x45954d4a // uaddwt z10.s, z10.s, z21.h\n" ".inst 0x45944929 // uaddwb z9.s, z9.s, z20.h\n" @@ -227,20 +227,20 @@ void sve_u8q_nhwc_avg_generic_depthfirst_impl( "ands x21, %x[n_valid_cells], #0x1\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x22, [x20], #0x8\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" - ".inst 0x4508abf7 // ushllb z23.h, z31.b, #0x0\n" - ".inst 0x4508aff6 // ushllt z22.h, z31.b, #0x0\n" - "ld1b { z29.b }, p3/Z, [x22, x26]\n" - "ld1b { z27.b }, p2/Z, [x22, x25]\n" - ".inst 0x4508abb5 // ushllb z21.h, z29.b, #0x0\n" - ".inst 0x4508afb4 // ushllt z20.h, z29.b, #0x0\n" - "ld1b { z25.b }, p1/Z, [x22, x24]\n" - ".inst 0x4508ab73 // ushllb z19.h, z27.b, #0x0\n" - ".inst 0x4508af72 // ushllt z18.h, z27.b, #0x0\n" + "ldr x20, [x22], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x27]\n" + ".inst 0x4508aa17 // ushllb z23.h, z16.b, #0x0\n" + ".inst 0x4508ae16 // ushllt z22.h, z16.b, #0x0\n" + "ld1b { z16.b }, p3/Z, [x20, x26]\n" + "ld1b { z17.b }, p2/Z, [x20, x25]\n" + ".inst 0x4508aa15 // ushllb z21.h, z16.b, #0x0\n" + ".inst 0x4508ae14 // ushllt z20.h, z16.b, #0x0\n" + "ld1b { z16.b }, p1/Z, [x20, x24]\n" + ".inst 0x4508aa33 // ushllb z19.h, z17.b, #0x0\n" + ".inst 0x4508ae32 // ushllt z18.h, z17.b, #0x0\n" "subs x21, x21, #0x1\n" - ".inst 0x4508ab31 // ushllb z17.h, z25.b, #0x0\n" - ".inst 0x4508af30 // ushllt z16.h, z25.b, #0x0\n" + ".inst 0x4508aa11 // ushllb z17.h, z16.b, #0x0\n" + ".inst 0x4508ae10 // ushllt z16.h, z16.b, #0x0\n" ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" @@ -393,55 +393,55 @@ void sve_u8q_nhwc_avg_generic_depthfirst_impl( "mov z14.d, z15.d\n" "mov z13.d, z15.d\n" "mov z12.d, z15.d\n" - "mov x20, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "cbz x23, 11f\n" - "ldp x22, x21, [x20, #0x0]\n" + "ldp x21, x20, [x22, #0x0]\n" "subs x23, x23, #0x1\n" - "add x20, x20, #0x10\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" - "ld1b { z30.b }, p4/Z, [x21, x27]\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 2 inputs loop - ".inst 0x455e0bf7 // uaddlb z23.h, z31.b, z30.b\n" - ".inst 0x455e0ff6 // uaddlt z22.h, z31.b, z30.b\n" - "ldp x22, x21, [x20, #0x0]\n" + ".inst 0x455e0bf1 // uaddlb z17.h, z31.b, z30.b\n" + ".inst 0x455e0ff0 // uaddlt z16.h, z31.b, z30.b\n" + "ldp x21, x20, [x22, #0x0]\n" "subs x23, x23, #0x1\n" - ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" - ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" - "add x20, x20, #0x10\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" - ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" - ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" - "ld1b { z30.b }, p4/Z, [x21, x27]\n" + ".inst 0x459149ef // uaddwb z15.s, z15.s, z17.h\n" + ".inst 0x45914dce // uaddwt z14.s, z14.s, z17.h\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + ".inst 0x459049ad // uaddwb z13.s, z13.s, z16.h\n" + ".inst 0x45904d8c // uaddwt z12.s, z12.s, z16.h\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 2 inputs tail - ".inst 0x455e0bf7 // uaddlb z23.h, z31.b, z30.b\n" - ".inst 0x455e0ff6 // uaddlt z22.h, z31.b, z30.b\n" - ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" - ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" - ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" - ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" + ".inst 0x455e0bf1 // uaddlb z17.h, z31.b, z30.b\n" + ".inst 0x455e0ff0 // uaddlt z16.h, z31.b, z30.b\n" + ".inst 0x459149ef // uaddwb z15.s, z15.s, z17.h\n" + ".inst 0x45914dce // uaddwt z14.s, z14.s, z17.h\n" + ".inst 0x459049ad // uaddwb z13.s, z13.s, z16.h\n" + ".inst 0x45904d8c // uaddwt z12.s, z12.s, z16.h\n" "11:" // Single vector of channels: Loop: After loop "ands x21, %x[n_valid_cells], #0x1\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x22, [x20], #0x8\n" - "ld1b { z31.b }, p4/Z, [x22, x27]\n" - ".inst 0x4508abf7 // ushllb z23.h, z31.b, #0x0\n" - ".inst 0x4508aff6 // ushllt z22.h, z31.b, #0x0\n" + "ldr x20, [x22], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x27]\n" + ".inst 0x4508aa11 // ushllb z17.h, z16.b, #0x0\n" + ".inst 0x4508ae10 // ushllt z16.h, z16.b, #0x0\n" "subs x21, x21, #0x1\n" - ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" - ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" - ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" - ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" + ".inst 0x459149ef // uaddwb z15.s, z15.s, z17.h\n" + ".inst 0x45914dce // uaddwt z14.s, z14.s, z17.h\n" + ".inst 0x459049ad // uaddwb z13.s, z13.s, z16.h\n" + ".inst 0x45904d8c // uaddwt z12.s, z12.s, z16.h\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End - "ld1rw { z18.s }, p0/Z, [%x[left_shift]]\n" + "ld1rw { z17.s }, p0/Z, [%x[left_shift]]\n" "ld1rw { z16.s }, p0/Z, [%x[combined_rescale_value]]\n" - ".inst 0x4482824f // srshl z15.s, p0/M, z15.s, z18.s\n" - ".inst 0x4482824e // srshl z14.s, p0/M, z14.s, z18.s\n" - ".inst 0x4482824d // srshl z13.s, p0/M, z13.s, z18.s\n" - ".inst 0x4482824c // srshl z12.s, p0/M, z12.s, z18.s\n" + ".inst 0x4482822f // srshl z15.s, p0/M, z15.s, z17.s\n" + ".inst 0x4482822e // srshl z14.s, p0/M, z14.s, z17.s\n" + ".inst 0x4482822d // srshl z13.s, p0/M, z13.s, z17.s\n" + ".inst 0x4482822c // srshl z12.s, p0/M, z12.s, z17.s\n" "ld1rw { z17.s }, p0/Z, [%x[right_shift]]\n" ".inst 0x04b075ef // sqrdmulh z15.s, z15.s, z16.s\n" ".inst 0x04b075ce // sqrdmulh z14.s, z14.s, z16.s\n" @@ -457,17 +457,17 @@ void sve_u8q_nhwc_avg_generic_depthfirst_impl( "add z14.s, z14.s, z16.s\n" "add z13.s, z13.s, z16.s\n" "add z12.s, z12.s, z16.s\n" - "mov z16.s, #0x0\n" - "smax z15.s, p0/M, z15.s, z16.s\n" - "smax z14.s, p0/M, z14.s, z16.s\n" - "mov z18.s, #0xff\n" - "smax z13.s, p0/M, z13.s, z16.s\n" - "smax z12.s, p0/M, z12.s, z16.s\n" - "smin z15.s, p0/M, z15.s, z18.s\n" - "smin z14.s, p0/M, z14.s, z18.s\n" + "mov z17.s, #0x0\n" + "smax z15.s, p0/M, z15.s, z17.s\n" + "smax z14.s, p0/M, z14.s, z17.s\n" + "mov z16.s, #0xff\n" + "smax z13.s, p0/M, z13.s, z17.s\n" + "smax z12.s, p0/M, z12.s, z17.s\n" + "smin z15.s, p0/M, z15.s, z16.s\n" + "smin z14.s, p0/M, z14.s, z16.s\n" "trn1 z17.h, z15.h, z14.h\n" - "smin z13.s, p0/M, z13.s, z18.s\n" - "smin z12.s, p0/M, z12.s, z18.s\n" + "smin z13.s, p0/M, z13.s, z16.s\n" + "smin z12.s, p0/M, z12.s, z16.s\n" "trn1 z16.h, z13.h, z12.h\n" "trn1 z16.b, z17.b, z16.b\n" "st1b { z16.b }, p4, [%x[outptr], x27]\n" diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8q_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8q_nhwc_max_generic_depthfirst/generic.cpp index a00cbc59d8..94522cdaaa 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8q_nhwc_max_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8q_nhwc_max_generic_depthfirst/generic.cpp @@ -56,68 +56,68 @@ void sve_u8q_nhwc_max_generic_depthfirst_impl( "lsr x25, %x[n_valid_cells], #0x2\n" "mov z8.b, #0x0\n" "mov z7.b, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "mov z6.b, #0x0\n" "mov z5.b, #0x0\n" "cbz x25, 4f\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldp x22, x21, [x20, #0x10]\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" "subs x25, x25, #0x1\n" - "add x20, x20, #0x20\n" - "ld1b { z4.b }, p4/Z, [x24, x9]\n" - "ld1b { z3.b }, p4/Z, [x23, x9]\n" - "ld1b { z2.b }, p4/Z, [x22, x9]\n" - "ld1b { z1.b }, p4/Z, [x21, x9]\n" - "ld1b { z0.b }, p3/Z, [x24, x28]\n" - "ld1b { z31.b }, p3/Z, [x23, x28]\n" - "ld1b { z22.b }, p3/Z, [x22, x28]\n" - "ld1b { z30.b }, p3/Z, [x21, x28]\n" - "ld1b { z29.b }, p2/Z, [x24, x27]\n" - "ld1b { z28.b }, p2/Z, [x23, x27]\n" - "ld1b { z21.b }, p2/Z, [x22, x27]\n" - "ld1b { z27.b }, p2/Z, [x21, x27]\n" - "ld1b { z26.b }, p1/Z, [x24, x26]\n" - "ld1b { z25.b }, p1/Z, [x23, x26]\n" - "ld1b { z20.b }, p1/Z, [x22, x26]\n" - "ld1b { z24.b }, p1/Z, [x21, x26]\n" + "add x24, x24, #0x20\n" + "ld1b { z4.b }, p4/Z, [x23, x9]\n" + "ld1b { z3.b }, p4/Z, [x22, x9]\n" + "ld1b { z2.b }, p4/Z, [x21, x9]\n" + "ld1b { z1.b }, p4/Z, [x20, x9]\n" + "ld1b { z0.b }, p3/Z, [x23, x28]\n" + "ld1b { z31.b }, p3/Z, [x22, x28]\n" + "ld1b { z22.b }, p3/Z, [x21, x28]\n" + "ld1b { z30.b }, p3/Z, [x20, x28]\n" + "ld1b { z29.b }, p2/Z, [x23, x27]\n" + "ld1b { z28.b }, p2/Z, [x22, x27]\n" + "ld1b { z21.b }, p2/Z, [x21, x27]\n" + "ld1b { z27.b }, p2/Z, [x20, x27]\n" + "ld1b { z26.b }, p1/Z, [x23, x26]\n" + "ld1b { z25.b }, p1/Z, [x22, x26]\n" + "ld1b { z20.b }, p1/Z, [x21, x26]\n" + "ld1b { z24.b }, p1/Z, [x20, x26]\n" "beq 3f\n" "2:" // 4-vectors of channels: 4 inputs loop "movprfx z19, z4\n umax z19.b, p0/M, z19.b, z3.b\n" "movprfx z23, z2\n umax z23.b, p0/M, z23.b, z1.b\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldp x22, x21, [x20, #0x10]\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" "movprfx z18, z0\n umax z18.b, p0/M, z18.b, z31.b\n" "umax z22.b, p0/M, z22.b, z30.b\n" - "ld1b { z4.b }, p4/Z, [x24, x9]\n" - "ld1b { z3.b }, p4/Z, [x23, x9]\n" + "ld1b { z4.b }, p4/Z, [x23, x9]\n" + "ld1b { z3.b }, p4/Z, [x22, x9]\n" "movprfx z17, z29\n umax z17.b, p0/M, z17.b, z28.b\n" "umax z21.b, p0/M, z21.b, z27.b\n" - "ld1b { z2.b }, p4/Z, [x22, x9]\n" - "ld1b { z1.b }, p4/Z, [x21, x9]\n" + "ld1b { z2.b }, p4/Z, [x21, x9]\n" + "ld1b { z1.b }, p4/Z, [x20, x9]\n" "movprfx z16, z26\n umax z16.b, p0/M, z16.b, z25.b\n" "umax z20.b, p0/M, z20.b, z24.b\n" - "ld1b { z0.b }, p3/Z, [x24, x28]\n" - "ld1b { z31.b }, p3/Z, [x23, x28]\n" + "ld1b { z0.b }, p3/Z, [x23, x28]\n" + "ld1b { z31.b }, p3/Z, [x22, x28]\n" "umax z19.b, p0/M, z19.b, z23.b\n" "umax z18.b, p0/M, z18.b, z22.b\n" - "ld1b { z22.b }, p3/Z, [x22, x28]\n" - "ld1b { z30.b }, p3/Z, [x21, x28]\n" + "ld1b { z22.b }, p3/Z, [x21, x28]\n" + "ld1b { z30.b }, p3/Z, [x20, x28]\n" "umax z17.b, p0/M, z17.b, z21.b\n" "umax z16.b, p0/M, z16.b, z20.b\n" - "ld1b { z29.b }, p2/Z, [x24, x27]\n" - "ld1b { z28.b }, p2/Z, [x23, x27]\n" + "ld1b { z29.b }, p2/Z, [x23, x27]\n" + "ld1b { z28.b }, p2/Z, [x22, x27]\n" "subs x25, x25, #0x1\n" "umax z8.b, p0/M, z8.b, z19.b\n" - "ld1b { z21.b }, p2/Z, [x22, x27]\n" - "ld1b { z27.b }, p2/Z, [x21, x27]\n" + "ld1b { z21.b }, p2/Z, [x21, x27]\n" + "ld1b { z27.b }, p2/Z, [x20, x27]\n" "umax z7.b, p0/M, z7.b, z18.b\n" "umax z6.b, p0/M, z6.b, z17.b\n" - "ld1b { z26.b }, p1/Z, [x24, x26]\n" - "ld1b { z25.b }, p1/Z, [x23, x26]\n" + "ld1b { z26.b }, p1/Z, [x23, x26]\n" + "ld1b { z25.b }, p1/Z, [x22, x26]\n" "umax z5.b, p0/M, z5.b, z16.b\n" - "add x20, x20, #0x20\n" - "ld1b { z20.b }, p1/Z, [x22, x26]\n" - "ld1b { z24.b }, p1/Z, [x21, x26]\n" + "add x24, x24, #0x20\n" + "ld1b { z20.b }, p1/Z, [x21, x26]\n" + "ld1b { z24.b }, p1/Z, [x20, x26]\n" "bgt 2b\n" "3:" // 4-vectors of channels: 4 inputs tail "movprfx z19, z4\n umax z19.b, p0/M, z19.b, z3.b\n" @@ -140,103 +140,103 @@ void sve_u8q_nhwc_max_generic_depthfirst_impl( "ands x21, %x[n_valid_cells], #0x3\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x24, [x20], #0x8\n" - "ld1b { z4.b }, p4/Z, [x24, x9]\n" + "ldr x20, [x24], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x9]\n" "subs x21, x21, #0x1\n" - "umax z8.b, p0/M, z8.b, z4.b\n" - "ld1b { z0.b }, p3/Z, [x24, x28]\n" - "ld1b { z29.b }, p2/Z, [x24, x27]\n" - "umax z7.b, p0/M, z7.b, z0.b\n" - "umax z6.b, p0/M, z6.b, z29.b\n" - "ld1b { z26.b }, p1/Z, [x24, x26]\n" - "umax z5.b, p0/M, z5.b, z26.b\n" + "umax z8.b, p0/M, z8.b, z16.b\n" + "ld1b { z17.b }, p3/Z, [x20, x28]\n" + "ld1b { z16.b }, p2/Z, [x20, x27]\n" + "umax z7.b, p0/M, z7.b, z17.b\n" + "umax z6.b, p0/M, z6.b, z16.b\n" + "ld1b { z16.b }, p1/Z, [x20, x26]\n" + "umax z5.b, p0/M, z5.b, z16.b\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End "add x20, %x[quant_params], %[offsetof_qp_input_offset]\n" - "ld1rw { z4.s }, p0/Z, [x20]\n" - ".inst 0x4508a918 // ushllb z24.h, z8.b, #0x0\n" - ".inst 0x4508ad17 // ushllt z23.h, z8.b, #0x0\n" - ".inst 0x4508a8f6 // ushllb z22.h, z7.b, #0x0\n" - ".inst 0x4508acf5 // ushllt z21.h, z7.b, #0x0\n" - "neg z4.s, p0/M, z4.s\n" - "add x20, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n" - ".inst 0x4508a8d4 // ushllb z20.h, z6.b, #0x0\n" - ".inst 0x4508acd3 // ushllt z19.h, z6.b, #0x0\n" "ld1rw { z3.s }, p0/Z, [x20]\n" + ".inst 0x4508a911 // ushllb z17.h, z8.b, #0x0\n" + ".inst 0x4508ad18 // ushllt z24.h, z8.b, #0x0\n" + ".inst 0x4508a8f7 // ushllb z23.h, z7.b, #0x0\n" + ".inst 0x4508acf6 // ushllt z22.h, z7.b, #0x0\n" + "neg z3.s, p0/M, z3.s\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n" + ".inst 0x4508a8d5 // ushllb z21.h, z6.b, #0x0\n" + ".inst 0x4508acd4 // ushllt z20.h, z6.b, #0x0\n" + "ld1rw { z2.s }, p0/Z, [x20]\n" "add x20, %x[quant_params], %[offsetof_qp_per_layer_mul]\n" - ".inst 0x4508a8b2 // ushllb z18.h, z5.b, #0x0\n" - ".inst 0x4508acb1 // ushllt z17.h, z5.b, #0x0\n" - "ld1rw { z16.s }, p0/Z, [x20]\n" + ".inst 0x4508a8b3 // ushllb z19.h, z5.b, #0x0\n" + ".inst 0x4508acb0 // ushllt z16.h, z5.b, #0x0\n" + "ld1rw { z18.s }, p0/Z, [x20]\n" "add x20, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n" - ".inst 0x45984082 // saddwb z2.s, z4.s, z24.h\n" - ".inst 0x45984481 // saddwt z1.s, z4.s, z24.h\n" - ".inst 0x44828062 // srshl z2.s, p0/M, z2.s, z3.s\n" - ".inst 0x44828061 // srshl z1.s, p0/M, z1.s, z3.s\n" - ".inst 0x45974080 // saddwb z0.s, z4.s, z23.h\n" - ".inst 0x4597449f // saddwt z31.s, z4.s, z23.h\n" - ".inst 0x44828060 // srshl z0.s, p0/M, z0.s, z3.s\n" - ".inst 0x4482807f // srshl z31.s, p0/M, z31.s, z3.s\n" - ".inst 0x4596409e // saddwb z30.s, z4.s, z22.h\n" - ".inst 0x4596449d // saddwt z29.s, z4.s, z22.h\n" - ".inst 0x4482807e // srshl z30.s, p0/M, z30.s, z3.s\n" - ".inst 0x4482807d // srshl z29.s, p0/M, z29.s, z3.s\n" - ".inst 0x4595409c // saddwb z28.s, z4.s, z21.h\n" - ".inst 0x4595449b // saddwt z27.s, z4.s, z21.h\n" - ".inst 0x4482807c // srshl z28.s, p0/M, z28.s, z3.s\n" - ".inst 0x4482807b // srshl z27.s, p0/M, z27.s, z3.s\n" - ".inst 0x4594409a // saddwb z26.s, z4.s, z20.h\n" - ".inst 0x45944499 // saddwt z25.s, z4.s, z20.h\n" - ".inst 0x4482807a // srshl z26.s, p0/M, z26.s, z3.s\n" - ".inst 0x44828079 // srshl z25.s, p0/M, z25.s, z3.s\n" - ".inst 0x45934098 // saddwb z24.s, z4.s, z19.h\n" - ".inst 0x45934497 // saddwt z23.s, z4.s, z19.h\n" - ".inst 0x44828078 // srshl z24.s, p0/M, z24.s, z3.s\n" - ".inst 0x44828077 // srshl z23.s, p0/M, z23.s, z3.s\n" - ".inst 0x45924096 // saddwb z22.s, z4.s, z18.h\n" - ".inst 0x45924495 // saddwt z21.s, z4.s, z18.h\n" - ".inst 0x44828076 // srshl z22.s, p0/M, z22.s, z3.s\n" - ".inst 0x44828075 // srshl z21.s, p0/M, z21.s, z3.s\n" - ".inst 0x45914094 // saddwb z20.s, z4.s, z17.h\n" - ".inst 0x45914493 // saddwt z19.s, z4.s, z17.h\n" - ".inst 0x44828074 // srshl z20.s, p0/M, z20.s, z3.s\n" - ".inst 0x44828073 // srshl z19.s, p0/M, z19.s, z3.s\n" - "ld1rw { z17.s }, p0/Z, [x20]\n" - ".inst 0x04b07442 // sqrdmulh z2.s, z2.s, z16.s\n" - ".inst 0x04b07421 // sqrdmulh z1.s, z1.s, z16.s\n" + ".inst 0x45914061 // saddwb z1.s, z3.s, z17.h\n" + ".inst 0x45914471 // saddwt z17.s, z3.s, z17.h\n" + ".inst 0x44828041 // srshl z1.s, p0/M, z1.s, z2.s\n" + ".inst 0x44828051 // srshl z17.s, p0/M, z17.s, z2.s\n" + ".inst 0x45984060 // saddwb z0.s, z3.s, z24.h\n" + ".inst 0x4598447f // saddwt z31.s, z3.s, z24.h\n" + ".inst 0x44828040 // srshl z0.s, p0/M, z0.s, z2.s\n" + ".inst 0x4482805f // srshl z31.s, p0/M, z31.s, z2.s\n" + ".inst 0x4597407e // saddwb z30.s, z3.s, z23.h\n" + ".inst 0x4597447d // saddwt z29.s, z3.s, z23.h\n" + ".inst 0x4482805e // srshl z30.s, p0/M, z30.s, z2.s\n" + ".inst 0x4482805d // srshl z29.s, p0/M, z29.s, z2.s\n" + ".inst 0x4596407c // saddwb z28.s, z3.s, z22.h\n" + ".inst 0x4596447b // saddwt z27.s, z3.s, z22.h\n" + ".inst 0x4482805c // srshl z28.s, p0/M, z28.s, z2.s\n" + ".inst 0x4482805b // srshl z27.s, p0/M, z27.s, z2.s\n" + ".inst 0x4595407a // saddwb z26.s, z3.s, z21.h\n" + ".inst 0x45954479 // saddwt z25.s, z3.s, z21.h\n" + ".inst 0x4482805a // srshl z26.s, p0/M, z26.s, z2.s\n" + ".inst 0x44828059 // srshl z25.s, p0/M, z25.s, z2.s\n" + ".inst 0x45944078 // saddwb z24.s, z3.s, z20.h\n" + ".inst 0x45944477 // saddwt z23.s, z3.s, z20.h\n" + ".inst 0x44828058 // srshl z24.s, p0/M, z24.s, z2.s\n" + ".inst 0x44828057 // srshl z23.s, p0/M, z23.s, z2.s\n" + ".inst 0x45934076 // saddwb z22.s, z3.s, z19.h\n" + ".inst 0x45934475 // saddwt z21.s, z3.s, z19.h\n" + ".inst 0x44828056 // srshl z22.s, p0/M, z22.s, z2.s\n" + ".inst 0x44828055 // srshl z21.s, p0/M, z21.s, z2.s\n" + ".inst 0x45904074 // saddwb z20.s, z3.s, z16.h\n" + ".inst 0x45904473 // saddwt z19.s, z3.s, z16.h\n" + ".inst 0x44828054 // srshl z20.s, p0/M, z20.s, z2.s\n" + ".inst 0x44828053 // srshl z19.s, p0/M, z19.s, z2.s\n" + "ld1rw { z16.s }, p0/Z, [x20]\n" + ".inst 0x04b27421 // sqrdmulh z1.s, z1.s, z18.s\n" + ".inst 0x04b27631 // sqrdmulh z17.s, z17.s, z18.s\n" "add x20, %x[quant_params], %[offsetof_qp_output_offset]\n" - ".inst 0x04b07400 // sqrdmulh z0.s, z0.s, z16.s\n" - ".inst 0x04b077ff // sqrdmulh z31.s, z31.s, z16.s\n" - ".inst 0x44828222 // srshl z2.s, p0/M, z2.s, z17.s\n" - ".inst 0x44828221 // srshl z1.s, p0/M, z1.s, z17.s\n" - ".inst 0x04b077de // sqrdmulh z30.s, z30.s, z16.s\n" - ".inst 0x04b077bd // sqrdmulh z29.s, z29.s, z16.s\n" - ".inst 0x44828220 // srshl z0.s, p0/M, z0.s, z17.s\n" - ".inst 0x4482823f // srshl z31.s, p0/M, z31.s, z17.s\n" - ".inst 0x04b0779c // sqrdmulh z28.s, z28.s, z16.s\n" - ".inst 0x04b0777b // sqrdmulh z27.s, z27.s, z16.s\n" - ".inst 0x4482823e // srshl z30.s, p0/M, z30.s, z17.s\n" - ".inst 0x4482823d // srshl z29.s, p0/M, z29.s, z17.s\n" - ".inst 0x04b0775a // sqrdmulh z26.s, z26.s, z16.s\n" - ".inst 0x04b07739 // sqrdmulh z25.s, z25.s, z16.s\n" - ".inst 0x4482823c // srshl z28.s, p0/M, z28.s, z17.s\n" - ".inst 0x4482823b // srshl z27.s, p0/M, z27.s, z17.s\n" - ".inst 0x04b07718 // sqrdmulh z24.s, z24.s, z16.s\n" - ".inst 0x04b076f7 // sqrdmulh z23.s, z23.s, z16.s\n" - ".inst 0x4482823a // srshl z26.s, p0/M, z26.s, z17.s\n" - ".inst 0x44828239 // srshl z25.s, p0/M, z25.s, z17.s\n" - ".inst 0x04b076d6 // sqrdmulh z22.s, z22.s, z16.s\n" - ".inst 0x04b076b5 // sqrdmulh z21.s, z21.s, z16.s\n" - ".inst 0x44828238 // srshl z24.s, p0/M, z24.s, z17.s\n" - ".inst 0x44828237 // srshl z23.s, p0/M, z23.s, z17.s\n" - ".inst 0x04b07694 // sqrdmulh z20.s, z20.s, z16.s\n" - ".inst 0x04b07673 // sqrdmulh z19.s, z19.s, z16.s\n" - ".inst 0x44828236 // srshl z22.s, p0/M, z22.s, z17.s\n" - ".inst 0x44828235 // srshl z21.s, p0/M, z21.s, z17.s\n" - ".inst 0x44828234 // srshl z20.s, p0/M, z20.s, z17.s\n" - ".inst 0x44828233 // srshl z19.s, p0/M, z19.s, z17.s\n" + ".inst 0x04b27400 // sqrdmulh z0.s, z0.s, z18.s\n" + ".inst 0x04b277ff // sqrdmulh z31.s, z31.s, z18.s\n" + ".inst 0x44828201 // srshl z1.s, p0/M, z1.s, z16.s\n" + ".inst 0x44828211 // srshl z17.s, p0/M, z17.s, z16.s\n" + ".inst 0x04b277de // sqrdmulh z30.s, z30.s, z18.s\n" + ".inst 0x04b277bd // sqrdmulh z29.s, z29.s, z18.s\n" + ".inst 0x44828200 // srshl z0.s, p0/M, z0.s, z16.s\n" + ".inst 0x4482821f // srshl z31.s, p0/M, z31.s, z16.s\n" + ".inst 0x04b2779c // sqrdmulh z28.s, z28.s, z18.s\n" + ".inst 0x04b2777b // sqrdmulh z27.s, z27.s, z18.s\n" + ".inst 0x4482821e // srshl z30.s, p0/M, z30.s, z16.s\n" + ".inst 0x4482821d // srshl z29.s, p0/M, z29.s, z16.s\n" + ".inst 0x04b2775a // sqrdmulh z26.s, z26.s, z18.s\n" + ".inst 0x04b27739 // sqrdmulh z25.s, z25.s, z18.s\n" + ".inst 0x4482821c // srshl z28.s, p0/M, z28.s, z16.s\n" + ".inst 0x4482821b // srshl z27.s, p0/M, z27.s, z16.s\n" + ".inst 0x04b27718 // sqrdmulh z24.s, z24.s, z18.s\n" + ".inst 0x04b276f7 // sqrdmulh z23.s, z23.s, z18.s\n" + ".inst 0x4482821a // srshl z26.s, p0/M, z26.s, z16.s\n" + ".inst 0x44828219 // srshl z25.s, p0/M, z25.s, z16.s\n" + ".inst 0x04b276d6 // sqrdmulh z22.s, z22.s, z18.s\n" + ".inst 0x04b276b5 // sqrdmulh z21.s, z21.s, z18.s\n" + ".inst 0x44828218 // srshl z24.s, p0/M, z24.s, z16.s\n" + ".inst 0x44828217 // srshl z23.s, p0/M, z23.s, z16.s\n" + ".inst 0x04b27694 // sqrdmulh z20.s, z20.s, z18.s\n" + ".inst 0x04b27673 // sqrdmulh z19.s, z19.s, z18.s\n" + ".inst 0x44828216 // srshl z22.s, p0/M, z22.s, z16.s\n" + ".inst 0x44828215 // srshl z21.s, p0/M, z21.s, z16.s\n" + ".inst 0x44828214 // srshl z20.s, p0/M, z20.s, z16.s\n" + ".inst 0x44828213 // srshl z19.s, p0/M, z19.s, z16.s\n" "ld1rw { z16.s }, p0/Z, [x20]\n" - "add z2.s, z2.s, z16.s\n" "add z1.s, z1.s, z16.s\n" + "add z17.s, z17.s, z16.s\n" "add z0.s, z0.s, z16.s\n" "add z31.s, z31.s, z16.s\n" "add z30.s, z30.s, z16.s\n" @@ -252,8 +252,8 @@ void sve_u8q_nhwc_max_generic_depthfirst_impl( "add z20.s, z20.s, z16.s\n" "add z19.s, z19.s, z16.s\n" "mov z16.s, #0x0\n" - "smax z2.s, p0/M, z2.s, z16.s\n" "smax z1.s, p0/M, z1.s, z16.s\n" + "smax z17.s, p0/M, z17.s, z16.s\n" "smax z0.s, p0/M, z0.s, z16.s\n" "smax z31.s, p0/M, z31.s, z16.s\n" "mov z18.s, #0xff\n" @@ -269,9 +269,9 @@ void sve_u8q_nhwc_max_generic_depthfirst_impl( "smax z21.s, p0/M, z21.s, z16.s\n" "smax z20.s, p0/M, z20.s, z16.s\n" "smax z19.s, p0/M, z19.s, z16.s\n" - "smin z2.s, p0/M, z2.s, z18.s\n" "smin z1.s, p0/M, z1.s, z18.s\n" - "trn1 z17.h, z2.h, z1.h\n" + "smin z17.s, p0/M, z17.s, z18.s\n" + "trn1 z17.h, z1.h, z17.h\n" "smin z0.s, p0/M, z0.s, z18.s\n" "smin z31.s, p0/M, z31.s, z18.s\n" "trn1 z16.h, z0.h, z31.h\n" @@ -313,91 +313,91 @@ void sve_u8q_nhwc_max_generic_depthfirst_impl( "8:" // Single vector of channels: Loop "lsr x25, %x[n_valid_cells], #0x2\n" "mov z8.b, #0x0\n" - "mov x20, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "cbz x25, 11f\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldp x22, x21, [x20, #0x10]\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" "subs x25, x25, #0x1\n" - "add x20, x20, #0x20\n" - "ld1b { z4.b }, p4/Z, [x24, x9]\n" - "ld1b { z3.b }, p4/Z, [x23, x9]\n" - "ld1b { z2.b }, p4/Z, [x22, x9]\n" - "ld1b { z1.b }, p4/Z, [x21, x9]\n" + "add x24, x24, #0x20\n" + "ld1b { z4.b }, p4/Z, [x23, x9]\n" + "ld1b { z3.b }, p4/Z, [x22, x9]\n" + "ld1b { z2.b }, p4/Z, [x21, x9]\n" + "ld1b { z1.b }, p4/Z, [x20, x9]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 4 inputs loop - "movprfx z19, z4\n umax z19.b, p0/M, z19.b, z3.b\n" - "movprfx z23, z2\n umax z23.b, p0/M, z23.b, z1.b\n" - "ldp x24, x23, [x20, #0x0]\n" - "ldp x22, x21, [x20, #0x10]\n" - "umax z19.b, p0/M, z19.b, z23.b\n" + "movprfx z16, z4\n umax z16.b, p0/M, z16.b, z3.b\n" + "movprfx z17, z2\n umax z17.b, p0/M, z17.b, z1.b\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "umax z16.b, p0/M, z16.b, z17.b\n" "subs x25, x25, #0x1\n" - "ld1b { z4.b }, p4/Z, [x24, x9]\n" - "ld1b { z3.b }, p4/Z, [x23, x9]\n" - "umax z8.b, p0/M, z8.b, z19.b\n" - "add x20, x20, #0x20\n" - "ld1b { z2.b }, p4/Z, [x22, x9]\n" - "ld1b { z1.b }, p4/Z, [x21, x9]\n" + "ld1b { z4.b }, p4/Z, [x23, x9]\n" + "ld1b { z3.b }, p4/Z, [x22, x9]\n" + "umax z8.b, p0/M, z8.b, z16.b\n" + "add x24, x24, #0x20\n" + "ld1b { z2.b }, p4/Z, [x21, x9]\n" + "ld1b { z1.b }, p4/Z, [x20, x9]\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 4 inputs tail - "movprfx z19, z4\n umax z19.b, p0/M, z19.b, z3.b\n" - "movprfx z23, z2\n umax z23.b, p0/M, z23.b, z1.b\n" - "umax z19.b, p0/M, z19.b, z23.b\n" - "umax z8.b, p0/M, z8.b, z19.b\n" + "movprfx z16, z4\n umax z16.b, p0/M, z16.b, z3.b\n" + "movprfx z17, z2\n umax z17.b, p0/M, z17.b, z1.b\n" + "umax z16.b, p0/M, z16.b, z17.b\n" + "umax z8.b, p0/M, z8.b, z16.b\n" "11:" // Single vector of channels: Loop: After loop "ands x21, %x[n_valid_cells], #0x3\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x24, [x20], #0x8\n" - "ld1b { z4.b }, p4/Z, [x24, x9]\n" + "ldr x20, [x24], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x9]\n" "subs x21, x21, #0x1\n" - "umax z8.b, p0/M, z8.b, z4.b\n" + "umax z8.b, p0/M, z8.b, z16.b\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End "add x20, %x[quant_params], %[offsetof_qp_input_offset]\n" - "ld1rw { z4.s }, p0/Z, [x20]\n" - ".inst 0x4508a918 // ushllb z24.h, z8.b, #0x0\n" - ".inst 0x4508ad17 // ushllt z23.h, z8.b, #0x0\n" - "neg z4.s, p0/M, z4.s\n" + "ld1rw { z18.s }, p0/Z, [x20]\n" + ".inst 0x4508a911 // ushllb z17.h, z8.b, #0x0\n" + ".inst 0x4508ad10 // ushllt z16.h, z8.b, #0x0\n" + "neg z18.s, p0/M, z18.s\n" "add x20, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n" - ".inst 0x45984082 // saddwb z2.s, z4.s, z24.h\n" - ".inst 0x45984481 // saddwt z1.s, z4.s, z24.h\n" - ".inst 0x45974080 // saddwb z0.s, z4.s, z23.h\n" - ".inst 0x4597449f // saddwt z31.s, z4.s, z23.h\n" - "ld1rw { z3.s }, p0/Z, [x20]\n" + ".inst 0x45914255 // saddwb z21.s, z18.s, z17.h\n" + ".inst 0x45914654 // saddwt z20.s, z18.s, z17.h\n" + ".inst 0x45904253 // saddwb z19.s, z18.s, z16.h\n" + ".inst 0x45904652 // saddwt z18.s, z18.s, z16.h\n" + "ld1rw { z17.s }, p0/Z, [x20]\n" "add x20, %x[quant_params], %[offsetof_qp_per_layer_mul]\n" "ld1rw { z16.s }, p0/Z, [x20]\n" - ".inst 0x44828062 // srshl z2.s, p0/M, z2.s, z3.s\n" - ".inst 0x44828061 // srshl z1.s, p0/M, z1.s, z3.s\n" - ".inst 0x04b07442 // sqrdmulh z2.s, z2.s, z16.s\n" - ".inst 0x44828060 // srshl z0.s, p0/M, z0.s, z3.s\n" - ".inst 0x4482807f // srshl z31.s, p0/M, z31.s, z3.s\n" - ".inst 0x04b07421 // sqrdmulh z1.s, z1.s, z16.s\n" - ".inst 0x04b07400 // sqrdmulh z0.s, z0.s, z16.s\n" + ".inst 0x44828235 // srshl z21.s, p0/M, z21.s, z17.s\n" + ".inst 0x44828234 // srshl z20.s, p0/M, z20.s, z17.s\n" + ".inst 0x04b076b5 // sqrdmulh z21.s, z21.s, z16.s\n" + ".inst 0x44828233 // srshl z19.s, p0/M, z19.s, z17.s\n" + ".inst 0x44828232 // srshl z18.s, p0/M, z18.s, z17.s\n" + ".inst 0x04b07694 // sqrdmulh z20.s, z20.s, z16.s\n" + ".inst 0x04b07673 // sqrdmulh z19.s, z19.s, z16.s\n" "add x20, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n" "ld1rw { z17.s }, p0/Z, [x20]\n" - ".inst 0x04b077ff // sqrdmulh z31.s, z31.s, z16.s\n" + ".inst 0x04b07652 // sqrdmulh z18.s, z18.s, z16.s\n" "add x20, %x[quant_params], %[offsetof_qp_output_offset]\n" - ".inst 0x44828222 // srshl z2.s, p0/M, z2.s, z17.s\n" - ".inst 0x44828221 // srshl z1.s, p0/M, z1.s, z17.s\n" + ".inst 0x44828235 // srshl z21.s, p0/M, z21.s, z17.s\n" + ".inst 0x44828234 // srshl z20.s, p0/M, z20.s, z17.s\n" "ld1rw { z16.s }, p0/Z, [x20]\n" - "add z2.s, z2.s, z16.s\n" - ".inst 0x44828220 // srshl z0.s, p0/M, z0.s, z17.s\n" - ".inst 0x4482823f // srshl z31.s, p0/M, z31.s, z17.s\n" - "add z1.s, z1.s, z16.s\n" - "add z0.s, z0.s, z16.s\n" - "add z31.s, z31.s, z16.s\n" + "add z21.s, z21.s, z16.s\n" + ".inst 0x44828233 // srshl z19.s, p0/M, z19.s, z17.s\n" + ".inst 0x44828232 // srshl z18.s, p0/M, z18.s, z17.s\n" + "add z20.s, z20.s, z16.s\n" + "add z19.s, z19.s, z16.s\n" + "add z18.s, z18.s, z16.s\n" "mov z16.s, #0x0\n" - "smax z2.s, p0/M, z2.s, z16.s\n" - "smax z1.s, p0/M, z1.s, z16.s\n" - "smax z0.s, p0/M, z0.s, z16.s\n" - "smax z31.s, p0/M, z31.s, z16.s\n" - "mov z18.s, #0xff\n" - "smin z2.s, p0/M, z2.s, z18.s\n" - "smin z1.s, p0/M, z1.s, z18.s\n" - "trn1 z17.h, z2.h, z1.h\n" - "smin z0.s, p0/M, z0.s, z18.s\n" - "smin z31.s, p0/M, z31.s, z18.s\n" - "trn1 z16.h, z0.h, z31.h\n" + "smax z21.s, p0/M, z21.s, z16.s\n" + "smax z20.s, p0/M, z20.s, z16.s\n" + "smax z19.s, p0/M, z19.s, z16.s\n" + "smax z18.s, p0/M, z18.s, z16.s\n" + "mov z16.s, #0xff\n" + "smin z21.s, p0/M, z21.s, z16.s\n" + "smin z20.s, p0/M, z20.s, z16.s\n" + "trn1 z17.h, z21.h, z20.h\n" + "smin z19.s, p0/M, z19.s, z16.s\n" + "smin z18.s, p0/M, z18.s, z16.s\n" + "trn1 z16.h, z19.h, z18.h\n" "trn1 z16.b, z17.b, z16.b\n" "st1b { z16.b }, p4, [%x[outptr], x9]\n" "incb x9\n" |