diff options
Diffstat (limited to 'src/core/NEON/kernels/arm_conv/pooling/kernels')
36 files changed, 5739 insertions, 0 deletions
diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp new file mode 100644 index 0000000000..250d92c051 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#pragma once + +namespace arm_conv { +namespace pooling { + +void sme_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst_impl(unsigned int, const __fp16 *const *const, __fp16 *const *const, bool, unsigned int, unsigned int, unsigned int, unsigned int); + +struct sme_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst : public DepthfirstStrategy<__fp16, __fp16> +{ + using Parent = DepthfirstStrategy<__fp16, __fp16>; + + const static auto pooling_type = PoolingType::AVERAGE; + const static auto pool_rows = 3u, pool_cols = 3u; + const static auto stride_rows = 1u, stride_cols = 1u; + + sme_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst(const CPUInfo *) + : Parent(pool_rows, pool_cols, stride_rows, stride_cols, 2, 2) {} + + Parent::KernelType get_kernel(void) const { return sme_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst_impl; } +}; + +} // namespace pooling +} // namespace arm_conv diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp new file mode 100644 index 0000000000..a8b6f185be --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp @@ -0,0 +1,209 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <algorithm> +#include <cstddef> +#include <cstdint> + +#if defined(__ARM_FEATURE_SVE) && defined(__ARM_FP16_ARGS) && defined(ARM_COMPUTE_ENABLE_SME) + +namespace arm_conv { +namespace pooling { + +void sme_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst_impl( + const unsigned int n_channels, + const __fp16 *const *const inptrs, + __fp16 *const *const outptrs, + const bool exclude_padding, + const unsigned int pad_left, + const unsigned int pad_top, + const unsigned int pad_right, + const unsigned int pad_bottom +) +{ + struct KernelArgs + { + const uint64_t n_channels; + const __fp16 *const *const inptrs; + __fp16 *const *const outptrs; + __fp16 rescale_vals[4]; + + KernelArgs( + unsigned int channels, + const __fp16 *const *input_ptrs, + __fp16 *const * output_ptrs, + bool exclude_padding, unsigned int pad_left, unsigned int pad_top, unsigned int pad_right, unsigned int pad_bottom + ) : n_channels(channels), + inptrs(input_ptrs), + outptrs(output_ptrs) + { + for (unsigned int i = 0; i < 2; i++) + { + const int start_i = 1*i - static_cast<int>(pad_top); + const int end_i = std::min<int>(start_i + 3, 4 - pad_top - pad_bottom); + const int valid_rows = end_i - std::max<int>(0, start_i); + + for (unsigned int j = 0; j < 2; j++) + { + const int start_j = 1*j - static_cast<int>(pad_left); + const int end_j = std::min<int>(start_j + 3, 4 - pad_left - pad_right); + const int valid_cols = end_j - std::max<int>(0, start_j); + + rescale_vals[i*2 + j] = static_cast<__fp16>(1.0f / static_cast<float>( + exclude_padding ? valid_rows * valid_cols : 9 + )); + } + } + } + }; + + const KernelArgs args(n_channels, inptrs, outptrs, exclude_padding, + pad_left, pad_top, pad_right, pad_bottom); + + __asm__ __volatile__( + "ldr x20, [%x[args], %[offsetof_outptrs]]\n" + ".inst 0xd503477f // SMSTART ZA\n" + "mov x4, #0x0\n" + "mov x19, #0x4\n" + "ldr x5, [%x[args], %[offsetof_inptrs]]\n" + "whilelt p0.h, XZR, x19\n" + "add x19, %x[args], %[offsetof_rescale]\n" + "ld1rqh { z4.h }, p0/Z, [x19]\n" + "ldr x6, [%x[args], %[offsetof_n_channels]]\n" + "whilelt p1.h, x4, x6\n" + "mov x7, #0x0\n" + "ldp x8, x17, [x20, #0x0]\n" + "ldp x16, x15, [x20, #0x10]\n" + "ldp x14, x13, [x5, #0x0]\n" + "ld1h { z3.h }, p1/Z, [x13, x4, LSL #1]\n" + "ldp x12, x11, [x5, #0x10]\n" + "ld1h { z2.h }, p1/Z, [x12, x4, LSL #1]\n" + "ldp x10, x9, [x5, #0x20]\n" + "ld1h { z1.h }, p1/Z, [x9, x4, LSL #1]\n" + "ldp x28, x27, [x5, #0x30]\n" + "ld1h { z0.h }, p1/Z, [x28, x4, LSL #1]\n" + "ldp x26, x25, [x5, #0x40]\n" + "ld1h { z31.h }, p1/Z, [x25, x4, LSL #1]\n" + "ldp x24, x23, [x5, #0x50]\n" + "ld1h { z30.h }, p1/Z, [x24, x4, LSL #1]\n" + "ldp x22, x21, [x5, #0x60]\n" + "ld1h { z29.h }, p1/Z, [x10, x4, LSL #1]\n" + "ldp x20, x19, [x5, #0x70]\n" + "ld1h { z28.h }, p1/Z, [x26, x4, LSL #1]\n" + "ld1h { z27.h }, p1/Z, [x27, x4, LSL #1]\n" + "ld1h { z22.h }, p1/Z, [x23, x4, LSL #1]\n" + "ld1h { z21.h }, p1/Z, [x21, x4, LSL #1]\n" + "ld1h { z20.h }, p1/Z, [x20, x4, LSL #1]\n" + "ld1h { z26.h }, p1/Z, [x14, x4, LSL #1]\n" + "ld1h { z25.h }, p1/Z, [x11, x4, LSL #1]\n" + "ld1h { z24.h }, p1/Z, [x22, x4, LSL #1]\n" + "ld1h { z23.h }, p1/Z, [x19, x4, LSL #1]\n" + "incw x4\n" + "whilelt p1.h, x4, x6\n" + "b.none 2f\n" + "1:" // Vector: Loop + "fadd z17.h, z1.h, z0.h\n" + "fadd z16.h, z31.h, z30.h\n" + "ld1h { z1.h }, p1/Z, [x9, x4, LSL #1]\n" + "whilelt p0.h, x7, x6\n" + "fadd z19.h, z17.h, z16.h\n" + "fadd z18.h, z3.h, z2.h\n" + "ld1h { z0.h }, p1/Z, [x28, x4, LSL #1]\n" + "fadd z17.h, z29.h, z28.h\n" + "fadd z22.h, z27.h, z22.h\n" + "ld1h { z31.h }, p1/Z, [x25, x4, LSL #1]\n" + "fadd z16.h, z21.h, z20.h\n" + "fadd z21.h, z18.h, z19.h\n" + "ld1h { z30.h }, p1/Z, [x24, x4, LSL #1]\n" + "fadd z20.h, z16.h, z19.h\n" + "fadd z19.h, z26.h, z17.h\n" + "ld1h { z3.h }, p1/Z, [x13, x4, LSL #1]\n" + "fadd z18.h, z25.h, z22.h\n" + "fadd z17.h, z24.h, z17.h\n" + "ld1h { z2.h }, p1/Z, [x12, x4, LSL #1]\n" + "fadd z16.h, z23.h, z22.h\n" + "fadd z19.h, z19.h, z21.h\n" + "ld1h { z29.h }, p1/Z, [x10, x4, LSL #1]\n" + "fadd z18.h, z18.h, z21.h\n" + "fadd z17.h, z17.h, z20.h\n" + "ld1h { z28.h }, p1/Z, [x26, x4, LSL #1]\n" + "fadd z16.h, z16.h, z20.h\n" + "ld1h { z27.h }, p1/Z, [x27, x4, LSL #1]\n" + "fmul z19.h, z19.h, z4.h[0]\n" + "ld1h { z22.h }, p1/Z, [x23, x4, LSL #1]\n" + "fmul z18.h, z18.h, z4.h[1]\n" + "fmul z17.h, z17.h, z4.h[2]\n" + "ld1h { z21.h }, p1/Z, [x21, x4, LSL #1]\n" + "fmul z16.h, z16.h, z4.h[3]\n" + "st1h { z19.h }, p0, [x8, x7, LSL #1]\n" + "ld1h { z20.h }, p1/Z, [x20, x4, LSL #1]\n" + "st1h { z18.h }, p0, [x17, x7, LSL #1]\n" + "ld1h { z26.h }, p1/Z, [x14, x4, LSL #1]\n" + "st1h { z17.h }, p0, [x16, x7, LSL #1]\n" + "ld1h { z25.h }, p1/Z, [x11, x4, LSL #1]\n" + "st1h { z16.h }, p0, [x15, x7, LSL #1]\n" + "incw x7\n" + "ld1h { z24.h }, p1/Z, [x22, x4, LSL #1]\n" + "ld1h { z23.h }, p1/Z, [x19, x4, LSL #1]\n" + "incw x4\n" + "whilelt p1.h, x4, x6\n" + "b.any 1b\n" + "2:" // Vector: Tail + "fadd z17.h, z1.h, z0.h\n" + "fadd z16.h, z31.h, z30.h\n" + "whilelt p0.h, x7, x6\n" + "fadd z19.h, z17.h, z16.h\n" + "fadd z18.h, z3.h, z2.h\n" + "fadd z17.h, z29.h, z28.h\n" + "fadd z22.h, z27.h, z22.h\n" + "fadd z16.h, z21.h, z20.h\n" + "fadd z21.h, z18.h, z19.h\n" + "fadd z20.h, z16.h, z19.h\n" + "fadd z19.h, z26.h, z17.h\n" + "fadd z18.h, z25.h, z22.h\n" + "fadd z17.h, z24.h, z17.h\n" + "fadd z16.h, z23.h, z22.h\n" + "fadd z19.h, z19.h, z21.h\n" + "fadd z18.h, z18.h, z21.h\n" + "fadd z17.h, z17.h, z20.h\n" + "fadd z16.h, z16.h, z20.h\n" + "fmul z19.h, z19.h, z4.h[0]\n" + "st1h { z19.h }, p0, [x8, x7, LSL #1]\n" + "fmul z18.h, z18.h, z4.h[1]\n" + "fmul z17.h, z17.h, z4.h[2]\n" + "st1h { z18.h }, p0, [x17, x7, LSL #1]\n" + "fmul z16.h, z16.h, z4.h[3]\n" + "st1h { z17.h }, p0, [x16, x7, LSL #1]\n" + "st1h { z16.h }, p0, [x15, x7, LSL #1]\n" + ".inst 0xd503467f // SMSTOP\n" + : + : [args] "r" (&args), [offsetof_inptrs] "I" (offsetof(KernelArgs, inptrs)), [offsetof_n_channels] "I" (offsetof(KernelArgs, n_channels)), [offsetof_outptrs] "I" (offsetof(KernelArgs, outptrs)), [offsetof_rescale] "I" (offsetof(KernelArgs, rescale_vals)) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(__ARM_FEATURE_SVE) && defined(__ARM_FP16_ARGS) && defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_avg_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_avg_generic_depthfirst.hpp new file mode 100644 index 0000000000..117eb36007 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_avg_generic_depthfirst.hpp @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstdint> + +#pragma once + +namespace arm_conv { +namespace pooling { + +void sme_fp16_nhwc_avg_generic_depthfirst_impl(const uint64_t window_cells, const uint64_t n_valid_cells, uint64_t n_channels, const __fp16 *const *const inptrs, __fp16 *outptr); + +struct sme_fp16_nhwc_avg_generic_depthfirst : IGenericDepthfirstStrategy<__fp16, __fp16> +{ + using Parent = IGenericDepthfirstStrategy<__fp16, __fp16>; + sme_fp16_nhwc_avg_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return sme_fp16_nhwc_avg_generic_depthfirst_impl; } +}; + +} // namespace pooling +} // namespace arm_conv diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_avg_generic_depthfirst/generic.cpp new file mode 100644 index 0000000000..2c1e698ade --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_avg_generic_depthfirst/generic.cpp @@ -0,0 +1,232 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if defined(ARM_COMPUTE_ENABLE_SME) + +#include <cstdint> + +namespace arm_conv { +namespace pooling { + + +void sme_fp16_nhwc_avg_generic_depthfirst_impl( + const uint64_t window_cells, + const uint64_t n_valid_cells, + uint64_t n_channels, + const __fp16 *const *const inptrs, + __fp16 *outptr +) +{ + const auto rescale_value = static_cast<__fp16>(1.0f / static_cast<float>(window_cells)); + + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "mov x28, #0x0\n" + "cnth x27\n" + "cnth x26, ALL, MUL #2\n" + "cnth x25, ALL, MUL #3\n" + "ptrue p0.b\n" + "whilelt p3.h, x28, %x[n_channels]\n" + "ld1rh { z6.h }, p0/Z, [%x[rescale_ptr]]\n" + "whilelt p2.h, x27, %x[n_channels]\n" + "whilelt p1.h, x26, %x[n_channels]\n" + "whilelt p0.h, x25, %x[n_channels]\n" + "b.none 7f\n" + "1:" // 4-vectors of channels + "lsr x24, %x[n_valid_cells], #0x2\n" + "mov z5.b, #0x0\n" + "mov z4.b, #0x0\n" + "mov x19, %x[inptrs]\n" + "mov z3.b, #0x0\n" + "mov z2.b, #0x0\n" + "cbz x24, 4f\n" + "ldp x23, x22, [x19, #0x0]\n" + "subs x24, x24, #0x1\n" + "ld1h { z1.h }, p3/Z, [x23, x28, LSL #1]\n" + "ldp x21, x20, [x19, #0x10]\n" + "add x19, x19, #0x20\n" + "ld1h { z0.h }, p3/Z, [x22, x28, LSL #1]\n" + "ld1h { z31.h }, p3/Z, [x21, x28, LSL #1]\n" + "ld1h { z30.h }, p3/Z, [x20, x28, LSL #1]\n" + "ld1h { z29.h }, p2/Z, [x23, x27, LSL #1]\n" + "ld1h { z22.h }, p2/Z, [x22, x27, LSL #1]\n" + "ld1h { z28.h }, p2/Z, [x21, x27, LSL #1]\n" + "ld1h { z18.h }, p2/Z, [x20, x27, LSL #1]\n" + "ld1h { z27.h }, p1/Z, [x23, x26, LSL #1]\n" + "ld1h { z21.h }, p1/Z, [x22, x26, LSL #1]\n" + "ld1h { z26.h }, p1/Z, [x21, x26, LSL #1]\n" + "ld1h { z17.h }, p1/Z, [x20, x26, LSL #1]\n" + "ld1h { z25.h }, p0/Z, [x23, x25, LSL #1]\n" + "ld1h { z20.h }, p0/Z, [x22, x25, LSL #1]\n" + "ld1h { z24.h }, p0/Z, [x21, x25, LSL #1]\n" + "ld1h { z16.h }, p0/Z, [x20, x25, LSL #1]\n" + "beq 3f\n" + "2:" // 4-vectors of channels: 4 inputs loop + "fadd z23.h, z1.h, z0.h\n" + "fadd z19.h, z31.h, z30.h\n" + "ldp x23, x22, [x19, #0x0]\n" + "subs x24, x24, #0x1\n" + "fadd z22.h, z29.h, z22.h\n" + "fadd z18.h, z28.h, z18.h\n" + "ldp x21, x20, [x19, #0x10]\n" + "add x19, x19, #0x20\n" + "fadd z21.h, z27.h, z21.h\n" + "fadd z17.h, z26.h, z17.h\n" + "ld1h { z1.h }, p3/Z, [x23, x28, LSL #1]\n" + "fadd z20.h, z25.h, z20.h\n" + "fadd z16.h, z24.h, z16.h\n" + "ld1h { z0.h }, p3/Z, [x22, x28, LSL #1]\n" + "fadd z19.h, z23.h, z19.h\n" + "fadd z18.h, z22.h, z18.h\n" + "ld1h { z31.h }, p3/Z, [x21, x28, LSL #1]\n" + "fadd z17.h, z21.h, z17.h\n" + "fadd z16.h, z20.h, z16.h\n" + "ld1h { z30.h }, p3/Z, [x20, x28, LSL #1]\n" + "fadd z5.h, z5.h, z19.h\n" + "fadd z4.h, z4.h, z18.h\n" + "ld1h { z29.h }, p2/Z, [x23, x27, LSL #1]\n" + "fadd z3.h, z3.h, z17.h\n" + "fadd z2.h, z2.h, z16.h\n" + "ld1h { z22.h }, p2/Z, [x22, x27, LSL #1]\n" + "ld1h { z28.h }, p2/Z, [x21, x27, LSL #1]\n" + "ld1h { z18.h }, p2/Z, [x20, x27, LSL #1]\n" + "ld1h { z27.h }, p1/Z, [x23, x26, LSL #1]\n" + "ld1h { z21.h }, p1/Z, [x22, x26, LSL #1]\n" + "ld1h { z26.h }, p1/Z, [x21, x26, LSL #1]\n" + "ld1h { z17.h }, p1/Z, [x20, x26, LSL #1]\n" + "ld1h { z25.h }, p0/Z, [x23, x25, LSL #1]\n" + "ld1h { z20.h }, p0/Z, [x22, x25, LSL #1]\n" + "ld1h { z24.h }, p0/Z, [x21, x25, LSL #1]\n" + "ld1h { z16.h }, p0/Z, [x20, x25, LSL #1]\n" + "bgt 2b\n" + "3:" // 4-vectors of channels: 4 inputs tail + "fadd z23.h, z1.h, z0.h\n" + "fadd z19.h, z31.h, z30.h\n" + "fadd z22.h, z29.h, z22.h\n" + "fadd z18.h, z28.h, z18.h\n" + "fadd z21.h, z27.h, z21.h\n" + "fadd z17.h, z26.h, z17.h\n" + "fadd z20.h, z25.h, z20.h\n" + "fadd z16.h, z24.h, z16.h\n" + "fadd z19.h, z23.h, z19.h\n" + "fadd z18.h, z22.h, z18.h\n" + "fadd z17.h, z21.h, z17.h\n" + "fadd z16.h, z20.h, z16.h\n" + "fadd z5.h, z5.h, z19.h\n" + "fadd z4.h, z4.h, z18.h\n" + "fadd z3.h, z3.h, z17.h\n" + "fadd z2.h, z2.h, z16.h\n" + "4:" // 4-vectors of channels: After loop + "ands x20, %x[n_valid_cells], #0x3\n" + "beq 6f\n" + "5:" // 4-vectors of channels: Single input loop + "ldr x23, [x19], #0x8\n" + "ld1h { z1.h }, p3/Z, [x23, x28, LSL #1]\n" + "subs x20, x20, #0x1\n" + "fadd z5.h, z5.h, z1.h\n" + "ld1h { z29.h }, p2/Z, [x23, x27, LSL #1]\n" + "fadd z4.h, z4.h, z29.h\n" + "ld1h { z27.h }, p1/Z, [x23, x26, LSL #1]\n" + "fadd z3.h, z3.h, z27.h\n" + "ld1h { z25.h }, p0/Z, [x23, x25, LSL #1]\n" + "fadd z2.h, z2.h, z25.h\n" + "bgt 5b\n" + "6:" // 4-vectors of channels: Single input loop: End + "fmul z5.h, z5.h, z6.h\n" + "fmul z4.h, z4.h, z6.h\n" + "st1h { z5.h }, p3, [%x[outptr], x28, LSL #1]\n" + "inch x28, ALL, MUL #4\n" + "fmul z3.h, z3.h, z6.h\n" + "fmul z2.h, z2.h, z6.h\n" + "st1h { z4.h }, p2, [%x[outptr], x27, LSL #1]\n" + "inch x27, ALL, MUL #4\n" + "st1h { z3.h }, p1, [%x[outptr], x26, LSL #1]\n" + "inch x26, ALL, MUL #4\n" + "st1h { z2.h }, p0, [%x[outptr], x25, LSL #1]\n" + "inch x25, ALL, MUL #4\n" + "whilelt p0.h, x25, %x[n_channels]\n" + "b.any 1b\n" + "7:" // Single vector of channels + "whilelt p3.h, x28, %x[n_channels]\n" + "b.none 14f\n" + "8:" // Single vector of channels: Loop + "lsr x24, %x[n_valid_cells], #0x2\n" + "mov z5.b, #0x0\n" + "mov x19, %x[inptrs]\n" + "cbz x24, 11f\n" + "ldp x23, x22, [x19, #0x0]\n" + "subs x24, x24, #0x1\n" + "ld1h { z1.h }, p3/Z, [x23, x28, LSL #1]\n" + "ldp x21, x20, [x19, #0x10]\n" + "add x19, x19, #0x20\n" + "ld1h { z0.h }, p3/Z, [x22, x28, LSL #1]\n" + "ld1h { z31.h }, p3/Z, [x21, x28, LSL #1]\n" + "ld1h { z30.h }, p3/Z, [x20, x28, LSL #1]\n" + "beq 10f\n" + "9:" // Single vector of channels: Loop: 4 inputs loop + "fadd z23.h, z1.h, z0.h\n" + "fadd z19.h, z31.h, z30.h\n" + "ldp x23, x22, [x19, #0x0]\n" + "subs x24, x24, #0x1\n" + "fadd z19.h, z23.h, z19.h\n" + "ldp x21, x20, [x19, #0x10]\n" + "fadd z5.h, z5.h, z19.h\n" + "add x19, x19, #0x20\n" + "ld1h { z1.h }, p3/Z, [x23, x28, LSL #1]\n" + "ld1h { z0.h }, p3/Z, [x22, x28, LSL #1]\n" + "ld1h { z31.h }, p3/Z, [x21, x28, LSL #1]\n" + "ld1h { z30.h }, p3/Z, [x20, x28, LSL #1]\n" + "bgt 9b\n" + "10:" // Single vector of channels: Loop: 4 inputs tail + "fadd z23.h, z1.h, z0.h\n" + "fadd z19.h, z31.h, z30.h\n" + "fadd z19.h, z23.h, z19.h\n" + "fadd z5.h, z5.h, z19.h\n" + "11:" // Single vector of channels: Loop: After loop + "ands x20, %x[n_valid_cells], #0x3\n" + "beq 13f\n" + "12:" // Single vector of channels: Loop: Single input loop + "ldr x23, [x19], #0x8\n" + "ld1h { z1.h }, p3/Z, [x23, x28, LSL #1]\n" + "subs x20, x20, #0x1\n" + "fadd z5.h, z5.h, z1.h\n" + "bgt 12b\n" + "13:" // Single vector of channels: Loop: Single input loop: End + "fmul z5.h, z5.h, z6.h\n" + "st1h { z5.h }, p3, [%x[outptr], x28, LSL #1]\n" + "inch x28\n" + "whilelt p3.h, x28, %x[n_channels]\n" + "b.any 8b\n" + "14:" // End + ".inst 0xd503467f // SMSTOP\n" + : + : [inptrs] "r" (inptrs), [n_channels] "r" (n_channels), [n_valid_cells] "r" (n_valid_cells), [outptr] "r" (outptr), [rescale_ptr] "r" (&rescale_value) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_max_2x2_s1_output2x2_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_max_2x2_s1_output2x2_depthfirst.hpp new file mode 100644 index 0000000000..9489c1f8da --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_max_2x2_s1_output2x2_depthfirst.hpp @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#pragma once + +namespace arm_conv { +namespace pooling { + +void sme_fp16_nhwc_max_2x2_s1_output2x2_depthfirst_impl(unsigned int, const __fp16 *const *const, __fp16 *const *const, bool, unsigned int, unsigned int, unsigned int, unsigned int); + +struct sme_fp16_nhwc_max_2x2_s1_output2x2_depthfirst : public DepthfirstStrategy<__fp16, __fp16> +{ + using Parent = DepthfirstStrategy<__fp16, __fp16>; + + const static auto pooling_type = PoolingType::MAX; + const static auto pool_rows = 2u, pool_cols = 2u; + const static auto stride_rows = 1u, stride_cols = 1u; + + sme_fp16_nhwc_max_2x2_s1_output2x2_depthfirst(const CPUInfo *) + : Parent(pool_rows, pool_cols, stride_rows, stride_cols, 2, 2) {} + + Parent::KernelType get_kernel(void) const { return sme_fp16_nhwc_max_2x2_s1_output2x2_depthfirst_impl; } +}; + +} // namespace pooling +} // namespace arm_conv diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp new file mode 100644 index 0000000000..fe2e7c834f --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + + +#include <cstddef> +#include <cstdint> + +#if defined(__ARM_FEATURE_SVE) && defined(__ARM_FP16_ARGS) && defined(ARM_COMPUTE_ENABLE_SME) + +namespace arm_conv { +namespace pooling { + +void sme_fp16_nhwc_max_2x2_s1_output2x2_depthfirst_impl( + const unsigned int n_channels, + const __fp16 *const *const inptrs, + __fp16 *const *const outptrs, + const bool exclude_padding, + const unsigned int pad_left, + const unsigned int pad_top, + const unsigned int pad_right, + const unsigned int pad_bottom +) +{ + struct KernelArgs + { + const uint64_t n_channels; + const __fp16 *const *const inptrs; + __fp16 *const *const outptrs; + KernelArgs( + unsigned int channels, + const __fp16 *const *input_ptrs, + __fp16 *const * output_ptrs, + bool, unsigned int, unsigned int, unsigned int, unsigned int + ) : n_channels(channels), + inptrs(input_ptrs), + outptrs(output_ptrs) + { + } + }; + + const KernelArgs args(n_channels, inptrs, outptrs, exclude_padding, + pad_left, pad_top, pad_right, pad_bottom); + + __asm__ __volatile__( + "ldr x20, [%x[args], %[offsetof_outptrs]]\n" + ".inst 0xd503477f // SMSTART ZA\n" + "mov x14, #0x0\n" + "ptrue p2.b\n" + "ldr x19, [%x[args], %[offsetof_inptrs]]\n" + "mov x13, #0x0\n" + "ldr x12, [%x[args], %[offsetof_n_channels]]\n" + "whilelt p1.h, x14, x12\n" + "ldp x11, x10, [x20, #0x0]\n" + "ldp x9, x28, [x20, #0x10]\n" + "ldp x27, x26, [x19, #0x0]\n" + "ld1h { z29.h }, p1/Z, [x26, x14, LSL #1]\n" + "ldp x25, x24, [x19, #0x10]\n" + "ld1h { z28.h }, p1/Z, [x24, x14, LSL #1]\n" + "ldp x23, x22, [x19, #0x20]\n" + "ld1h { z27.h }, p1/Z, [x23, x14, LSL #1]\n" + "ldp x21, x20, [x19, #0x30]\n" + "ld1h { z26.h }, p1/Z, [x20, x14, LSL #1]\n" + "ldr x19, [x19, #0x40]\n" + "ld1h { z20.h }, p1/Z, [x27, x14, LSL #1]\n" + "ld1h { z25.h }, p1/Z, [x22, x14, LSL #1]\n" + "ld1h { z24.h }, p1/Z, [x25, x14, LSL #1]\n" + "ld1h { z23.h }, p1/Z, [x21, x14, LSL #1]\n" + "ld1h { z19.h }, p1/Z, [x19, x14, LSL #1]\n" + "incw x14\n" + "whilelt p1.h, x14, x12\n" + "b.none 2f\n" + "1:" // Vector: Loop + "movprfx z22, z29\n fmax z22.h, p2/M, z22.h, z27.h\n" + "movprfx z21, z27\n fmax z21.h, p2/M, z21.h, z26.h\n" + "ld1h { z29.h }, p1/Z, [x26, x14, LSL #1]\n" + "whilelt p0.h, x13, x12\n" + "movprfx z18, z28\n fmax z18.h, p2/M, z18.h, z20.h\n" + "movprfx z20, z25\n fmax z20.h, p2/M, z20.h, z24.h\n" + "ld1h { z27.h }, p1/Z, [x23, x14, LSL #1]\n" + "movprfx z17, z23\n fmax z17.h, p2/M, z17.h, z28.h\n" + "movprfx z16, z25\n fmax z16.h, p2/M, z16.h, z19.h\n" + "ld1h { z26.h }, p1/Z, [x20, x14, LSL #1]\n" + "ld1h { z28.h }, p1/Z, [x24, x14, LSL #1]\n" + "movprfx z19, z18\n fmax z19.h, p2/M, z19.h, z22.h\n" + "movprfx z18, z22\n fmax z18.h, p2/M, z18.h, z20.h\n" + "ld1h { z20.h }, p1/Z, [x27, x14, LSL #1]\n" + "fmax z17.h, p2/M, z17.h, z21.h\n" + "fmax z16.h, p2/M, z16.h, z21.h\n" + "ld1h { z25.h }, p1/Z, [x22, x14, LSL #1]\n" + "st1h { z19.h }, p0, [x11, x13, LSL #1]\n" + "ld1h { z24.h }, p1/Z, [x25, x14, LSL #1]\n" + "st1h { z18.h }, p0, [x10, x13, LSL #1]\n" + "ld1h { z23.h }, p1/Z, [x21, x14, LSL #1]\n" + "st1h { z17.h }, p0, [x9, x13, LSL #1]\n" + "ld1h { z19.h }, p1/Z, [x19, x14, LSL #1]\n" + "incw x14\n" + "whilelt p1.h, x14, x12\n" + "st1h { z16.h }, p0, [x28, x13, LSL #1]\n" + "incw x13\n" + "b.any 1b\n" + "2:" // Vector: Tail + "movprfx z22, z29\n fmax z22.h, p2/M, z22.h, z27.h\n" + "movprfx z21, z27\n fmax z21.h, p2/M, z21.h, z26.h\n" + "whilelt p0.h, x13, x12\n" + "movprfx z18, z28\n fmax z18.h, p2/M, z18.h, z20.h\n" + "movprfx z20, z25\n fmax z20.h, p2/M, z20.h, z24.h\n" + "movprfx z17, z23\n fmax z17.h, p2/M, z17.h, z28.h\n" + "movprfx z16, z25\n fmax z16.h, p2/M, z16.h, z19.h\n" + "movprfx z19, z18\n fmax z19.h, p2/M, z19.h, z22.h\n" + "movprfx z18, z22\n fmax z18.h, p2/M, z18.h, z20.h\n" + "st1h { z19.h }, p0, [x11, x13, LSL #1]\n" + "fmax z17.h, p2/M, z17.h, z21.h\n" + "fmax z16.h, p2/M, z16.h, z21.h\n" + "st1h { z18.h }, p0, [x10, x13, LSL #1]\n" + "st1h { z17.h }, p0, [x9, x13, LSL #1]\n" + "st1h { z16.h }, p0, [x28, x13, LSL #1]\n" + ".inst 0xd503467f // SMSTOP\n" + : + : [args] "r" (&args), [offsetof_inptrs] "I" (offsetof(KernelArgs, inptrs)), [offsetof_n_channels] "I" (offsetof(KernelArgs, n_channels)), [offsetof_outptrs] "I" (offsetof(KernelArgs, outptrs)) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x9", "x10", "x11", "x12", "x13", "x14", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(__ARM_FEATURE_SVE) && defined(__ARM_FP16_ARGS) && defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_max_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_max_generic_depthfirst.hpp new file mode 100644 index 0000000000..33ff1f2154 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_max_generic_depthfirst.hpp @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstdint> + +#pragma once + +namespace arm_conv { +namespace pooling { + +void sme_fp16_nhwc_max_generic_depthfirst_impl(const uint64_t, const uint64_t n_valid_cells, uint64_t n_channels, const __fp16 *const *const inptrs, __fp16 *outptr); + +struct sme_fp16_nhwc_max_generic_depthfirst : IGenericDepthfirstStrategy<__fp16, __fp16> +{ + using Parent = IGenericDepthfirstStrategy<__fp16, __fp16>; + sme_fp16_nhwc_max_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return sme_fp16_nhwc_max_generic_depthfirst_impl; } +}; + +} // namespace pooling +} // namespace arm_conv diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_max_generic_depthfirst/generic.cpp new file mode 100644 index 0000000000..1bb27e39a3 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_max_generic_depthfirst/generic.cpp @@ -0,0 +1,224 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if defined(ARM_COMPUTE_ENABLE_SME) + +#include <cstdint> + +namespace arm_conv { +namespace pooling { + + +void sme_fp16_nhwc_max_generic_depthfirst_impl( + const uint64_t, + const uint64_t n_valid_cells, + uint64_t n_channels, + const __fp16 *const *const inptrs, + __fp16 *outptr +) +{ + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "mov x28, #0x0\n" + "cnth x27\n" + "cnth x26, ALL, MUL #2\n" + "cnth x25, ALL, MUL #3\n" + "whilelt p4.h, x28, %x[n_channels]\n" + "whilelt p3.h, x27, %x[n_channels]\n" + "whilelt p2.h, x26, %x[n_channels]\n" + "whilelt p1.h, x25, %x[n_channels]\n" + "ptrue p0.b\n" + "b.none 7f\n" + "1:" // 4-vectors of channels + "lsr x24, %x[n_valid_cells], #0x2\n" + "mov z4.h, #0xfc00\n" + "mov z3.h, #0xfc00\n" + "mov x19, %x[inptrs]\n" + "mov z2.h, #0xfc00\n" + "mov z1.h, #0xfc00\n" + "cbz x24, 4f\n" + "ldp x23, x22, [x19, #0x0]\n" + "subs x24, x24, #0x1\n" + "ld1h { z0.h }, p4/Z, [x23, x28, LSL #1]\n" + "ldp x21, x20, [x19, #0x10]\n" + "add x19, x19, #0x20\n" + "ld1h { z31.h }, p4/Z, [x22, x28, LSL #1]\n" + "ld1h { z23.h }, p4/Z, [x21, x28, LSL #1]\n" + "ld1h { z30.h }, p4/Z, [x20, x28, LSL #1]\n" + "ld1h { z18.h }, p3/Z, [x23, x27, LSL #1]\n" + "ld1h { z29.h }, p3/Z, [x22, x27, LSL #1]\n" + "ld1h { z22.h }, p3/Z, [x21, x27, LSL #1]\n" + "ld1h { z28.h }, p3/Z, [x20, x27, LSL #1]\n" + "ld1h { z17.h }, p2/Z, [x23, x26, LSL #1]\n" + "ld1h { z27.h }, p2/Z, [x22, x26, LSL #1]\n" + "ld1h { z21.h }, p2/Z, [x21, x26, LSL #1]\n" + "ld1h { z26.h }, p2/Z, [x20, x26, LSL #1]\n" + "ld1h { z16.h }, p1/Z, [x23, x25, LSL #1]\n" + "ld1h { z25.h }, p1/Z, [x22, x25, LSL #1]\n" + "ld1h { z20.h }, p1/Z, [x21, x25, LSL #1]\n" + "ld1h { z24.h }, p1/Z, [x20, x25, LSL #1]\n" + "beq 3f\n" + "2:" // 4-vectors of channels: 4 inputs loop + "movprfx z19, z0\n fmax z19.h, p0/M, z19.h, z31.h\n" + "fmax z23.h, p0/M, z23.h, z30.h\n" + "ldp x23, x22, [x19, #0x0]\n" + "subs x24, x24, #0x1\n" + "fmax z18.h, p0/M, z18.h, z29.h\n" + "fmax z22.h, p0/M, z22.h, z28.h\n" + "ldp x21, x20, [x19, #0x10]\n" + "add x19, x19, #0x20\n" + "fmax z17.h, p0/M, z17.h, z27.h\n" + "fmax z21.h, p0/M, z21.h, z26.h\n" + "ld1h { z0.h }, p4/Z, [x23, x28, LSL #1]\n" + "fmax z16.h, p0/M, z16.h, z25.h\n" + "fmax z20.h, p0/M, z20.h, z24.h\n" + "ld1h { z31.h }, p4/Z, [x22, x28, LSL #1]\n" + "fmax z19.h, p0/M, z19.h, z23.h\n" + "fmax z18.h, p0/M, z18.h, z22.h\n" + "ld1h { z23.h }, p4/Z, [x21, x28, LSL #1]\n" + "fmax z17.h, p0/M, z17.h, z21.h\n" + "fmax z16.h, p0/M, z16.h, z20.h\n" + "ld1h { z30.h }, p4/Z, [x20, x28, LSL #1]\n" + "fmax z4.h, p0/M, z4.h, z19.h\n" + "fmax z3.h, p0/M, z3.h, z18.h\n" + "ld1h { z18.h }, p3/Z, [x23, x27, LSL #1]\n" + "fmax z2.h, p0/M, z2.h, z17.h\n" + "fmax z1.h, p0/M, z1.h, z16.h\n" + "ld1h { z29.h }, p3/Z, [x22, x27, LSL #1]\n" + "ld1h { z22.h }, p3/Z, [x21, x27, LSL #1]\n" + "ld1h { z28.h }, p3/Z, [x20, x27, LSL #1]\n" + "ld1h { z17.h }, p2/Z, [x23, x26, LSL #1]\n" + "ld1h { z27.h }, p2/Z, [x22, x26, LSL #1]\n" + "ld1h { z21.h }, p2/Z, [x21, x26, LSL #1]\n" + "ld1h { z26.h }, p2/Z, [x20, x26, LSL #1]\n" + "ld1h { z16.h }, p1/Z, [x23, x25, LSL #1]\n" + "ld1h { z25.h }, p1/Z, [x22, x25, LSL #1]\n" + "ld1h { z20.h }, p1/Z, [x21, x25, LSL #1]\n" + "ld1h { z24.h }, p1/Z, [x20, x25, LSL #1]\n" + "bgt 2b\n" + "3:" // 4-vectors of channels: 4 inputs tail + "movprfx z19, z0\n fmax z19.h, p0/M, z19.h, z31.h\n" + "fmax z23.h, p0/M, z23.h, z30.h\n" + "fmax z18.h, p0/M, z18.h, z29.h\n" + "fmax z22.h, p0/M, z22.h, z28.h\n" + "fmax z17.h, p0/M, z17.h, z27.h\n" + "fmax z21.h, p0/M, z21.h, z26.h\n" + "fmax z16.h, p0/M, z16.h, z25.h\n" + "fmax z20.h, p0/M, z20.h, z24.h\n" + "fmax z19.h, p0/M, z19.h, z23.h\n" + "fmax z18.h, p0/M, z18.h, z22.h\n" + "fmax z17.h, p0/M, z17.h, z21.h\n" + "fmax z16.h, p0/M, z16.h, z20.h\n" + "fmax z4.h, p0/M, z4.h, z19.h\n" + "fmax z3.h, p0/M, z3.h, z18.h\n" + "fmax z2.h, p0/M, z2.h, z17.h\n" + "fmax z1.h, p0/M, z1.h, z16.h\n" + "4:" // 4-vectors of channels: After loop + "ands x20, %x[n_valid_cells], #0x3\n" + "beq 6f\n" + "5:" // 4-vectors of channels: Single input loop + "ldr x23, [x19], #0x8\n" + "ld1h { z0.h }, p4/Z, [x23, x28, LSL #1]\n" + "subs x20, x20, #0x1\n" + "fmax z4.h, p0/M, z4.h, z0.h\n" + "ld1h { z18.h }, p3/Z, [x23, x27, LSL #1]\n" + "fmax z3.h, p0/M, z3.h, z18.h\n" + "ld1h { z17.h }, p2/Z, [x23, x26, LSL #1]\n" + "fmax z2.h, p0/M, z2.h, z17.h\n" + "ld1h { z16.h }, p1/Z, [x23, x25, LSL #1]\n" + "fmax z1.h, p0/M, z1.h, z16.h\n" + "bgt 5b\n" + "6:" // 4-vectors of channels: Single input loop: End + "st1h { z4.h }, p4, [%x[outptr], x28, LSL #1]\n" + "inch x28, ALL, MUL #4\n" + "st1h { z3.h }, p3, [%x[outptr], x27, LSL #1]\n" + "inch x27, ALL, MUL #4\n" + "st1h { z2.h }, p2, [%x[outptr], x26, LSL #1]\n" + "inch x26, ALL, MUL #4\n" + "st1h { z1.h }, p1, [%x[outptr], x25, LSL #1]\n" + "inch x25, ALL, MUL #4\n" + "whilelt p1.h, x25, %x[n_channels]\n" + "b.any 1b\n" + "7:" // Single vector of channels + "whilelt p4.h, x28, %x[n_channels]\n" + "b.none 14f\n" + "8:" // Single vector of channels: Loop + "lsr x24, %x[n_valid_cells], #0x2\n" + "mov z4.h, #0xfc00\n" + "mov x19, %x[inptrs]\n" + "cbz x24, 11f\n" + "ldp x23, x22, [x19, #0x0]\n" + "subs x24, x24, #0x1\n" + "ld1h { z0.h }, p4/Z, [x23, x28, LSL #1]\n" + "ldp x21, x20, [x19, #0x10]\n" + "add x19, x19, #0x20\n" + "ld1h { z31.h }, p4/Z, [x22, x28, LSL #1]\n" + "ld1h { z23.h }, p4/Z, [x21, x28, LSL #1]\n" + "ld1h { z30.h }, p4/Z, [x20, x28, LSL #1]\n" + "beq 10f\n" + "9:" // Single vector of channels: Loop: 4 inputs loop + "movprfx z19, z0\n fmax z19.h, p0/M, z19.h, z31.h\n" + "fmax z23.h, p0/M, z23.h, z30.h\n" + "ldp x23, x22, [x19, #0x0]\n" + "subs x24, x24, #0x1\n" + "fmax z19.h, p0/M, z19.h, z23.h\n" + "ldp x21, x20, [x19, #0x10]\n" + "fmax z4.h, p0/M, z4.h, z19.h\n" + "add x19, x19, #0x20\n" + "ld1h { z0.h }, p4/Z, [x23, x28, LSL #1]\n" + "ld1h { z31.h }, p4/Z, [x22, x28, LSL #1]\n" + "ld1h { z23.h }, p4/Z, [x21, x28, LSL #1]\n" + "ld1h { z30.h }, p4/Z, [x20, x28, LSL #1]\n" + "bgt 9b\n" + "10:" // Single vector of channels: Loop: 4 inputs tail + "movprfx z19, z0\n fmax z19.h, p0/M, z19.h, z31.h\n" + "fmax z23.h, p0/M, z23.h, z30.h\n" + "fmax z19.h, p0/M, z19.h, z23.h\n" + "fmax z4.h, p0/M, z4.h, z19.h\n" + "11:" // Single vector of channels: Loop: After loop + "ands x20, %x[n_valid_cells], #0x3\n" + "beq 13f\n" + "12:" // Single vector of channels: Loop: Single input loop + "ldr x23, [x19], #0x8\n" + "ld1h { z0.h }, p4/Z, [x23, x28, LSL #1]\n" + "subs x20, x20, #0x1\n" + "fmax z4.h, p0/M, z4.h, z0.h\n" + "bgt 12b\n" + "13:" // Single vector of channels: Loop: Single input loop: End + "st1h { z4.h }, p4, [%x[outptr], x28, LSL #1]\n" + "inch x28\n" + "whilelt p4.h, x28, %x[n_channels]\n" + "b.any 8b\n" + "14:" // End + ".inst 0xd503467f // SMSTOP\n" + : + : [inptrs] "r" (inptrs), [n_channels] "r" (n_channels), [n_valid_cells] "r" (n_valid_cells), [outptr] "r" (outptr) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp new file mode 100644 index 0000000000..fa1b441371 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#pragma once + +namespace arm_conv { +namespace pooling { + +void sme_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst_impl(unsigned int, const float *const *const, float *const *const, bool, unsigned int, unsigned int, unsigned int, unsigned int); + +struct sme_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst : public DepthfirstStrategy<float, float> +{ + using Parent = DepthfirstStrategy<float, float>; + + const static auto pooling_type = PoolingType::AVERAGE; + const static auto pool_rows = 3u, pool_cols = 3u; + const static auto stride_rows = 1u, stride_cols = 1u; + + sme_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst(const CPUInfo *) + : Parent(pool_rows, pool_cols, stride_rows, stride_cols, 2, 2) {} + + Parent::KernelType get_kernel(void) const { return sme_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst_impl; } +}; + +} // namespace pooling +} // namespace arm_conv diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp new file mode 100644 index 0000000000..602ef59159 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp @@ -0,0 +1,209 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <algorithm> +#include <cstddef> +#include <cstdint> + +#if defined(__ARM_FEATURE_SVE) && defined(ARM_COMPUTE_ENABLE_SME) + +namespace arm_conv { +namespace pooling { + +void sme_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst_impl( + const unsigned int n_channels, + const float *const *const inptrs, + float *const *const outptrs, + const bool exclude_padding, + const unsigned int pad_left, + const unsigned int pad_top, + const unsigned int pad_right, + const unsigned int pad_bottom +) +{ + struct KernelArgs + { + const uint64_t n_channels; + const float *const *const inptrs; + float *const *const outptrs; + float rescale_vals[4]; + + KernelArgs( + unsigned int channels, + const float *const *input_ptrs, + float *const * output_ptrs, + bool exclude_padding, unsigned int pad_left, unsigned int pad_top, unsigned int pad_right, unsigned int pad_bottom + ) : n_channels(channels), + inptrs(input_ptrs), + outptrs(output_ptrs) + { + for (unsigned int i = 0; i < 2; i++) + { + const int start_i = 1*i - static_cast<int>(pad_top); + const int end_i = std::min<int>(start_i + 3, 4 - pad_top - pad_bottom); + const int valid_rows = end_i - std::max<int>(0, start_i); + + for (unsigned int j = 0; j < 2; j++) + { + const int start_j = 1*j - static_cast<int>(pad_left); + const int end_j = std::min<int>(start_j + 3, 4 - pad_left - pad_right); + const int valid_cols = end_j - std::max<int>(0, start_j); + + rescale_vals[i*2 + j] = static_cast<float>(1.0f / static_cast<float>( + exclude_padding ? valid_rows * valid_cols : 9 + )); + } + } + } + }; + + const KernelArgs args(n_channels, inptrs, outptrs, exclude_padding, + pad_left, pad_top, pad_right, pad_bottom); + + __asm__ __volatile__( + "ldr x20, [%x[args], %[offsetof_outptrs]]\n" + ".inst 0xd503477f // SMSTART ZA\n" + "mov x4, #0x0\n" + "mov x19, #0x4\n" + "ldr x5, [%x[args], %[offsetof_inptrs]]\n" + "whilelt p0.s, XZR, x19\n" + "add x19, %x[args], %[offsetof_rescale]\n" + "ld1rqw { z4.s }, p0/Z, [x19]\n" + "ldr x6, [%x[args], %[offsetof_n_channels]]\n" + "whilelt p1.s, x4, x6\n" + "mov x7, #0x0\n" + "ldp x8, x17, [x20, #0x0]\n" + "ldp x16, x15, [x20, #0x10]\n" + "ldp x14, x13, [x5, #0x0]\n" + "ld1w { z3.s }, p1/Z, [x13, x4, LSL #2]\n" + "ldp x12, x11, [x5, #0x10]\n" + "ld1w { z2.s }, p1/Z, [x12, x4, LSL #2]\n" + "ldp x10, x9, [x5, #0x20]\n" + "ld1w { z1.s }, p1/Z, [x9, x4, LSL #2]\n" + "ldp x28, x27, [x5, #0x30]\n" + "ld1w { z0.s }, p1/Z, [x28, x4, LSL #2]\n" + "ldp x26, x25, [x5, #0x40]\n" + "ld1w { z31.s }, p1/Z, [x25, x4, LSL #2]\n" + "ldp x24, x23, [x5, #0x50]\n" + "ld1w { z30.s }, p1/Z, [x24, x4, LSL #2]\n" + "ldp x22, x21, [x5, #0x60]\n" + "ld1w { z29.s }, p1/Z, [x10, x4, LSL #2]\n" + "ldp x20, x19, [x5, #0x70]\n" + "ld1w { z28.s }, p1/Z, [x26, x4, LSL #2]\n" + "ld1w { z27.s }, p1/Z, [x27, x4, LSL #2]\n" + "ld1w { z22.s }, p1/Z, [x23, x4, LSL #2]\n" + "ld1w { z21.s }, p1/Z, [x21, x4, LSL #2]\n" + "ld1w { z20.s }, p1/Z, [x20, x4, LSL #2]\n" + "ld1w { z26.s }, p1/Z, [x14, x4, LSL #2]\n" + "ld1w { z25.s }, p1/Z, [x11, x4, LSL #2]\n" + "ld1w { z24.s }, p1/Z, [x22, x4, LSL #2]\n" + "ld1w { z23.s }, p1/Z, [x19, x4, LSL #2]\n" + "incw x4\n" + "whilelt p1.s, x4, x6\n" + "b.none 2f\n" + "1:" // Vector: Loop + "fadd z17.s, z1.s, z0.s\n" + "fadd z16.s, z31.s, z30.s\n" + "ld1w { z1.s }, p1/Z, [x9, x4, LSL #2]\n" + "whilelt p0.s, x7, x6\n" + "fadd z19.s, z17.s, z16.s\n" + "fadd z18.s, z3.s, z2.s\n" + "ld1w { z0.s }, p1/Z, [x28, x4, LSL #2]\n" + "fadd z17.s, z29.s, z28.s\n" + "fadd z22.s, z27.s, z22.s\n" + "ld1w { z31.s }, p1/Z, [x25, x4, LSL #2]\n" + "fadd z16.s, z21.s, z20.s\n" + "fadd z21.s, z18.s, z19.s\n" + "ld1w { z30.s }, p1/Z, [x24, x4, LSL #2]\n" + "fadd z20.s, z16.s, z19.s\n" + "fadd z19.s, z26.s, z17.s\n" + "ld1w { z3.s }, p1/Z, [x13, x4, LSL #2]\n" + "fadd z18.s, z25.s, z22.s\n" + "fadd z17.s, z24.s, z17.s\n" + "ld1w { z2.s }, p1/Z, [x12, x4, LSL #2]\n" + "fadd z16.s, z23.s, z22.s\n" + "fadd z19.s, z19.s, z21.s\n" + "ld1w { z29.s }, p1/Z, [x10, x4, LSL #2]\n" + "fadd z18.s, z18.s, z21.s\n" + "fadd z17.s, z17.s, z20.s\n" + "ld1w { z28.s }, p1/Z, [x26, x4, LSL #2]\n" + "fadd z16.s, z16.s, z20.s\n" + "ld1w { z27.s }, p1/Z, [x27, x4, LSL #2]\n" + "fmul z19.s, z19.s, z4.s[0]\n" + "ld1w { z22.s }, p1/Z, [x23, x4, LSL #2]\n" + "fmul z18.s, z18.s, z4.s[1]\n" + "fmul z17.s, z17.s, z4.s[2]\n" + "ld1w { z21.s }, p1/Z, [x21, x4, LSL #2]\n" + "fmul z16.s, z16.s, z4.s[3]\n" + "st1w { z19.s }, p0, [x8, x7, LSL #2]\n" + "ld1w { z20.s }, p1/Z, [x20, x4, LSL #2]\n" + "st1w { z18.s }, p0, [x17, x7, LSL #2]\n" + "ld1w { z26.s }, p1/Z, [x14, x4, LSL #2]\n" + "st1w { z17.s }, p0, [x16, x7, LSL #2]\n" + "ld1w { z25.s }, p1/Z, [x11, x4, LSL #2]\n" + "st1w { z16.s }, p0, [x15, x7, LSL #2]\n" + "incw x7\n" + "ld1w { z24.s }, p1/Z, [x22, x4, LSL #2]\n" + "ld1w { z23.s }, p1/Z, [x19, x4, LSL #2]\n" + "incw x4\n" + "whilelt p1.s, x4, x6\n" + "b.any 1b\n" + "2:" // Vector: Tail + "fadd z17.s, z1.s, z0.s\n" + "fadd z16.s, z31.s, z30.s\n" + "whilelt p0.s, x7, x6\n" + "fadd z19.s, z17.s, z16.s\n" + "fadd z18.s, z3.s, z2.s\n" + "fadd z17.s, z29.s, z28.s\n" + "fadd z22.s, z27.s, z22.s\n" + "fadd z16.s, z21.s, z20.s\n" + "fadd z21.s, z18.s, z19.s\n" + "fadd z20.s, z16.s, z19.s\n" + "fadd z19.s, z26.s, z17.s\n" + "fadd z18.s, z25.s, z22.s\n" + "fadd z17.s, z24.s, z17.s\n" + "fadd z16.s, z23.s, z22.s\n" + "fadd z19.s, z19.s, z21.s\n" + "fadd z18.s, z18.s, z21.s\n" + "fadd z17.s, z17.s, z20.s\n" + "fadd z16.s, z16.s, z20.s\n" + "fmul z19.s, z19.s, z4.s[0]\n" + "st1w { z19.s }, p0, [x8, x7, LSL #2]\n" + "fmul z18.s, z18.s, z4.s[1]\n" + "fmul z17.s, z17.s, z4.s[2]\n" + "st1w { z18.s }, p0, [x17, x7, LSL #2]\n" + "fmul z16.s, z16.s, z4.s[3]\n" + "st1w { z17.s }, p0, [x16, x7, LSL #2]\n" + "st1w { z16.s }, p0, [x15, x7, LSL #2]\n" + ".inst 0xd503467f // SMSTOP\n" + : + : [args] "r" (&args), [offsetof_inptrs] "I" (offsetof(KernelArgs, inptrs)), [offsetof_n_channels] "I" (offsetof(KernelArgs, n_channels)), [offsetof_outptrs] "I" (offsetof(KernelArgs, outptrs)), [offsetof_rescale] "I" (offsetof(KernelArgs, rescale_vals)) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(__ARM_FEATURE_SVE) && defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_avg_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_avg_generic_depthfirst.hpp new file mode 100644 index 0000000000..814c89ca23 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_avg_generic_depthfirst.hpp @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstdint> + +#pragma once + +namespace arm_conv { +namespace pooling { + +void sme_fp32_nhwc_avg_generic_depthfirst_impl(const uint64_t window_cells, const uint64_t n_valid_cells, uint64_t n_channels, const float *const *const inptrs, float *outptr); + +struct sme_fp32_nhwc_avg_generic_depthfirst : IGenericDepthfirstStrategy<float, float> +{ + using Parent = IGenericDepthfirstStrategy<float, float>; + sme_fp32_nhwc_avg_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return sme_fp32_nhwc_avg_generic_depthfirst_impl; } +}; + +} // namespace pooling +} // namespace arm_conv diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_avg_generic_depthfirst/generic.cpp new file mode 100644 index 0000000000..08630dba05 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_avg_generic_depthfirst/generic.cpp @@ -0,0 +1,232 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if defined(ARM_COMPUTE_ENABLE_SME) + +#include <cstdint> + +namespace arm_conv { +namespace pooling { + + +void sme_fp32_nhwc_avg_generic_depthfirst_impl( + const uint64_t window_cells, + const uint64_t n_valid_cells, + uint64_t n_channels, + const float *const *const inptrs, + float *outptr +) +{ + const auto rescale_value = static_cast<float>(1.0f / static_cast<float>(window_cells)); + + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "mov x28, #0x0\n" + "cntw x27\n" + "cntw x26, ALL, MUL #2\n" + "cntw x25, ALL, MUL #3\n" + "ptrue p0.b\n" + "whilelt p3.s, x28, %x[n_channels]\n" + "ld1rw { z6.s }, p0/Z, [%x[rescale_ptr]]\n" + "whilelt p2.s, x27, %x[n_channels]\n" + "whilelt p1.s, x26, %x[n_channels]\n" + "whilelt p0.s, x25, %x[n_channels]\n" + "b.none 7f\n" + "1:" // 4-vectors of channels + "lsr x24, %x[n_valid_cells], #0x2\n" + "mov z5.b, #0x0\n" + "mov z4.b, #0x0\n" + "mov x19, %x[inptrs]\n" + "mov z3.b, #0x0\n" + "mov z2.b, #0x0\n" + "cbz x24, 4f\n" + "ldp x23, x22, [x19, #0x0]\n" + "subs x24, x24, #0x1\n" + "ld1w { z1.s }, p3/Z, [x23, x28, LSL #2]\n" + "ldp x21, x20, [x19, #0x10]\n" + "add x19, x19, #0x20\n" + "ld1w { z0.s }, p3/Z, [x22, x28, LSL #2]\n" + "ld1w { z31.s }, p3/Z, [x21, x28, LSL #2]\n" + "ld1w { z30.s }, p3/Z, [x20, x28, LSL #2]\n" + "ld1w { z29.s }, p2/Z, [x23, x27, LSL #2]\n" + "ld1w { z22.s }, p2/Z, [x22, x27, LSL #2]\n" + "ld1w { z28.s }, p2/Z, [x21, x27, LSL #2]\n" + "ld1w { z18.s }, p2/Z, [x20, x27, LSL #2]\n" + "ld1w { z27.s }, p1/Z, [x23, x26, LSL #2]\n" + "ld1w { z21.s }, p1/Z, [x22, x26, LSL #2]\n" + "ld1w { z26.s }, p1/Z, [x21, x26, LSL #2]\n" + "ld1w { z17.s }, p1/Z, [x20, x26, LSL #2]\n" + "ld1w { z25.s }, p0/Z, [x23, x25, LSL #2]\n" + "ld1w { z20.s }, p0/Z, [x22, x25, LSL #2]\n" + "ld1w { z24.s }, p0/Z, [x21, x25, LSL #2]\n" + "ld1w { z16.s }, p0/Z, [x20, x25, LSL #2]\n" + "beq 3f\n" + "2:" // 4-vectors of channels: 4 inputs loop + "fadd z23.s, z1.s, z0.s\n" + "fadd z19.s, z31.s, z30.s\n" + "ldp x23, x22, [x19, #0x0]\n" + "subs x24, x24, #0x1\n" + "fadd z22.s, z29.s, z22.s\n" + "fadd z18.s, z28.s, z18.s\n" + "ldp x21, x20, [x19, #0x10]\n" + "add x19, x19, #0x20\n" + "fadd z21.s, z27.s, z21.s\n" + "fadd z17.s, z26.s, z17.s\n" + "ld1w { z1.s }, p3/Z, [x23, x28, LSL #2]\n" + "fadd z20.s, z25.s, z20.s\n" + "fadd z16.s, z24.s, z16.s\n" + "ld1w { z0.s }, p3/Z, [x22, x28, LSL #2]\n" + "fadd z19.s, z23.s, z19.s\n" + "fadd z18.s, z22.s, z18.s\n" + "ld1w { z31.s }, p3/Z, [x21, x28, LSL #2]\n" + "fadd z17.s, z21.s, z17.s\n" + "fadd z16.s, z20.s, z16.s\n" + "ld1w { z30.s }, p3/Z, [x20, x28, LSL #2]\n" + "fadd z5.s, z5.s, z19.s\n" + "fadd z4.s, z4.s, z18.s\n" + "ld1w { z29.s }, p2/Z, [x23, x27, LSL #2]\n" + "fadd z3.s, z3.s, z17.s\n" + "fadd z2.s, z2.s, z16.s\n" + "ld1w { z22.s }, p2/Z, [x22, x27, LSL #2]\n" + "ld1w { z28.s }, p2/Z, [x21, x27, LSL #2]\n" + "ld1w { z18.s }, p2/Z, [x20, x27, LSL #2]\n" + "ld1w { z27.s }, p1/Z, [x23, x26, LSL #2]\n" + "ld1w { z21.s }, p1/Z, [x22, x26, LSL #2]\n" + "ld1w { z26.s }, p1/Z, [x21, x26, LSL #2]\n" + "ld1w { z17.s }, p1/Z, [x20, x26, LSL #2]\n" + "ld1w { z25.s }, p0/Z, [x23, x25, LSL #2]\n" + "ld1w { z20.s }, p0/Z, [x22, x25, LSL #2]\n" + "ld1w { z24.s }, p0/Z, [x21, x25, LSL #2]\n" + "ld1w { z16.s }, p0/Z, [x20, x25, LSL #2]\n" + "bgt 2b\n" + "3:" // 4-vectors of channels: 4 inputs tail + "fadd z23.s, z1.s, z0.s\n" + "fadd z19.s, z31.s, z30.s\n" + "fadd z22.s, z29.s, z22.s\n" + "fadd z18.s, z28.s, z18.s\n" + "fadd z21.s, z27.s, z21.s\n" + "fadd z17.s, z26.s, z17.s\n" + "fadd z20.s, z25.s, z20.s\n" + "fadd z16.s, z24.s, z16.s\n" + "fadd z19.s, z23.s, z19.s\n" + "fadd z18.s, z22.s, z18.s\n" + "fadd z17.s, z21.s, z17.s\n" + "fadd z16.s, z20.s, z16.s\n" + "fadd z5.s, z5.s, z19.s\n" + "fadd z4.s, z4.s, z18.s\n" + "fadd z3.s, z3.s, z17.s\n" + "fadd z2.s, z2.s, z16.s\n" + "4:" // 4-vectors of channels: After loop + "ands x20, %x[n_valid_cells], #0x3\n" + "beq 6f\n" + "5:" // 4-vectors of channels: Single input loop + "ldr x23, [x19], #0x8\n" + "ld1w { z1.s }, p3/Z, [x23, x28, LSL #2]\n" + "subs x20, x20, #0x1\n" + "fadd z5.s, z5.s, z1.s\n" + "ld1w { z29.s }, p2/Z, [x23, x27, LSL #2]\n" + "fadd z4.s, z4.s, z29.s\n" + "ld1w { z27.s }, p1/Z, [x23, x26, LSL #2]\n" + "fadd z3.s, z3.s, z27.s\n" + "ld1w { z25.s }, p0/Z, [x23, x25, LSL #2]\n" + "fadd z2.s, z2.s, z25.s\n" + "bgt 5b\n" + "6:" // 4-vectors of channels: Single input loop: End + "fmul z5.s, z5.s, z6.s\n" + "fmul z4.s, z4.s, z6.s\n" + "st1w { z5.s }, p3, [%x[outptr], x28, LSL #2]\n" + "incw x28, ALL, MUL #4\n" + "fmul z3.s, z3.s, z6.s\n" + "fmul z2.s, z2.s, z6.s\n" + "st1w { z4.s }, p2, [%x[outptr], x27, LSL #2]\n" + "incw x27, ALL, MUL #4\n" + "st1w { z3.s }, p1, [%x[outptr], x26, LSL #2]\n" + "incw x26, ALL, MUL #4\n" + "st1w { z2.s }, p0, [%x[outptr], x25, LSL #2]\n" + "incw x25, ALL, MUL #4\n" + "whilelt p0.s, x25, %x[n_channels]\n" + "b.any 1b\n" + "7:" // Single vector of channels + "whilelt p3.s, x28, %x[n_channels]\n" + "b.none 14f\n" + "8:" // Single vector of channels: Loop + "lsr x24, %x[n_valid_cells], #0x2\n" + "mov z5.b, #0x0\n" + "mov x19, %x[inptrs]\n" + "cbz x24, 11f\n" + "ldp x23, x22, [x19, #0x0]\n" + "subs x24, x24, #0x1\n" + "ld1w { z1.s }, p3/Z, [x23, x28, LSL #2]\n" + "ldp x21, x20, [x19, #0x10]\n" + "add x19, x19, #0x20\n" + "ld1w { z0.s }, p3/Z, [x22, x28, LSL #2]\n" + "ld1w { z31.s }, p3/Z, [x21, x28, LSL #2]\n" + "ld1w { z30.s }, p3/Z, [x20, x28, LSL #2]\n" + "beq 10f\n" + "9:" // Single vector of channels: Loop: 4 inputs loop + "fadd z23.s, z1.s, z0.s\n" + "fadd z19.s, z31.s, z30.s\n" + "ldp x23, x22, [x19, #0x0]\n" + "subs x24, x24, #0x1\n" + "fadd z19.s, z23.s, z19.s\n" + "ldp x21, x20, [x19, #0x10]\n" + "fadd z5.s, z5.s, z19.s\n" + "add x19, x19, #0x20\n" + "ld1w { z1.s }, p3/Z, [x23, x28, LSL #2]\n" + "ld1w { z0.s }, p3/Z, [x22, x28, LSL #2]\n" + "ld1w { z31.s }, p3/Z, [x21, x28, LSL #2]\n" + "ld1w { z30.s }, p3/Z, [x20, x28, LSL #2]\n" + "bgt 9b\n" + "10:" // Single vector of channels: Loop: 4 inputs tail + "fadd z23.s, z1.s, z0.s\n" + "fadd z19.s, z31.s, z30.s\n" + "fadd z19.s, z23.s, z19.s\n" + "fadd z5.s, z5.s, z19.s\n" + "11:" // Single vector of channels: Loop: After loop + "ands x20, %x[n_valid_cells], #0x3\n" + "beq 13f\n" + "12:" // Single vector of channels: Loop: Single input loop + "ldr x23, [x19], #0x8\n" + "ld1w { z1.s }, p3/Z, [x23, x28, LSL #2]\n" + "subs x20, x20, #0x1\n" + "fadd z5.s, z5.s, z1.s\n" + "bgt 12b\n" + "13:" // Single vector of channels: Loop: Single input loop: End + "fmul z5.s, z5.s, z6.s\n" + "st1w { z5.s }, p3, [%x[outptr], x28, LSL #2]\n" + "incw x28\n" + "whilelt p3.s, x28, %x[n_channels]\n" + "b.any 8b\n" + "14:" // End + ".inst 0xd503467f // SMSTOP\n" + : + : [inptrs] "r" (inptrs), [n_channels] "r" (n_channels), [n_valid_cells] "r" (n_valid_cells), [outptr] "r" (outptr), [rescale_ptr] "r" (&rescale_value) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_max_2x2_s1_output2x2_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_max_2x2_s1_output2x2_depthfirst.hpp new file mode 100644 index 0000000000..4e3cd6e228 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_max_2x2_s1_output2x2_depthfirst.hpp @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#pragma once + +namespace arm_conv { +namespace pooling { + +void sme_fp32_nhwc_max_2x2_s1_output2x2_depthfirst_impl(unsigned int, const float *const *const, float *const *const, bool, unsigned int, unsigned int, unsigned int, unsigned int); + +struct sme_fp32_nhwc_max_2x2_s1_output2x2_depthfirst : public DepthfirstStrategy<float, float> +{ + using Parent = DepthfirstStrategy<float, float>; + + const static auto pooling_type = PoolingType::MAX; + const static auto pool_rows = 2u, pool_cols = 2u; + const static auto stride_rows = 1u, stride_cols = 1u; + + sme_fp32_nhwc_max_2x2_s1_output2x2_depthfirst(const CPUInfo *) + : Parent(pool_rows, pool_cols, stride_rows, stride_cols, 2, 2) {} + + Parent::KernelType get_kernel(void) const { return sme_fp32_nhwc_max_2x2_s1_output2x2_depthfirst_impl; } +}; + +} // namespace pooling +} // namespace arm_conv diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp new file mode 100644 index 0000000000..be254d307b --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + + +#include <cstddef> +#include <cstdint> + +#if defined(__ARM_FEATURE_SVE) && defined(ARM_COMPUTE_ENABLE_SME) + +namespace arm_conv { +namespace pooling { + +void sme_fp32_nhwc_max_2x2_s1_output2x2_depthfirst_impl( + const unsigned int n_channels, + const float *const *const inptrs, + float *const *const outptrs, + const bool exclude_padding, + const unsigned int pad_left, + const unsigned int pad_top, + const unsigned int pad_right, + const unsigned int pad_bottom +) +{ + struct KernelArgs + { + const uint64_t n_channels; + const float *const *const inptrs; + float *const *const outptrs; + KernelArgs( + unsigned int channels, + const float *const *input_ptrs, + float *const * output_ptrs, + bool, unsigned int, unsigned int, unsigned int, unsigned int + ) : n_channels(channels), + inptrs(input_ptrs), + outptrs(output_ptrs) + { + } + }; + + const KernelArgs args(n_channels, inptrs, outptrs, exclude_padding, + pad_left, pad_top, pad_right, pad_bottom); + + __asm__ __volatile__( + "ldr x20, [%x[args], %[offsetof_outptrs]]\n" + ".inst 0xd503477f // SMSTART ZA\n" + "mov x14, #0x0\n" + "ptrue p2.b\n" + "ldr x19, [%x[args], %[offsetof_inptrs]]\n" + "mov x13, #0x0\n" + "ldr x12, [%x[args], %[offsetof_n_channels]]\n" + "whilelt p1.s, x14, x12\n" + "ldp x11, x10, [x20, #0x0]\n" + "ldp x9, x28, [x20, #0x10]\n" + "ldp x27, x26, [x19, #0x0]\n" + "ld1w { z29.s }, p1/Z, [x26, x14, LSL #2]\n" + "ldp x25, x24, [x19, #0x10]\n" + "ld1w { z28.s }, p1/Z, [x24, x14, LSL #2]\n" + "ldp x23, x22, [x19, #0x20]\n" + "ld1w { z27.s }, p1/Z, [x23, x14, LSL #2]\n" + "ldp x21, x20, [x19, #0x30]\n" + "ld1w { z26.s }, p1/Z, [x20, x14, LSL #2]\n" + "ldr x19, [x19, #0x40]\n" + "ld1w { z20.s }, p1/Z, [x27, x14, LSL #2]\n" + "ld1w { z25.s }, p1/Z, [x22, x14, LSL #2]\n" + "ld1w { z24.s }, p1/Z, [x25, x14, LSL #2]\n" + "ld1w { z23.s }, p1/Z, [x21, x14, LSL #2]\n" + "ld1w { z19.s }, p1/Z, [x19, x14, LSL #2]\n" + "incw x14\n" + "whilelt p1.s, x14, x12\n" + "b.none 2f\n" + "1:" // Vector: Loop + "movprfx z22, z29\n fmax z22.s, p2/M, z22.s, z27.s\n" + "movprfx z21, z27\n fmax z21.s, p2/M, z21.s, z26.s\n" + "ld1w { z29.s }, p1/Z, [x26, x14, LSL #2]\n" + "whilelt p0.s, x13, x12\n" + "movprfx z18, z28\n fmax z18.s, p2/M, z18.s, z20.s\n" + "movprfx z20, z25\n fmax z20.s, p2/M, z20.s, z24.s\n" + "ld1w { z27.s }, p1/Z, [x23, x14, LSL #2]\n" + "movprfx z17, z23\n fmax z17.s, p2/M, z17.s, z28.s\n" + "movprfx z16, z25\n fmax z16.s, p2/M, z16.s, z19.s\n" + "ld1w { z26.s }, p1/Z, [x20, x14, LSL #2]\n" + "ld1w { z28.s }, p1/Z, [x24, x14, LSL #2]\n" + "movprfx z19, z18\n fmax z19.s, p2/M, z19.s, z22.s\n" + "movprfx z18, z22\n fmax z18.s, p2/M, z18.s, z20.s\n" + "ld1w { z20.s }, p1/Z, [x27, x14, LSL #2]\n" + "fmax z17.s, p2/M, z17.s, z21.s\n" + "fmax z16.s, p2/M, z16.s, z21.s\n" + "ld1w { z25.s }, p1/Z, [x22, x14, LSL #2]\n" + "st1w { z19.s }, p0, [x11, x13, LSL #2]\n" + "ld1w { z24.s }, p1/Z, [x25, x14, LSL #2]\n" + "st1w { z18.s }, p0, [x10, x13, LSL #2]\n" + "ld1w { z23.s }, p1/Z, [x21, x14, LSL #2]\n" + "st1w { z17.s }, p0, [x9, x13, LSL #2]\n" + "ld1w { z19.s }, p1/Z, [x19, x14, LSL #2]\n" + "incw x14\n" + "whilelt p1.s, x14, x12\n" + "st1w { z16.s }, p0, [x28, x13, LSL #2]\n" + "incw x13\n" + "b.any 1b\n" + "2:" // Vector: Tail + "movprfx z22, z29\n fmax z22.s, p2/M, z22.s, z27.s\n" + "movprfx z21, z27\n fmax z21.s, p2/M, z21.s, z26.s\n" + "whilelt p0.s, x13, x12\n" + "movprfx z18, z28\n fmax z18.s, p2/M, z18.s, z20.s\n" + "movprfx z20, z25\n fmax z20.s, p2/M, z20.s, z24.s\n" + "movprfx z17, z23\n fmax z17.s, p2/M, z17.s, z28.s\n" + "movprfx z16, z25\n fmax z16.s, p2/M, z16.s, z19.s\n" + "movprfx z19, z18\n fmax z19.s, p2/M, z19.s, z22.s\n" + "movprfx z18, z22\n fmax z18.s, p2/M, z18.s, z20.s\n" + "st1w { z19.s }, p0, [x11, x13, LSL #2]\n" + "fmax z17.s, p2/M, z17.s, z21.s\n" + "fmax z16.s, p2/M, z16.s, z21.s\n" + "st1w { z18.s }, p0, [x10, x13, LSL #2]\n" + "st1w { z17.s }, p0, [x9, x13, LSL #2]\n" + "st1w { z16.s }, p0, [x28, x13, LSL #2]\n" + ".inst 0xd503467f // SMSTOP\n" + : + : [args] "r" (&args), [offsetof_inptrs] "I" (offsetof(KernelArgs, inptrs)), [offsetof_n_channels] "I" (offsetof(KernelArgs, n_channels)), [offsetof_outptrs] "I" (offsetof(KernelArgs, outptrs)) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x9", "x10", "x11", "x12", "x13", "x14", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(__ARM_FEATURE_SVE) && defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_max_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_max_generic_depthfirst.hpp new file mode 100644 index 0000000000..0c0e445c7a --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_max_generic_depthfirst.hpp @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstdint> + +#pragma once + +namespace arm_conv { +namespace pooling { + +void sme_fp32_nhwc_max_generic_depthfirst_impl(const uint64_t, const uint64_t n_valid_cells, uint64_t n_channels, const float *const *const inptrs, float *outptr); + +struct sme_fp32_nhwc_max_generic_depthfirst : IGenericDepthfirstStrategy<float, float> +{ + using Parent = IGenericDepthfirstStrategy<float, float>; + sme_fp32_nhwc_max_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return sme_fp32_nhwc_max_generic_depthfirst_impl; } +}; + +} // namespace pooling +} // namespace arm_conv diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_max_generic_depthfirst/generic.cpp new file mode 100644 index 0000000000..b9f90ea2ef --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_max_generic_depthfirst/generic.cpp @@ -0,0 +1,224 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if defined(ARM_COMPUTE_ENABLE_SME) + +#include <cstdint> + +namespace arm_conv { +namespace pooling { + + +void sme_fp32_nhwc_max_generic_depthfirst_impl( + const uint64_t, + const uint64_t n_valid_cells, + uint64_t n_channels, + const float *const *const inptrs, + float *outptr +) +{ + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "mov x28, #0x0\n" + "cntw x27\n" + "cntw x26, ALL, MUL #2\n" + "cntw x25, ALL, MUL #3\n" + "whilelt p4.s, x28, %x[n_channels]\n" + "whilelt p3.s, x27, %x[n_channels]\n" + "whilelt p2.s, x26, %x[n_channels]\n" + "whilelt p1.s, x25, %x[n_channels]\n" + "ptrue p0.b\n" + "b.none 7f\n" + "1:" // 4-vectors of channels + "lsr x24, %x[n_valid_cells], #0x2\n" + "mov z4.s, #0xff800000\n" + "mov z3.s, #0xff800000\n" + "mov x19, %x[inptrs]\n" + "mov z2.s, #0xff800000\n" + "mov z1.s, #0xff800000\n" + "cbz x24, 4f\n" + "ldp x23, x22, [x19, #0x0]\n" + "subs x24, x24, #0x1\n" + "ld1w { z0.s }, p4/Z, [x23, x28, LSL #2]\n" + "ldp x21, x20, [x19, #0x10]\n" + "add x19, x19, #0x20\n" + "ld1w { z31.s }, p4/Z, [x22, x28, LSL #2]\n" + "ld1w { z23.s }, p4/Z, [x21, x28, LSL #2]\n" + "ld1w { z30.s }, p4/Z, [x20, x28, LSL #2]\n" + "ld1w { z18.s }, p3/Z, [x23, x27, LSL #2]\n" + "ld1w { z29.s }, p3/Z, [x22, x27, LSL #2]\n" + "ld1w { z22.s }, p3/Z, [x21, x27, LSL #2]\n" + "ld1w { z28.s }, p3/Z, [x20, x27, LSL #2]\n" + "ld1w { z17.s }, p2/Z, [x23, x26, LSL #2]\n" + "ld1w { z27.s }, p2/Z, [x22, x26, LSL #2]\n" + "ld1w { z21.s }, p2/Z, [x21, x26, LSL #2]\n" + "ld1w { z26.s }, p2/Z, [x20, x26, LSL #2]\n" + "ld1w { z16.s }, p1/Z, [x23, x25, LSL #2]\n" + "ld1w { z25.s }, p1/Z, [x22, x25, LSL #2]\n" + "ld1w { z20.s }, p1/Z, [x21, x25, LSL #2]\n" + "ld1w { z24.s }, p1/Z, [x20, x25, LSL #2]\n" + "beq 3f\n" + "2:" // 4-vectors of channels: 4 inputs loop + "movprfx z19, z0\n fmax z19.s, p0/M, z19.s, z31.s\n" + "fmax z23.s, p0/M, z23.s, z30.s\n" + "ldp x23, x22, [x19, #0x0]\n" + "subs x24, x24, #0x1\n" + "fmax z18.s, p0/M, z18.s, z29.s\n" + "fmax z22.s, p0/M, z22.s, z28.s\n" + "ldp x21, x20, [x19, #0x10]\n" + "add x19, x19, #0x20\n" + "fmax z17.s, p0/M, z17.s, z27.s\n" + "fmax z21.s, p0/M, z21.s, z26.s\n" + "ld1w { z0.s }, p4/Z, [x23, x28, LSL #2]\n" + "fmax z16.s, p0/M, z16.s, z25.s\n" + "fmax z20.s, p0/M, z20.s, z24.s\n" + "ld1w { z31.s }, p4/Z, [x22, x28, LSL #2]\n" + "fmax z19.s, p0/M, z19.s, z23.s\n" + "fmax z18.s, p0/M, z18.s, z22.s\n" + "ld1w { z23.s }, p4/Z, [x21, x28, LSL #2]\n" + "fmax z17.s, p0/M, z17.s, z21.s\n" + "fmax z16.s, p0/M, z16.s, z20.s\n" + "ld1w { z30.s }, p4/Z, [x20, x28, LSL #2]\n" + "fmax z4.s, p0/M, z4.s, z19.s\n" + "fmax z3.s, p0/M, z3.s, z18.s\n" + "ld1w { z18.s }, p3/Z, [x23, x27, LSL #2]\n" + "fmax z2.s, p0/M, z2.s, z17.s\n" + "fmax z1.s, p0/M, z1.s, z16.s\n" + "ld1w { z29.s }, p3/Z, [x22, x27, LSL #2]\n" + "ld1w { z22.s }, p3/Z, [x21, x27, LSL #2]\n" + "ld1w { z28.s }, p3/Z, [x20, x27, LSL #2]\n" + "ld1w { z17.s }, p2/Z, [x23, x26, LSL #2]\n" + "ld1w { z27.s }, p2/Z, [x22, x26, LSL #2]\n" + "ld1w { z21.s }, p2/Z, [x21, x26, LSL #2]\n" + "ld1w { z26.s }, p2/Z, [x20, x26, LSL #2]\n" + "ld1w { z16.s }, p1/Z, [x23, x25, LSL #2]\n" + "ld1w { z25.s }, p1/Z, [x22, x25, LSL #2]\n" + "ld1w { z20.s }, p1/Z, [x21, x25, LSL #2]\n" + "ld1w { z24.s }, p1/Z, [x20, x25, LSL #2]\n" + "bgt 2b\n" + "3:" // 4-vectors of channels: 4 inputs tail + "movprfx z19, z0\n fmax z19.s, p0/M, z19.s, z31.s\n" + "fmax z23.s, p0/M, z23.s, z30.s\n" + "fmax z18.s, p0/M, z18.s, z29.s\n" + "fmax z22.s, p0/M, z22.s, z28.s\n" + "fmax z17.s, p0/M, z17.s, z27.s\n" + "fmax z21.s, p0/M, z21.s, z26.s\n" + "fmax z16.s, p0/M, z16.s, z25.s\n" + "fmax z20.s, p0/M, z20.s, z24.s\n" + "fmax z19.s, p0/M, z19.s, z23.s\n" + "fmax z18.s, p0/M, z18.s, z22.s\n" + "fmax z17.s, p0/M, z17.s, z21.s\n" + "fmax z16.s, p0/M, z16.s, z20.s\n" + "fmax z4.s, p0/M, z4.s, z19.s\n" + "fmax z3.s, p0/M, z3.s, z18.s\n" + "fmax z2.s, p0/M, z2.s, z17.s\n" + "fmax z1.s, p0/M, z1.s, z16.s\n" + "4:" // 4-vectors of channels: After loop + "ands x20, %x[n_valid_cells], #0x3\n" + "beq 6f\n" + "5:" // 4-vectors of channels: Single input loop + "ldr x23, [x19], #0x8\n" + "ld1w { z0.s }, p4/Z, [x23, x28, LSL #2]\n" + "subs x20, x20, #0x1\n" + "fmax z4.s, p0/M, z4.s, z0.s\n" + "ld1w { z18.s }, p3/Z, [x23, x27, LSL #2]\n" + "fmax z3.s, p0/M, z3.s, z18.s\n" + "ld1w { z17.s }, p2/Z, [x23, x26, LSL #2]\n" + "fmax z2.s, p0/M, z2.s, z17.s\n" + "ld1w { z16.s }, p1/Z, [x23, x25, LSL #2]\n" + "fmax z1.s, p0/M, z1.s, z16.s\n" + "bgt 5b\n" + "6:" // 4-vectors of channels: Single input loop: End + "st1w { z4.s }, p4, [%x[outptr], x28, LSL #2]\n" + "incw x28, ALL, MUL #4\n" + "st1w { z3.s }, p3, [%x[outptr], x27, LSL #2]\n" + "incw x27, ALL, MUL #4\n" + "st1w { z2.s }, p2, [%x[outptr], x26, LSL #2]\n" + "incw x26, ALL, MUL #4\n" + "st1w { z1.s }, p1, [%x[outptr], x25, LSL #2]\n" + "incw x25, ALL, MUL #4\n" + "whilelt p1.s, x25, %x[n_channels]\n" + "b.any 1b\n" + "7:" // Single vector of channels + "whilelt p4.s, x28, %x[n_channels]\n" + "b.none 14f\n" + "8:" // Single vector of channels: Loop + "lsr x24, %x[n_valid_cells], #0x2\n" + "mov z4.s, #0xff800000\n" + "mov x19, %x[inptrs]\n" + "cbz x24, 11f\n" + "ldp x23, x22, [x19, #0x0]\n" + "subs x24, x24, #0x1\n" + "ld1w { z0.s }, p4/Z, [x23, x28, LSL #2]\n" + "ldp x21, x20, [x19, #0x10]\n" + "add x19, x19, #0x20\n" + "ld1w { z31.s }, p4/Z, [x22, x28, LSL #2]\n" + "ld1w { z23.s }, p4/Z, [x21, x28, LSL #2]\n" + "ld1w { z30.s }, p4/Z, [x20, x28, LSL #2]\n" + "beq 10f\n" + "9:" // Single vector of channels: Loop: 4 inputs loop + "movprfx z19, z0\n fmax z19.s, p0/M, z19.s, z31.s\n" + "fmax z23.s, p0/M, z23.s, z30.s\n" + "ldp x23, x22, [x19, #0x0]\n" + "subs x24, x24, #0x1\n" + "fmax z19.s, p0/M, z19.s, z23.s\n" + "ldp x21, x20, [x19, #0x10]\n" + "fmax z4.s, p0/M, z4.s, z19.s\n" + "add x19, x19, #0x20\n" + "ld1w { z0.s }, p4/Z, [x23, x28, LSL #2]\n" + "ld1w { z31.s }, p4/Z, [x22, x28, LSL #2]\n" + "ld1w { z23.s }, p4/Z, [x21, x28, LSL #2]\n" + "ld1w { z30.s }, p4/Z, [x20, x28, LSL #2]\n" + "bgt 9b\n" + "10:" // Single vector of channels: Loop: 4 inputs tail + "movprfx z19, z0\n fmax z19.s, p0/M, z19.s, z31.s\n" + "fmax z23.s, p0/M, z23.s, z30.s\n" + "fmax z19.s, p0/M, z19.s, z23.s\n" + "fmax z4.s, p0/M, z4.s, z19.s\n" + "11:" // Single vector of channels: Loop: After loop + "ands x20, %x[n_valid_cells], #0x3\n" + "beq 13f\n" + "12:" // Single vector of channels: Loop: Single input loop + "ldr x23, [x19], #0x8\n" + "ld1w { z0.s }, p4/Z, [x23, x28, LSL #2]\n" + "subs x20, x20, #0x1\n" + "fmax z4.s, p0/M, z4.s, z0.s\n" + "bgt 12b\n" + "13:" // Single vector of channels: Loop: Single input loop: End + "st1w { z4.s }, p4, [%x[outptr], x28, LSL #2]\n" + "incw x28\n" + "whilelt p4.s, x28, %x[n_channels]\n" + "b.any 8b\n" + "14:" // End + ".inst 0xd503467f // SMSTOP\n" + : + : [inptrs] "r" (inptrs), [n_channels] "r" (n_channels), [n_valid_cells] "r" (n_valid_cells), [outptr] "r" (outptr) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_avg_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_avg_generic_depthfirst.hpp new file mode 100644 index 0000000000..e383a4c3bd --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_avg_generic_depthfirst.hpp @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstdint> + +#pragma once + +namespace arm_conv { +namespace pooling { + +void sme_s8_nhwc_avg_generic_depthfirst_impl(const uint64_t window_cells, const uint64_t n_valid_cells, uint64_t n_channels, const int8_t *const *const inptrs, int8_t *outptr); + +struct sme_s8_nhwc_avg_generic_depthfirst : IGenericDepthfirstStrategy<int8_t, int8_t> +{ + using Parent = IGenericDepthfirstStrategy<int8_t, int8_t>; + sme_s8_nhwc_avg_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return sme_s8_nhwc_avg_generic_depthfirst_impl; } +}; + +} // namespace pooling +} // namespace arm_conv diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_avg_generic_depthfirst/generic.cpp new file mode 100644 index 0000000000..c5066d1017 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_avg_generic_depthfirst/generic.cpp @@ -0,0 +1,417 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if defined(ARM_COMPUTE_ENABLE_SME) + +#include <cstdint> +#include <cstring> +#include <cmath> + + +namespace arm_conv { +namespace pooling { + +namespace { + struct RescaleParams + { + int32_t multiplier, shift; + }; + + constexpr RescaleParams rescale_params[8] = { + {0x40000000, -0}, // 1/2 + {0x55555556, -1}, // 1/3 + {0x40000000, -1}, // 1/4 + {0x66666666, -2}, // 1/5 + {0x55555556, -2}, // 1/6 + {0x49249249, -2}, // 1/7 + {0x40000000, -2}, // 1/8 + {0x71c71c72, -3}, // 1/9 + }; +} + +void sme_s8_nhwc_avg_generic_depthfirst_impl( + const uint64_t window_cells, + const uint64_t n_valid_cells, + uint64_t n_channels, + const int8_t *const *const inptrs, + int8_t *outptr +) +{ + if (n_valid_cells == 1 && window_cells == 1) + { + // In this case, simply copy from the input to the output + std::memcpy(outptr, *inptrs, n_channels); + return; + } + + // Compute (or look up) the rescale values + int32_t shift_value = 0, rescale_value = 0; + if (2 <= window_cells && window_cells <= 9) + { + auto ¶ms = rescale_params[window_cells - 2]; + rescale_value = params.multiplier; + shift_value = params.shift; + } + else + { + auto f_rescale_value = 1.0f / static_cast<float>(window_cells); + + shift_value = 0; + while (f_rescale_value < 0.5f) + { + shift_value--; + f_rescale_value *= 2.0f; + } + + rescale_value = static_cast<int32_t>(round(f_rescale_value * static_cast<float>(1ll << 31))); + if (static_cast<int64_t>(rescale_value) == (1ll << 31)) + { + shift_value++; + rescale_value >>= 1; + } + } + + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "mov x26, #0x0\n" + "cntb x25\n" + "cntb x24, ALL, MUL #2\n" + "cntb x23, ALL, MUL #3\n" + "whilelt p4.b, x26, %x[n_channels]\n" + "whilelt p3.b, x25, %x[n_channels]\n" + "whilelt p2.b, x24, %x[n_channels]\n" + "whilelt p1.b, x23, %x[n_channels]\n" + "ptrue p0.b\n" + "b.none 7f\n" + "1:" // 4-vectors of channels + "lsr x22, %x[n_valid_cells], #0x1\n" + "mov z15.s, #0x0\n" + "mov z14.s, #0x0\n" + "mov x19, %x[inptrs]\n" + "mov z13.s, #0x0\n" + "mov z12.s, #0x0\n" + "mov z11.s, #0x0\n" + "mov z10.s, #0x0\n" + "mov z9.s, #0x0\n" + "mov z8.s, #0x0\n" + "mov z7.s, #0x0\n" + "mov z6.s, #0x0\n" + "mov z5.s, #0x0\n" + "mov z4.s, #0x0\n" + "mov z3.s, #0x0\n" + "mov z2.s, #0x0\n" + "mov z1.s, #0x0\n" + "mov z0.s, #0x0\n" + "cbz x22, 4f\n" + "ldp x21, x20, [x19, #0x0]\n" + "subs x22, x22, #0x1\n" + "add x19, x19, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x26]\n" + "ld1b { z30.b }, p4/Z, [x20, x26]\n" + "ld1b { z29.b }, p3/Z, [x21, x25]\n" + "ld1b { z28.b }, p3/Z, [x20, x25]\n" + "ld1b { z27.b }, p2/Z, [x21, x24]\n" + "ld1b { z26.b }, p2/Z, [x20, x24]\n" + "ld1b { z25.b }, p1/Z, [x21, x23]\n" + "ld1b { z24.b }, p1/Z, [x20, x23]\n" + "beq 3f\n" + "2:" // 4-vectors of channels: 2 inputs loop + ".inst 0x455e03f7 // saddlb z23.h, z31.b, z30.b\n" + ".inst 0x455e07f6 // saddlt z22.h, z31.b, z30.b\n" + "ldp x21, x20, [x19, #0x0]\n" + "subs x22, x22, #0x1\n" + ".inst 0x455c03b5 // saddlb z21.h, z29.b, z28.b\n" + ".inst 0x455c07b4 // saddlt z20.h, z29.b, z28.b\n" + "add x19, x19, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x26]\n" + ".inst 0x455a0373 // saddlb z19.h, z27.b, z26.b\n" + ".inst 0x455a0772 // saddlt z18.h, z27.b, z26.b\n" + "ld1b { z30.b }, p4/Z, [x20, x26]\n" + ".inst 0x45580331 // saddlb z17.h, z25.b, z24.b\n" + ".inst 0x45580730 // saddlt z16.h, z25.b, z24.b\n" + "ld1b { z29.b }, p3/Z, [x21, x25]\n" + ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" + ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" + "ld1b { z28.b }, p3/Z, [x20, x25]\n" + ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" + ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" + "ld1b { z27.b }, p2/Z, [x21, x24]\n" + ".inst 0x4595416b // saddwb z11.s, z11.s, z21.h\n" + ".inst 0x4595454a // saddwt z10.s, z10.s, z21.h\n" + "ld1b { z26.b }, p2/Z, [x20, x24]\n" + ".inst 0x45944129 // saddwb z9.s, z9.s, z20.h\n" + ".inst 0x45944508 // saddwt z8.s, z8.s, z20.h\n" + "ld1b { z25.b }, p1/Z, [x21, x23]\n" + ".inst 0x459340e7 // saddwb z7.s, z7.s, z19.h\n" + ".inst 0x459344c6 // saddwt z6.s, z6.s, z19.h\n" + "ld1b { z24.b }, p1/Z, [x20, x23]\n" + ".inst 0x459240a5 // saddwb z5.s, z5.s, z18.h\n" + ".inst 0x45924484 // saddwt z4.s, z4.s, z18.h\n" + ".inst 0x45914063 // saddwb z3.s, z3.s, z17.h\n" + ".inst 0x45914442 // saddwt z2.s, z2.s, z17.h\n" + ".inst 0x45904021 // saddwb z1.s, z1.s, z16.h\n" + ".inst 0x45904400 // saddwt z0.s, z0.s, z16.h\n" + "bgt 2b\n" + "3:" // 4-vectors of channels: 2 inputs tail + ".inst 0x455e03f7 // saddlb z23.h, z31.b, z30.b\n" + ".inst 0x455e07f6 // saddlt z22.h, z31.b, z30.b\n" + ".inst 0x455c03b5 // saddlb z21.h, z29.b, z28.b\n" + ".inst 0x455c07b4 // saddlt z20.h, z29.b, z28.b\n" + ".inst 0x455a0373 // saddlb z19.h, z27.b, z26.b\n" + ".inst 0x455a0772 // saddlt z18.h, z27.b, z26.b\n" + ".inst 0x45580331 // saddlb z17.h, z25.b, z24.b\n" + ".inst 0x45580730 // saddlt z16.h, z25.b, z24.b\n" + ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" + ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" + ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" + ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" + ".inst 0x4595416b // saddwb z11.s, z11.s, z21.h\n" + ".inst 0x4595454a // saddwt z10.s, z10.s, z21.h\n" + ".inst 0x45944129 // saddwb z9.s, z9.s, z20.h\n" + ".inst 0x45944508 // saddwt z8.s, z8.s, z20.h\n" + ".inst 0x459340e7 // saddwb z7.s, z7.s, z19.h\n" + ".inst 0x459344c6 // saddwt z6.s, z6.s, z19.h\n" + ".inst 0x459240a5 // saddwb z5.s, z5.s, z18.h\n" + ".inst 0x45924484 // saddwt z4.s, z4.s, z18.h\n" + ".inst 0x45914063 // saddwb z3.s, z3.s, z17.h\n" + ".inst 0x45914442 // saddwt z2.s, z2.s, z17.h\n" + ".inst 0x45904021 // saddwb z1.s, z1.s, z16.h\n" + ".inst 0x45904400 // saddwt z0.s, z0.s, z16.h\n" + "4:" // 4-vectors of channels: After loop + "ands x20, %x[n_valid_cells], #0x1\n" + "beq 6f\n" + "5:" // 4-vectors of channels: Single input loop + "ldr x21, [x19], #0x8\n" + "ld1b { z31.b }, p4/Z, [x21, x26]\n" + ".inst 0x4508a3f7 // sshllb z23.h, z31.b, #0x0\n" + ".inst 0x4508a7f6 // sshllt z22.h, z31.b, #0x0\n" + "ld1b { z29.b }, p3/Z, [x21, x25]\n" + ".inst 0x4508a3b5 // sshllb z21.h, z29.b, #0x0\n" + ".inst 0x4508a7b4 // sshllt z20.h, z29.b, #0x0\n" + "subs x20, x20, #0x1\n" + "ld1b { z27.b }, p2/Z, [x21, x24]\n" + ".inst 0x4508a373 // sshllb z19.h, z27.b, #0x0\n" + ".inst 0x4508a772 // sshllt z18.h, z27.b, #0x0\n" + "ld1b { z25.b }, p1/Z, [x21, x23]\n" + ".inst 0x4508a331 // sshllb z17.h, z25.b, #0x0\n" + ".inst 0x4508a730 // sshllt z16.h, z25.b, #0x0\n" + ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" + ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" + ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" + ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" + ".inst 0x4595416b // saddwb z11.s, z11.s, z21.h\n" + ".inst 0x4595454a // saddwt z10.s, z10.s, z21.h\n" + ".inst 0x45944129 // saddwb z9.s, z9.s, z20.h\n" + ".inst 0x45944508 // saddwt z8.s, z8.s, z20.h\n" + ".inst 0x459340e7 // saddwb z7.s, z7.s, z19.h\n" + ".inst 0x459344c6 // saddwt z6.s, z6.s, z19.h\n" + ".inst 0x459240a5 // saddwb z5.s, z5.s, z18.h\n" + ".inst 0x45924484 // saddwt z4.s, z4.s, z18.h\n" + ".inst 0x45914063 // saddwb z3.s, z3.s, z17.h\n" + ".inst 0x45914442 // saddwt z2.s, z2.s, z17.h\n" + ".inst 0x45904021 // saddwb z1.s, z1.s, z16.h\n" + ".inst 0x45904400 // saddwt z0.s, z0.s, z16.h\n" + "bgt 5b\n" + "6:" // 4-vectors of channels: Single input loop: End + "ld1rw { z17.s }, p0/Z, [%x[rescale_ptr]]\n" + ".inst 0x04b175ef // sqdmulh z15.s, z15.s, z17.s\n" + ".inst 0x04b175ce // sqdmulh z14.s, z14.s, z17.s\n" + ".inst 0x04b175ad // sqdmulh z13.s, z13.s, z17.s\n" + ".inst 0x04b1758c // sqdmulh z12.s, z12.s, z17.s\n" + "ld1rw { z16.s }, p0/Z, [%x[shift_ptr]]\n" + ".inst 0x04b1756b // sqdmulh z11.s, z11.s, z17.s\n" + ".inst 0x04b1754a // sqdmulh z10.s, z10.s, z17.s\n" + ".inst 0x04b17529 // sqdmulh z9.s, z9.s, z17.s\n" + ".inst 0x04b17508 // sqdmulh z8.s, z8.s, z17.s\n" + ".inst 0x04b174e7 // sqdmulh z7.s, z7.s, z17.s\n" + ".inst 0x04b174c6 // sqdmulh z6.s, z6.s, z17.s\n" + ".inst 0x04b174a5 // sqdmulh z5.s, z5.s, z17.s\n" + ".inst 0x04b17484 // sqdmulh z4.s, z4.s, z17.s\n" + ".inst 0x04b17463 // sqdmulh z3.s, z3.s, z17.s\n" + ".inst 0x04b17442 // sqdmulh z2.s, z2.s, z17.s\n" + ".inst 0x04b17421 // sqdmulh z1.s, z1.s, z17.s\n" + ".inst 0x04b17400 // sqdmulh z0.s, z0.s, z17.s\n" + "mov z19.s, #0x7f\n" + ".inst 0x4482820f // srshl z15.s, p0/M, z15.s, z16.s\n" + ".inst 0x4482820e // srshl z14.s, p0/M, z14.s, z16.s\n" + ".inst 0x4482820d // srshl z13.s, p0/M, z13.s, z16.s\n" + ".inst 0x4482820c // srshl z12.s, p0/M, z12.s, z16.s\n" + ".inst 0x4482820b // srshl z11.s, p0/M, z11.s, z16.s\n" + ".inst 0x4482820a // srshl z10.s, p0/M, z10.s, z16.s\n" + ".inst 0x44828209 // srshl z9.s, p0/M, z9.s, z16.s\n" + ".inst 0x44828208 // srshl z8.s, p0/M, z8.s, z16.s\n" + ".inst 0x44828207 // srshl z7.s, p0/M, z7.s, z16.s\n" + ".inst 0x44828206 // srshl z6.s, p0/M, z6.s, z16.s\n" + ".inst 0x44828205 // srshl z5.s, p0/M, z5.s, z16.s\n" + ".inst 0x44828204 // srshl z4.s, p0/M, z4.s, z16.s\n" + ".inst 0x44828203 // srshl z3.s, p0/M, z3.s, z16.s\n" + ".inst 0x44828202 // srshl z2.s, p0/M, z2.s, z16.s\n" + ".inst 0x44828201 // srshl z1.s, p0/M, z1.s, z16.s\n" + ".inst 0x44828200 // srshl z0.s, p0/M, z0.s, z16.s\n" + "not z16.s, p0/M, z19.s\n" + "smax z15.s, p0/M, z15.s, z16.s\n" + "smax z14.s, p0/M, z14.s, z16.s\n" + "smax z13.s, p0/M, z13.s, z16.s\n" + "smax z12.s, p0/M, z12.s, z16.s\n" + "smax z11.s, p0/M, z11.s, z16.s\n" + "smax z10.s, p0/M, z10.s, z16.s\n" + "smax z9.s, p0/M, z9.s, z16.s\n" + "smax z8.s, p0/M, z8.s, z16.s\n" + "smax z7.s, p0/M, z7.s, z16.s\n" + "smax z6.s, p0/M, z6.s, z16.s\n" + "smax z5.s, p0/M, z5.s, z16.s\n" + "smax z4.s, p0/M, z4.s, z16.s\n" + "smax z3.s, p0/M, z3.s, z16.s\n" + "smax z2.s, p0/M, z2.s, z16.s\n" + "smax z1.s, p0/M, z1.s, z16.s\n" + "smax z0.s, p0/M, z0.s, z16.s\n" + "smin z15.s, p0/M, z15.s, z19.s\n" + "smin z14.s, p0/M, z14.s, z19.s\n" + "trn1 z23.h, z15.h, z14.h\n" + "smin z13.s, p0/M, z13.s, z19.s\n" + "smin z12.s, p0/M, z12.s, z19.s\n" + "trn1 z16.h, z13.h, z12.h\n" + "smin z11.s, p0/M, z11.s, z19.s\n" + "smin z10.s, p0/M, z10.s, z19.s\n" + "trn1 z22.h, z11.h, z10.h\n" + "smin z9.s, p0/M, z9.s, z19.s\n" + "smin z8.s, p0/M, z8.s, z19.s\n" + "trn1 z18.h, z9.h, z8.h\n" + "smin z7.s, p0/M, z7.s, z19.s\n" + "smin z6.s, p0/M, z6.s, z19.s\n" + "trn1 z21.h, z7.h, z6.h\n" + "smin z5.s, p0/M, z5.s, z19.s\n" + "smin z4.s, p0/M, z4.s, z19.s\n" + "trn1 z17.h, z5.h, z4.h\n" + "smin z3.s, p0/M, z3.s, z19.s\n" + "smin z2.s, p0/M, z2.s, z19.s\n" + "trn1 z20.h, z3.h, z2.h\n" + "smin z1.s, p0/M, z1.s, z19.s\n" + "smin z0.s, p0/M, z0.s, z19.s\n" + "trn1 z19.h, z1.h, z0.h\n" + "trn1 z16.b, z23.b, z16.b\n" + "trn1 z18.b, z22.b, z18.b\n" + "st1b { z16.b }, p4, [%x[outptr], x26]\n" + "incb x26, ALL, MUL #4\n" + "trn1 z17.b, z21.b, z17.b\n" + "trn1 z16.b, z20.b, z19.b\n" + "st1b { z18.b }, p3, [%x[outptr], x25]\n" + "incb x25, ALL, MUL #4\n" + "st1b { z17.b }, p2, [%x[outptr], x24]\n" + "incb x24, ALL, MUL #4\n" + "st1b { z16.b }, p1, [%x[outptr], x23]\n" + "incb x23, ALL, MUL #4\n" + "whilelt p1.b, x23, %x[n_channels]\n" + "b.any 1b\n" + "7:" // Single vector of channels + "whilelt p4.b, x26, %x[n_channels]\n" + "b.none 14f\n" + "8:" // Single vector of channels: Loop + "lsr x22, %x[n_valid_cells], #0x1\n" + "mov z15.s, #0x0\n" + "mov z14.s, #0x0\n" + "mov x19, %x[inptrs]\n" + "mov z13.s, #0x0\n" + "mov z12.s, #0x0\n" + "cbz x22, 11f\n" + "ldp x21, x20, [x19, #0x0]\n" + "subs x22, x22, #0x1\n" + "add x19, x19, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x26]\n" + "ld1b { z30.b }, p4/Z, [x20, x26]\n" + "beq 10f\n" + "9:" // Single vector of channels: Loop: 2 inputs loop + ".inst 0x455e03f7 // saddlb z23.h, z31.b, z30.b\n" + ".inst 0x455e07f6 // saddlt z22.h, z31.b, z30.b\n" + "ldp x21, x20, [x19, #0x0]\n" + "subs x22, x22, #0x1\n" + ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" + ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" + "add x19, x19, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x26]\n" + ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" + ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" + "ld1b { z30.b }, p4/Z, [x20, x26]\n" + "bgt 9b\n" + "10:" // Single vector of channels: Loop: 2 inputs tail + ".inst 0x455e03f7 // saddlb z23.h, z31.b, z30.b\n" + ".inst 0x455e07f6 // saddlt z22.h, z31.b, z30.b\n" + ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" + ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" + ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" + ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" + "11:" // Single vector of channels: Loop: After loop + "ands x20, %x[n_valid_cells], #0x1\n" + "beq 13f\n" + "12:" // Single vector of channels: Loop: Single input loop + "ldr x21, [x19], #0x8\n" + "ld1b { z31.b }, p4/Z, [x21, x26]\n" + ".inst 0x4508a3f7 // sshllb z23.h, z31.b, #0x0\n" + ".inst 0x4508a7f6 // sshllt z22.h, z31.b, #0x0\n" + "subs x20, x20, #0x1\n" + ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" + ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" + ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" + ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" + "bgt 12b\n" + "13:" // Single vector of channels: Loop: Single input loop: End + "ld1rw { z17.s }, p0/Z, [%x[rescale_ptr]]\n" + ".inst 0x04b175ef // sqdmulh z15.s, z15.s, z17.s\n" + ".inst 0x04b175ce // sqdmulh z14.s, z14.s, z17.s\n" + ".inst 0x04b175ad // sqdmulh z13.s, z13.s, z17.s\n" + ".inst 0x04b1758c // sqdmulh z12.s, z12.s, z17.s\n" + "ld1rw { z16.s }, p0/Z, [%x[shift_ptr]]\n" + "mov z19.s, #0x7f\n" + ".inst 0x4482820f // srshl z15.s, p0/M, z15.s, z16.s\n" + ".inst 0x4482820e // srshl z14.s, p0/M, z14.s, z16.s\n" + ".inst 0x4482820d // srshl z13.s, p0/M, z13.s, z16.s\n" + ".inst 0x4482820c // srshl z12.s, p0/M, z12.s, z16.s\n" + "not z16.s, p0/M, z19.s\n" + "smax z15.s, p0/M, z15.s, z16.s\n" + "smax z14.s, p0/M, z14.s, z16.s\n" + "smax z13.s, p0/M, z13.s, z16.s\n" + "smax z12.s, p0/M, z12.s, z16.s\n" + "smin z15.s, p0/M, z15.s, z19.s\n" + "smin z14.s, p0/M, z14.s, z19.s\n" + "trn1 z23.h, z15.h, z14.h\n" + "smin z13.s, p0/M, z13.s, z19.s\n" + "smin z12.s, p0/M, z12.s, z19.s\n" + "trn1 z16.h, z13.h, z12.h\n" + "trn1 z16.b, z23.b, z16.b\n" + "st1b { z16.b }, p4, [%x[outptr], x26]\n" + "incb x26\n" + "whilelt p4.b, x26, %x[n_channels]\n" + "b.any 8b\n" + "14:" // End + ".inst 0xd503467f // SMSTOP\n" + : + : [inptrs] "r" (inptrs), [n_channels] "r" (n_channels), [n_valid_cells] "r" (n_valid_cells), [outptr] "r" (outptr), [rescale_ptr] "r" (&rescale_value), [shift_ptr] "r" (&shift_value) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp new file mode 100644 index 0000000000..1613970618 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#pragma once + +namespace arm_conv { +namespace pooling { + +void sme_s8_nhwc_max_2x2_s1_output2x2_depthfirst_impl(unsigned int, const int8_t *const *const, int8_t *const *const, bool, unsigned int, unsigned int, unsigned int, unsigned int); + +struct sme_s8_nhwc_max_2x2_s1_output2x2_depthfirst : public DepthfirstStrategy<int8_t, int8_t> +{ + using Parent = DepthfirstStrategy<int8_t, int8_t>; + + const static auto pooling_type = PoolingType::MAX; + const static auto pool_rows = 2u, pool_cols = 2u; + const static auto stride_rows = 1u, stride_cols = 1u; + + sme_s8_nhwc_max_2x2_s1_output2x2_depthfirst(const CPUInfo *) + : Parent(pool_rows, pool_cols, stride_rows, stride_cols, 2, 2) {} + + Parent::KernelType get_kernel(void) const { return sme_s8_nhwc_max_2x2_s1_output2x2_depthfirst_impl; } +}; + +} // namespace pooling +} // namespace arm_conv diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp new file mode 100644 index 0000000000..d25bec0edb --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + + +#include <cstddef> +#include <cstdint> + +#if defined(__ARM_FEATURE_SVE) && defined(ARM_COMPUTE_ENABLE_SME) + +namespace arm_conv { +namespace pooling { + +void sme_s8_nhwc_max_2x2_s1_output2x2_depthfirst_impl( + const unsigned int n_channels, + const int8_t *const *const inptrs, + int8_t *const *const outptrs, + const bool exclude_padding, + const unsigned int pad_left, + const unsigned int pad_top, + const unsigned int pad_right, + const unsigned int pad_bottom +) +{ + struct KernelArgs + { + const uint64_t n_channels; + const int8_t *const *const inptrs; + int8_t *const *const outptrs; + KernelArgs( + unsigned int channels, + const int8_t *const *input_ptrs, + int8_t *const * output_ptrs, + bool, unsigned int, unsigned int, unsigned int, unsigned int + ) : n_channels(channels), + inptrs(input_ptrs), + outptrs(output_ptrs) + { + } + }; + + const KernelArgs args(n_channels, inptrs, outptrs, exclude_padding, + pad_left, pad_top, pad_right, pad_bottom); + + __asm__ __volatile__( + "ldr x20, [%x[args], %[offsetof_outptrs]]\n" + ".inst 0xd503477f // SMSTART ZA\n" + "mov x14, #0x0\n" + "ptrue p2.b\n" + "ldr x19, [%x[args], %[offsetof_inptrs]]\n" + "mov x13, #0x0\n" + "ldr x12, [%x[args], %[offsetof_n_channels]]\n" + "whilelt p1.b, x14, x12\n" + "ldp x11, x10, [x20, #0x0]\n" + "ldp x9, x28, [x20, #0x10]\n" + "ldp x27, x26, [x19, #0x0]\n" + "ld1b { z29.b }, p1/Z, [x26, x14]\n" + "ldp x25, x24, [x19, #0x10]\n" + "ld1b { z28.b }, p1/Z, [x24, x14]\n" + "ldp x23, x22, [x19, #0x20]\n" + "ld1b { z27.b }, p1/Z, [x23, x14]\n" + "ldp x21, x20, [x19, #0x30]\n" + "ld1b { z26.b }, p1/Z, [x20, x14]\n" + "ldr x19, [x19, #0x40]\n" + "ld1b { z20.b }, p1/Z, [x27, x14]\n" + "ld1b { z25.b }, p1/Z, [x22, x14]\n" + "ld1b { z24.b }, p1/Z, [x25, x14]\n" + "ld1b { z23.b }, p1/Z, [x21, x14]\n" + "ld1b { z19.b }, p1/Z, [x19, x14]\n" + "incw x14\n" + "whilelt p1.b, x14, x12\n" + "b.none 2f\n" + "1:" // Vector: Loop + "movprfx z22, z29\n smax z22.b, p2/M, z22.b, z27.b\n" + "movprfx z21, z27\n smax z21.b, p2/M, z21.b, z26.b\n" + "ld1b { z29.b }, p1/Z, [x26, x14]\n" + "whilelt p0.b, x13, x12\n" + "movprfx z18, z28\n smax z18.b, p2/M, z18.b, z20.b\n" + "movprfx z20, z25\n smax z20.b, p2/M, z20.b, z24.b\n" + "ld1b { z27.b }, p1/Z, [x23, x14]\n" + "movprfx z17, z23\n smax z17.b, p2/M, z17.b, z28.b\n" + "movprfx z16, z25\n smax z16.b, p2/M, z16.b, z19.b\n" + "ld1b { z26.b }, p1/Z, [x20, x14]\n" + "ld1b { z28.b }, p1/Z, [x24, x14]\n" + "movprfx z19, z18\n smax z19.b, p2/M, z19.b, z22.b\n" + "movprfx z18, z22\n smax z18.b, p2/M, z18.b, z20.b\n" + "ld1b { z20.b }, p1/Z, [x27, x14]\n" + "smax z17.b, p2/M, z17.b, z21.b\n" + "smax z16.b, p2/M, z16.b, z21.b\n" + "ld1b { z25.b }, p1/Z, [x22, x14]\n" + "st1b { z19.b }, p0, [x11, x13]\n" + "ld1b { z24.b }, p1/Z, [x25, x14]\n" + "st1b { z18.b }, p0, [x10, x13]\n" + "ld1b { z23.b }, p1/Z, [x21, x14]\n" + "st1b { z17.b }, p0, [x9, x13]\n" + "ld1b { z19.b }, p1/Z, [x19, x14]\n" + "incw x14\n" + "whilelt p1.b, x14, x12\n" + "st1b { z16.b }, p0, [x28, x13]\n" + "incw x13\n" + "b.any 1b\n" + "2:" // Vector: Tail + "movprfx z22, z29\n smax z22.b, p2/M, z22.b, z27.b\n" + "movprfx z21, z27\n smax z21.b, p2/M, z21.b, z26.b\n" + "whilelt p0.b, x13, x12\n" + "movprfx z18, z28\n smax z18.b, p2/M, z18.b, z20.b\n" + "movprfx z20, z25\n smax z20.b, p2/M, z20.b, z24.b\n" + "movprfx z17, z23\n smax z17.b, p2/M, z17.b, z28.b\n" + "movprfx z16, z25\n smax z16.b, p2/M, z16.b, z19.b\n" + "movprfx z19, z18\n smax z19.b, p2/M, z19.b, z22.b\n" + "movprfx z18, z22\n smax z18.b, p2/M, z18.b, z20.b\n" + "st1b { z19.b }, p0, [x11, x13]\n" + "smax z17.b, p2/M, z17.b, z21.b\n" + "smax z16.b, p2/M, z16.b, z21.b\n" + "st1b { z18.b }, p0, [x10, x13]\n" + "st1b { z17.b }, p0, [x9, x13]\n" + "st1b { z16.b }, p0, [x28, x13]\n" + ".inst 0xd503467f // SMSTOP\n" + : + : [args] "r" (&args), [offsetof_inptrs] "I" (offsetof(KernelArgs, inptrs)), [offsetof_n_channels] "I" (offsetof(KernelArgs, n_channels)), [offsetof_outptrs] "I" (offsetof(KernelArgs, outptrs)) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x9", "x10", "x11", "x12", "x13", "x14", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(__ARM_FEATURE_SVE) && defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_max_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_max_generic_depthfirst.hpp new file mode 100644 index 0000000000..56aa120cfe --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_max_generic_depthfirst.hpp @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstdint> + +#pragma once + +namespace arm_conv { +namespace pooling { + +void sme_s8_nhwc_max_generic_depthfirst_impl(const uint64_t, const uint64_t n_valid_cells, uint64_t n_channels, const int8_t *const *const inptrs, int8_t *outptr); + +struct sme_s8_nhwc_max_generic_depthfirst : IGenericDepthfirstStrategy<int8_t, int8_t> +{ + using Parent = IGenericDepthfirstStrategy<int8_t, int8_t>; + sme_s8_nhwc_max_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return sme_s8_nhwc_max_generic_depthfirst_impl; } +}; + +} // namespace pooling +} // namespace arm_conv diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_max_generic_depthfirst/generic.cpp new file mode 100644 index 0000000000..86ad4fec27 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_max_generic_depthfirst/generic.cpp @@ -0,0 +1,224 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if defined(ARM_COMPUTE_ENABLE_SME) + +#include <cstdint> + +namespace arm_conv { +namespace pooling { + + +void sme_s8_nhwc_max_generic_depthfirst_impl( + const uint64_t, + const uint64_t n_valid_cells, + uint64_t n_channels, + const int8_t *const *const inptrs, + int8_t *outptr +) +{ + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "mov x28, #0x0\n" + "cntb x27\n" + "cntb x26, ALL, MUL #2\n" + "cntb x25, ALL, MUL #3\n" + "whilelt p4.b, x28, %x[n_channels]\n" + "whilelt p3.b, x27, %x[n_channels]\n" + "whilelt p2.b, x26, %x[n_channels]\n" + "whilelt p1.b, x25, %x[n_channels]\n" + "ptrue p0.b\n" + "b.none 7f\n" + "1:" // 4-vectors of channels + "lsr x24, %x[n_valid_cells], #0x2\n" + "mov z4.b, #0x80\n" + "mov z3.b, #0x80\n" + "mov x19, %x[inptrs]\n" + "mov z2.b, #0x80\n" + "mov z1.b, #0x80\n" + "cbz x24, 4f\n" + "ldp x23, x22, [x19, #0x0]\n" + "subs x24, x24, #0x1\n" + "ld1b { z0.b }, p4/Z, [x23, x28]\n" + "ldp x21, x20, [x19, #0x10]\n" + "add x19, x19, #0x20\n" + "ld1b { z31.b }, p4/Z, [x22, x28]\n" + "ld1b { z23.b }, p4/Z, [x21, x28]\n" + "ld1b { z30.b }, p4/Z, [x20, x28]\n" + "ld1b { z18.b }, p3/Z, [x23, x27]\n" + "ld1b { z29.b }, p3/Z, [x22, x27]\n" + "ld1b { z22.b }, p3/Z, [x21, x27]\n" + "ld1b { z28.b }, p3/Z, [x20, x27]\n" + "ld1b { z17.b }, p2/Z, [x23, x26]\n" + "ld1b { z27.b }, p2/Z, [x22, x26]\n" + "ld1b { z21.b }, p2/Z, [x21, x26]\n" + "ld1b { z26.b }, p2/Z, [x20, x26]\n" + "ld1b { z16.b }, p1/Z, [x23, x25]\n" + "ld1b { z25.b }, p1/Z, [x22, x25]\n" + "ld1b { z20.b }, p1/Z, [x21, x25]\n" + "ld1b { z24.b }, p1/Z, [x20, x25]\n" + "beq 3f\n" + "2:" // 4-vectors of channels: 4 inputs loop + "movprfx z19, z0\n smax z19.b, p0/M, z19.b, z31.b\n" + "smax z23.b, p0/M, z23.b, z30.b\n" + "ldp x23, x22, [x19, #0x0]\n" + "subs x24, x24, #0x1\n" + "smax z18.b, p0/M, z18.b, z29.b\n" + "smax z22.b, p0/M, z22.b, z28.b\n" + "ldp x21, x20, [x19, #0x10]\n" + "add x19, x19, #0x20\n" + "smax z17.b, p0/M, z17.b, z27.b\n" + "smax z21.b, p0/M, z21.b, z26.b\n" + "ld1b { z0.b }, p4/Z, [x23, x28]\n" + "smax z16.b, p0/M, z16.b, z25.b\n" + "smax z20.b, p0/M, z20.b, z24.b\n" + "ld1b { z31.b }, p4/Z, [x22, x28]\n" + "smax z19.b, p0/M, z19.b, z23.b\n" + "smax z18.b, p0/M, z18.b, z22.b\n" + "ld1b { z23.b }, p4/Z, [x21, x28]\n" + "smax z17.b, p0/M, z17.b, z21.b\n" + "smax z16.b, p0/M, z16.b, z20.b\n" + "ld1b { z30.b }, p4/Z, [x20, x28]\n" + "smax z4.b, p0/M, z4.b, z19.b\n" + "smax z3.b, p0/M, z3.b, z18.b\n" + "ld1b { z18.b }, p3/Z, [x23, x27]\n" + "smax z2.b, p0/M, z2.b, z17.b\n" + "smax z1.b, p0/M, z1.b, z16.b\n" + "ld1b { z29.b }, p3/Z, [x22, x27]\n" + "ld1b { z22.b }, p3/Z, [x21, x27]\n" + "ld1b { z28.b }, p3/Z, [x20, x27]\n" + "ld1b { z17.b }, p2/Z, [x23, x26]\n" + "ld1b { z27.b }, p2/Z, [x22, x26]\n" + "ld1b { z21.b }, p2/Z, [x21, x26]\n" + "ld1b { z26.b }, p2/Z, [x20, x26]\n" + "ld1b { z16.b }, p1/Z, [x23, x25]\n" + "ld1b { z25.b }, p1/Z, [x22, x25]\n" + "ld1b { z20.b }, p1/Z, [x21, x25]\n" + "ld1b { z24.b }, p1/Z, [x20, x25]\n" + "bgt 2b\n" + "3:" // 4-vectors of channels: 4 inputs tail + "movprfx z19, z0\n smax z19.b, p0/M, z19.b, z31.b\n" + "smax z23.b, p0/M, z23.b, z30.b\n" + "smax z18.b, p0/M, z18.b, z29.b\n" + "smax z22.b, p0/M, z22.b, z28.b\n" + "smax z17.b, p0/M, z17.b, z27.b\n" + "smax z21.b, p0/M, z21.b, z26.b\n" + "smax z16.b, p0/M, z16.b, z25.b\n" + "smax z20.b, p0/M, z20.b, z24.b\n" + "smax z19.b, p0/M, z19.b, z23.b\n" + "smax z18.b, p0/M, z18.b, z22.b\n" + "smax z17.b, p0/M, z17.b, z21.b\n" + "smax z16.b, p0/M, z16.b, z20.b\n" + "smax z4.b, p0/M, z4.b, z19.b\n" + "smax z3.b, p0/M, z3.b, z18.b\n" + "smax z2.b, p0/M, z2.b, z17.b\n" + "smax z1.b, p0/M, z1.b, z16.b\n" + "4:" // 4-vectors of channels: After loop + "ands x20, %x[n_valid_cells], #0x3\n" + "beq 6f\n" + "5:" // 4-vectors of channels: Single input loop + "ldr x23, [x19], #0x8\n" + "ld1b { z0.b }, p4/Z, [x23, x28]\n" + "subs x20, x20, #0x1\n" + "smax z4.b, p0/M, z4.b, z0.b\n" + "ld1b { z18.b }, p3/Z, [x23, x27]\n" + "smax z3.b, p0/M, z3.b, z18.b\n" + "ld1b { z17.b }, p2/Z, [x23, x26]\n" + "smax z2.b, p0/M, z2.b, z17.b\n" + "ld1b { z16.b }, p1/Z, [x23, x25]\n" + "smax z1.b, p0/M, z1.b, z16.b\n" + "bgt 5b\n" + "6:" // 4-vectors of channels: Single input loop: End + "st1b { z4.b }, p4, [%x[outptr], x28]\n" + "incb x28, ALL, MUL #4\n" + "st1b { z3.b }, p3, [%x[outptr], x27]\n" + "incb x27, ALL, MUL #4\n" + "st1b { z2.b }, p2, [%x[outptr], x26]\n" + "incb x26, ALL, MUL #4\n" + "st1b { z1.b }, p1, [%x[outptr], x25]\n" + "incb x25, ALL, MUL #4\n" + "whilelt p1.b, x25, %x[n_channels]\n" + "b.any 1b\n" + "7:" // Single vector of channels + "whilelt p4.b, x28, %x[n_channels]\n" + "b.none 14f\n" + "8:" // Single vector of channels: Loop + "lsr x24, %x[n_valid_cells], #0x2\n" + "mov z4.b, #0x80\n" + "mov x19, %x[inptrs]\n" + "cbz x24, 11f\n" + "ldp x23, x22, [x19, #0x0]\n" + "subs x24, x24, #0x1\n" + "ld1b { z0.b }, p4/Z, [x23, x28]\n" + "ldp x21, x20, [x19, #0x10]\n" + "add x19, x19, #0x20\n" + "ld1b { z31.b }, p4/Z, [x22, x28]\n" + "ld1b { z23.b }, p4/Z, [x21, x28]\n" + "ld1b { z30.b }, p4/Z, [x20, x28]\n" + "beq 10f\n" + "9:" // Single vector of channels: Loop: 4 inputs loop + "movprfx z19, z0\n smax z19.b, p0/M, z19.b, z31.b\n" + "smax z23.b, p0/M, z23.b, z30.b\n" + "ldp x23, x22, [x19, #0x0]\n" + "subs x24, x24, #0x1\n" + "smax z19.b, p0/M, z19.b, z23.b\n" + "ldp x21, x20, [x19, #0x10]\n" + "smax z4.b, p0/M, z4.b, z19.b\n" + "add x19, x19, #0x20\n" + "ld1b { z0.b }, p4/Z, [x23, x28]\n" + "ld1b { z31.b }, p4/Z, [x22, x28]\n" + "ld1b { z23.b }, p4/Z, [x21, x28]\n" + "ld1b { z30.b }, p4/Z, [x20, x28]\n" + "bgt 9b\n" + "10:" // Single vector of channels: Loop: 4 inputs tail + "movprfx z19, z0\n smax z19.b, p0/M, z19.b, z31.b\n" + "smax z23.b, p0/M, z23.b, z30.b\n" + "smax z19.b, p0/M, z19.b, z23.b\n" + "smax z4.b, p0/M, z4.b, z19.b\n" + "11:" // Single vector of channels: Loop: After loop + "ands x20, %x[n_valid_cells], #0x3\n" + "beq 13f\n" + "12:" // Single vector of channels: Loop: Single input loop + "ldr x23, [x19], #0x8\n" + "ld1b { z0.b }, p4/Z, [x23, x28]\n" + "subs x20, x20, #0x1\n" + "smax z4.b, p0/M, z4.b, z0.b\n" + "bgt 12b\n" + "13:" // Single vector of channels: Loop: Single input loop: End + "st1b { z4.b }, p4, [%x[outptr], x28]\n" + "incb x28\n" + "whilelt p4.b, x28, %x[n_channels]\n" + "b.any 8b\n" + "14:" // End + ".inst 0xd503467f // SMSTOP\n" + : + : [inptrs] "r" (inptrs), [n_channels] "r" (n_channels), [n_valid_cells] "r" (n_valid_cells), [outptr] "r" (outptr) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8q_nhwc_avg_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8q_nhwc_avg_generic_depthfirst.hpp new file mode 100644 index 0000000000..ee02c60bc1 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8q_nhwc_avg_generic_depthfirst.hpp @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstdint> + +#pragma once + +namespace arm_conv { +namespace pooling { + +void sme_s8q_nhwc_avg_generic_depthfirst_impl(const uint64_t window_cells, const uint64_t n_valid_cells, uint64_t n_channels, const int8_t *const *const inptrs, int8_t *outptr, const Requantize32 &qp); + +struct sme_s8q_nhwc_avg_generic_depthfirst : IGenericDepthfirstStrategy<int8_t, int8_t, Requantize32> +{ + using Parent = IGenericDepthfirstStrategy<int8_t, int8_t, Requantize32>; + sme_s8q_nhwc_avg_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return sme_s8q_nhwc_avg_generic_depthfirst_impl; } +}; + +} // namespace pooling +} // namespace arm_conv diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8q_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8q_nhwc_avg_generic_depthfirst/generic.cpp new file mode 100644 index 0000000000..28b7426d11 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8q_nhwc_avg_generic_depthfirst/generic.cpp @@ -0,0 +1,458 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if defined(ARM_COMPUTE_ENABLE_SME) + +#include "src/core/NEON/kernels/assembly/pooling.hpp" +#include <cstdint> +#include <cstring> +#include <cmath> + + +namespace arm_conv { +namespace pooling { + +namespace { + struct RescaleParams + { + int32_t multiplier, shift; + }; + + constexpr RescaleParams rescale_params[8] = { + {0x40000000, -0}, // 1/2 + {0x55555556, -1}, // 1/3 + {0x40000000, -1}, // 1/4 + {0x66666666, -2}, // 1/5 + {0x55555556, -2}, // 1/6 + {0x49249249, -2}, // 1/7 + {0x40000000, -2}, // 1/8 + {0x71c71c72, -3}, // 1/9 + }; +} + +void sme_s8q_nhwc_avg_generic_depthfirst_impl( + const uint64_t window_cells, + const uint64_t n_valid_cells, + uint64_t n_channels, + const int8_t *const *const inptrs, + int8_t *outptr, + const Requantize32 &qp +) +{ + if (n_valid_cells == 1 && window_cells == 1) + { + // In this case, simply copy from the input to the output + std::memcpy(outptr, *inptrs, n_channels); + return; + } + + // Compute (or look up) the rescale values + int32_t shift_value = 0, rescale_value = 0; + if (2 <= window_cells && window_cells <= 9) + { + auto ¶ms = rescale_params[window_cells - 2]; + rescale_value = params.multiplier; + shift_value = params.shift; + } + else + { + auto f_rescale_value = 1.0f / static_cast<float>(window_cells); + + shift_value = 0; + while (f_rescale_value < 0.5f) + { + shift_value--; + f_rescale_value *= 2.0f; + } + + rescale_value = static_cast<int32_t>(round(f_rescale_value * static_cast<float>(1ll << 31))); + if (static_cast<int64_t>(rescale_value) == (1ll << 31)) + { + shift_value++; + rescale_value >>= 1; + } + } + + // Combine together the rescale value for the requantization and the scaling + // factor for the average pool. + const int32_t shift = qp.per_layer_left_shift - qp.per_layer_right_shift + shift_value; + const int32_t left_shift = shift > 0 ? shift : 0; + const int32_t right_shift = shift <= 0 ? shift : 0; + + int32_t combined_rescale_value = 0; + __asm__ __volatile__ ( + "mov v16.s[0], %w[per_layer_mul]\n" + "mov v17.s[0], %w[rescale_value]\n" + "sqrdmulh s18, s16, s17\n" + "mov %w[combined_rescale_value], v18.s[0]\n" + : [combined_rescale_value] "=r" (combined_rescale_value) + : [per_layer_mul] "r" (qp.per_layer_mul), [rescale_value] "r" (rescale_value) + : "v16", "v17", "v18" + ); + + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "mov x26, #0x0\n" + "cntb x25\n" + "cntb x24, ALL, MUL #2\n" + "cntb x23, ALL, MUL #3\n" + "whilelt p4.b, x26, %x[n_channels]\n" + "whilelt p3.b, x25, %x[n_channels]\n" + "whilelt p2.b, x24, %x[n_channels]\n" + "whilelt p1.b, x23, %x[n_channels]\n" + "ptrue p0.b\n" + "b.none 7f\n" + "1:" // 4-vectors of channels + "lsr x22, %x[n_valid_cells], #0x1\n" + "mov z15.s, #0x0\n" + "mov z14.s, #0x0\n" + "mov x19, %x[inptrs]\n" + "mov z13.s, #0x0\n" + "mov z12.s, #0x0\n" + "mov z11.s, #0x0\n" + "mov z10.s, #0x0\n" + "mov z9.s, #0x0\n" + "mov z8.s, #0x0\n" + "mov z7.s, #0x0\n" + "mov z6.s, #0x0\n" + "mov z5.s, #0x0\n" + "mov z4.s, #0x0\n" + "mov z3.s, #0x0\n" + "mov z2.s, #0x0\n" + "mov z1.s, #0x0\n" + "mov z0.s, #0x0\n" + "cbz x22, 4f\n" + "ldp x21, x20, [x19, #0x0]\n" + "subs x22, x22, #0x1\n" + "add x19, x19, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x26]\n" + "ld1b { z30.b }, p4/Z, [x20, x26]\n" + "ld1b { z29.b }, p3/Z, [x21, x25]\n" + "ld1b { z28.b }, p3/Z, [x20, x25]\n" + "ld1b { z27.b }, p2/Z, [x21, x24]\n" + "ld1b { z26.b }, p2/Z, [x20, x24]\n" + "ld1b { z25.b }, p1/Z, [x21, x23]\n" + "ld1b { z24.b }, p1/Z, [x20, x23]\n" + "beq 3f\n" + "2:" // 4-vectors of channels: 2 inputs loop + ".inst 0x455e03f7 // saddlb z23.h, z31.b, z30.b\n" + ".inst 0x455e07f6 // saddlt z22.h, z31.b, z30.b\n" + "ldp x21, x20, [x19, #0x0]\n" + "subs x22, x22, #0x1\n" + ".inst 0x455c03b5 // saddlb z21.h, z29.b, z28.b\n" + ".inst 0x455c07b4 // saddlt z20.h, z29.b, z28.b\n" + "add x19, x19, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x26]\n" + ".inst 0x455a0373 // saddlb z19.h, z27.b, z26.b\n" + ".inst 0x455a0772 // saddlt z18.h, z27.b, z26.b\n" + "ld1b { z30.b }, p4/Z, [x20, x26]\n" + ".inst 0x45580331 // saddlb z17.h, z25.b, z24.b\n" + ".inst 0x45580730 // saddlt z16.h, z25.b, z24.b\n" + "ld1b { z29.b }, p3/Z, [x21, x25]\n" + ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" + ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" + "ld1b { z28.b }, p3/Z, [x20, x25]\n" + ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" + ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" + "ld1b { z27.b }, p2/Z, [x21, x24]\n" + ".inst 0x4595416b // saddwb z11.s, z11.s, z21.h\n" + ".inst 0x4595454a // saddwt z10.s, z10.s, z21.h\n" + "ld1b { z26.b }, p2/Z, [x20, x24]\n" + ".inst 0x45944129 // saddwb z9.s, z9.s, z20.h\n" + ".inst 0x45944508 // saddwt z8.s, z8.s, z20.h\n" + "ld1b { z25.b }, p1/Z, [x21, x23]\n" + ".inst 0x459340e7 // saddwb z7.s, z7.s, z19.h\n" + ".inst 0x459344c6 // saddwt z6.s, z6.s, z19.h\n" + "ld1b { z24.b }, p1/Z, [x20, x23]\n" + ".inst 0x459240a5 // saddwb z5.s, z5.s, z18.h\n" + ".inst 0x45924484 // saddwt z4.s, z4.s, z18.h\n" + ".inst 0x45914063 // saddwb z3.s, z3.s, z17.h\n" + ".inst 0x45914442 // saddwt z2.s, z2.s, z17.h\n" + ".inst 0x45904021 // saddwb z1.s, z1.s, z16.h\n" + ".inst 0x45904400 // saddwt z0.s, z0.s, z16.h\n" + "bgt 2b\n" + "3:" // 4-vectors of channels: 2 inputs tail + ".inst 0x455e03f7 // saddlb z23.h, z31.b, z30.b\n" + ".inst 0x455e07f6 // saddlt z22.h, z31.b, z30.b\n" + ".inst 0x455c03b5 // saddlb z21.h, z29.b, z28.b\n" + ".inst 0x455c07b4 // saddlt z20.h, z29.b, z28.b\n" + ".inst 0x455a0373 // saddlb z19.h, z27.b, z26.b\n" + ".inst 0x455a0772 // saddlt z18.h, z27.b, z26.b\n" + ".inst 0x45580331 // saddlb z17.h, z25.b, z24.b\n" + ".inst 0x45580730 // saddlt z16.h, z25.b, z24.b\n" + ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" + ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" + ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" + ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" + ".inst 0x4595416b // saddwb z11.s, z11.s, z21.h\n" + ".inst 0x4595454a // saddwt z10.s, z10.s, z21.h\n" + ".inst 0x45944129 // saddwb z9.s, z9.s, z20.h\n" + ".inst 0x45944508 // saddwt z8.s, z8.s, z20.h\n" + ".inst 0x459340e7 // saddwb z7.s, z7.s, z19.h\n" + ".inst 0x459344c6 // saddwt z6.s, z6.s, z19.h\n" + ".inst 0x459240a5 // saddwb z5.s, z5.s, z18.h\n" + ".inst 0x45924484 // saddwt z4.s, z4.s, z18.h\n" + ".inst 0x45914063 // saddwb z3.s, z3.s, z17.h\n" + ".inst 0x45914442 // saddwt z2.s, z2.s, z17.h\n" + ".inst 0x45904021 // saddwb z1.s, z1.s, z16.h\n" + ".inst 0x45904400 // saddwt z0.s, z0.s, z16.h\n" + "4:" // 4-vectors of channels: After loop + "ands x20, %x[n_valid_cells], #0x1\n" + "beq 6f\n" + "5:" // 4-vectors of channels: Single input loop + "ldr x21, [x19], #0x8\n" + "ld1b { z31.b }, p4/Z, [x21, x26]\n" + ".inst 0x4508a3f7 // sshllb z23.h, z31.b, #0x0\n" + ".inst 0x4508a7f6 // sshllt z22.h, z31.b, #0x0\n" + "ld1b { z29.b }, p3/Z, [x21, x25]\n" + ".inst 0x4508a3b5 // sshllb z21.h, z29.b, #0x0\n" + ".inst 0x4508a7b4 // sshllt z20.h, z29.b, #0x0\n" + "subs x20, x20, #0x1\n" + "ld1b { z27.b }, p2/Z, [x21, x24]\n" + ".inst 0x4508a373 // sshllb z19.h, z27.b, #0x0\n" + ".inst 0x4508a772 // sshllt z18.h, z27.b, #0x0\n" + "ld1b { z25.b }, p1/Z, [x21, x23]\n" + ".inst 0x4508a331 // sshllb z17.h, z25.b, #0x0\n" + ".inst 0x4508a730 // sshllt z16.h, z25.b, #0x0\n" + ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" + ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" + ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" + ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" + ".inst 0x4595416b // saddwb z11.s, z11.s, z21.h\n" + ".inst 0x4595454a // saddwt z10.s, z10.s, z21.h\n" + ".inst 0x45944129 // saddwb z9.s, z9.s, z20.h\n" + ".inst 0x45944508 // saddwt z8.s, z8.s, z20.h\n" + ".inst 0x459340e7 // saddwb z7.s, z7.s, z19.h\n" + ".inst 0x459344c6 // saddwt z6.s, z6.s, z19.h\n" + ".inst 0x459240a5 // saddwb z5.s, z5.s, z18.h\n" + ".inst 0x45924484 // saddwt z4.s, z4.s, z18.h\n" + ".inst 0x45914063 // saddwb z3.s, z3.s, z17.h\n" + ".inst 0x45914442 // saddwt z2.s, z2.s, z17.h\n" + ".inst 0x45904021 // saddwb z1.s, z1.s, z16.h\n" + ".inst 0x45904400 // saddwt z0.s, z0.s, z16.h\n" + "bgt 5b\n" + "6:" // 4-vectors of channels: Single input loop: End + "ld1rw { z18.s }, p0/Z, [%x[left_shift]]\n" + ".inst 0x4482824f // srshl z15.s, p0/M, z15.s, z18.s\n" + ".inst 0x4482824e // srshl z14.s, p0/M, z14.s, z18.s\n" + ".inst 0x4482824d // srshl z13.s, p0/M, z13.s, z18.s\n" + ".inst 0x4482824c // srshl z12.s, p0/M, z12.s, z18.s\n" + "ld1rw { z17.s }, p0/Z, [%x[combined_rescale_value]]\n" + ".inst 0x4482824b // srshl z11.s, p0/M, z11.s, z18.s\n" + ".inst 0x4482824a // srshl z10.s, p0/M, z10.s, z18.s\n" + "ld1rw { z16.s }, p0/Z, [%x[right_shift]]\n" + ".inst 0x44828249 // srshl z9.s, p0/M, z9.s, z18.s\n" + ".inst 0x44828248 // srshl z8.s, p0/M, z8.s, z18.s\n" + ".inst 0x44828247 // srshl z7.s, p0/M, z7.s, z18.s\n" + ".inst 0x44828246 // srshl z6.s, p0/M, z6.s, z18.s\n" + ".inst 0x44828245 // srshl z5.s, p0/M, z5.s, z18.s\n" + ".inst 0x44828244 // srshl z4.s, p0/M, z4.s, z18.s\n" + ".inst 0x44828243 // srshl z3.s, p0/M, z3.s, z18.s\n" + ".inst 0x44828242 // srshl z2.s, p0/M, z2.s, z18.s\n" + ".inst 0x44828241 // srshl z1.s, p0/M, z1.s, z18.s\n" + ".inst 0x44828240 // srshl z0.s, p0/M, z0.s, z18.s\n" + ".inst 0x04b175ef // sqrdmulh z15.s, z15.s, z17.s\n" + ".inst 0x04b175ce // sqrdmulh z14.s, z14.s, z17.s\n" + ".inst 0x04b175ad // sqrdmulh z13.s, z13.s, z17.s\n" + ".inst 0x04b1758c // sqrdmulh z12.s, z12.s, z17.s\n" + ".inst 0x04b1756b // sqrdmulh z11.s, z11.s, z17.s\n" + ".inst 0x04b1754a // sqrdmulh z10.s, z10.s, z17.s\n" + ".inst 0x04b17529 // sqrdmulh z9.s, z9.s, z17.s\n" + ".inst 0x04b17508 // sqrdmulh z8.s, z8.s, z17.s\n" + ".inst 0x04b174e7 // sqrdmulh z7.s, z7.s, z17.s\n" + ".inst 0x04b174c6 // sqrdmulh z6.s, z6.s, z17.s\n" + ".inst 0x04b174a5 // sqrdmulh z5.s, z5.s, z17.s\n" + ".inst 0x04b17484 // sqrdmulh z4.s, z4.s, z17.s\n" + ".inst 0x04b17463 // sqrdmulh z3.s, z3.s, z17.s\n" + ".inst 0x04b17442 // sqrdmulh z2.s, z2.s, z17.s\n" + ".inst 0x04b17421 // sqrdmulh z1.s, z1.s, z17.s\n" + ".inst 0x04b17400 // sqrdmulh z0.s, z0.s, z17.s\n" + "mov z19.s, #0x7f\n" + ".inst 0x4482820f // srshl z15.s, p0/M, z15.s, z16.s\n" + ".inst 0x4482820e // srshl z14.s, p0/M, z14.s, z16.s\n" + ".inst 0x4482820d // srshl z13.s, p0/M, z13.s, z16.s\n" + ".inst 0x4482820c // srshl z12.s, p0/M, z12.s, z16.s\n" + ".inst 0x4482820b // srshl z11.s, p0/M, z11.s, z16.s\n" + ".inst 0x4482820a // srshl z10.s, p0/M, z10.s, z16.s\n" + ".inst 0x44828209 // srshl z9.s, p0/M, z9.s, z16.s\n" + ".inst 0x44828208 // srshl z8.s, p0/M, z8.s, z16.s\n" + ".inst 0x44828207 // srshl z7.s, p0/M, z7.s, z16.s\n" + ".inst 0x44828206 // srshl z6.s, p0/M, z6.s, z16.s\n" + ".inst 0x44828205 // srshl z5.s, p0/M, z5.s, z16.s\n" + ".inst 0x44828204 // srshl z4.s, p0/M, z4.s, z16.s\n" + ".inst 0x44828203 // srshl z3.s, p0/M, z3.s, z16.s\n" + ".inst 0x44828202 // srshl z2.s, p0/M, z2.s, z16.s\n" + ".inst 0x44828201 // srshl z1.s, p0/M, z1.s, z16.s\n" + ".inst 0x44828200 // srshl z0.s, p0/M, z0.s, z16.s\n" + "not z16.s, p0/M, z19.s\n" + "smax z15.s, p0/M, z15.s, z16.s\n" + "smax z14.s, p0/M, z14.s, z16.s\n" + "smax z13.s, p0/M, z13.s, z16.s\n" + "smax z12.s, p0/M, z12.s, z16.s\n" + "smax z11.s, p0/M, z11.s, z16.s\n" + "smax z10.s, p0/M, z10.s, z16.s\n" + "smax z9.s, p0/M, z9.s, z16.s\n" + "smax z8.s, p0/M, z8.s, z16.s\n" + "smax z7.s, p0/M, z7.s, z16.s\n" + "smax z6.s, p0/M, z6.s, z16.s\n" + "smax z5.s, p0/M, z5.s, z16.s\n" + "smax z4.s, p0/M, z4.s, z16.s\n" + "smax z3.s, p0/M, z3.s, z16.s\n" + "smax z2.s, p0/M, z2.s, z16.s\n" + "smax z1.s, p0/M, z1.s, z16.s\n" + "smax z0.s, p0/M, z0.s, z16.s\n" + "smin z15.s, p0/M, z15.s, z19.s\n" + "smin z14.s, p0/M, z14.s, z19.s\n" + "trn1 z23.h, z15.h, z14.h\n" + "smin z13.s, p0/M, z13.s, z19.s\n" + "smin z12.s, p0/M, z12.s, z19.s\n" + "trn1 z16.h, z13.h, z12.h\n" + "smin z11.s, p0/M, z11.s, z19.s\n" + "smin z10.s, p0/M, z10.s, z19.s\n" + "trn1 z22.h, z11.h, z10.h\n" + "smin z9.s, p0/M, z9.s, z19.s\n" + "smin z8.s, p0/M, z8.s, z19.s\n" + "trn1 z18.h, z9.h, z8.h\n" + "smin z7.s, p0/M, z7.s, z19.s\n" + "smin z6.s, p0/M, z6.s, z19.s\n" + "trn1 z21.h, z7.h, z6.h\n" + "smin z5.s, p0/M, z5.s, z19.s\n" + "smin z4.s, p0/M, z4.s, z19.s\n" + "trn1 z17.h, z5.h, z4.h\n" + "smin z3.s, p0/M, z3.s, z19.s\n" + "smin z2.s, p0/M, z2.s, z19.s\n" + "trn1 z20.h, z3.h, z2.h\n" + "smin z1.s, p0/M, z1.s, z19.s\n" + "smin z0.s, p0/M, z0.s, z19.s\n" + "trn1 z19.h, z1.h, z0.h\n" + "trn1 z16.b, z23.b, z16.b\n" + "trn1 z18.b, z22.b, z18.b\n" + "st1b { z16.b }, p4, [%x[outptr], x26]\n" + "incb x26, ALL, MUL #4\n" + "trn1 z17.b, z21.b, z17.b\n" + "trn1 z16.b, z20.b, z19.b\n" + "st1b { z18.b }, p3, [%x[outptr], x25]\n" + "incb x25, ALL, MUL #4\n" + "st1b { z17.b }, p2, [%x[outptr], x24]\n" + "incb x24, ALL, MUL #4\n" + "st1b { z16.b }, p1, [%x[outptr], x23]\n" + "incb x23, ALL, MUL #4\n" + "whilelt p1.b, x23, %x[n_channels]\n" + "b.any 1b\n" + "7:" // Single vector of channels + "whilelt p4.b, x26, %x[n_channels]\n" + "b.none 14f\n" + "8:" // Single vector of channels: Loop + "lsr x22, %x[n_valid_cells], #0x1\n" + "mov z15.s, #0x0\n" + "mov z14.s, #0x0\n" + "mov x19, %x[inptrs]\n" + "mov z13.s, #0x0\n" + "mov z12.s, #0x0\n" + "cbz x22, 11f\n" + "ldp x21, x20, [x19, #0x0]\n" + "subs x22, x22, #0x1\n" + "add x19, x19, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x26]\n" + "ld1b { z30.b }, p4/Z, [x20, x26]\n" + "beq 10f\n" + "9:" // Single vector of channels: Loop: 2 inputs loop + ".inst 0x455e03f7 // saddlb z23.h, z31.b, z30.b\n" + ".inst 0x455e07f6 // saddlt z22.h, z31.b, z30.b\n" + "ldp x21, x20, [x19, #0x0]\n" + "subs x22, x22, #0x1\n" + ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" + ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" + "add x19, x19, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x26]\n" + ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" + ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" + "ld1b { z30.b }, p4/Z, [x20, x26]\n" + "bgt 9b\n" + "10:" // Single vector of channels: Loop: 2 inputs tail + ".inst 0x455e03f7 // saddlb z23.h, z31.b, z30.b\n" + ".inst 0x455e07f6 // saddlt z22.h, z31.b, z30.b\n" + ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" + ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" + ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" + ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" + "11:" // Single vector of channels: Loop: After loop + "ands x20, %x[n_valid_cells], #0x1\n" + "beq 13f\n" + "12:" // Single vector of channels: Loop: Single input loop + "ldr x21, [x19], #0x8\n" + "ld1b { z31.b }, p4/Z, [x21, x26]\n" + ".inst 0x4508a3f7 // sshllb z23.h, z31.b, #0x0\n" + ".inst 0x4508a7f6 // sshllt z22.h, z31.b, #0x0\n" + "subs x20, x20, #0x1\n" + ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" + ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" + ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" + ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" + "bgt 12b\n" + "13:" // Single vector of channels: Loop: Single input loop: End + "ld1rw { z18.s }, p0/Z, [%x[left_shift]]\n" + ".inst 0x4482824f // srshl z15.s, p0/M, z15.s, z18.s\n" + ".inst 0x4482824e // srshl z14.s, p0/M, z14.s, z18.s\n" + ".inst 0x4482824d // srshl z13.s, p0/M, z13.s, z18.s\n" + ".inst 0x4482824c // srshl z12.s, p0/M, z12.s, z18.s\n" + "ld1rw { z17.s }, p0/Z, [%x[combined_rescale_value]]\n" + ".inst 0x04b175ef // sqrdmulh z15.s, z15.s, z17.s\n" + ".inst 0x04b175ce // sqrdmulh z14.s, z14.s, z17.s\n" + "ld1rw { z16.s }, p0/Z, [%x[right_shift]]\n" + ".inst 0x04b175ad // sqrdmulh z13.s, z13.s, z17.s\n" + ".inst 0x04b1758c // sqrdmulh z12.s, z12.s, z17.s\n" + "mov z19.s, #0x7f\n" + ".inst 0x4482820f // srshl z15.s, p0/M, z15.s, z16.s\n" + ".inst 0x4482820e // srshl z14.s, p0/M, z14.s, z16.s\n" + ".inst 0x4482820d // srshl z13.s, p0/M, z13.s, z16.s\n" + ".inst 0x4482820c // srshl z12.s, p0/M, z12.s, z16.s\n" + "not z16.s, p0/M, z19.s\n" + "smax z15.s, p0/M, z15.s, z16.s\n" + "smax z14.s, p0/M, z14.s, z16.s\n" + "smax z13.s, p0/M, z13.s, z16.s\n" + "smax z12.s, p0/M, z12.s, z16.s\n" + "smin z15.s, p0/M, z15.s, z19.s\n" + "smin z14.s, p0/M, z14.s, z19.s\n" + "trn1 z23.h, z15.h, z14.h\n" + "smin z13.s, p0/M, z13.s, z19.s\n" + "smin z12.s, p0/M, z12.s, z19.s\n" + "trn1 z16.h, z13.h, z12.h\n" + "trn1 z16.b, z23.b, z16.b\n" + "st1b { z16.b }, p4, [%x[outptr], x26]\n" + "incb x26\n" + "whilelt p4.b, x26, %x[n_channels]\n" + "b.any 8b\n" + "14:" // End + ".inst 0xd503467f // SMSTOP\n" + : + : [combined_rescale_value] "r" (&combined_rescale_value), [inptrs] "r" (inptrs), [left_shift] "r" (&left_shift), [n_channels] "r" (n_channels), [n_valid_cells] "r" (n_valid_cells), [outptr] "r" (outptr), [right_shift] "r" (&right_shift) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8q_nhwc_max_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8q_nhwc_max_generic_depthfirst.hpp new file mode 100644 index 0000000000..050aff397e --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8q_nhwc_max_generic_depthfirst.hpp @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstdint> + +#pragma once + +namespace arm_conv { +namespace pooling { + +void sme_s8q_nhwc_max_generic_depthfirst_impl(const uint64_t, const uint64_t n_valid_cells, uint64_t n_channels, const int8_t *const *const inptrs, int8_t *outptr, const Requantize32 &qp); + +struct sme_s8q_nhwc_max_generic_depthfirst : IGenericDepthfirstStrategy<int8_t, int8_t, Requantize32> +{ + using Parent = IGenericDepthfirstStrategy<int8_t, int8_t, Requantize32>; + sme_s8q_nhwc_max_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return sme_s8q_nhwc_max_generic_depthfirst_impl; } +}; + +} // namespace pooling +} // namespace arm_conv diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8q_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8q_nhwc_max_generic_depthfirst/generic.cpp new file mode 100644 index 0000000000..3d13991b43 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8q_nhwc_max_generic_depthfirst/generic.cpp @@ -0,0 +1,387 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if defined(ARM_COMPUTE_ENABLE_SME) + +#include "src/core/NEON/kernels/assembly/pooling.hpp" +#include <cstdint> + +namespace arm_conv { +namespace pooling { + + +void sme_s8q_nhwc_max_generic_depthfirst_impl( + const uint64_t, + const uint64_t n_valid_cells, + uint64_t n_channels, + const int8_t *const *const inptrs, + int8_t *outptr, + const Requantize32 &qp +) +{ + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "mov x28, #0x0\n" + "cntb x27\n" + "cntb x26, ALL, MUL #2\n" + "cntb x25, ALL, MUL #3\n" + "whilelt p4.b, x28, %x[n_channels]\n" + "whilelt p3.b, x27, %x[n_channels]\n" + "whilelt p2.b, x26, %x[n_channels]\n" + "whilelt p1.b, x25, %x[n_channels]\n" + "ptrue p0.b\n" + "b.none 7f\n" + "1:" // 4-vectors of channels + "lsr x24, %x[n_valid_cells], #0x2\n" + "mov z4.b, #0x80\n" + "mov z3.b, #0x80\n" + "mov x19, %x[inptrs]\n" + "mov z2.b, #0x80\n" + "mov z1.b, #0x80\n" + "cbz x24, 4f\n" + "ldp x23, x22, [x19, #0x0]\n" + "subs x24, x24, #0x1\n" + "ld1b { z0.b }, p4/Z, [x23, x28]\n" + "ldp x21, x20, [x19, #0x10]\n" + "add x19, x19, #0x20\n" + "ld1b { z31.b }, p4/Z, [x22, x28]\n" + "ld1b { z23.b }, p4/Z, [x21, x28]\n" + "ld1b { z30.b }, p4/Z, [x20, x28]\n" + "ld1b { z18.b }, p3/Z, [x23, x27]\n" + "ld1b { z29.b }, p3/Z, [x22, x27]\n" + "ld1b { z22.b }, p3/Z, [x21, x27]\n" + "ld1b { z28.b }, p3/Z, [x20, x27]\n" + "ld1b { z17.b }, p2/Z, [x23, x26]\n" + "ld1b { z27.b }, p2/Z, [x22, x26]\n" + "ld1b { z21.b }, p2/Z, [x21, x26]\n" + "ld1b { z26.b }, p2/Z, [x20, x26]\n" + "ld1b { z16.b }, p1/Z, [x23, x25]\n" + "ld1b { z25.b }, p1/Z, [x22, x25]\n" + "ld1b { z20.b }, p1/Z, [x21, x25]\n" + "ld1b { z24.b }, p1/Z, [x20, x25]\n" + "beq 3f\n" + "2:" // 4-vectors of channels: 4 inputs loop + "movprfx z19, z0\n smax z19.b, p0/M, z19.b, z31.b\n" + "smax z23.b, p0/M, z23.b, z30.b\n" + "ldp x23, x22, [x19, #0x0]\n" + "subs x24, x24, #0x1\n" + "smax z18.b, p0/M, z18.b, z29.b\n" + "smax z22.b, p0/M, z22.b, z28.b\n" + "ldp x21, x20, [x19, #0x10]\n" + "add x19, x19, #0x20\n" + "smax z17.b, p0/M, z17.b, z27.b\n" + "smax z21.b, p0/M, z21.b, z26.b\n" + "ld1b { z0.b }, p4/Z, [x23, x28]\n" + "smax z16.b, p0/M, z16.b, z25.b\n" + "smax z20.b, p0/M, z20.b, z24.b\n" + "ld1b { z31.b }, p4/Z, [x22, x28]\n" + "smax z19.b, p0/M, z19.b, z23.b\n" + "smax z18.b, p0/M, z18.b, z22.b\n" + "ld1b { z23.b }, p4/Z, [x21, x28]\n" + "smax z17.b, p0/M, z17.b, z21.b\n" + "smax z16.b, p0/M, z16.b, z20.b\n" + "ld1b { z30.b }, p4/Z, [x20, x28]\n" + "smax z4.b, p0/M, z4.b, z19.b\n" + "smax z3.b, p0/M, z3.b, z18.b\n" + "ld1b { z18.b }, p3/Z, [x23, x27]\n" + "smax z2.b, p0/M, z2.b, z17.b\n" + "smax z1.b, p0/M, z1.b, z16.b\n" + "ld1b { z29.b }, p3/Z, [x22, x27]\n" + "ld1b { z22.b }, p3/Z, [x21, x27]\n" + "ld1b { z28.b }, p3/Z, [x20, x27]\n" + "ld1b { z17.b }, p2/Z, [x23, x26]\n" + "ld1b { z27.b }, p2/Z, [x22, x26]\n" + "ld1b { z21.b }, p2/Z, [x21, x26]\n" + "ld1b { z26.b }, p2/Z, [x20, x26]\n" + "ld1b { z16.b }, p1/Z, [x23, x25]\n" + "ld1b { z25.b }, p1/Z, [x22, x25]\n" + "ld1b { z20.b }, p1/Z, [x21, x25]\n" + "ld1b { z24.b }, p1/Z, [x20, x25]\n" + "bgt 2b\n" + "3:" // 4-vectors of channels: 4 inputs tail + "movprfx z19, z0\n smax z19.b, p0/M, z19.b, z31.b\n" + "smax z23.b, p0/M, z23.b, z30.b\n" + "smax z18.b, p0/M, z18.b, z29.b\n" + "smax z22.b, p0/M, z22.b, z28.b\n" + "smax z17.b, p0/M, z17.b, z27.b\n" + "smax z21.b, p0/M, z21.b, z26.b\n" + "smax z16.b, p0/M, z16.b, z25.b\n" + "smax z20.b, p0/M, z20.b, z24.b\n" + "smax z19.b, p0/M, z19.b, z23.b\n" + "smax z18.b, p0/M, z18.b, z22.b\n" + "smax z17.b, p0/M, z17.b, z21.b\n" + "smax z16.b, p0/M, z16.b, z20.b\n" + "smax z4.b, p0/M, z4.b, z19.b\n" + "smax z3.b, p0/M, z3.b, z18.b\n" + "smax z2.b, p0/M, z2.b, z17.b\n" + "smax z1.b, p0/M, z1.b, z16.b\n" + "4:" // 4-vectors of channels: After loop + "ands x20, %x[n_valid_cells], #0x3\n" + "beq 6f\n" + "5:" // 4-vectors of channels: Single input loop + "ldr x23, [x19], #0x8\n" + "ld1b { z0.b }, p4/Z, [x23, x28]\n" + "subs x20, x20, #0x1\n" + "smax z4.b, p0/M, z4.b, z0.b\n" + "ld1b { z18.b }, p3/Z, [x23, x27]\n" + "smax z3.b, p0/M, z3.b, z18.b\n" + "ld1b { z17.b }, p2/Z, [x23, x26]\n" + "smax z2.b, p0/M, z2.b, z17.b\n" + "ld1b { z16.b }, p1/Z, [x23, x25]\n" + "smax z1.b, p0/M, z1.b, z16.b\n" + "bgt 5b\n" + "6:" // 4-vectors of channels: Single input loop: End + ".inst 0x4508a097 // sshllb z23.h, z4.b, #0x0\n" + ".inst 0x4508a496 // sshllt z22.h, z4.b, #0x0\n" + "add x19, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n" + "ld1rw { z4.s }, p0/Z, [x19]\n" + ".inst 0x4508a075 // sshllb z21.h, z3.b, #0x0\n" + ".inst 0x4508a472 // sshllt z18.h, z3.b, #0x0\n" + "add x19, %x[quant_params], %[offsetof_qp_per_layer_mul]\n" + "ld1rw { z3.s }, p0/Z, [x19]\n" + ".inst 0x4508a054 // sshllb z20.h, z2.b, #0x0\n" + ".inst 0x4508a451 // sshllt z17.h, z2.b, #0x0\n" + "add x19, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n" + "ld1rw { z2.s }, p0/Z, [x19]\n" + ".inst 0x4508a033 // sshllb z19.h, z1.b, #0x0\n" + ".inst 0x4508a430 // sshllt z16.h, z1.b, #0x0\n" + ".inst 0x4510a2e1 // sshllb z1.s, z23.h, #0x0\n" + ".inst 0x4510a6f7 // sshllt z23.s, z23.h, #0x0\n" + ".inst 0x4510a2c0 // sshllb z0.s, z22.h, #0x0\n" + ".inst 0x4510a6df // sshllt z31.s, z22.h, #0x0\n" + ".inst 0x4510a2be // sshllb z30.s, z21.h, #0x0\n" + ".inst 0x4510a6b6 // sshllt z22.s, z21.h, #0x0\n" + ".inst 0x4510a25d // sshllb z29.s, z18.h, #0x0\n" + ".inst 0x4510a652 // sshllt z18.s, z18.h, #0x0\n" + ".inst 0x4510a29c // sshllb z28.s, z20.h, #0x0\n" + ".inst 0x4510a695 // sshllt z21.s, z20.h, #0x0\n" + ".inst 0x4510a23b // sshllb z27.s, z17.h, #0x0\n" + ".inst 0x4510a631 // sshllt z17.s, z17.h, #0x0\n" + ".inst 0x4510a27a // sshllb z26.s, z19.h, #0x0\n" + ".inst 0x4510a674 // sshllt z20.s, z19.h, #0x0\n" + ".inst 0x4510a219 // sshllb z25.s, z16.h, #0x0\n" + ".inst 0x4510a618 // sshllt z24.s, z16.h, #0x0\n" + ".inst 0x44828081 // srshl z1.s, p0/M, z1.s, z4.s\n" + ".inst 0x44828097 // srshl z23.s, p0/M, z23.s, z4.s\n" + ".inst 0x44828080 // srshl z0.s, p0/M, z0.s, z4.s\n" + ".inst 0x4482809f // srshl z31.s, p0/M, z31.s, z4.s\n" + ".inst 0x4482809e // srshl z30.s, p0/M, z30.s, z4.s\n" + ".inst 0x44828096 // srshl z22.s, p0/M, z22.s, z4.s\n" + ".inst 0x4482809d // srshl z29.s, p0/M, z29.s, z4.s\n" + ".inst 0x44828092 // srshl z18.s, p0/M, z18.s, z4.s\n" + ".inst 0x4482809c // srshl z28.s, p0/M, z28.s, z4.s\n" + ".inst 0x44828095 // srshl z21.s, p0/M, z21.s, z4.s\n" + ".inst 0x4482809b // srshl z27.s, p0/M, z27.s, z4.s\n" + ".inst 0x44828091 // srshl z17.s, p0/M, z17.s, z4.s\n" + ".inst 0x4482809a // srshl z26.s, p0/M, z26.s, z4.s\n" + ".inst 0x44828094 // srshl z20.s, p0/M, z20.s, z4.s\n" + ".inst 0x44828099 // srshl z25.s, p0/M, z25.s, z4.s\n" + ".inst 0x44828098 // srshl z24.s, p0/M, z24.s, z4.s\n" + ".inst 0x04a37421 // sqrdmulh z1.s, z1.s, z3.s\n" + ".inst 0x04a376f7 // sqrdmulh z23.s, z23.s, z3.s\n" + ".inst 0x04a37400 // sqrdmulh z0.s, z0.s, z3.s\n" + ".inst 0x04a377ff // sqrdmulh z31.s, z31.s, z3.s\n" + ".inst 0x04a377de // sqrdmulh z30.s, z30.s, z3.s\n" + ".inst 0x04a376d6 // sqrdmulh z22.s, z22.s, z3.s\n" + ".inst 0x04a377bd // sqrdmulh z29.s, z29.s, z3.s\n" + ".inst 0x04a37652 // sqrdmulh z18.s, z18.s, z3.s\n" + ".inst 0x04a3779c // sqrdmulh z28.s, z28.s, z3.s\n" + ".inst 0x04a376b5 // sqrdmulh z21.s, z21.s, z3.s\n" + ".inst 0x04a3777b // sqrdmulh z27.s, z27.s, z3.s\n" + ".inst 0x04a37631 // sqrdmulh z17.s, z17.s, z3.s\n" + ".inst 0x04a3775a // sqrdmulh z26.s, z26.s, z3.s\n" + ".inst 0x04a37694 // sqrdmulh z20.s, z20.s, z3.s\n" + ".inst 0x04a37739 // sqrdmulh z25.s, z25.s, z3.s\n" + ".inst 0x04a37718 // sqrdmulh z24.s, z24.s, z3.s\n" + "mov z19.s, #0x7f\n" + ".inst 0x44828041 // srshl z1.s, p0/M, z1.s, z2.s\n" + ".inst 0x44828057 // srshl z23.s, p0/M, z23.s, z2.s\n" + ".inst 0x44828040 // srshl z0.s, p0/M, z0.s, z2.s\n" + ".inst 0x4482805f // srshl z31.s, p0/M, z31.s, z2.s\n" + ".inst 0x4482805e // srshl z30.s, p0/M, z30.s, z2.s\n" + ".inst 0x44828056 // srshl z22.s, p0/M, z22.s, z2.s\n" + ".inst 0x4482805d // srshl z29.s, p0/M, z29.s, z2.s\n" + ".inst 0x44828052 // srshl z18.s, p0/M, z18.s, z2.s\n" + ".inst 0x4482805c // srshl z28.s, p0/M, z28.s, z2.s\n" + ".inst 0x44828055 // srshl z21.s, p0/M, z21.s, z2.s\n" + ".inst 0x4482805b // srshl z27.s, p0/M, z27.s, z2.s\n" + ".inst 0x44828051 // srshl z17.s, p0/M, z17.s, z2.s\n" + ".inst 0x4482805a // srshl z26.s, p0/M, z26.s, z2.s\n" + ".inst 0x44828054 // srshl z20.s, p0/M, z20.s, z2.s\n" + ".inst 0x44828059 // srshl z25.s, p0/M, z25.s, z2.s\n" + ".inst 0x44828058 // srshl z24.s, p0/M, z24.s, z2.s\n" + "not z16.s, p0/M, z19.s\n" + "smax z1.s, p0/M, z1.s, z16.s\n" + "smax z23.s, p0/M, z23.s, z16.s\n" + "smax z0.s, p0/M, z0.s, z16.s\n" + "smax z31.s, p0/M, z31.s, z16.s\n" + "smax z30.s, p0/M, z30.s, z16.s\n" + "smax z22.s, p0/M, z22.s, z16.s\n" + "smax z29.s, p0/M, z29.s, z16.s\n" + "smax z18.s, p0/M, z18.s, z16.s\n" + "smax z28.s, p0/M, z28.s, z16.s\n" + "smax z21.s, p0/M, z21.s, z16.s\n" + "smax z27.s, p0/M, z27.s, z16.s\n" + "smax z17.s, p0/M, z17.s, z16.s\n" + "smax z26.s, p0/M, z26.s, z16.s\n" + "smax z20.s, p0/M, z20.s, z16.s\n" + "smax z25.s, p0/M, z25.s, z16.s\n" + "smax z24.s, p0/M, z24.s, z16.s\n" + "smin z1.s, p0/M, z1.s, z19.s\n" + "smin z23.s, p0/M, z23.s, z19.s\n" + "trn1 z23.h, z1.h, z23.h\n" + "smin z0.s, p0/M, z0.s, z19.s\n" + "smin z31.s, p0/M, z31.s, z19.s\n" + "trn1 z16.h, z0.h, z31.h\n" + "smin z30.s, p0/M, z30.s, z19.s\n" + "smin z22.s, p0/M, z22.s, z19.s\n" + "trn1 z22.h, z30.h, z22.h\n" + "smin z29.s, p0/M, z29.s, z19.s\n" + "smin z18.s, p0/M, z18.s, z19.s\n" + "trn1 z18.h, z29.h, z18.h\n" + "smin z28.s, p0/M, z28.s, z19.s\n" + "smin z21.s, p0/M, z21.s, z19.s\n" + "trn1 z21.h, z28.h, z21.h\n" + "smin z27.s, p0/M, z27.s, z19.s\n" + "smin z17.s, p0/M, z17.s, z19.s\n" + "trn1 z17.h, z27.h, z17.h\n" + "smin z26.s, p0/M, z26.s, z19.s\n" + "smin z20.s, p0/M, z20.s, z19.s\n" + "trn1 z20.h, z26.h, z20.h\n" + "smin z25.s, p0/M, z25.s, z19.s\n" + "smin z24.s, p0/M, z24.s, z19.s\n" + "trn1 z19.h, z25.h, z24.h\n" + "trn1 z16.b, z23.b, z16.b\n" + "trn1 z18.b, z22.b, z18.b\n" + "st1b { z16.b }, p4, [%x[outptr], x28]\n" + "incb x28, ALL, MUL #4\n" + "trn1 z17.b, z21.b, z17.b\n" + "trn1 z16.b, z20.b, z19.b\n" + "st1b { z18.b }, p3, [%x[outptr], x27]\n" + "incb x27, ALL, MUL #4\n" + "st1b { z17.b }, p2, [%x[outptr], x26]\n" + "incb x26, ALL, MUL #4\n" + "st1b { z16.b }, p1, [%x[outptr], x25]\n" + "incb x25, ALL, MUL #4\n" + "whilelt p1.b, x25, %x[n_channels]\n" + "b.any 1b\n" + "7:" // Single vector of channels + "whilelt p4.b, x28, %x[n_channels]\n" + "b.none 14f\n" + "8:" // Single vector of channels: Loop + "lsr x24, %x[n_valid_cells], #0x2\n" + "mov z4.b, #0x80\n" + "mov x19, %x[inptrs]\n" + "cbz x24, 11f\n" + "ldp x23, x22, [x19, #0x0]\n" + "subs x24, x24, #0x1\n" + "ld1b { z0.b }, p4/Z, [x23, x28]\n" + "ldp x21, x20, [x19, #0x10]\n" + "add x19, x19, #0x20\n" + "ld1b { z31.b }, p4/Z, [x22, x28]\n" + "ld1b { z23.b }, p4/Z, [x21, x28]\n" + "ld1b { z30.b }, p4/Z, [x20, x28]\n" + "beq 10f\n" + "9:" // Single vector of channels: Loop: 4 inputs loop + "movprfx z19, z0\n smax z19.b, p0/M, z19.b, z31.b\n" + "smax z23.b, p0/M, z23.b, z30.b\n" + "ldp x23, x22, [x19, #0x0]\n" + "subs x24, x24, #0x1\n" + "smax z19.b, p0/M, z19.b, z23.b\n" + "ldp x21, x20, [x19, #0x10]\n" + "smax z4.b, p0/M, z4.b, z19.b\n" + "add x19, x19, #0x20\n" + "ld1b { z0.b }, p4/Z, [x23, x28]\n" + "ld1b { z31.b }, p4/Z, [x22, x28]\n" + "ld1b { z23.b }, p4/Z, [x21, x28]\n" + "ld1b { z30.b }, p4/Z, [x20, x28]\n" + "bgt 9b\n" + "10:" // Single vector of channels: Loop: 4 inputs tail + "movprfx z19, z0\n smax z19.b, p0/M, z19.b, z31.b\n" + "smax z23.b, p0/M, z23.b, z30.b\n" + "smax z19.b, p0/M, z19.b, z23.b\n" + "smax z4.b, p0/M, z4.b, z19.b\n" + "11:" // Single vector of channels: Loop: After loop + "ands x20, %x[n_valid_cells], #0x3\n" + "beq 13f\n" + "12:" // Single vector of channels: Loop: Single input loop + "ldr x23, [x19], #0x8\n" + "ld1b { z0.b }, p4/Z, [x23, x28]\n" + "subs x20, x20, #0x1\n" + "smax z4.b, p0/M, z4.b, z0.b\n" + "bgt 12b\n" + "13:" // Single vector of channels: Loop: Single input loop: End + ".inst 0x4508a097 // sshllb z23.h, z4.b, #0x0\n" + ".inst 0x4508a496 // sshllt z22.h, z4.b, #0x0\n" + "add x19, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n" + "ld1rw { z4.s }, p0/Z, [x19]\n" + ".inst 0x4510a2e1 // sshllb z1.s, z23.h, #0x0\n" + ".inst 0x4510a6f7 // sshllt z23.s, z23.h, #0x0\n" + "add x19, %x[quant_params], %[offsetof_qp_per_layer_mul]\n" + "ld1rw { z3.s }, p0/Z, [x19]\n" + ".inst 0x4510a2c0 // sshllb z0.s, z22.h, #0x0\n" + ".inst 0x4510a6df // sshllt z31.s, z22.h, #0x0\n" + "add x19, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n" + "ld1rw { z2.s }, p0/Z, [x19]\n" + ".inst 0x44828081 // srshl z1.s, p0/M, z1.s, z4.s\n" + ".inst 0x44828097 // srshl z23.s, p0/M, z23.s, z4.s\n" + ".inst 0x44828080 // srshl z0.s, p0/M, z0.s, z4.s\n" + ".inst 0x4482809f // srshl z31.s, p0/M, z31.s, z4.s\n" + ".inst 0x04a37421 // sqrdmulh z1.s, z1.s, z3.s\n" + ".inst 0x04a376f7 // sqrdmulh z23.s, z23.s, z3.s\n" + ".inst 0x04a37400 // sqrdmulh z0.s, z0.s, z3.s\n" + ".inst 0x04a377ff // sqrdmulh z31.s, z31.s, z3.s\n" + "mov z19.s, #0x7f\n" + ".inst 0x44828041 // srshl z1.s, p0/M, z1.s, z2.s\n" + ".inst 0x44828057 // srshl z23.s, p0/M, z23.s, z2.s\n" + ".inst 0x44828040 // srshl z0.s, p0/M, z0.s, z2.s\n" + ".inst 0x4482805f // srshl z31.s, p0/M, z31.s, z2.s\n" + "not z16.s, p0/M, z19.s\n" + "smax z1.s, p0/M, z1.s, z16.s\n" + "smax z23.s, p0/M, z23.s, z16.s\n" + "smax z0.s, p0/M, z0.s, z16.s\n" + "smax z31.s, p0/M, z31.s, z16.s\n" + "smin z1.s, p0/M, z1.s, z19.s\n" + "smin z23.s, p0/M, z23.s, z19.s\n" + "trn1 z23.h, z1.h, z23.h\n" + "smin z0.s, p0/M, z0.s, z19.s\n" + "smin z31.s, p0/M, z31.s, z19.s\n" + "trn1 z16.h, z0.h, z31.h\n" + "trn1 z16.b, z23.b, z16.b\n" + "st1b { z16.b }, p4, [%x[outptr], x28]\n" + "incb x28\n" + "whilelt p4.b, x28, %x[n_channels]\n" + "b.any 8b\n" + "14:" // End + ".inst 0xd503467f // SMSTOP\n" + : + : [inptrs] "r" (inptrs), [n_channels] "r" (n_channels), [n_valid_cells] "r" (n_valid_cells), [offsetof_qp_per_layer_left_shift] "I" (offsetof(Requantize32, per_layer_left_shift)), [offsetof_qp_per_layer_mul] "I" (offsetof(Requantize32, per_layer_mul)), [offsetof_qp_per_layer_right_shift] "I" (offsetof(Requantize32, per_layer_right_shift)), [outptr] "r" (outptr), [quant_params] "r" (&qp) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_avg_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_avg_generic_depthfirst.hpp new file mode 100644 index 0000000000..2cdb2883c2 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_avg_generic_depthfirst.hpp @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstdint> + +#pragma once + +namespace arm_conv { +namespace pooling { + +void sme_u8_nhwc_avg_generic_depthfirst_impl(const uint64_t window_cells, const uint64_t n_valid_cells, uint64_t n_channels, const uint8_t *const *const inptrs, uint8_t *outptr); + +struct sme_u8_nhwc_avg_generic_depthfirst : IGenericDepthfirstStrategy<uint8_t, uint8_t> +{ + using Parent = IGenericDepthfirstStrategy<uint8_t, uint8_t>; + sme_u8_nhwc_avg_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return sme_u8_nhwc_avg_generic_depthfirst_impl; } +}; + +} // namespace pooling +} // namespace arm_conv diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_avg_generic_depthfirst/generic.cpp new file mode 100644 index 0000000000..e529e4c4d0 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_avg_generic_depthfirst/generic.cpp @@ -0,0 +1,417 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if defined(ARM_COMPUTE_ENABLE_SME) + +#include <cstdint> +#include <cstring> +#include <cmath> + + +namespace arm_conv { +namespace pooling { + +namespace { + struct RescaleParams + { + int32_t multiplier, shift; + }; + + constexpr RescaleParams rescale_params[8] = { + {0x40000000, -0}, // 1/2 + {0x55555556, -1}, // 1/3 + {0x40000000, -1}, // 1/4 + {0x66666666, -2}, // 1/5 + {0x55555556, -2}, // 1/6 + {0x49249249, -2}, // 1/7 + {0x40000000, -2}, // 1/8 + {0x71c71c72, -3}, // 1/9 + }; +} + +void sme_u8_nhwc_avg_generic_depthfirst_impl( + const uint64_t window_cells, + const uint64_t n_valid_cells, + uint64_t n_channels, + const uint8_t *const *const inptrs, + uint8_t *outptr +) +{ + if (n_valid_cells == 1 && window_cells == 1) + { + // In this case, simply copy from the input to the output + std::memcpy(outptr, *inptrs, n_channels); + return; + } + + // Compute (or look up) the rescale values + int32_t shift_value = 0, rescale_value = 0; + if (2 <= window_cells && window_cells <= 9) + { + auto ¶ms = rescale_params[window_cells - 2]; + rescale_value = params.multiplier; + shift_value = params.shift; + } + else + { + auto f_rescale_value = 1.0f / static_cast<float>(window_cells); + + shift_value = 0; + while (f_rescale_value < 0.5f) + { + shift_value--; + f_rescale_value *= 2.0f; + } + + rescale_value = static_cast<int32_t>(round(f_rescale_value * static_cast<float>(1ll << 31))); + if (static_cast<int64_t>(rescale_value) == (1ll << 31)) + { + shift_value++; + rescale_value >>= 1; + } + } + + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "mov x26, #0x0\n" + "cntb x25\n" + "cntb x24, ALL, MUL #2\n" + "cntb x23, ALL, MUL #3\n" + "whilelt p4.b, x26, %x[n_channels]\n" + "whilelt p3.b, x25, %x[n_channels]\n" + "whilelt p2.b, x24, %x[n_channels]\n" + "whilelt p1.b, x23, %x[n_channels]\n" + "ptrue p0.b\n" + "b.none 7f\n" + "1:" // 4-vectors of channels + "lsr x22, %x[n_valid_cells], #0x1\n" + "mov z15.s, #0x0\n" + "mov z14.s, #0x0\n" + "mov x19, %x[inptrs]\n" + "mov z13.s, #0x0\n" + "mov z12.s, #0x0\n" + "mov z11.s, #0x0\n" + "mov z10.s, #0x0\n" + "mov z9.s, #0x0\n" + "mov z8.s, #0x0\n" + "mov z7.s, #0x0\n" + "mov z6.s, #0x0\n" + "mov z5.s, #0x0\n" + "mov z4.s, #0x0\n" + "mov z3.s, #0x0\n" + "mov z2.s, #0x0\n" + "mov z1.s, #0x0\n" + "mov z0.s, #0x0\n" + "cbz x22, 4f\n" + "ldp x21, x20, [x19, #0x0]\n" + "subs x22, x22, #0x1\n" + "add x19, x19, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x26]\n" + "ld1b { z30.b }, p4/Z, [x20, x26]\n" + "ld1b { z29.b }, p3/Z, [x21, x25]\n" + "ld1b { z28.b }, p3/Z, [x20, x25]\n" + "ld1b { z27.b }, p2/Z, [x21, x24]\n" + "ld1b { z26.b }, p2/Z, [x20, x24]\n" + "ld1b { z25.b }, p1/Z, [x21, x23]\n" + "ld1b { z24.b }, p1/Z, [x20, x23]\n" + "beq 3f\n" + "2:" // 4-vectors of channels: 2 inputs loop + ".inst 0x455e0bf7 // uaddlb z23.h, z31.b, z30.b\n" + ".inst 0x455e0ff6 // uaddlt z22.h, z31.b, z30.b\n" + "ldp x21, x20, [x19, #0x0]\n" + "subs x22, x22, #0x1\n" + ".inst 0x455c0bb5 // uaddlb z21.h, z29.b, z28.b\n" + ".inst 0x455c0fb4 // uaddlt z20.h, z29.b, z28.b\n" + "add x19, x19, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x26]\n" + ".inst 0x455a0b73 // uaddlb z19.h, z27.b, z26.b\n" + ".inst 0x455a0f72 // uaddlt z18.h, z27.b, z26.b\n" + "ld1b { z30.b }, p4/Z, [x20, x26]\n" + ".inst 0x45580b31 // uaddlb z17.h, z25.b, z24.b\n" + ".inst 0x45580f30 // uaddlt z16.h, z25.b, z24.b\n" + "ld1b { z29.b }, p3/Z, [x21, x25]\n" + ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" + ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" + "ld1b { z28.b }, p3/Z, [x20, x25]\n" + ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" + ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" + "ld1b { z27.b }, p2/Z, [x21, x24]\n" + ".inst 0x4595496b // uaddwb z11.s, z11.s, z21.h\n" + ".inst 0x45954d4a // uaddwt z10.s, z10.s, z21.h\n" + "ld1b { z26.b }, p2/Z, [x20, x24]\n" + ".inst 0x45944929 // uaddwb z9.s, z9.s, z20.h\n" + ".inst 0x45944d08 // uaddwt z8.s, z8.s, z20.h\n" + "ld1b { z25.b }, p1/Z, [x21, x23]\n" + ".inst 0x459348e7 // uaddwb z7.s, z7.s, z19.h\n" + ".inst 0x45934cc6 // uaddwt z6.s, z6.s, z19.h\n" + "ld1b { z24.b }, p1/Z, [x20, x23]\n" + ".inst 0x459248a5 // uaddwb z5.s, z5.s, z18.h\n" + ".inst 0x45924c84 // uaddwt z4.s, z4.s, z18.h\n" + ".inst 0x45914863 // uaddwb z3.s, z3.s, z17.h\n" + ".inst 0x45914c42 // uaddwt z2.s, z2.s, z17.h\n" + ".inst 0x45904821 // uaddwb z1.s, z1.s, z16.h\n" + ".inst 0x45904c00 // uaddwt z0.s, z0.s, z16.h\n" + "bgt 2b\n" + "3:" // 4-vectors of channels: 2 inputs tail + ".inst 0x455e0bf7 // uaddlb z23.h, z31.b, z30.b\n" + ".inst 0x455e0ff6 // uaddlt z22.h, z31.b, z30.b\n" + ".inst 0x455c0bb5 // uaddlb z21.h, z29.b, z28.b\n" + ".inst 0x455c0fb4 // uaddlt z20.h, z29.b, z28.b\n" + ".inst 0x455a0b73 // uaddlb z19.h, z27.b, z26.b\n" + ".inst 0x455a0f72 // uaddlt z18.h, z27.b, z26.b\n" + ".inst 0x45580b31 // uaddlb z17.h, z25.b, z24.b\n" + ".inst 0x45580f30 // uaddlt z16.h, z25.b, z24.b\n" + ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" + ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" + ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" + ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" + ".inst 0x4595496b // uaddwb z11.s, z11.s, z21.h\n" + ".inst 0x45954d4a // uaddwt z10.s, z10.s, z21.h\n" + ".inst 0x45944929 // uaddwb z9.s, z9.s, z20.h\n" + ".inst 0x45944d08 // uaddwt z8.s, z8.s, z20.h\n" + ".inst 0x459348e7 // uaddwb z7.s, z7.s, z19.h\n" + ".inst 0x45934cc6 // uaddwt z6.s, z6.s, z19.h\n" + ".inst 0x459248a5 // uaddwb z5.s, z5.s, z18.h\n" + ".inst 0x45924c84 // uaddwt z4.s, z4.s, z18.h\n" + ".inst 0x45914863 // uaddwb z3.s, z3.s, z17.h\n" + ".inst 0x45914c42 // uaddwt z2.s, z2.s, z17.h\n" + ".inst 0x45904821 // uaddwb z1.s, z1.s, z16.h\n" + ".inst 0x45904c00 // uaddwt z0.s, z0.s, z16.h\n" + "4:" // 4-vectors of channels: After loop + "ands x20, %x[n_valid_cells], #0x1\n" + "beq 6f\n" + "5:" // 4-vectors of channels: Single input loop + "ldr x21, [x19], #0x8\n" + "ld1b { z31.b }, p4/Z, [x21, x26]\n" + ".inst 0x4508abf7 // ushllb z23.h, z31.b, #0x0\n" + ".inst 0x4508aff6 // ushllt z22.h, z31.b, #0x0\n" + "ld1b { z29.b }, p3/Z, [x21, x25]\n" + ".inst 0x4508abb5 // ushllb z21.h, z29.b, #0x0\n" + ".inst 0x4508afb4 // ushllt z20.h, z29.b, #0x0\n" + "subs x20, x20, #0x1\n" + "ld1b { z27.b }, p2/Z, [x21, x24]\n" + ".inst 0x4508ab73 // ushllb z19.h, z27.b, #0x0\n" + ".inst 0x4508af72 // ushllt z18.h, z27.b, #0x0\n" + "ld1b { z25.b }, p1/Z, [x21, x23]\n" + ".inst 0x4508ab31 // ushllb z17.h, z25.b, #0x0\n" + ".inst 0x4508af30 // ushllt z16.h, z25.b, #0x0\n" + ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" + ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" + ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" + ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" + ".inst 0x4595496b // uaddwb z11.s, z11.s, z21.h\n" + ".inst 0x45954d4a // uaddwt z10.s, z10.s, z21.h\n" + ".inst 0x45944929 // uaddwb z9.s, z9.s, z20.h\n" + ".inst 0x45944d08 // uaddwt z8.s, z8.s, z20.h\n" + ".inst 0x459348e7 // uaddwb z7.s, z7.s, z19.h\n" + ".inst 0x45934cc6 // uaddwt z6.s, z6.s, z19.h\n" + ".inst 0x459248a5 // uaddwb z5.s, z5.s, z18.h\n" + ".inst 0x45924c84 // uaddwt z4.s, z4.s, z18.h\n" + ".inst 0x45914863 // uaddwb z3.s, z3.s, z17.h\n" + ".inst 0x45914c42 // uaddwt z2.s, z2.s, z17.h\n" + ".inst 0x45904821 // uaddwb z1.s, z1.s, z16.h\n" + ".inst 0x45904c00 // uaddwt z0.s, z0.s, z16.h\n" + "bgt 5b\n" + "6:" // 4-vectors of channels: Single input loop: End + "ld1rw { z17.s }, p0/Z, [%x[rescale_ptr]]\n" + ".inst 0x04b175ef // sqdmulh z15.s, z15.s, z17.s\n" + ".inst 0x04b175ce // sqdmulh z14.s, z14.s, z17.s\n" + ".inst 0x04b175ad // sqdmulh z13.s, z13.s, z17.s\n" + ".inst 0x04b1758c // sqdmulh z12.s, z12.s, z17.s\n" + "ld1rw { z16.s }, p0/Z, [%x[shift_ptr]]\n" + ".inst 0x04b1756b // sqdmulh z11.s, z11.s, z17.s\n" + ".inst 0x04b1754a // sqdmulh z10.s, z10.s, z17.s\n" + ".inst 0x04b17529 // sqdmulh z9.s, z9.s, z17.s\n" + ".inst 0x04b17508 // sqdmulh z8.s, z8.s, z17.s\n" + ".inst 0x04b174e7 // sqdmulh z7.s, z7.s, z17.s\n" + ".inst 0x04b174c6 // sqdmulh z6.s, z6.s, z17.s\n" + ".inst 0x04b174a5 // sqdmulh z5.s, z5.s, z17.s\n" + ".inst 0x04b17484 // sqdmulh z4.s, z4.s, z17.s\n" + ".inst 0x04b17463 // sqdmulh z3.s, z3.s, z17.s\n" + ".inst 0x04b17442 // sqdmulh z2.s, z2.s, z17.s\n" + ".inst 0x04b17421 // sqdmulh z1.s, z1.s, z17.s\n" + ".inst 0x04b17400 // sqdmulh z0.s, z0.s, z17.s\n" + ".inst 0x4482820f // srshl z15.s, p0/M, z15.s, z16.s\n" + ".inst 0x4482820e // srshl z14.s, p0/M, z14.s, z16.s\n" + ".inst 0x4482820d // srshl z13.s, p0/M, z13.s, z16.s\n" + ".inst 0x4482820c // srshl z12.s, p0/M, z12.s, z16.s\n" + ".inst 0x4482820b // srshl z11.s, p0/M, z11.s, z16.s\n" + ".inst 0x4482820a // srshl z10.s, p0/M, z10.s, z16.s\n" + ".inst 0x44828209 // srshl z9.s, p0/M, z9.s, z16.s\n" + ".inst 0x44828208 // srshl z8.s, p0/M, z8.s, z16.s\n" + ".inst 0x44828207 // srshl z7.s, p0/M, z7.s, z16.s\n" + ".inst 0x44828206 // srshl z6.s, p0/M, z6.s, z16.s\n" + ".inst 0x44828205 // srshl z5.s, p0/M, z5.s, z16.s\n" + ".inst 0x44828204 // srshl z4.s, p0/M, z4.s, z16.s\n" + ".inst 0x44828203 // srshl z3.s, p0/M, z3.s, z16.s\n" + ".inst 0x44828202 // srshl z2.s, p0/M, z2.s, z16.s\n" + ".inst 0x44828201 // srshl z1.s, p0/M, z1.s, z16.s\n" + ".inst 0x44828200 // srshl z0.s, p0/M, z0.s, z16.s\n" + "mov z16.s, #0x0\n" + "mov z19.s, #0xff\n" + "smax z15.s, p0/M, z15.s, z16.s\n" + "smax z14.s, p0/M, z14.s, z16.s\n" + "smax z13.s, p0/M, z13.s, z16.s\n" + "smax z12.s, p0/M, z12.s, z16.s\n" + "smax z11.s, p0/M, z11.s, z16.s\n" + "smax z10.s, p0/M, z10.s, z16.s\n" + "smax z9.s, p0/M, z9.s, z16.s\n" + "smax z8.s, p0/M, z8.s, z16.s\n" + "smax z7.s, p0/M, z7.s, z16.s\n" + "smax z6.s, p0/M, z6.s, z16.s\n" + "smax z5.s, p0/M, z5.s, z16.s\n" + "smax z4.s, p0/M, z4.s, z16.s\n" + "smax z3.s, p0/M, z3.s, z16.s\n" + "smax z2.s, p0/M, z2.s, z16.s\n" + "smax z1.s, p0/M, z1.s, z16.s\n" + "smax z0.s, p0/M, z0.s, z16.s\n" + "smin z15.s, p0/M, z15.s, z19.s\n" + "smin z14.s, p0/M, z14.s, z19.s\n" + "trn1 z23.h, z15.h, z14.h\n" + "smin z13.s, p0/M, z13.s, z19.s\n" + "smin z12.s, p0/M, z12.s, z19.s\n" + "trn1 z16.h, z13.h, z12.h\n" + "smin z11.s, p0/M, z11.s, z19.s\n" + "smin z10.s, p0/M, z10.s, z19.s\n" + "trn1 z22.h, z11.h, z10.h\n" + "smin z9.s, p0/M, z9.s, z19.s\n" + "smin z8.s, p0/M, z8.s, z19.s\n" + "trn1 z18.h, z9.h, z8.h\n" + "smin z7.s, p0/M, z7.s, z19.s\n" + "smin z6.s, p0/M, z6.s, z19.s\n" + "trn1 z21.h, z7.h, z6.h\n" + "smin z5.s, p0/M, z5.s, z19.s\n" + "smin z4.s, p0/M, z4.s, z19.s\n" + "trn1 z17.h, z5.h, z4.h\n" + "smin z3.s, p0/M, z3.s, z19.s\n" + "smin z2.s, p0/M, z2.s, z19.s\n" + "trn1 z20.h, z3.h, z2.h\n" + "smin z1.s, p0/M, z1.s, z19.s\n" + "smin z0.s, p0/M, z0.s, z19.s\n" + "trn1 z19.h, z1.h, z0.h\n" + "trn1 z16.b, z23.b, z16.b\n" + "trn1 z18.b, z22.b, z18.b\n" + "st1b { z16.b }, p4, [%x[outptr], x26]\n" + "incb x26, ALL, MUL #4\n" + "trn1 z17.b, z21.b, z17.b\n" + "trn1 z16.b, z20.b, z19.b\n" + "st1b { z18.b }, p3, [%x[outptr], x25]\n" + "incb x25, ALL, MUL #4\n" + "st1b { z17.b }, p2, [%x[outptr], x24]\n" + "incb x24, ALL, MUL #4\n" + "st1b { z16.b }, p1, [%x[outptr], x23]\n" + "incb x23, ALL, MUL #4\n" + "whilelt p1.b, x23, %x[n_channels]\n" + "b.any 1b\n" + "7:" // Single vector of channels + "whilelt p4.b, x26, %x[n_channels]\n" + "b.none 14f\n" + "8:" // Single vector of channels: Loop + "lsr x22, %x[n_valid_cells], #0x1\n" + "mov z15.s, #0x0\n" + "mov z14.s, #0x0\n" + "mov x19, %x[inptrs]\n" + "mov z13.s, #0x0\n" + "mov z12.s, #0x0\n" + "cbz x22, 11f\n" + "ldp x21, x20, [x19, #0x0]\n" + "subs x22, x22, #0x1\n" + "add x19, x19, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x26]\n" + "ld1b { z30.b }, p4/Z, [x20, x26]\n" + "beq 10f\n" + "9:" // Single vector of channels: Loop: 2 inputs loop + ".inst 0x455e0bf7 // uaddlb z23.h, z31.b, z30.b\n" + ".inst 0x455e0ff6 // uaddlt z22.h, z31.b, z30.b\n" + "ldp x21, x20, [x19, #0x0]\n" + "subs x22, x22, #0x1\n" + ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" + ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" + "add x19, x19, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x26]\n" + ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" + ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" + "ld1b { z30.b }, p4/Z, [x20, x26]\n" + "bgt 9b\n" + "10:" // Single vector of channels: Loop: 2 inputs tail + ".inst 0x455e0bf7 // uaddlb z23.h, z31.b, z30.b\n" + ".inst 0x455e0ff6 // uaddlt z22.h, z31.b, z30.b\n" + ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" + ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" + ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" + ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" + "11:" // Single vector of channels: Loop: After loop + "ands x20, %x[n_valid_cells], #0x1\n" + "beq 13f\n" + "12:" // Single vector of channels: Loop: Single input loop + "ldr x21, [x19], #0x8\n" + "ld1b { z31.b }, p4/Z, [x21, x26]\n" + ".inst 0x4508abf7 // ushllb z23.h, z31.b, #0x0\n" + ".inst 0x4508aff6 // ushllt z22.h, z31.b, #0x0\n" + "subs x20, x20, #0x1\n" + ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" + ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" + ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" + ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" + "bgt 12b\n" + "13:" // Single vector of channels: Loop: Single input loop: End + "ld1rw { z17.s }, p0/Z, [%x[rescale_ptr]]\n" + ".inst 0x04b175ef // sqdmulh z15.s, z15.s, z17.s\n" + ".inst 0x04b175ce // sqdmulh z14.s, z14.s, z17.s\n" + ".inst 0x04b175ad // sqdmulh z13.s, z13.s, z17.s\n" + ".inst 0x04b1758c // sqdmulh z12.s, z12.s, z17.s\n" + "ld1rw { z16.s }, p0/Z, [%x[shift_ptr]]\n" + ".inst 0x4482820f // srshl z15.s, p0/M, z15.s, z16.s\n" + ".inst 0x4482820e // srshl z14.s, p0/M, z14.s, z16.s\n" + ".inst 0x4482820d // srshl z13.s, p0/M, z13.s, z16.s\n" + ".inst 0x4482820c // srshl z12.s, p0/M, z12.s, z16.s\n" + "mov z16.s, #0x0\n" + "mov z19.s, #0xff\n" + "smax z15.s, p0/M, z15.s, z16.s\n" + "smax z14.s, p0/M, z14.s, z16.s\n" + "smax z13.s, p0/M, z13.s, z16.s\n" + "smax z12.s, p0/M, z12.s, z16.s\n" + "smin z15.s, p0/M, z15.s, z19.s\n" + "smin z14.s, p0/M, z14.s, z19.s\n" + "trn1 z23.h, z15.h, z14.h\n" + "smin z13.s, p0/M, z13.s, z19.s\n" + "smin z12.s, p0/M, z12.s, z19.s\n" + "trn1 z16.h, z13.h, z12.h\n" + "trn1 z16.b, z23.b, z16.b\n" + "st1b { z16.b }, p4, [%x[outptr], x26]\n" + "incb x26\n" + "whilelt p4.b, x26, %x[n_channels]\n" + "b.any 8b\n" + "14:" // End + ".inst 0xd503467f // SMSTOP\n" + : + : [inptrs] "r" (inptrs), [n_channels] "r" (n_channels), [n_valid_cells] "r" (n_valid_cells), [outptr] "r" (outptr), [rescale_ptr] "r" (&rescale_value), [shift_ptr] "r" (&shift_value) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp new file mode 100644 index 0000000000..6d5f53d7a5 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#pragma once + +namespace arm_conv { +namespace pooling { + +void sme_u8_nhwc_max_2x2_s1_output2x2_depthfirst_impl(unsigned int, const uint8_t *const *const, uint8_t *const *const, bool, unsigned int, unsigned int, unsigned int, unsigned int); + +struct sme_u8_nhwc_max_2x2_s1_output2x2_depthfirst : public DepthfirstStrategy<uint8_t, uint8_t> +{ + using Parent = DepthfirstStrategy<uint8_t, uint8_t>; + + const static auto pooling_type = PoolingType::MAX; + const static auto pool_rows = 2u, pool_cols = 2u; + const static auto stride_rows = 1u, stride_cols = 1u; + + sme_u8_nhwc_max_2x2_s1_output2x2_depthfirst(const CPUInfo *) + : Parent(pool_rows, pool_cols, stride_rows, stride_cols, 2, 2) {} + + Parent::KernelType get_kernel(void) const { return sme_u8_nhwc_max_2x2_s1_output2x2_depthfirst_impl; } +}; + +} // namespace pooling +} // namespace arm_conv diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp new file mode 100644 index 0000000000..d76755ae3a --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + + +#include <cstddef> +#include <cstdint> + +#if defined(__ARM_FEATURE_SVE) && defined(ARM_COMPUTE_ENABLE_SME) + +namespace arm_conv { +namespace pooling { + +void sme_u8_nhwc_max_2x2_s1_output2x2_depthfirst_impl( + const unsigned int n_channels, + const uint8_t *const *const inptrs, + uint8_t *const *const outptrs, + const bool exclude_padding, + const unsigned int pad_left, + const unsigned int pad_top, + const unsigned int pad_right, + const unsigned int pad_bottom +) +{ + struct KernelArgs + { + const uint64_t n_channels; + const uint8_t *const *const inptrs; + uint8_t *const *const outptrs; + KernelArgs( + unsigned int channels, + const uint8_t *const *input_ptrs, + uint8_t *const * output_ptrs, + bool, unsigned int, unsigned int, unsigned int, unsigned int + ) : n_channels(channels), + inptrs(input_ptrs), + outptrs(output_ptrs) + { + } + }; + + const KernelArgs args(n_channels, inptrs, outptrs, exclude_padding, + pad_left, pad_top, pad_right, pad_bottom); + + __asm__ __volatile__( + "ldr x20, [%x[args], %[offsetof_outptrs]]\n" + ".inst 0xd503477f // SMSTART ZA\n" + "mov x14, #0x0\n" + "ptrue p2.b\n" + "ldr x19, [%x[args], %[offsetof_inptrs]]\n" + "mov x13, #0x0\n" + "ldr x12, [%x[args], %[offsetof_n_channels]]\n" + "whilelt p1.b, x14, x12\n" + "ldp x11, x10, [x20, #0x0]\n" + "ldp x9, x28, [x20, #0x10]\n" + "ldp x27, x26, [x19, #0x0]\n" + "ld1b { z29.b }, p1/Z, [x26, x14]\n" + "ldp x25, x24, [x19, #0x10]\n" + "ld1b { z28.b }, p1/Z, [x24, x14]\n" + "ldp x23, x22, [x19, #0x20]\n" + "ld1b { z27.b }, p1/Z, [x23, x14]\n" + "ldp x21, x20, [x19, #0x30]\n" + "ld1b { z26.b }, p1/Z, [x20, x14]\n" + "ldr x19, [x19, #0x40]\n" + "ld1b { z20.b }, p1/Z, [x27, x14]\n" + "ld1b { z25.b }, p1/Z, [x22, x14]\n" + "ld1b { z24.b }, p1/Z, [x25, x14]\n" + "ld1b { z23.b }, p1/Z, [x21, x14]\n" + "ld1b { z19.b }, p1/Z, [x19, x14]\n" + "incw x14\n" + "whilelt p1.b, x14, x12\n" + "b.none 2f\n" + "1:" // Vector: Loop + "movprfx z22, z29\n umax z22.b, p2/M, z22.b, z27.b\n" + "movprfx z21, z27\n umax z21.b, p2/M, z21.b, z26.b\n" + "ld1b { z29.b }, p1/Z, [x26, x14]\n" + "whilelt p0.b, x13, x12\n" + "movprfx z18, z28\n umax z18.b, p2/M, z18.b, z20.b\n" + "movprfx z20, z25\n umax z20.b, p2/M, z20.b, z24.b\n" + "ld1b { z27.b }, p1/Z, [x23, x14]\n" + "movprfx z17, z23\n umax z17.b, p2/M, z17.b, z28.b\n" + "movprfx z16, z25\n umax z16.b, p2/M, z16.b, z19.b\n" + "ld1b { z26.b }, p1/Z, [x20, x14]\n" + "ld1b { z28.b }, p1/Z, [x24, x14]\n" + "movprfx z19, z18\n umax z19.b, p2/M, z19.b, z22.b\n" + "movprfx z18, z22\n umax z18.b, p2/M, z18.b, z20.b\n" + "ld1b { z20.b }, p1/Z, [x27, x14]\n" + "umax z17.b, p2/M, z17.b, z21.b\n" + "umax z16.b, p2/M, z16.b, z21.b\n" + "ld1b { z25.b }, p1/Z, [x22, x14]\n" + "st1b { z19.b }, p0, [x11, x13]\n" + "ld1b { z24.b }, p1/Z, [x25, x14]\n" + "st1b { z18.b }, p0, [x10, x13]\n" + "ld1b { z23.b }, p1/Z, [x21, x14]\n" + "st1b { z17.b }, p0, [x9, x13]\n" + "ld1b { z19.b }, p1/Z, [x19, x14]\n" + "incw x14\n" + "whilelt p1.b, x14, x12\n" + "st1b { z16.b }, p0, [x28, x13]\n" + "incw x13\n" + "b.any 1b\n" + "2:" // Vector: Tail + "movprfx z22, z29\n umax z22.b, p2/M, z22.b, z27.b\n" + "movprfx z21, z27\n umax z21.b, p2/M, z21.b, z26.b\n" + "whilelt p0.b, x13, x12\n" + "movprfx z18, z28\n umax z18.b, p2/M, z18.b, z20.b\n" + "movprfx z20, z25\n umax z20.b, p2/M, z20.b, z24.b\n" + "movprfx z17, z23\n umax z17.b, p2/M, z17.b, z28.b\n" + "movprfx z16, z25\n umax z16.b, p2/M, z16.b, z19.b\n" + "movprfx z19, z18\n umax z19.b, p2/M, z19.b, z22.b\n" + "movprfx z18, z22\n umax z18.b, p2/M, z18.b, z20.b\n" + "st1b { z19.b }, p0, [x11, x13]\n" + "umax z17.b, p2/M, z17.b, z21.b\n" + "umax z16.b, p2/M, z16.b, z21.b\n" + "st1b { z18.b }, p0, [x10, x13]\n" + "st1b { z17.b }, p0, [x9, x13]\n" + "st1b { z16.b }, p0, [x28, x13]\n" + ".inst 0xd503467f // SMSTOP\n" + : + : [args] "r" (&args), [offsetof_inptrs] "I" (offsetof(KernelArgs, inptrs)), [offsetof_n_channels] "I" (offsetof(KernelArgs, n_channels)), [offsetof_outptrs] "I" (offsetof(KernelArgs, outptrs)) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x9", "x10", "x11", "x12", "x13", "x14", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(__ARM_FEATURE_SVE) && defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_max_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_max_generic_depthfirst.hpp new file mode 100644 index 0000000000..5c637ec3c3 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_max_generic_depthfirst.hpp @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstdint> + +#pragma once + +namespace arm_conv { +namespace pooling { + +void sme_u8_nhwc_max_generic_depthfirst_impl(const uint64_t, const uint64_t n_valid_cells, uint64_t n_channels, const uint8_t *const *const inptrs, uint8_t *outptr); + +struct sme_u8_nhwc_max_generic_depthfirst : IGenericDepthfirstStrategy<uint8_t, uint8_t> +{ + using Parent = IGenericDepthfirstStrategy<uint8_t, uint8_t>; + sme_u8_nhwc_max_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return sme_u8_nhwc_max_generic_depthfirst_impl; } +}; + +} // namespace pooling +} // namespace arm_conv diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_max_generic_depthfirst/generic.cpp new file mode 100644 index 0000000000..21af2eb5b1 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_max_generic_depthfirst/generic.cpp @@ -0,0 +1,224 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if defined(ARM_COMPUTE_ENABLE_SME) + +#include <cstdint> + +namespace arm_conv { +namespace pooling { + + +void sme_u8_nhwc_max_generic_depthfirst_impl( + const uint64_t, + const uint64_t n_valid_cells, + uint64_t n_channels, + const uint8_t *const *const inptrs, + uint8_t *outptr +) +{ + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "mov x28, #0x0\n" + "cntb x27\n" + "cntb x26, ALL, MUL #2\n" + "cntb x25, ALL, MUL #3\n" + "whilelt p4.b, x28, %x[n_channels]\n" + "whilelt p3.b, x27, %x[n_channels]\n" + "whilelt p2.b, x26, %x[n_channels]\n" + "whilelt p1.b, x25, %x[n_channels]\n" + "ptrue p0.b\n" + "b.none 7f\n" + "1:" // 4-vectors of channels + "lsr x24, %x[n_valid_cells], #0x2\n" + "mov z4.b, #0x0\n" + "mov z3.b, #0x0\n" + "mov x19, %x[inptrs]\n" + "mov z2.b, #0x0\n" + "mov z1.b, #0x0\n" + "cbz x24, 4f\n" + "ldp x23, x22, [x19, #0x0]\n" + "subs x24, x24, #0x1\n" + "ld1b { z0.b }, p4/Z, [x23, x28]\n" + "ldp x21, x20, [x19, #0x10]\n" + "add x19, x19, #0x20\n" + "ld1b { z31.b }, p4/Z, [x22, x28]\n" + "ld1b { z23.b }, p4/Z, [x21, x28]\n" + "ld1b { z30.b }, p4/Z, [x20, x28]\n" + "ld1b { z18.b }, p3/Z, [x23, x27]\n" + "ld1b { z29.b }, p3/Z, [x22, x27]\n" + "ld1b { z22.b }, p3/Z, [x21, x27]\n" + "ld1b { z28.b }, p3/Z, [x20, x27]\n" + "ld1b { z17.b }, p2/Z, [x23, x26]\n" + "ld1b { z27.b }, p2/Z, [x22, x26]\n" + "ld1b { z21.b }, p2/Z, [x21, x26]\n" + "ld1b { z26.b }, p2/Z, [x20, x26]\n" + "ld1b { z16.b }, p1/Z, [x23, x25]\n" + "ld1b { z25.b }, p1/Z, [x22, x25]\n" + "ld1b { z20.b }, p1/Z, [x21, x25]\n" + "ld1b { z24.b }, p1/Z, [x20, x25]\n" + "beq 3f\n" + "2:" // 4-vectors of channels: 4 inputs loop + "movprfx z19, z0\n umax z19.b, p0/M, z19.b, z31.b\n" + "umax z23.b, p0/M, z23.b, z30.b\n" + "ldp x23, x22, [x19, #0x0]\n" + "subs x24, x24, #0x1\n" + "umax z18.b, p0/M, z18.b, z29.b\n" + "umax z22.b, p0/M, z22.b, z28.b\n" + "ldp x21, x20, [x19, #0x10]\n" + "add x19, x19, #0x20\n" + "umax z17.b, p0/M, z17.b, z27.b\n" + "umax z21.b, p0/M, z21.b, z26.b\n" + "ld1b { z0.b }, p4/Z, [x23, x28]\n" + "umax z16.b, p0/M, z16.b, z25.b\n" + "umax z20.b, p0/M, z20.b, z24.b\n" + "ld1b { z31.b }, p4/Z, [x22, x28]\n" + "umax z19.b, p0/M, z19.b, z23.b\n" + "umax z18.b, p0/M, z18.b, z22.b\n" + "ld1b { z23.b }, p4/Z, [x21, x28]\n" + "umax z17.b, p0/M, z17.b, z21.b\n" + "umax z16.b, p0/M, z16.b, z20.b\n" + "ld1b { z30.b }, p4/Z, [x20, x28]\n" + "umax z4.b, p0/M, z4.b, z19.b\n" + "umax z3.b, p0/M, z3.b, z18.b\n" + "ld1b { z18.b }, p3/Z, [x23, x27]\n" + "umax z2.b, p0/M, z2.b, z17.b\n" + "umax z1.b, p0/M, z1.b, z16.b\n" + "ld1b { z29.b }, p3/Z, [x22, x27]\n" + "ld1b { z22.b }, p3/Z, [x21, x27]\n" + "ld1b { z28.b }, p3/Z, [x20, x27]\n" + "ld1b { z17.b }, p2/Z, [x23, x26]\n" + "ld1b { z27.b }, p2/Z, [x22, x26]\n" + "ld1b { z21.b }, p2/Z, [x21, x26]\n" + "ld1b { z26.b }, p2/Z, [x20, x26]\n" + "ld1b { z16.b }, p1/Z, [x23, x25]\n" + "ld1b { z25.b }, p1/Z, [x22, x25]\n" + "ld1b { z20.b }, p1/Z, [x21, x25]\n" + "ld1b { z24.b }, p1/Z, [x20, x25]\n" + "bgt 2b\n" + "3:" // 4-vectors of channels: 4 inputs tail + "movprfx z19, z0\n umax z19.b, p0/M, z19.b, z31.b\n" + "umax z23.b, p0/M, z23.b, z30.b\n" + "umax z18.b, p0/M, z18.b, z29.b\n" + "umax z22.b, p0/M, z22.b, z28.b\n" + "umax z17.b, p0/M, z17.b, z27.b\n" + "umax z21.b, p0/M, z21.b, z26.b\n" + "umax z16.b, p0/M, z16.b, z25.b\n" + "umax z20.b, p0/M, z20.b, z24.b\n" + "umax z19.b, p0/M, z19.b, z23.b\n" + "umax z18.b, p0/M, z18.b, z22.b\n" + "umax z17.b, p0/M, z17.b, z21.b\n" + "umax z16.b, p0/M, z16.b, z20.b\n" + "umax z4.b, p0/M, z4.b, z19.b\n" + "umax z3.b, p0/M, z3.b, z18.b\n" + "umax z2.b, p0/M, z2.b, z17.b\n" + "umax z1.b, p0/M, z1.b, z16.b\n" + "4:" // 4-vectors of channels: After loop + "ands x20, %x[n_valid_cells], #0x3\n" + "beq 6f\n" + "5:" // 4-vectors of channels: Single input loop + "ldr x23, [x19], #0x8\n" + "ld1b { z0.b }, p4/Z, [x23, x28]\n" + "subs x20, x20, #0x1\n" + "umax z4.b, p0/M, z4.b, z0.b\n" + "ld1b { z18.b }, p3/Z, [x23, x27]\n" + "umax z3.b, p0/M, z3.b, z18.b\n" + "ld1b { z17.b }, p2/Z, [x23, x26]\n" + "umax z2.b, p0/M, z2.b, z17.b\n" + "ld1b { z16.b }, p1/Z, [x23, x25]\n" + "umax z1.b, p0/M, z1.b, z16.b\n" + "bgt 5b\n" + "6:" // 4-vectors of channels: Single input loop: End + "st1b { z4.b }, p4, [%x[outptr], x28]\n" + "incb x28, ALL, MUL #4\n" + "st1b { z3.b }, p3, [%x[outptr], x27]\n" + "incb x27, ALL, MUL #4\n" + "st1b { z2.b }, p2, [%x[outptr], x26]\n" + "incb x26, ALL, MUL #4\n" + "st1b { z1.b }, p1, [%x[outptr], x25]\n" + "incb x25, ALL, MUL #4\n" + "whilelt p1.b, x25, %x[n_channels]\n" + "b.any 1b\n" + "7:" // Single vector of channels + "whilelt p4.b, x28, %x[n_channels]\n" + "b.none 14f\n" + "8:" // Single vector of channels: Loop + "lsr x24, %x[n_valid_cells], #0x2\n" + "mov z4.b, #0x0\n" + "mov x19, %x[inptrs]\n" + "cbz x24, 11f\n" + "ldp x23, x22, [x19, #0x0]\n" + "subs x24, x24, #0x1\n" + "ld1b { z0.b }, p4/Z, [x23, x28]\n" + "ldp x21, x20, [x19, #0x10]\n" + "add x19, x19, #0x20\n" + "ld1b { z31.b }, p4/Z, [x22, x28]\n" + "ld1b { z23.b }, p4/Z, [x21, x28]\n" + "ld1b { z30.b }, p4/Z, [x20, x28]\n" + "beq 10f\n" + "9:" // Single vector of channels: Loop: 4 inputs loop + "movprfx z19, z0\n umax z19.b, p0/M, z19.b, z31.b\n" + "umax z23.b, p0/M, z23.b, z30.b\n" + "ldp x23, x22, [x19, #0x0]\n" + "subs x24, x24, #0x1\n" + "umax z19.b, p0/M, z19.b, z23.b\n" + "ldp x21, x20, [x19, #0x10]\n" + "umax z4.b, p0/M, z4.b, z19.b\n" + "add x19, x19, #0x20\n" + "ld1b { z0.b }, p4/Z, [x23, x28]\n" + "ld1b { z31.b }, p4/Z, [x22, x28]\n" + "ld1b { z23.b }, p4/Z, [x21, x28]\n" + "ld1b { z30.b }, p4/Z, [x20, x28]\n" + "bgt 9b\n" + "10:" // Single vector of channels: Loop: 4 inputs tail + "movprfx z19, z0\n umax z19.b, p0/M, z19.b, z31.b\n" + "umax z23.b, p0/M, z23.b, z30.b\n" + "umax z19.b, p0/M, z19.b, z23.b\n" + "umax z4.b, p0/M, z4.b, z19.b\n" + "11:" // Single vector of channels: Loop: After loop + "ands x20, %x[n_valid_cells], #0x3\n" + "beq 13f\n" + "12:" // Single vector of channels: Loop: Single input loop + "ldr x23, [x19], #0x8\n" + "ld1b { z0.b }, p4/Z, [x23, x28]\n" + "subs x20, x20, #0x1\n" + "umax z4.b, p0/M, z4.b, z0.b\n" + "bgt 12b\n" + "13:" // Single vector of channels: Loop: Single input loop: End + "st1b { z4.b }, p4, [%x[outptr], x28]\n" + "incb x28\n" + "whilelt p4.b, x28, %x[n_channels]\n" + "b.any 8b\n" + "14:" // End + ".inst 0xd503467f // SMSTOP\n" + : + : [inptrs] "r" (inptrs), [n_channels] "r" (n_channels), [n_valid_cells] "r" (n_valid_cells), [outptr] "r" (outptr) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8q_nhwc_avg_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8q_nhwc_avg_generic_depthfirst.hpp new file mode 100644 index 0000000000..2930993800 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8q_nhwc_avg_generic_depthfirst.hpp @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstdint> + +#pragma once + +namespace arm_conv { +namespace pooling { + +void sme_u8q_nhwc_avg_generic_depthfirst_impl(const uint64_t window_cells, const uint64_t n_valid_cells, uint64_t n_channels, const uint8_t *const *const inptrs, uint8_t *outptr, const Requantize32 &qp); + +struct sme_u8q_nhwc_avg_generic_depthfirst : IGenericDepthfirstStrategy<uint8_t, uint8_t, Requantize32> +{ + using Parent = IGenericDepthfirstStrategy<uint8_t, uint8_t, Requantize32>; + sme_u8q_nhwc_avg_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return sme_u8q_nhwc_avg_generic_depthfirst_impl; } +}; + +} // namespace pooling +} // namespace arm_conv diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8q_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8q_nhwc_avg_generic_depthfirst/generic.cpp new file mode 100644 index 0000000000..8a3cafa2c1 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8q_nhwc_avg_generic_depthfirst/generic.cpp @@ -0,0 +1,487 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if defined(ARM_COMPUTE_ENABLE_SME) + +#include "src/core/NEON/kernels/assembly/pooling.hpp" +#include <cstdint> +#include <cstring> +#include <cmath> + + +namespace arm_conv { +namespace pooling { + +namespace { + struct RescaleParams + { + int32_t multiplier, shift; + }; + + constexpr RescaleParams rescale_params[8] = { + {0x40000000, -0}, // 1/2 + {0x55555556, -1}, // 1/3 + {0x40000000, -1}, // 1/4 + {0x66666666, -2}, // 1/5 + {0x55555556, -2}, // 1/6 + {0x49249249, -2}, // 1/7 + {0x40000000, -2}, // 1/8 + {0x71c71c72, -3}, // 1/9 + }; +} + +void sme_u8q_nhwc_avg_generic_depthfirst_impl( + const uint64_t window_cells, + const uint64_t n_valid_cells, + uint64_t n_channels, + const uint8_t *const *const inptrs, + uint8_t *outptr, + const Requantize32 &qp +) +{ + if (n_valid_cells == 1 && window_cells == 1) + { + // In this case, simply copy from the input to the output + std::memcpy(outptr, *inptrs, n_channels); + return; + } + + // Compute (or look up) the rescale values + int32_t shift_value = 0, rescale_value = 0; + if (2 <= window_cells && window_cells <= 9) + { + auto ¶ms = rescale_params[window_cells - 2]; + rescale_value = params.multiplier; + shift_value = params.shift; + } + else + { + auto f_rescale_value = 1.0f / static_cast<float>(window_cells); + + shift_value = 0; + while (f_rescale_value < 0.5f) + { + shift_value--; + f_rescale_value *= 2.0f; + } + + rescale_value = static_cast<int32_t>(round(f_rescale_value * static_cast<float>(1ll << 31))); + if (static_cast<int64_t>(rescale_value) == (1ll << 31)) + { + shift_value++; + rescale_value >>= 1; + } + } + + + // Initialise the accumulators such that the offsets are subtracted for all + // valid inputs. + const int32_t accumulator_init = -qp.input_offset * n_valid_cells; + + // Combine together the rescale value for the requantization and the scaling + // factor for the average pool. + const int32_t shift = qp.per_layer_left_shift - qp.per_layer_right_shift + shift_value; + const int32_t left_shift = shift > 0 ? shift : 0; + const int32_t right_shift = shift <= 0 ? shift : 0; + + int32_t combined_rescale_value = 0; + __asm__ __volatile__ ( + "mov v16.s[0], %w[per_layer_mul]\n" + "mov v17.s[0], %w[rescale_value]\n" + "sqrdmulh s18, s16, s17\n" + "mov %w[combined_rescale_value], v18.s[0]\n" + : [combined_rescale_value] "=r" (combined_rescale_value) + : [per_layer_mul] "r" (qp.per_layer_mul), [rescale_value] "r" (rescale_value) + : "v16", "v17", "v18" + ); + + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "mov x26, #0x0\n" + "cntb x25\n" + "cntb x24, ALL, MUL #2\n" + "cntb x23, ALL, MUL #3\n" + "whilelt p4.b, x26, %x[n_channels]\n" + "whilelt p3.b, x25, %x[n_channels]\n" + "whilelt p2.b, x24, %x[n_channels]\n" + "whilelt p1.b, x23, %x[n_channels]\n" + "ptrue p0.b\n" + "b.none 7f\n" + "1:" // 4-vectors of channels + "ld1rw { z15.s }, p0/Z, [%x[accumulator_init]]\n" + "lsr x22, %x[n_valid_cells], #0x1\n" + "mov z14.d, z15.d\n" + "mov z13.d, z15.d\n" + "mov z12.d, z15.d\n" + "mov z11.d, z15.d\n" + "mov x19, %x[inptrs]\n" + "mov z10.d, z15.d\n" + "mov z9.d, z15.d\n" + "mov z8.d, z15.d\n" + "mov z7.d, z15.d\n" + "mov z6.d, z15.d\n" + "mov z5.d, z15.d\n" + "mov z4.d, z15.d\n" + "mov z3.d, z15.d\n" + "mov z2.d, z15.d\n" + "mov z1.d, z15.d\n" + "mov z0.d, z15.d\n" + "cbz x22, 4f\n" + "ldp x21, x20, [x19, #0x0]\n" + "subs x22, x22, #0x1\n" + "add x19, x19, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x26]\n" + "ld1b { z30.b }, p4/Z, [x20, x26]\n" + "ld1b { z29.b }, p3/Z, [x21, x25]\n" + "ld1b { z28.b }, p3/Z, [x20, x25]\n" + "ld1b { z27.b }, p2/Z, [x21, x24]\n" + "ld1b { z26.b }, p2/Z, [x20, x24]\n" + "ld1b { z25.b }, p1/Z, [x21, x23]\n" + "ld1b { z24.b }, p1/Z, [x20, x23]\n" + "beq 3f\n" + "2:" // 4-vectors of channels: 2 inputs loop + ".inst 0x455e0bf7 // uaddlb z23.h, z31.b, z30.b\n" + ".inst 0x455e0ff6 // uaddlt z22.h, z31.b, z30.b\n" + "ldp x21, x20, [x19, #0x0]\n" + "subs x22, x22, #0x1\n" + ".inst 0x455c0bb5 // uaddlb z21.h, z29.b, z28.b\n" + ".inst 0x455c0fb4 // uaddlt z20.h, z29.b, z28.b\n" + "add x19, x19, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x26]\n" + ".inst 0x455a0b73 // uaddlb z19.h, z27.b, z26.b\n" + ".inst 0x455a0f72 // uaddlt z18.h, z27.b, z26.b\n" + "ld1b { z30.b }, p4/Z, [x20, x26]\n" + ".inst 0x45580b31 // uaddlb z17.h, z25.b, z24.b\n" + ".inst 0x45580f30 // uaddlt z16.h, z25.b, z24.b\n" + "ld1b { z29.b }, p3/Z, [x21, x25]\n" + ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" + ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" + "ld1b { z28.b }, p3/Z, [x20, x25]\n" + ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" + ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" + "ld1b { z27.b }, p2/Z, [x21, x24]\n" + ".inst 0x4595496b // uaddwb z11.s, z11.s, z21.h\n" + ".inst 0x45954d4a // uaddwt z10.s, z10.s, z21.h\n" + "ld1b { z26.b }, p2/Z, [x20, x24]\n" + ".inst 0x45944929 // uaddwb z9.s, z9.s, z20.h\n" + ".inst 0x45944d08 // uaddwt z8.s, z8.s, z20.h\n" + "ld1b { z25.b }, p1/Z, [x21, x23]\n" + ".inst 0x459348e7 // uaddwb z7.s, z7.s, z19.h\n" + ".inst 0x45934cc6 // uaddwt z6.s, z6.s, z19.h\n" + "ld1b { z24.b }, p1/Z, [x20, x23]\n" + ".inst 0x459248a5 // uaddwb z5.s, z5.s, z18.h\n" + ".inst 0x45924c84 // uaddwt z4.s, z4.s, z18.h\n" + ".inst 0x45914863 // uaddwb z3.s, z3.s, z17.h\n" + ".inst 0x45914c42 // uaddwt z2.s, z2.s, z17.h\n" + ".inst 0x45904821 // uaddwb z1.s, z1.s, z16.h\n" + ".inst 0x45904c00 // uaddwt z0.s, z0.s, z16.h\n" + "bgt 2b\n" + "3:" // 4-vectors of channels: 2 inputs tail + ".inst 0x455e0bf7 // uaddlb z23.h, z31.b, z30.b\n" + ".inst 0x455e0ff6 // uaddlt z22.h, z31.b, z30.b\n" + ".inst 0x455c0bb5 // uaddlb z21.h, z29.b, z28.b\n" + ".inst 0x455c0fb4 // uaddlt z20.h, z29.b, z28.b\n" + ".inst 0x455a0b73 // uaddlb z19.h, z27.b, z26.b\n" + ".inst 0x455a0f72 // uaddlt z18.h, z27.b, z26.b\n" + ".inst 0x45580b31 // uaddlb z17.h, z25.b, z24.b\n" + ".inst 0x45580f30 // uaddlt z16.h, z25.b, z24.b\n" + ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" + ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" + ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" + ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" + ".inst 0x4595496b // uaddwb z11.s, z11.s, z21.h\n" + ".inst 0x45954d4a // uaddwt z10.s, z10.s, z21.h\n" + ".inst 0x45944929 // uaddwb z9.s, z9.s, z20.h\n" + ".inst 0x45944d08 // uaddwt z8.s, z8.s, z20.h\n" + ".inst 0x459348e7 // uaddwb z7.s, z7.s, z19.h\n" + ".inst 0x45934cc6 // uaddwt z6.s, z6.s, z19.h\n" + ".inst 0x459248a5 // uaddwb z5.s, z5.s, z18.h\n" + ".inst 0x45924c84 // uaddwt z4.s, z4.s, z18.h\n" + ".inst 0x45914863 // uaddwb z3.s, z3.s, z17.h\n" + ".inst 0x45914c42 // uaddwt z2.s, z2.s, z17.h\n" + ".inst 0x45904821 // uaddwb z1.s, z1.s, z16.h\n" + ".inst 0x45904c00 // uaddwt z0.s, z0.s, z16.h\n" + "4:" // 4-vectors of channels: After loop + "ands x20, %x[n_valid_cells], #0x1\n" + "beq 6f\n" + "5:" // 4-vectors of channels: Single input loop + "ldr x21, [x19], #0x8\n" + "ld1b { z31.b }, p4/Z, [x21, x26]\n" + ".inst 0x4508abf7 // ushllb z23.h, z31.b, #0x0\n" + ".inst 0x4508aff6 // ushllt z22.h, z31.b, #0x0\n" + "ld1b { z29.b }, p3/Z, [x21, x25]\n" + ".inst 0x4508abb5 // ushllb z21.h, z29.b, #0x0\n" + ".inst 0x4508afb4 // ushllt z20.h, z29.b, #0x0\n" + "subs x20, x20, #0x1\n" + "ld1b { z27.b }, p2/Z, [x21, x24]\n" + ".inst 0x4508ab73 // ushllb z19.h, z27.b, #0x0\n" + ".inst 0x4508af72 // ushllt z18.h, z27.b, #0x0\n" + "ld1b { z25.b }, p1/Z, [x21, x23]\n" + ".inst 0x4508ab31 // ushllb z17.h, z25.b, #0x0\n" + ".inst 0x4508af30 // ushllt z16.h, z25.b, #0x0\n" + ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" + ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" + ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" + ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" + ".inst 0x4595496b // uaddwb z11.s, z11.s, z21.h\n" + ".inst 0x45954d4a // uaddwt z10.s, z10.s, z21.h\n" + ".inst 0x45944929 // uaddwb z9.s, z9.s, z20.h\n" + ".inst 0x45944d08 // uaddwt z8.s, z8.s, z20.h\n" + ".inst 0x459348e7 // uaddwb z7.s, z7.s, z19.h\n" + ".inst 0x45934cc6 // uaddwt z6.s, z6.s, z19.h\n" + ".inst 0x459248a5 // uaddwb z5.s, z5.s, z18.h\n" + ".inst 0x45924c84 // uaddwt z4.s, z4.s, z18.h\n" + ".inst 0x45914863 // uaddwb z3.s, z3.s, z17.h\n" + ".inst 0x45914c42 // uaddwt z2.s, z2.s, z17.h\n" + ".inst 0x45904821 // uaddwb z1.s, z1.s, z16.h\n" + ".inst 0x45904c00 // uaddwt z0.s, z0.s, z16.h\n" + "bgt 5b\n" + "6:" // 4-vectors of channels: Single input loop: End + "ld1rw { z19.s }, p0/Z, [%x[left_shift]]\n" + ".inst 0x4482826f // srshl z15.s, p0/M, z15.s, z19.s\n" + ".inst 0x4482826e // srshl z14.s, p0/M, z14.s, z19.s\n" + "add x19, %x[quant_params], %[offsetof_qp_output_offset]\n" + ".inst 0x4482826d // srshl z13.s, p0/M, z13.s, z19.s\n" + ".inst 0x4482826c // srshl z12.s, p0/M, z12.s, z19.s\n" + "ld1rw { z18.s }, p0/Z, [%x[combined_rescale_value]]\n" + ".inst 0x4482826b // srshl z11.s, p0/M, z11.s, z19.s\n" + ".inst 0x4482826a // srshl z10.s, p0/M, z10.s, z19.s\n" + "ld1rw { z17.s }, p0/Z, [%x[right_shift]]\n" + ".inst 0x44828269 // srshl z9.s, p0/M, z9.s, z19.s\n" + ".inst 0x44828268 // srshl z8.s, p0/M, z8.s, z19.s\n" + "ld1rw { z16.s }, p0/Z, [x19]\n" + ".inst 0x44828267 // srshl z7.s, p0/M, z7.s, z19.s\n" + ".inst 0x44828266 // srshl z6.s, p0/M, z6.s, z19.s\n" + ".inst 0x44828265 // srshl z5.s, p0/M, z5.s, z19.s\n" + ".inst 0x44828264 // srshl z4.s, p0/M, z4.s, z19.s\n" + ".inst 0x44828263 // srshl z3.s, p0/M, z3.s, z19.s\n" + ".inst 0x44828262 // srshl z2.s, p0/M, z2.s, z19.s\n" + ".inst 0x44828261 // srshl z1.s, p0/M, z1.s, z19.s\n" + ".inst 0x44828260 // srshl z0.s, p0/M, z0.s, z19.s\n" + ".inst 0x04b275ef // sqrdmulh z15.s, z15.s, z18.s\n" + ".inst 0x04b275ce // sqrdmulh z14.s, z14.s, z18.s\n" + ".inst 0x04b275ad // sqrdmulh z13.s, z13.s, z18.s\n" + ".inst 0x04b2758c // sqrdmulh z12.s, z12.s, z18.s\n" + ".inst 0x04b2756b // sqrdmulh z11.s, z11.s, z18.s\n" + ".inst 0x04b2754a // sqrdmulh z10.s, z10.s, z18.s\n" + ".inst 0x04b27529 // sqrdmulh z9.s, z9.s, z18.s\n" + ".inst 0x04b27508 // sqrdmulh z8.s, z8.s, z18.s\n" + ".inst 0x04b274e7 // sqrdmulh z7.s, z7.s, z18.s\n" + ".inst 0x04b274c6 // sqrdmulh z6.s, z6.s, z18.s\n" + ".inst 0x04b274a5 // sqrdmulh z5.s, z5.s, z18.s\n" + ".inst 0x04b27484 // sqrdmulh z4.s, z4.s, z18.s\n" + ".inst 0x04b27463 // sqrdmulh z3.s, z3.s, z18.s\n" + ".inst 0x04b27442 // sqrdmulh z2.s, z2.s, z18.s\n" + ".inst 0x04b27421 // sqrdmulh z1.s, z1.s, z18.s\n" + ".inst 0x04b27400 // sqrdmulh z0.s, z0.s, z18.s\n" + ".inst 0x4482822f // srshl z15.s, p0/M, z15.s, z17.s\n" + ".inst 0x4482822e // srshl z14.s, p0/M, z14.s, z17.s\n" + ".inst 0x4482822d // srshl z13.s, p0/M, z13.s, z17.s\n" + ".inst 0x4482822c // srshl z12.s, p0/M, z12.s, z17.s\n" + ".inst 0x4482822b // srshl z11.s, p0/M, z11.s, z17.s\n" + ".inst 0x4482822a // srshl z10.s, p0/M, z10.s, z17.s\n" + ".inst 0x44828229 // srshl z9.s, p0/M, z9.s, z17.s\n" + ".inst 0x44828228 // srshl z8.s, p0/M, z8.s, z17.s\n" + ".inst 0x44828227 // srshl z7.s, p0/M, z7.s, z17.s\n" + ".inst 0x44828226 // srshl z6.s, p0/M, z6.s, z17.s\n" + ".inst 0x44828225 // srshl z5.s, p0/M, z5.s, z17.s\n" + ".inst 0x44828224 // srshl z4.s, p0/M, z4.s, z17.s\n" + ".inst 0x44828223 // srshl z3.s, p0/M, z3.s, z17.s\n" + ".inst 0x44828222 // srshl z2.s, p0/M, z2.s, z17.s\n" + ".inst 0x44828221 // srshl z1.s, p0/M, z1.s, z17.s\n" + ".inst 0x44828220 // srshl z0.s, p0/M, z0.s, z17.s\n" + "add z15.s, z15.s, z16.s\n" + "add z14.s, z14.s, z16.s\n" + "add z13.s, z13.s, z16.s\n" + "add z12.s, z12.s, z16.s\n" + "add z11.s, z11.s, z16.s\n" + "add z10.s, z10.s, z16.s\n" + "add z9.s, z9.s, z16.s\n" + "add z8.s, z8.s, z16.s\n" + "add z7.s, z7.s, z16.s\n" + "add z6.s, z6.s, z16.s\n" + "add z5.s, z5.s, z16.s\n" + "add z4.s, z4.s, z16.s\n" + "add z3.s, z3.s, z16.s\n" + "add z2.s, z2.s, z16.s\n" + "add z1.s, z1.s, z16.s\n" + "add z0.s, z0.s, z16.s\n" + "mov z16.s, #0x0\n" + "mov z19.s, #0xff\n" + "smax z15.s, p0/M, z15.s, z16.s\n" + "smax z14.s, p0/M, z14.s, z16.s\n" + "smax z13.s, p0/M, z13.s, z16.s\n" + "smax z12.s, p0/M, z12.s, z16.s\n" + "smax z11.s, p0/M, z11.s, z16.s\n" + "smax z10.s, p0/M, z10.s, z16.s\n" + "smax z9.s, p0/M, z9.s, z16.s\n" + "smax z8.s, p0/M, z8.s, z16.s\n" + "smax z7.s, p0/M, z7.s, z16.s\n" + "smax z6.s, p0/M, z6.s, z16.s\n" + "smax z5.s, p0/M, z5.s, z16.s\n" + "smax z4.s, p0/M, z4.s, z16.s\n" + "smax z3.s, p0/M, z3.s, z16.s\n" + "smax z2.s, p0/M, z2.s, z16.s\n" + "smax z1.s, p0/M, z1.s, z16.s\n" + "smax z0.s, p0/M, z0.s, z16.s\n" + "smin z15.s, p0/M, z15.s, z19.s\n" + "smin z14.s, p0/M, z14.s, z19.s\n" + "trn1 z23.h, z15.h, z14.h\n" + "smin z13.s, p0/M, z13.s, z19.s\n" + "smin z12.s, p0/M, z12.s, z19.s\n" + "trn1 z16.h, z13.h, z12.h\n" + "smin z11.s, p0/M, z11.s, z19.s\n" + "smin z10.s, p0/M, z10.s, z19.s\n" + "trn1 z22.h, z11.h, z10.h\n" + "smin z9.s, p0/M, z9.s, z19.s\n" + "smin z8.s, p0/M, z8.s, z19.s\n" + "trn1 z18.h, z9.h, z8.h\n" + "smin z7.s, p0/M, z7.s, z19.s\n" + "smin z6.s, p0/M, z6.s, z19.s\n" + "trn1 z21.h, z7.h, z6.h\n" + "smin z5.s, p0/M, z5.s, z19.s\n" + "smin z4.s, p0/M, z4.s, z19.s\n" + "trn1 z17.h, z5.h, z4.h\n" + "smin z3.s, p0/M, z3.s, z19.s\n" + "smin z2.s, p0/M, z2.s, z19.s\n" + "trn1 z20.h, z3.h, z2.h\n" + "smin z1.s, p0/M, z1.s, z19.s\n" + "smin z0.s, p0/M, z0.s, z19.s\n" + "trn1 z19.h, z1.h, z0.h\n" + "trn1 z16.b, z23.b, z16.b\n" + "trn1 z18.b, z22.b, z18.b\n" + "st1b { z16.b }, p4, [%x[outptr], x26]\n" + "incb x26, ALL, MUL #4\n" + "trn1 z17.b, z21.b, z17.b\n" + "trn1 z16.b, z20.b, z19.b\n" + "st1b { z18.b }, p3, [%x[outptr], x25]\n" + "incb x25, ALL, MUL #4\n" + "st1b { z17.b }, p2, [%x[outptr], x24]\n" + "incb x24, ALL, MUL #4\n" + "st1b { z16.b }, p1, [%x[outptr], x23]\n" + "incb x23, ALL, MUL #4\n" + "whilelt p1.b, x23, %x[n_channels]\n" + "b.any 1b\n" + "7:" // Single vector of channels + "whilelt p4.b, x26, %x[n_channels]\n" + "b.none 14f\n" + "8:" // Single vector of channels: Loop + "ld1rw { z15.s }, p0/Z, [%x[accumulator_init]]\n" + "lsr x22, %x[n_valid_cells], #0x1\n" + "mov z14.d, z15.d\n" + "mov z13.d, z15.d\n" + "mov z12.d, z15.d\n" + "mov x19, %x[inptrs]\n" + "cbz x22, 11f\n" + "ldp x21, x20, [x19, #0x0]\n" + "subs x22, x22, #0x1\n" + "add x19, x19, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x26]\n" + "ld1b { z30.b }, p4/Z, [x20, x26]\n" + "beq 10f\n" + "9:" // Single vector of channels: Loop: 2 inputs loop + ".inst 0x455e0bf7 // uaddlb z23.h, z31.b, z30.b\n" + ".inst 0x455e0ff6 // uaddlt z22.h, z31.b, z30.b\n" + "ldp x21, x20, [x19, #0x0]\n" + "subs x22, x22, #0x1\n" + ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" + ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" + "add x19, x19, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x26]\n" + ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" + ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" + "ld1b { z30.b }, p4/Z, [x20, x26]\n" + "bgt 9b\n" + "10:" // Single vector of channels: Loop: 2 inputs tail + ".inst 0x455e0bf7 // uaddlb z23.h, z31.b, z30.b\n" + ".inst 0x455e0ff6 // uaddlt z22.h, z31.b, z30.b\n" + ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" + ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" + ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" + ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" + "11:" // Single vector of channels: Loop: After loop + "ands x20, %x[n_valid_cells], #0x1\n" + "beq 13f\n" + "12:" // Single vector of channels: Loop: Single input loop + "ldr x21, [x19], #0x8\n" + "ld1b { z31.b }, p4/Z, [x21, x26]\n" + ".inst 0x4508abf7 // ushllb z23.h, z31.b, #0x0\n" + ".inst 0x4508aff6 // ushllt z22.h, z31.b, #0x0\n" + "subs x20, x20, #0x1\n" + ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" + ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" + ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" + ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" + "bgt 12b\n" + "13:" // Single vector of channels: Loop: Single input loop: End + "ld1rw { z19.s }, p0/Z, [%x[left_shift]]\n" + ".inst 0x4482826f // srshl z15.s, p0/M, z15.s, z19.s\n" + ".inst 0x4482826e // srshl z14.s, p0/M, z14.s, z19.s\n" + "add x19, %x[quant_params], %[offsetof_qp_output_offset]\n" + ".inst 0x4482826d // srshl z13.s, p0/M, z13.s, z19.s\n" + ".inst 0x4482826c // srshl z12.s, p0/M, z12.s, z19.s\n" + "ld1rw { z18.s }, p0/Z, [%x[combined_rescale_value]]\n" + ".inst 0x04b275ef // sqrdmulh z15.s, z15.s, z18.s\n" + ".inst 0x04b275ce // sqrdmulh z14.s, z14.s, z18.s\n" + "ld1rw { z17.s }, p0/Z, [%x[right_shift]]\n" + ".inst 0x04b275ad // sqrdmulh z13.s, z13.s, z18.s\n" + ".inst 0x04b2758c // sqrdmulh z12.s, z12.s, z18.s\n" + "ld1rw { z16.s }, p0/Z, [x19]\n" + ".inst 0x4482822f // srshl z15.s, p0/M, z15.s, z17.s\n" + ".inst 0x4482822e // srshl z14.s, p0/M, z14.s, z17.s\n" + ".inst 0x4482822d // srshl z13.s, p0/M, z13.s, z17.s\n" + ".inst 0x4482822c // srshl z12.s, p0/M, z12.s, z17.s\n" + "add z15.s, z15.s, z16.s\n" + "add z14.s, z14.s, z16.s\n" + "add z13.s, z13.s, z16.s\n" + "add z12.s, z12.s, z16.s\n" + "mov z16.s, #0x0\n" + "mov z19.s, #0xff\n" + "smax z15.s, p0/M, z15.s, z16.s\n" + "smax z14.s, p0/M, z14.s, z16.s\n" + "smax z13.s, p0/M, z13.s, z16.s\n" + "smax z12.s, p0/M, z12.s, z16.s\n" + "smin z15.s, p0/M, z15.s, z19.s\n" + "smin z14.s, p0/M, z14.s, z19.s\n" + "trn1 z23.h, z15.h, z14.h\n" + "smin z13.s, p0/M, z13.s, z19.s\n" + "smin z12.s, p0/M, z12.s, z19.s\n" + "trn1 z16.h, z13.h, z12.h\n" + "trn1 z16.b, z23.b, z16.b\n" + "st1b { z16.b }, p4, [%x[outptr], x26]\n" + "incb x26\n" + "whilelt p4.b, x26, %x[n_channels]\n" + "b.any 8b\n" + "14:" // End + ".inst 0xd503467f // SMSTOP\n" + : + : [accumulator_init] "r" (&accumulator_init), [combined_rescale_value] "r" (&combined_rescale_value), [inptrs] "r" (inptrs), [left_shift] "r" (&left_shift), [n_channels] "r" (n_channels), [n_valid_cells] "r" (n_valid_cells), [offsetof_qp_output_offset] "I" (offsetof(Requantize32, output_offset)), [outptr] "r" (outptr), [quant_params] "r" (&qp), [right_shift] "r" (&right_shift) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8q_nhwc_max_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8q_nhwc_max_generic_depthfirst.hpp new file mode 100644 index 0000000000..d7bf6cbd08 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8q_nhwc_max_generic_depthfirst.hpp @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstdint> + +#pragma once + +namespace arm_conv { +namespace pooling { + +void sme_u8q_nhwc_max_generic_depthfirst_impl(const uint64_t, const uint64_t n_valid_cells, uint64_t n_channels, const uint8_t *const *const inptrs, uint8_t *outptr, const Requantize32 &qp); + +struct sme_u8q_nhwc_max_generic_depthfirst : IGenericDepthfirstStrategy<uint8_t, uint8_t, Requantize32> +{ + using Parent = IGenericDepthfirstStrategy<uint8_t, uint8_t, Requantize32>; + sme_u8q_nhwc_max_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return sme_u8q_nhwc_max_generic_depthfirst_impl; } +}; + +} // namespace pooling +} // namespace arm_conv diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8q_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8q_nhwc_max_generic_depthfirst/generic.cpp new file mode 100644 index 0000000000..7914e357c4 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8q_nhwc_max_generic_depthfirst/generic.cpp @@ -0,0 +1,417 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if defined(ARM_COMPUTE_ENABLE_SME) + +#include "src/core/NEON/kernels/assembly/pooling.hpp" +#include <cstdint> + +namespace arm_conv { +namespace pooling { + + +void sme_u8q_nhwc_max_generic_depthfirst_impl( + const uint64_t, + const uint64_t n_valid_cells, + uint64_t n_channels, + const uint8_t *const *const inptrs, + uint8_t *outptr, + const Requantize32 &qp +) +{ + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "mov x28, #0x0\n" + "cntb x27\n" + "cntb x26, ALL, MUL #2\n" + "cntb x25, ALL, MUL #3\n" + "whilelt p4.b, x28, %x[n_channels]\n" + "whilelt p3.b, x27, %x[n_channels]\n" + "whilelt p2.b, x26, %x[n_channels]\n" + "whilelt p1.b, x25, %x[n_channels]\n" + "ptrue p0.b\n" + "b.none 7f\n" + "1:" // 4-vectors of channels + "lsr x24, %x[n_valid_cells], #0x2\n" + "mov z5.b, #0x0\n" + "mov z3.b, #0x0\n" + "mov x19, %x[inptrs]\n" + "mov z2.b, #0x0\n" + "mov z1.b, #0x0\n" + "cbz x24, 4f\n" + "ldp x23, x22, [x19, #0x0]\n" + "subs x24, x24, #0x1\n" + "ld1b { z0.b }, p4/Z, [x23, x28]\n" + "ldp x21, x20, [x19, #0x10]\n" + "add x19, x19, #0x20\n" + "ld1b { z31.b }, p4/Z, [x22, x28]\n" + "ld1b { z23.b }, p4/Z, [x21, x28]\n" + "ld1b { z30.b }, p4/Z, [x20, x28]\n" + "ld1b { z18.b }, p3/Z, [x23, x27]\n" + "ld1b { z29.b }, p3/Z, [x22, x27]\n" + "ld1b { z22.b }, p3/Z, [x21, x27]\n" + "ld1b { z28.b }, p3/Z, [x20, x27]\n" + "ld1b { z17.b }, p2/Z, [x23, x26]\n" + "ld1b { z27.b }, p2/Z, [x22, x26]\n" + "ld1b { z21.b }, p2/Z, [x21, x26]\n" + "ld1b { z26.b }, p2/Z, [x20, x26]\n" + "ld1b { z16.b }, p1/Z, [x23, x25]\n" + "ld1b { z25.b }, p1/Z, [x22, x25]\n" + "ld1b { z20.b }, p1/Z, [x21, x25]\n" + "ld1b { z24.b }, p1/Z, [x20, x25]\n" + "beq 3f\n" + "2:" // 4-vectors of channels: 4 inputs loop + "movprfx z19, z0\n umax z19.b, p0/M, z19.b, z31.b\n" + "umax z23.b, p0/M, z23.b, z30.b\n" + "ldp x23, x22, [x19, #0x0]\n" + "subs x24, x24, #0x1\n" + "umax z18.b, p0/M, z18.b, z29.b\n" + "umax z22.b, p0/M, z22.b, z28.b\n" + "ldp x21, x20, [x19, #0x10]\n" + "add x19, x19, #0x20\n" + "umax z17.b, p0/M, z17.b, z27.b\n" + "umax z21.b, p0/M, z21.b, z26.b\n" + "ld1b { z0.b }, p4/Z, [x23, x28]\n" + "umax z16.b, p0/M, z16.b, z25.b\n" + "umax z20.b, p0/M, z20.b, z24.b\n" + "ld1b { z31.b }, p4/Z, [x22, x28]\n" + "umax z19.b, p0/M, z19.b, z23.b\n" + "umax z18.b, p0/M, z18.b, z22.b\n" + "ld1b { z23.b }, p4/Z, [x21, x28]\n" + "umax z17.b, p0/M, z17.b, z21.b\n" + "umax z16.b, p0/M, z16.b, z20.b\n" + "ld1b { z30.b }, p4/Z, [x20, x28]\n" + "umax z5.b, p0/M, z5.b, z19.b\n" + "umax z3.b, p0/M, z3.b, z18.b\n" + "ld1b { z18.b }, p3/Z, [x23, x27]\n" + "umax z2.b, p0/M, z2.b, z17.b\n" + "umax z1.b, p0/M, z1.b, z16.b\n" + "ld1b { z29.b }, p3/Z, [x22, x27]\n" + "ld1b { z22.b }, p3/Z, [x21, x27]\n" + "ld1b { z28.b }, p3/Z, [x20, x27]\n" + "ld1b { z17.b }, p2/Z, [x23, x26]\n" + "ld1b { z27.b }, p2/Z, [x22, x26]\n" + "ld1b { z21.b }, p2/Z, [x21, x26]\n" + "ld1b { z26.b }, p2/Z, [x20, x26]\n" + "ld1b { z16.b }, p1/Z, [x23, x25]\n" + "ld1b { z25.b }, p1/Z, [x22, x25]\n" + "ld1b { z20.b }, p1/Z, [x21, x25]\n" + "ld1b { z24.b }, p1/Z, [x20, x25]\n" + "bgt 2b\n" + "3:" // 4-vectors of channels: 4 inputs tail + "movprfx z19, z0\n umax z19.b, p0/M, z19.b, z31.b\n" + "umax z23.b, p0/M, z23.b, z30.b\n" + "umax z18.b, p0/M, z18.b, z29.b\n" + "umax z22.b, p0/M, z22.b, z28.b\n" + "umax z17.b, p0/M, z17.b, z27.b\n" + "umax z21.b, p0/M, z21.b, z26.b\n" + "umax z16.b, p0/M, z16.b, z25.b\n" + "umax z20.b, p0/M, z20.b, z24.b\n" + "umax z19.b, p0/M, z19.b, z23.b\n" + "umax z18.b, p0/M, z18.b, z22.b\n" + "umax z17.b, p0/M, z17.b, z21.b\n" + "umax z16.b, p0/M, z16.b, z20.b\n" + "umax z5.b, p0/M, z5.b, z19.b\n" + "umax z3.b, p0/M, z3.b, z18.b\n" + "umax z2.b, p0/M, z2.b, z17.b\n" + "umax z1.b, p0/M, z1.b, z16.b\n" + "4:" // 4-vectors of channels: After loop + "ands x20, %x[n_valid_cells], #0x3\n" + "beq 6f\n" + "5:" // 4-vectors of channels: Single input loop + "ldr x23, [x19], #0x8\n" + "ld1b { z0.b }, p4/Z, [x23, x28]\n" + "subs x20, x20, #0x1\n" + "umax z5.b, p0/M, z5.b, z0.b\n" + "ld1b { z18.b }, p3/Z, [x23, x27]\n" + "umax z3.b, p0/M, z3.b, z18.b\n" + "ld1b { z17.b }, p2/Z, [x23, x26]\n" + "umax z2.b, p0/M, z2.b, z17.b\n" + "ld1b { z16.b }, p1/Z, [x23, x25]\n" + "umax z1.b, p0/M, z1.b, z16.b\n" + "bgt 5b\n" + "6:" // 4-vectors of channels: Single input loop: End + "add x19, %x[quant_params], %[offsetof_qp_input_offset]\n" + "ld1rw { z4.s }, p0/Z, [x19]\n" + ".inst 0x4508a8b7 // ushllb z23.h, z5.b, #0x0\n" + ".inst 0x4508acb9 // ushllt z25.h, z5.b, #0x0\n" + ".inst 0x4508a876 // ushllb z22.h, z3.b, #0x0\n" + ".inst 0x4508ac72 // ushllt z18.h, z3.b, #0x0\n" + "add x19, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n" + "ld1rw { z3.s }, p0/Z, [x19]\n" + ".inst 0x4508a855 // ushllb z21.h, z2.b, #0x0\n" + ".inst 0x4508ac51 // ushllt z17.h, z2.b, #0x0\n" + "add x19, %x[quant_params], %[offsetof_qp_per_layer_mul]\n" + "ld1rw { z2.s }, p0/Z, [x19]\n" + ".inst 0x4508a834 // ushllb z20.h, z1.b, #0x0\n" + ".inst 0x4508ac38 // ushllt z24.h, z1.b, #0x0\n" + "add x19, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n" + "ld1rw { z19.s }, p0/Z, [x19]\n" + "neg z4.s, p0/M, z4.s\n" + ".inst 0x45974081 // saddwb z1.s, z4.s, z23.h\n" + "add x19, %x[quant_params], %[offsetof_qp_output_offset]\n" + "ld1rw { z16.s }, p0/Z, [x19]\n" + ".inst 0x45974497 // saddwt z23.s, z4.s, z23.h\n" + ".inst 0x45994080 // saddwb z0.s, z4.s, z25.h\n" + ".inst 0x4599449f // saddwt z31.s, z4.s, z25.h\n" + ".inst 0x4596409e // saddwb z30.s, z4.s, z22.h\n" + ".inst 0x45964496 // saddwt z22.s, z4.s, z22.h\n" + ".inst 0x4592409d // saddwb z29.s, z4.s, z18.h\n" + ".inst 0x45924492 // saddwt z18.s, z4.s, z18.h\n" + ".inst 0x4595409c // saddwb z28.s, z4.s, z21.h\n" + ".inst 0x45954495 // saddwt z21.s, z4.s, z21.h\n" + ".inst 0x4591409b // saddwb z27.s, z4.s, z17.h\n" + ".inst 0x45914491 // saddwt z17.s, z4.s, z17.h\n" + ".inst 0x4594409a // saddwb z26.s, z4.s, z20.h\n" + ".inst 0x45944494 // saddwt z20.s, z4.s, z20.h\n" + ".inst 0x45984099 // saddwb z25.s, z4.s, z24.h\n" + ".inst 0x45984498 // saddwt z24.s, z4.s, z24.h\n" + ".inst 0x44828061 // srshl z1.s, p0/M, z1.s, z3.s\n" + ".inst 0x44828077 // srshl z23.s, p0/M, z23.s, z3.s\n" + ".inst 0x44828060 // srshl z0.s, p0/M, z0.s, z3.s\n" + ".inst 0x4482807f // srshl z31.s, p0/M, z31.s, z3.s\n" + ".inst 0x4482807e // srshl z30.s, p0/M, z30.s, z3.s\n" + ".inst 0x44828076 // srshl z22.s, p0/M, z22.s, z3.s\n" + ".inst 0x4482807d // srshl z29.s, p0/M, z29.s, z3.s\n" + ".inst 0x44828072 // srshl z18.s, p0/M, z18.s, z3.s\n" + ".inst 0x4482807c // srshl z28.s, p0/M, z28.s, z3.s\n" + ".inst 0x44828075 // srshl z21.s, p0/M, z21.s, z3.s\n" + ".inst 0x4482807b // srshl z27.s, p0/M, z27.s, z3.s\n" + ".inst 0x44828071 // srshl z17.s, p0/M, z17.s, z3.s\n" + ".inst 0x4482807a // srshl z26.s, p0/M, z26.s, z3.s\n" + ".inst 0x44828074 // srshl z20.s, p0/M, z20.s, z3.s\n" + ".inst 0x44828079 // srshl z25.s, p0/M, z25.s, z3.s\n" + ".inst 0x44828078 // srshl z24.s, p0/M, z24.s, z3.s\n" + ".inst 0x04a27421 // sqrdmulh z1.s, z1.s, z2.s\n" + ".inst 0x04a276f7 // sqrdmulh z23.s, z23.s, z2.s\n" + ".inst 0x04a27400 // sqrdmulh z0.s, z0.s, z2.s\n" + ".inst 0x04a277ff // sqrdmulh z31.s, z31.s, z2.s\n" + ".inst 0x04a277de // sqrdmulh z30.s, z30.s, z2.s\n" + ".inst 0x04a276d6 // sqrdmulh z22.s, z22.s, z2.s\n" + ".inst 0x04a277bd // sqrdmulh z29.s, z29.s, z2.s\n" + ".inst 0x04a27652 // sqrdmulh z18.s, z18.s, z2.s\n" + ".inst 0x04a2779c // sqrdmulh z28.s, z28.s, z2.s\n" + ".inst 0x04a276b5 // sqrdmulh z21.s, z21.s, z2.s\n" + ".inst 0x04a2777b // sqrdmulh z27.s, z27.s, z2.s\n" + ".inst 0x04a27631 // sqrdmulh z17.s, z17.s, z2.s\n" + ".inst 0x04a2775a // sqrdmulh z26.s, z26.s, z2.s\n" + ".inst 0x04a27694 // sqrdmulh z20.s, z20.s, z2.s\n" + ".inst 0x04a27739 // sqrdmulh z25.s, z25.s, z2.s\n" + ".inst 0x04a27718 // sqrdmulh z24.s, z24.s, z2.s\n" + ".inst 0x44828261 // srshl z1.s, p0/M, z1.s, z19.s\n" + ".inst 0x44828277 // srshl z23.s, p0/M, z23.s, z19.s\n" + ".inst 0x44828260 // srshl z0.s, p0/M, z0.s, z19.s\n" + ".inst 0x4482827f // srshl z31.s, p0/M, z31.s, z19.s\n" + ".inst 0x4482827e // srshl z30.s, p0/M, z30.s, z19.s\n" + ".inst 0x44828276 // srshl z22.s, p0/M, z22.s, z19.s\n" + ".inst 0x4482827d // srshl z29.s, p0/M, z29.s, z19.s\n" + ".inst 0x44828272 // srshl z18.s, p0/M, z18.s, z19.s\n" + ".inst 0x4482827c // srshl z28.s, p0/M, z28.s, z19.s\n" + ".inst 0x44828275 // srshl z21.s, p0/M, z21.s, z19.s\n" + ".inst 0x4482827b // srshl z27.s, p0/M, z27.s, z19.s\n" + ".inst 0x44828271 // srshl z17.s, p0/M, z17.s, z19.s\n" + ".inst 0x4482827a // srshl z26.s, p0/M, z26.s, z19.s\n" + ".inst 0x44828274 // srshl z20.s, p0/M, z20.s, z19.s\n" + ".inst 0x44828279 // srshl z25.s, p0/M, z25.s, z19.s\n" + ".inst 0x44828278 // srshl z24.s, p0/M, z24.s, z19.s\n" + "add z1.s, z1.s, z16.s\n" + "add z23.s, z23.s, z16.s\n" + "add z0.s, z0.s, z16.s\n" + "add z31.s, z31.s, z16.s\n" + "add z30.s, z30.s, z16.s\n" + "add z22.s, z22.s, z16.s\n" + "add z29.s, z29.s, z16.s\n" + "add z18.s, z18.s, z16.s\n" + "add z28.s, z28.s, z16.s\n" + "add z21.s, z21.s, z16.s\n" + "add z27.s, z27.s, z16.s\n" + "add z17.s, z17.s, z16.s\n" + "add z26.s, z26.s, z16.s\n" + "add z20.s, z20.s, z16.s\n" + "add z25.s, z25.s, z16.s\n" + "add z24.s, z24.s, z16.s\n" + "mov z16.s, #0x0\n" + "mov z19.s, #0xff\n" + "smax z1.s, p0/M, z1.s, z16.s\n" + "smax z23.s, p0/M, z23.s, z16.s\n" + "smax z0.s, p0/M, z0.s, z16.s\n" + "smax z31.s, p0/M, z31.s, z16.s\n" + "smax z30.s, p0/M, z30.s, z16.s\n" + "smax z22.s, p0/M, z22.s, z16.s\n" + "smax z29.s, p0/M, z29.s, z16.s\n" + "smax z18.s, p0/M, z18.s, z16.s\n" + "smax z28.s, p0/M, z28.s, z16.s\n" + "smax z21.s, p0/M, z21.s, z16.s\n" + "smax z27.s, p0/M, z27.s, z16.s\n" + "smax z17.s, p0/M, z17.s, z16.s\n" + "smax z26.s, p0/M, z26.s, z16.s\n" + "smax z20.s, p0/M, z20.s, z16.s\n" + "smax z25.s, p0/M, z25.s, z16.s\n" + "smax z24.s, p0/M, z24.s, z16.s\n" + "smin z1.s, p0/M, z1.s, z19.s\n" + "smin z23.s, p0/M, z23.s, z19.s\n" + "smin z0.s, p0/M, z0.s, z19.s\n" + "trn1 z23.h, z1.h, z23.h\n" + "smin z31.s, p0/M, z31.s, z19.s\n" + "smin z30.s, p0/M, z30.s, z19.s\n" + "trn1 z16.h, z0.h, z31.h\n" + "smin z22.s, p0/M, z22.s, z19.s\n" + "smin z29.s, p0/M, z29.s, z19.s\n" + "trn1 z22.h, z30.h, z22.h\n" + "smin z18.s, p0/M, z18.s, z19.s\n" + "smin z28.s, p0/M, z28.s, z19.s\n" + "trn1 z18.h, z29.h, z18.h\n" + "smin z21.s, p0/M, z21.s, z19.s\n" + "smin z27.s, p0/M, z27.s, z19.s\n" + "trn1 z21.h, z28.h, z21.h\n" + "smin z17.s, p0/M, z17.s, z19.s\n" + "smin z26.s, p0/M, z26.s, z19.s\n" + "trn1 z17.h, z27.h, z17.h\n" + "smin z20.s, p0/M, z20.s, z19.s\n" + "smin z25.s, p0/M, z25.s, z19.s\n" + "trn1 z20.h, z26.h, z20.h\n" + "smin z24.s, p0/M, z24.s, z19.s\n" + "trn1 z19.h, z25.h, z24.h\n" + "trn1 z16.b, z23.b, z16.b\n" + "trn1 z18.b, z22.b, z18.b\n" + "trn1 z17.b, z21.b, z17.b\n" + "st1b { z16.b }, p4, [%x[outptr], x28]\n" + "incb x28, ALL, MUL #4\n" + "trn1 z16.b, z20.b, z19.b\n" + "st1b { z18.b }, p3, [%x[outptr], x27]\n" + "incb x27, ALL, MUL #4\n" + "st1b { z17.b }, p2, [%x[outptr], x26]\n" + "incb x26, ALL, MUL #4\n" + "st1b { z16.b }, p1, [%x[outptr], x25]\n" + "incb x25, ALL, MUL #4\n" + "whilelt p1.b, x25, %x[n_channels]\n" + "b.any 1b\n" + "7:" // Single vector of channels + "whilelt p4.b, x28, %x[n_channels]\n" + "b.none 14f\n" + "8:" // Single vector of channels: Loop + "lsr x24, %x[n_valid_cells], #0x2\n" + "mov z5.b, #0x0\n" + "mov x19, %x[inptrs]\n" + "cbz x24, 11f\n" + "ldp x23, x22, [x19, #0x0]\n" + "subs x24, x24, #0x1\n" + "ld1b { z0.b }, p4/Z, [x23, x28]\n" + "ldp x21, x20, [x19, #0x10]\n" + "add x19, x19, #0x20\n" + "ld1b { z31.b }, p4/Z, [x22, x28]\n" + "ld1b { z23.b }, p4/Z, [x21, x28]\n" + "ld1b { z30.b }, p4/Z, [x20, x28]\n" + "beq 10f\n" + "9:" // Single vector of channels: Loop: 4 inputs loop + "movprfx z19, z0\n umax z19.b, p0/M, z19.b, z31.b\n" + "umax z23.b, p0/M, z23.b, z30.b\n" + "ldp x23, x22, [x19, #0x0]\n" + "subs x24, x24, #0x1\n" + "umax z19.b, p0/M, z19.b, z23.b\n" + "ldp x21, x20, [x19, #0x10]\n" + "umax z5.b, p0/M, z5.b, z19.b\n" + "add x19, x19, #0x20\n" + "ld1b { z0.b }, p4/Z, [x23, x28]\n" + "ld1b { z31.b }, p4/Z, [x22, x28]\n" + "ld1b { z23.b }, p4/Z, [x21, x28]\n" + "ld1b { z30.b }, p4/Z, [x20, x28]\n" + "bgt 9b\n" + "10:" // Single vector of channels: Loop: 4 inputs tail + "movprfx z19, z0\n umax z19.b, p0/M, z19.b, z31.b\n" + "umax z23.b, p0/M, z23.b, z30.b\n" + "umax z19.b, p0/M, z19.b, z23.b\n" + "umax z5.b, p0/M, z5.b, z19.b\n" + "11:" // Single vector of channels: Loop: After loop + "ands x20, %x[n_valid_cells], #0x3\n" + "beq 13f\n" + "12:" // Single vector of channels: Loop: Single input loop + "ldr x23, [x19], #0x8\n" + "ld1b { z0.b }, p4/Z, [x23, x28]\n" + "subs x20, x20, #0x1\n" + "umax z5.b, p0/M, z5.b, z0.b\n" + "bgt 12b\n" + "13:" // Single vector of channels: Loop: Single input loop: End + "add x19, %x[quant_params], %[offsetof_qp_input_offset]\n" + "ld1rw { z4.s }, p0/Z, [x19]\n" + ".inst 0x4508a8b7 // ushllb z23.h, z5.b, #0x0\n" + ".inst 0x4508acb9 // ushllt z25.h, z5.b, #0x0\n" + "neg z4.s, p0/M, z4.s\n" + ".inst 0x45974081 // saddwb z1.s, z4.s, z23.h\n" + "add x19, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n" + "ld1rw { z3.s }, p0/Z, [x19]\n" + ".inst 0x45974497 // saddwt z23.s, z4.s, z23.h\n" + ".inst 0x45994080 // saddwb z0.s, z4.s, z25.h\n" + "add x19, %x[quant_params], %[offsetof_qp_per_layer_mul]\n" + "ld1rw { z2.s }, p0/Z, [x19]\n" + ".inst 0x4599449f // saddwt z31.s, z4.s, z25.h\n" + ".inst 0x44828061 // srshl z1.s, p0/M, z1.s, z3.s\n" + "add x19, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n" + "ld1rw { z19.s }, p0/Z, [x19]\n" + ".inst 0x44828077 // srshl z23.s, p0/M, z23.s, z3.s\n" + ".inst 0x44828060 // srshl z0.s, p0/M, z0.s, z3.s\n" + "add x19, %x[quant_params], %[offsetof_qp_output_offset]\n" + "ld1rw { z16.s }, p0/Z, [x19]\n" + ".inst 0x4482807f // srshl z31.s, p0/M, z31.s, z3.s\n" + ".inst 0x04a27421 // sqrdmulh z1.s, z1.s, z2.s\n" + ".inst 0x04a276f7 // sqrdmulh z23.s, z23.s, z2.s\n" + ".inst 0x04a27400 // sqrdmulh z0.s, z0.s, z2.s\n" + ".inst 0x04a277ff // sqrdmulh z31.s, z31.s, z2.s\n" + ".inst 0x44828261 // srshl z1.s, p0/M, z1.s, z19.s\n" + ".inst 0x44828277 // srshl z23.s, p0/M, z23.s, z19.s\n" + ".inst 0x44828260 // srshl z0.s, p0/M, z0.s, z19.s\n" + ".inst 0x4482827f // srshl z31.s, p0/M, z31.s, z19.s\n" + "add z1.s, z1.s, z16.s\n" + "add z23.s, z23.s, z16.s\n" + "add z0.s, z0.s, z16.s\n" + "add z31.s, z31.s, z16.s\n" + "mov z16.s, #0x0\n" + "mov z19.s, #0xff\n" + "smax z1.s, p0/M, z1.s, z16.s\n" + "smax z23.s, p0/M, z23.s, z16.s\n" + "smax z0.s, p0/M, z0.s, z16.s\n" + "smax z31.s, p0/M, z31.s, z16.s\n" + "smin z1.s, p0/M, z1.s, z19.s\n" + "smin z23.s, p0/M, z23.s, z19.s\n" + "smin z0.s, p0/M, z0.s, z19.s\n" + "trn1 z23.h, z1.h, z23.h\n" + "smin z31.s, p0/M, z31.s, z19.s\n" + "trn1 z16.h, z0.h, z31.h\n" + "trn1 z16.b, z23.b, z16.b\n" + "st1b { z16.b }, p4, [%x[outptr], x28]\n" + "incb x28\n" + "whilelt p4.b, x28, %x[n_channels]\n" + "b.any 8b\n" + "14:" // End + ".inst 0xd503467f // SMSTOP\n" + : + : [inptrs] "r" (inptrs), [n_channels] "r" (n_channels), [n_valid_cells] "r" (n_valid_cells), [offsetof_qp_input_offset] "I" (offsetof(Requantize32, input_offset)), [offsetof_qp_output_offset] "I" (offsetof(Requantize32, output_offset)), [offsetof_qp_per_layer_left_shift] "I" (offsetof(Requantize32, per_layer_left_shift)), [offsetof_qp_per_layer_mul] "I" (offsetof(Requantize32, per_layer_mul)), [offsetof_qp_per_layer_right_shift] "I" (offsetof(Requantize32, per_layer_right_shift)), [outptr] "r" (outptr), [quant_params] "r" (&qp) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) |