diff options
Diffstat (limited to 'src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_avg_generic_depthfirst')
-rw-r--r-- | src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_avg_generic_depthfirst/generic.cpp | 252 |
1 files changed, 126 insertions, 126 deletions
diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_avg_generic_depthfirst/generic.cpp index a2487b0592..e889782fa3 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_avg_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_avg_generic_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -115,16 +115,16 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( __asm__ __volatile__( "cmp %x[n_channels], #0x40\n" - "mov x26, #0x0\n" - "mov x25, #0x10\n" // cntb _, ALL, #1 - "mov x24, #0x20\n" // cntb _, ALL, #2 - "mov x23, #0x30\n" // cntb _, ALL, #3 + "mov x27, #0x0\n" + "mov x26, #0x10\n" // cntb _, ALL, #1 + "mov x25, #0x20\n" // cntb _, ALL, #2 + "mov x24, #0x30\n" // cntb _, ALL, #3 "blt 7f\n" "1:" // 4-vectors of channels - "lsr x22, %x[n_valid_cells], #0x1\n" + "lsr x23, %x[n_valid_cells], #0x1\n" "movi v15.4s, #0x0\n" "movi v14.4s, #0x0\n" - "mov x19, %x[inptrs]\n" + "mov x20, %x[inptrs]\n" "movi v13.4s, #0x0\n" "movi v12.4s, #0x0\n" "movi v11.4s, #0x0\n" @@ -139,43 +139,43 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( "movi v2.4s, #0x0\n" "movi v1.4s, #0x0\n" "movi v0.4s, #0x0\n" - "cbz x22, 4f\n" - "ldp x21, x20, [x19, #0x0]\n" - "subs x22, x22, #0x1\n" - "add x19, x19, #0x10\n" - "ldr q31, [x21, x26]\n" - "ldr q30, [x20, x26]\n" - "ldr q29, [x21, x25]\n" - "ldr q28, [x20, x25]\n" - "ldr q27, [x21, x24]\n" - "ldr q26, [x20, x24]\n" - "ldr q25, [x21, x23]\n" - "ldr q24, [x20, x23]\n" + "cbz x23, 4f\n" + "ldp x22, x21, [x20, #0x0]\n" + "ldr q31, [x22, x27]\n" + "subs x23, x23, #0x1\n" + "add x20, x20, #0x10\n" + "ldr q30, [x21, x27]\n" + "ldr q29, [x22, x26]\n" + "ldr q28, [x21, x26]\n" + "ldr q27, [x22, x25]\n" + "ldr q26, [x21, x25]\n" + "ldr q25, [x22, x24]\n" + "ldr q24, [x21, x24]\n" "beq 3f\n" "2:" // 4-vectors of channels: 2 inputs loop "saddl v23.8h, v31.8b, v30.8b\n" "saddl2 v22.8h, v31.16b, v30.16b\n" - "ldp x21, x20, [x19, #0x0]\n" - "subs x22, x22, #0x1\n" + "ldp x22, x21, [x20, #0x0]\n" + "ldr q31, [x22, x27]\n" + "ldr q30, [x21, x27]\n" "saddl v21.8h, v29.8b, v28.8b\n" "saddl2 v20.8h, v29.16b, v28.16b\n" - "add x19, x19, #0x10\n" - "ldr q31, [x21, x26]\n" + "ldr q29, [x22, x26]\n" + "ldr q28, [x21, x26]\n" "saddl v19.8h, v27.8b, v26.8b\n" "saddl2 v18.8h, v27.16b, v26.16b\n" - "ldr q30, [x20, x26]\n" - "ldr q29, [x21, x25]\n" - "saddl v17.8h, v25.8b, v24.8b\n" - "saddl2 v16.8h, v25.16b, v24.16b\n" - "ldr q28, [x20, x25]\n" - "ldr q27, [x21, x24]\n" + "ldr q27, [x22, x25]\n" + "ldr q26, [x21, x25]\n" + "subs x23, x23, #0x1\n" "saddw v15.4s, v15.4s, v23.4h\n" "saddw2 v14.4s, v14.4s, v23.8h\n" - "ldr q26, [x20, x24]\n" - "ldr q25, [x21, x23]\n" + "saddl v17.8h, v25.8b, v24.8b\n" + "saddl2 v16.8h, v25.16b, v24.16b\n" + "ldr q25, [x22, x24]\n" + "add x20, x20, #0x10\n" "saddw v13.4s, v13.4s, v22.4h\n" "saddw2 v12.4s, v12.4s, v22.8h\n" - "ldr q24, [x20, x23]\n" + "ldr q24, [x21, x24]\n" "saddw v11.4s, v11.4s, v21.4h\n" "saddw2 v10.4s, v10.4s, v21.8h\n" "saddw v9.4s, v9.4s, v20.4h\n" @@ -215,21 +215,21 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( "saddw v1.4s, v1.4s, v16.4h\n" "saddw2 v0.4s, v0.4s, v16.8h\n" "4:" // 4-vectors of channels: After loop - "ands x20, %x[n_valid_cells], #0x1\n" + "ands x21, %x[n_valid_cells], #0x1\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x21, [x19], #0x8\n" - "ldr q31, [x21, x26]\n" + "ldr x22, [x20], #0x8\n" + "ldr q31, [x22, x27]\n" "sxtl v23.8h, v31.8b\n" "sxtl2 v22.8h, v31.16b\n" - "ldr q29, [x21, x25]\n" - "ldr q27, [x21, x24]\n" + "ldr q29, [x22, x26]\n" + "ldr q27, [x22, x25]\n" "sxtl v21.8h, v29.8b\n" "sxtl2 v20.8h, v29.16b\n" - "ldr q25, [x21, x23]\n" + "ldr q25, [x22, x24]\n" "sxtl v19.8h, v27.8b\n" "sxtl2 v18.8h, v27.16b\n" - "subs x20, x20, #0x1\n" + "subs x21, x21, #0x1\n" "sxtl v17.8h, v25.8b\n" "sxtl2 v16.8h, v25.16b\n" "saddw v15.4s, v15.4s, v23.4h\n" @@ -254,9 +254,9 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( "ld1r { v17.4s }, [%x[combined_rescale_value]]\n" "srshl v15.4s, v15.4s, v18.4s\n" "srshl v14.4s, v14.4s, v18.4s\n" + "ld1r { v16.4s }, [%x[right_shift]]\n" "srshl v13.4s, v13.4s, v18.4s\n" "srshl v12.4s, v12.4s, v18.4s\n" - "ld1r { v16.4s }, [%x[right_shift]]\n" "sub %x[n_channels], %x[n_channels], #0x40\n" "srshl v11.4s, v11.4s, v18.4s\n" "srshl v10.4s, v10.4s, v18.4s\n" @@ -347,47 +347,47 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( "uzp1 v19.16b, v1.16b, v0.16b\n" "uzp1 v16.16b, v23.16b, v16.16b\n" "uzp1 v18.16b, v22.16b, v18.16b\n" - "str q16, [%x[outptr], x26]\n" - "add x26, x26, #0x40\n" + "str q16, [%x[outptr], x27]\n" + "add x27, x27, #0x40\n" "uzp1 v17.16b, v21.16b, v17.16b\n" "uzp1 v16.16b, v20.16b, v19.16b\n" - "str q18, [%x[outptr], x25]\n" + "str q18, [%x[outptr], x26]\n" + "add x26, x26, #0x40\n" + "str q17, [%x[outptr], x25]\n" "add x25, x25, #0x40\n" - "str q17, [%x[outptr], x24]\n" + "str q16, [%x[outptr], x24]\n" "add x24, x24, #0x40\n" - "str q16, [%x[outptr], x23]\n" - "add x23, x23, #0x40\n" "bge 1b\n" "cbz %x[n_channels], 43f\n" "7:" // Single vector of channels "cmp %x[n_channels], #0x10\n" "blt 14f\n" "8:" // Single vector of channels: Loop - "lsr x22, %x[n_valid_cells], #0x1\n" + "lsr x23, %x[n_valid_cells], #0x1\n" "movi v15.4s, #0x0\n" "movi v14.4s, #0x0\n" - "mov x19, %x[inptrs]\n" + "mov x20, %x[inptrs]\n" "movi v13.4s, #0x0\n" "movi v12.4s, #0x0\n" - "cbz x22, 11f\n" - "ldp x21, x20, [x19, #0x0]\n" - "subs x22, x22, #0x1\n" - "add x19, x19, #0x10\n" - "ldr q31, [x21, x26]\n" - "ldr q30, [x20, x26]\n" + "cbz x23, 11f\n" + "ldp x22, x21, [x20, #0x0]\n" + "ldr q31, [x22, x27]\n" + "subs x23, x23, #0x1\n" + "add x20, x20, #0x10\n" + "ldr q30, [x21, x27]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 2 inputs loop "saddl v23.8h, v31.8b, v30.8b\n" "saddl2 v22.8h, v31.16b, v30.16b\n" - "ldp x21, x20, [x19, #0x0]\n" - "subs x22, x22, #0x1\n" + "ldp x22, x21, [x20, #0x0]\n" + "ldr q31, [x22, x27]\n" + "ldr q30, [x21, x27]\n" + "subs x23, x23, #0x1\n" "saddw v15.4s, v15.4s, v23.4h\n" "saddw2 v14.4s, v14.4s, v23.8h\n" - "add x19, x19, #0x10\n" - "ldr q31, [x21, x26]\n" "saddw v13.4s, v13.4s, v22.4h\n" "saddw2 v12.4s, v12.4s, v22.8h\n" - "ldr q30, [x20, x26]\n" + "add x20, x20, #0x10\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 2 inputs tail "saddl v23.8h, v31.8b, v30.8b\n" @@ -397,14 +397,14 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( "saddw v13.4s, v13.4s, v22.4h\n" "saddw2 v12.4s, v12.4s, v22.8h\n" "11:" // Single vector of channels: Loop: After loop - "ands x20, %x[n_valid_cells], #0x1\n" + "ands x21, %x[n_valid_cells], #0x1\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x21, [x19], #0x8\n" - "ldr q31, [x21, x26]\n" + "ldr x22, [x20], #0x8\n" + "ldr q31, [x22, x27]\n" "sxtl v23.8h, v31.8b\n" "sxtl2 v22.8h, v31.16b\n" - "subs x20, x20, #0x1\n" + "subs x21, x21, #0x1\n" "saddw v15.4s, v15.4s, v23.4h\n" "saddw2 v14.4s, v14.4s, v23.8h\n" "saddw v13.4s, v13.4s, v22.4h\n" @@ -415,9 +415,9 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( "ld1r { v17.4s }, [%x[combined_rescale_value]]\n" "srshl v15.4s, v15.4s, v18.4s\n" "srshl v14.4s, v14.4s, v18.4s\n" + "ld1r { v16.4s }, [%x[right_shift]]\n" "srshl v13.4s, v13.4s, v18.4s\n" "srshl v12.4s, v12.4s, v18.4s\n" - "ld1r { v16.4s }, [%x[right_shift]]\n" "sub %x[n_channels], %x[n_channels], #0x10\n" "sqrdmulh v15.4s, v15.4s, v17.4s\n" "sqrdmulh v14.4s, v14.4s, v17.4s\n" @@ -441,149 +441,149 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( "uzp1 v23.16b, v15.16b, v14.16b\n" "uzp1 v16.16b, v13.16b, v12.16b\n" "uzp1 v16.16b, v23.16b, v16.16b\n" - "str q16, [%x[outptr], x26]\n" - "add x26, x26, #0x10\n" + "str q16, [%x[outptr], x27]\n" + "add x27, x27, #0x10\n" "bge 8b\n" "cbz %x[n_channels], 43f\n" "14:" // Oddments - "lsr x22, %x[n_valid_cells], #0x1\n" - "add %x[outptr], %x[outptr], x26\n" + "lsr x23, %x[n_valid_cells], #0x1\n" + "add %x[outptr], %x[outptr], x27\n" "movi v15.4s, #0x0\n" "movi v14.4s, #0x0\n" "movi v13.4s, #0x0\n" "movi v12.4s, #0x0\n" - "mov x19, %x[inptrs]\n" - "cbz x22, 24f\n" + "mov x20, %x[inptrs]\n" + "cbz x23, 24f\n" "15:" // Oddments: 2 inputs loop - "ldp x21, x20, [x19, #0x0]\n" - "add x19, x19, #0x10\n" - "add x21, x21, x26\n" + "ldp x22, x21, [x20, #0x0]\n" + "add x20, x20, #0x10\n" + "add x22, x22, x27\n" "movi v31.16b, #0x0\n" - "add x20, x20, x26\n" + "add x21, x21, x27\n" "movi v30.16b, #0x0\n" "tbz %x[n_channels], #3, 19f\n" - "ldr d31, [x21], #0x8\n" - "ldr d30, [x20], #0x8\n" + "ldr d31, [x22], #0x8\n" + "ldr d30, [x21], #0x8\n" "tbz %x[n_channels], #2, 17f\n" - "ld1 { v31.s }[2], [x21], #0x4\n" - "ld1 { v30.s }[2], [x20], #0x4\n" + "ld1 { v31.s }[2], [x22], #0x4\n" + "ld1 { v30.s }[2], [x21], #0x4\n" "tbz %x[n_channels], #1, 16f\n" - "ld1 { v31.h }[6], [x21], #0x2\n" - "ld1 { v30.h }[6], [x20], #0x2\n" + "ld1 { v31.h }[6], [x22], #0x2\n" + "ld1 { v30.h }[6], [x21], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v31.b }[14], [x21], #0x1\n" - "ld1 { v30.b }[14], [x20], #0x1\n" + "ld1 { v31.b }[14], [x22], #0x1\n" + "ld1 { v30.b }[14], [x21], #0x1\n" "b 23f\n" "16:" // Oddments: 2 inputs loop: Load: Bit 3: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ld1 { v31.b }[12], [x21], #0x1\n" - "ld1 { v30.b }[12], [x20], #0x1\n" + "ld1 { v31.b }[12], [x22], #0x1\n" + "ld1 { v30.b }[12], [x21], #0x1\n" "b 23f\n" "17:" // Oddments: 2 inputs loop: Load: Bit 3: Bit 2: Unset "tbz %x[n_channels], #1, 18f\n" - "ld1 { v31.h }[4], [x21], #0x2\n" - "ld1 { v30.h }[4], [x20], #0x2\n" + "ld1 { v31.h }[4], [x22], #0x2\n" + "ld1 { v30.h }[4], [x21], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v31.b }[10], [x21], #0x1\n" - "ld1 { v30.b }[10], [x20], #0x1\n" + "ld1 { v31.b }[10], [x22], #0x1\n" + "ld1 { v30.b }[10], [x21], #0x1\n" "b 23f\n" "18:" // Oddments: 2 inputs loop: Load: Bit 3: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ld1 { v31.b }[8], [x21], #0x1\n" - "ld1 { v30.b }[8], [x20], #0x1\n" + "ld1 { v31.b }[8], [x22], #0x1\n" + "ld1 { v30.b }[8], [x21], #0x1\n" "b 23f\n" "19:" // Oddments: 2 inputs loop: Load: Bit 3: Unset "tbz %x[n_channels], #2, 21f\n" - "ldr s31, [x21], #0x4\n" - "ldr s30, [x20], #0x4\n" + "ldr s31, [x22], #0x4\n" + "ldr s30, [x21], #0x4\n" "tbz %x[n_channels], #1, 20f\n" - "ld1 { v31.h }[2], [x21], #0x2\n" - "ld1 { v30.h }[2], [x20], #0x2\n" + "ld1 { v31.h }[2], [x22], #0x2\n" + "ld1 { v30.h }[2], [x21], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v31.b }[6], [x21], #0x1\n" - "ld1 { v30.b }[6], [x20], #0x1\n" + "ld1 { v31.b }[6], [x22], #0x1\n" + "ld1 { v30.b }[6], [x21], #0x1\n" "b 23f\n" "20:" // Oddments: 2 inputs loop: Load: Bit 3: Unset: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ld1 { v31.b }[4], [x21], #0x1\n" - "ld1 { v30.b }[4], [x20], #0x1\n" + "ld1 { v31.b }[4], [x22], #0x1\n" + "ld1 { v30.b }[4], [x21], #0x1\n" "b 23f\n" "21:" // Oddments: 2 inputs loop: Load: Bit 3: Unset: Bit 2: Unset "tbz %x[n_channels], #1, 22f\n" - "ldr h31, [x21], #0x2\n" - "ldr h30, [x20], #0x2\n" + "ldr h31, [x22], #0x2\n" + "ldr h30, [x21], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v31.b }[2], [x21], #0x1\n" - "ld1 { v30.b }[2], [x20], #0x1\n" + "ld1 { v31.b }[2], [x22], #0x1\n" + "ld1 { v30.b }[2], [x21], #0x1\n" "b 23f\n" "22:" // Oddments: 2 inputs loop: Load: Bit 3: Unset: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ldr b31, [x21], #0x1\n" - "ldr b30, [x20], #0x1\n" + "ldr b31, [x22], #0x1\n" + "ldr b30, [x21], #0x1\n" "23:" // Oddments: 2 inputs loop: Load: Bit 3: End "saddl v23.8h, v31.8b, v30.8b\n" "saddl2 v22.8h, v31.16b, v30.16b\n" - "subs x22, x22, #0x1\n" + "subs x23, x23, #0x1\n" "saddw v15.4s, v15.4s, v23.4h\n" "saddw2 v14.4s, v14.4s, v23.8h\n" "saddw v13.4s, v13.4s, v22.4h\n" "saddw2 v12.4s, v12.4s, v22.8h\n" "bgt 15b\n" "24:" // Oddments: After loop - "ands x20, %x[n_valid_cells], #0x1\n" + "ands x21, %x[n_valid_cells], #0x1\n" "beq 34f\n" "25:" // Oddments: Single input loop - "ldr x21, [x19], #0x8\n" - "add x21, x21, x26\n" + "ldr x22, [x20], #0x8\n" + "add x22, x22, x27\n" "movi v31.16b, #0x0\n" "tbz %x[n_channels], #3, 29f\n" - "ldr d31, [x21], #0x8\n" + "ldr d31, [x22], #0x8\n" "tbz %x[n_channels], #2, 27f\n" - "ld1 { v31.s }[2], [x21], #0x4\n" + "ld1 { v31.s }[2], [x22], #0x4\n" "tbz %x[n_channels], #1, 26f\n" - "ld1 { v31.h }[6], [x21], #0x2\n" + "ld1 { v31.h }[6], [x22], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v31.b }[14], [x21], #0x1\n" + "ld1 { v31.b }[14], [x22], #0x1\n" "b 33f\n" "26:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ld1 { v31.b }[12], [x21], #0x1\n" + "ld1 { v31.b }[12], [x22], #0x1\n" "b 33f\n" "27:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Unset "tbz %x[n_channels], #1, 28f\n" - "ld1 { v31.h }[4], [x21], #0x2\n" + "ld1 { v31.h }[4], [x22], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v31.b }[10], [x21], #0x1\n" + "ld1 { v31.b }[10], [x22], #0x1\n" "b 33f\n" "28:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ld1 { v31.b }[8], [x21], #0x1\n" + "ld1 { v31.b }[8], [x22], #0x1\n" "b 33f\n" "29:" // Oddments: Single input loop: Load: Bit 3: Unset "tbz %x[n_channels], #2, 31f\n" - "ldr s31, [x21], #0x4\n" + "ldr s31, [x22], #0x4\n" "tbz %x[n_channels], #1, 30f\n" - "ld1 { v31.h }[2], [x21], #0x2\n" + "ld1 { v31.h }[2], [x22], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v31.b }[6], [x21], #0x1\n" + "ld1 { v31.b }[6], [x22], #0x1\n" "b 33f\n" "30:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ld1 { v31.b }[4], [x21], #0x1\n" + "ld1 { v31.b }[4], [x22], #0x1\n" "b 33f\n" "31:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Unset "tbz %x[n_channels], #1, 32f\n" - "ldr h31, [x21], #0x2\n" + "ldr h31, [x22], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v31.b }[2], [x21], #0x1\n" + "ld1 { v31.b }[2], [x22], #0x1\n" "b 33f\n" "32:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ldr b31, [x21], #0x1\n" + "ldr b31, [x22], #0x1\n" "33:" // Oddments: Single input loop: Load: Bit 3: End "sxtl v23.8h, v31.8b\n" "sxtl2 v22.8h, v31.16b\n" - "subs x20, x20, #0x1\n" + "subs x21, x21, #0x1\n" "saddw v15.4s, v15.4s, v23.4h\n" "saddw2 v14.4s, v14.4s, v23.8h\n" "saddw v13.4s, v13.4s, v22.4h\n" @@ -594,9 +594,9 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( "ld1r { v17.4s }, [%x[combined_rescale_value]]\n" "srshl v15.4s, v15.4s, v18.4s\n" "srshl v14.4s, v14.4s, v18.4s\n" + "ld1r { v16.4s }, [%x[right_shift]]\n" "srshl v13.4s, v13.4s, v18.4s\n" "srshl v12.4s, v12.4s, v18.4s\n" - "ld1r { v16.4s }, [%x[right_shift]]\n" "sqrdmulh v15.4s, v15.4s, v17.4s\n" "sqrdmulh v14.4s, v14.4s, v17.4s\n" "sqrdmulh v13.4s, v13.4s, v17.4s\n" @@ -666,7 +666,7 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( "43:" // End : [n_channels] "+&r" (n_channels), [outptr] "+&r" (outptr) : [combined_rescale_value] "r" (&combined_rescale_value), [inptrs] "r" (inptrs), [left_shift] "r" (&left_shift), [n_valid_cells] "r" (n_valid_cells), [right_shift] "r" (&right_shift) - : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26" + : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); } |