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path: root/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp
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Diffstat (limited to 'src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp')
-rw-r--r--src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp179
1 files changed, 91 insertions, 88 deletions
diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp
index ea7e2195d1..f4202de1ed 100644
--- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp
+++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021 Arm Limited.
+ * Copyright (c) 2021-2023 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -26,6 +26,8 @@
#include <cstddef>
#include <cstdint>
+#if defined(__aarch64__)
+
namespace arm_conv {
namespace pooling {
@@ -61,114 +63,115 @@ void a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst_impl(
pad_left, pad_top, pad_right, pad_bottom);
__asm__ __volatile__(
- "ldr x15, [%x[args], %[offsetof_n_channels]]\n"
- "mov x14, #0x0\n"
- "ldr x20, [%x[args], %[offsetof_outptrs]]\n"
- "mov x13, #0x0\n"
- "ldr x19, [%x[args], %[offsetof_inptrs]]\n"
- "cmp x15, #0x4\n"
- "ldp x12, x11, [x20, #0x0]\n"
- "ldp x10, x9, [x20, #0x10]\n"
- "ldp x28, x27, [x19, #0x0]\n"
- "ldp x26, x25, [x19, #0x10]\n"
- "ldp x24, x23, [x19, #0x20]\n"
- "ldp x22, x21, [x19, #0x30]\n"
- "ldr x20, [x19, #0x40]\n"
+ "ldr x16, [%x[args], %[offsetof_n_channels]]\n"
+ "ldr x21, [%x[args], %[offsetof_outptrs]]\n"
+ "cmp x16, #0x4\n"
+ "mov x15, #0x0\n"
+ "ldr x20, [%x[args], %[offsetof_inptrs]]\n"
+ "ldp x14, x13, [x21, #0x0]\n"
+ "mov x12, #0x0\n"
+ "ldp x11, x10, [x21, #0x10]\n"
+ "ldp x9, x28, [x20, #0x0]\n"
+ "ldp x27, x26, [x20, #0x10]\n"
+ "ldp x25, x24, [x20, #0x20]\n"
+ "ldp x23, x22, [x20, #0x30]\n"
+ "ldr x21, [x20, #0x40]\n"
"blt 3f\n"
- "ldr q30, [x27, x14]\n"
- "lsr x19, x15, #0x2\n"
- "ldr q29, [x24, x14]\n"
- "sub x15, x15, x19, LSL #2\n"
- "ldr q28, [x21, x14]\n"
- "subs x19, x19, #0x1\n"
- "ldr q27, [x25, x14]\n"
- "ldr q26, [x28, x14]\n"
- "ldr q25, [x23, x14]\n"
- "ldr q24, [x26, x14]\n"
- "ldr q23, [x22, x14]\n"
- "ldr q22, [x20, x14]\n"
- "add x14, x14, #0x10\n"
+ "ldr q30, [x28, x15]\n"
+ "ldr q29, [x25, x15]\n"
+ "lsr x20, x16, #0x2\n"
+ "sub x16, x16, x20, LSL #2\n"
+ "ldr q28, [x22, x15]\n"
+ "ldr q27, [x26, x15]\n"
+ "subs x20, x20, #0x1\n"
+ "ldr q26, [x9, x15]\n"
+ "ldr q25, [x27, x15]\n"
+ "ldr q24, [x24, x15]\n"
+ "ldr q23, [x23, x15]\n"
+ "ldr q22, [x21, x15]\n"
+ "add x15, x15, #0x10\n"
"beq 2f\n"
"1:" // Vector: Loop
"fmax v21.4s, v30.4s, v29.4s\n"
- "ldr q30, [x27, x14]\n"
- "subs x19, x19, #0x1\n"
+ "ldr q30, [x28, x15]\n"
"fmax v20.4s, v29.4s, v28.4s\n"
- "ldr q29, [x24, x14]\n"
+ "ldr q29, [x25, x15]\n"
+ "ldr q28, [x22, x15]\n"
"fmax v19.4s, v27.4s, v26.4s\n"
- "ldr q28, [x21, x14]\n"
+ "ldr q26, [x9, x15]\n"
"fmax v18.4s, v25.4s, v24.4s\n"
- "ldr q26, [x28, x14]\n"
- "fmax v17.4s, v23.4s, v27.4s\n"
- "ldr q27, [x25, x14]\n"
- "fmax v16.4s, v25.4s, v22.4s\n"
- "ldr q25, [x23, x14]\n"
+ "ldr q25, [x27, x15]\n"
+ "fmax v17.4s, v27.4s, v23.4s\n"
+ "ldr q27, [x26, x15]\n"
+ "fmax v16.4s, v24.4s, v22.4s\n"
+ "ldr q24, [x24, x15]\n"
+ "ldr q23, [x23, x15]\n"
+ "subs x20, x20, #0x1\n"
"fmax v19.4s, v21.4s, v19.4s\n"
- "ldr q24, [x26, x14]\n"
- "fmax v18.4s, v21.4s, v18.4s\n"
- "ldr q23, [x22, x14]\n"
- "fmax v17.4s, v20.4s, v17.4s\n"
- "ldr q22, [x20, x14]\n"
- "add x14, x14, #0x10\n"
+ "ldr q22, [x21, x15]\n"
+ "fmax v18.4s, v18.4s, v21.4s\n"
+ "fmax v17.4s, v17.4s, v20.4s\n"
+ "add x15, x15, #0x10\n"
"fmax v16.4s, v20.4s, v16.4s\n"
- "str q19, [x12, x13]\n"
- "str q18, [x11, x13]\n"
- "str q17, [x10, x13]\n"
- "str q16, [x9, x13]\n"
- "add x13, x13, #0x10\n"
+ "str q19, [x14, x12]\n"
+ "str q18, [x13, x12]\n"
+ "str q17, [x11, x12]\n"
+ "str q16, [x10, x12]\n"
+ "add x12, x12, #0x10\n"
"bgt 1b\n"
"2:" // Vector: Tail
"fmax v21.4s, v30.4s, v29.4s\n"
"fmax v20.4s, v29.4s, v28.4s\n"
- "fmax v19.4s, v27.4s, v26.4s\n"
+ "fmax v16.4s, v27.4s, v26.4s\n"
"fmax v18.4s, v25.4s, v24.4s\n"
- "fmax v17.4s, v23.4s, v27.4s\n"
- "fmax v16.4s, v25.4s, v22.4s\n"
- "fmax v19.4s, v21.4s, v19.4s\n"
- "str q19, [x12, x13]\n"
- "fmax v18.4s, v21.4s, v18.4s\n"
- "fmax v17.4s, v20.4s, v17.4s\n"
- "str q18, [x11, x13]\n"
- "fmax v16.4s, v20.4s, v16.4s\n"
- "str q17, [x10, x13]\n"
- "str q16, [x9, x13]\n"
- "add x13, x13, #0x10\n"
- "cbz x15, 4f\n"
+ "fmax v17.4s, v27.4s, v23.4s\n"
+ "fmax v19.4s, v24.4s, v22.4s\n"
+ "fmax v16.4s, v21.4s, v16.4s\n"
+ "fmax v18.4s, v18.4s, v21.4s\n"
+ "str q16, [x14, x12]\n"
+ "fmax v17.4s, v17.4s, v20.4s\n"
+ "fmax v16.4s, v20.4s, v19.4s\n"
+ "str q18, [x13, x12]\n"
+ "str q17, [x11, x12]\n"
+ "str q16, [x10, x12]\n"
+ "add x12, x12, #0x10\n"
+ "cbz x16, 4f\n"
"3:" // Oddments
- "ldr s30, [x27, x14]\n"
- "subs x15, x15, #0x1\n"
- "ldr s29, [x24, x14]\n"
- "fmax v21.4s, v30.4s, v29.4s\n"
- "ldr s28, [x21, x14]\n"
- "ldr s27, [x25, x14]\n"
- "fmax v20.4s, v29.4s, v28.4s\n"
- "ldr s26, [x28, x14]\n"
- "ldr s25, [x23, x14]\n"
- "fmax v19.4s, v27.4s, v26.4s\n"
- "ldr s24, [x26, x14]\n"
- "ldr s23, [x22, x14]\n"
- "fmax v19.4s, v21.4s, v19.4s\n"
- "ldr s22, [x20, x14]\n"
- "add x14, x14, #0x4\n"
- "fmax v18.4s, v25.4s, v24.4s\n"
- "str s19, [x12, x13]\n"
- "fmax v17.4s, v23.4s, v27.4s\n"
- "fmax v16.4s, v25.4s, v22.4s\n"
- "fmax v18.4s, v21.4s, v18.4s\n"
- "str s18, [x11, x13]\n"
- "fmax v17.4s, v20.4s, v17.4s\n"
- "fmax v16.4s, v20.4s, v16.4s\n"
- "str s17, [x10, x13]\n"
- "str s16, [x9, x13]\n"
- "add x13, x13, #0x4\n"
+ "ldr s16, [x28, x15]\n"
+ "ldr s17, [x25, x15]\n"
+ "fmax v23.4s, v16.4s, v17.4s\n"
+ "subs x16, x16, #0x1\n"
+ "ldr s16, [x22, x15]\n"
+ "ldr s22, [x26, x15]\n"
+ "fmax v21.4s, v17.4s, v16.4s\n"
+ "ldr s16, [x9, x15]\n"
+ "ldr s17, [x27, x15]\n"
+ "fmax v16.4s, v22.4s, v16.4s\n"
+ "fmax v20.4s, v23.4s, v16.4s\n"
+ "ldr s19, [x24, x15]\n"
+ "ldr s16, [x23, x15]\n"
+ "fmax v18.4s, v17.4s, v19.4s\n"
+ "fmax v17.4s, v22.4s, v16.4s\n"
+ "ldr s16, [x21, x15]\n"
+ "fmax v16.4s, v19.4s, v16.4s\n"
+ "add x15, x15, #0x4\n"
+ "fmax v18.4s, v18.4s, v23.4s\n"
+ "fmax v17.4s, v17.4s, v21.4s\n"
+ "fmax v16.4s, v21.4s, v16.4s\n"
+ "str s20, [x14, x12]\n"
+ "str s18, [x13, x12]\n"
+ "str s17, [x11, x12]\n"
+ "str s16, [x10, x12]\n"
+ "add x12, x12, #0x4\n"
"bgt 3b\n"
"4:" // End
-
:
: [args] "r" (&args), [offsetof_inptrs] "I" (offsetof(KernelArgs, inptrs)), [offsetof_n_channels] "I" (offsetof(KernelArgs, n_channels)), [offsetof_outptrs] "I" (offsetof(KernelArgs, outptrs))
- : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28"
+ : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28"
);
}
} // namespace pooling
} // namespace arm_conv
+
+#endif // defined(__aarch64__)
generated by cgit v1.2.1 (git 2.23.0) at 2024-05-03 18:51:43 +0000