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Diffstat (limited to 'src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8qa_nhwc_3x3_s2_output2x2_mla_depthfirst/generic.cpp')
-rw-r--r--src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8qa_nhwc_3x3_s2_output2x2_mla_depthfirst/generic.cpp1850
1 files changed, 925 insertions, 925 deletions
diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8qa_nhwc_3x3_s2_output2x2_mla_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8qa_nhwc_3x3_s2_output2x2_mla_depthfirst/generic.cpp
index a1e5c669b7..42ff502b0f 100644
--- a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8qa_nhwc_3x3_s2_output2x2_mla_depthfirst/generic.cpp
+++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8qa_nhwc_3x3_s2_output2x2_mla_depthfirst/generic.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022-2023 Arm Limited.
+ * Copyright (c) 2022 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -100,324 +100,324 @@ void a64_u8qa_nhwc_3x3_s2_output2x2_mla_depthfirst_impl(
requant_muls, requant_shifts, outptrs);
__asm__ __volatile__(
- "ldr x7, [%x[params], %[offsetof_Params_n_channels]]\n"
- "ldr x23, [%x[params], %[offsetof_Params_requant]]\n"
- "lsr x8, x7, #0x3\n"
- "add x20, x23, %[offsetof_Requantize32_b_offset]\n"
- "ld1r { v19.16b }, [x20]\n"
- "ldr x22, [%x[params], %[offsetof_Params_outptrs]]\n"
- "add x21, x23, %[offsetof_Requantize32_c_offset]\n"
- "add x20, x23, %[offsetof_Requantize32_minval]\n"
- "ld1r { v12.8h }, [x21]\n"
+ "ldr x19, [%x[params], %[offsetof_Params_requant]]\n"
+ "ldr x8, [%x[params], %[offsetof_Params_n_channels]]\n"
+ "add x23, x19, %[offsetof_Requantize32_b_offset]\n"
+ "add x22, x19, %[offsetof_Requantize32_c_offset]\n"
+ "ldr x21, [%x[params], %[offsetof_Params_outptrs]]\n"
+ "add x20, x19, %[offsetof_Requantize32_minval]\n"
+ "add x19, x19, %[offsetof_Requantize32_maxval]\n"
+ "ldr x17, [%x[params], %[offsetof_Params_weights]]\n"
+ "ld1r { v16.16b }, [x23]\n"
+ "ld1r { v12.8h }, [x22]\n"
+ "lsr x16, x8, #0x3\n"
+ "mov x15, #0x0\n"
"ld1r { v14.8h }, [x20]\n"
- "add x20, x23, %[offsetof_Requantize32_maxval]\n"
- "mov x17, #0x0\n"
- "ld1r { v23.8h }, [x20]\n"
- "mov x16, #0x0\n"
- "add x15, %x[params], %[offsetof_Params_inptrs]\n"
- "ldr x14, [%x[params], %[offsetof_Params_weights]]\n"
- "ldr x13, [%x[params], %[offsetof_Params_requant_muls]]\n"
- "ldr x12, [%x[params], %[offsetof_Params_requant_shifts]]\n"
- "ldp x11, x10, [x22, #0x0]\n"
- "ldp x9, x28, [x22, #0x10]\n"
- "cbz x8, 3f\n"
- "ldr d0, [x14, #0x0]\n"
- "ldr d1, [x14, #0x8]\n"
- "subs x8, x8, #0x1\n"
- "usubl v0.8h, v0.8b, v19.8b\n"
- "ldr d2, [x14, #0x10]\n"
- "ldr d3, [x14, #0x18]\n"
- "usubl v1.8h, v1.8b, v19.8b\n"
- "usubl v2.8h, v2.8b, v19.8b\n"
- "ldr d4, [x14, #0x20]\n"
- "ldr d5, [x14, #0x28]\n"
- "usubl v3.8h, v3.8b, v19.8b\n"
- "usubl v4.8h, v4.8b, v19.8b\n"
- "ldr d6, [x14, #0x30]\n"
- "ldr d7, [x14, #0x38]\n"
- "usubl v5.8h, v5.8b, v19.8b\n"
- "usubl v6.8h, v6.8b, v19.8b\n"
- "ldr d8, [x14, #0x40]\n"
- "ldr x22, [%x[params], %[offsetof_Params_bias]]\n"
- "usubl v7.8h, v7.8b, v19.8b\n"
- "usubl v8.8h, v8.8b, v19.8b\n"
- "ldr q15, [x22, #0x0]\n"
- "ldr q13, [x22, #0x10]\n"
- "add x22, x22, #0x20\n"
- "str x22, [%x[params], %[offsetof_Params_bias]]\n"
- "ldp x27, x26, [x15, #0x0]\n"
- "ldp x25, x24, [x15, #0x10]\n"
- "mov v17.16b, v15.16b\n"
- "mov v20.16b, v13.16b\n"
- "ldp x23, x22, [x15, #0x20]\n"
- "ldp x21, x20, [x15, #0x30]\n"
+ "ld1r { v21.8h }, [x19]\n"
+ "mov x14, #0x0\n"
+ "add x13, %x[params], %[offsetof_Params_inptrs]\n"
+ "ldr x12, [%x[params], %[offsetof_Params_requant_muls]]\n"
+ "ldr x11, [%x[params], %[offsetof_Params_requant_shifts]]\n"
+ "ldp x10, x9, [x21, #0x0]\n"
+ "ldp x28, x27, [x21, #0x10]\n"
+ "cbz x16, 3f\n"
+ "ldr x19, [%x[params], %[offsetof_Params_bias]]\n"
+ "ldr q15, [x19, #0x0]\n"
+ "subs x16, x16, #0x1\n"
+ "mov v13.16b, v15.16b\n"
+ "ldr q18, [x19, #0x10]\n"
+ "add x19, x19, #0x20\n"
+ "str x19, [%x[params], %[offsetof_Params_bias]]\n"
+ "ldr d0, [x17, #0x0]\n"
+ "ldr d1, [x17, #0x8]\n"
+ "ldr d2, [x17, #0x10]\n"
+ "mov v17.16b, v18.16b\n"
"mov v11.16b, v15.16b\n"
- "mov v10.16b, v13.16b\n"
- "ldr d31, [x27, x17]\n"
- "ldr d30, [x26, x17]\n"
- "mov v9.16b, v15.16b\n"
- "mov v22.16b, v13.16b\n"
- "ldr d29, [x25, x17]\n"
- "ldr d28, [x24, x17]\n"
+ "ldr d3, [x17, #0x18]\n"
+ "ldr d4, [x17, #0x20]\n"
+ "mov v10.16b, v18.16b\n"
+ "mov v23.16b, v15.16b\n"
+ "ldr d5, [x17, #0x28]\n"
+ "ldr d6, [x17, #0x30]\n"
+ "mov v9.16b, v18.16b\n"
+ "usubl v0.8h, v0.8b, v16.8b\n"
+ "ldr d7, [x17, #0x38]\n"
+ "ldr d8, [x17, #0x40]\n"
+ "usubl v1.8h, v1.8b, v16.8b\n"
+ "usubl v2.8h, v2.8b, v16.8b\n"
+ "ldp x26, x25, [x13, #0x0]\n"
+ "ldp x24, x23, [x13, #0x10]\n"
+ "usubl v3.8h, v3.8b, v16.8b\n"
+ "usubl v4.8h, v4.8b, v16.8b\n"
+ "ldp x22, x21, [x13, #0x20]\n"
+ "ldp x20, x19, [x13, #0x30]\n"
+ "usubl v5.8h, v5.8b, v16.8b\n"
+ "usubl v6.8h, v6.8b, v16.8b\n"
+ "ldr d31, [x26, x15]\n"
+ "ldr d30, [x25, x15]\n"
+ "usubl v7.8h, v7.8b, v16.8b\n"
+ "usubl v8.8h, v8.8b, v16.8b\n"
+ "ldr d29, [x24, x15]\n"
+ "ldr d28, [x23, x15]\n"
"ushll v31.8h, v31.8b, #0x0\n"
"ushll v30.8h, v30.8b, #0x0\n"
- "ldr d27, [x23, x17]\n"
- "ldr d26, [x22, x17]\n"
+ "ldr d27, [x22, x15]\n"
+ "ldr d26, [x21, x15]\n"
"ushll v29.8h, v29.8b, #0x0\n"
"ushll v28.8h, v28.8b, #0x0\n"
- "ldr d25, [x21, x17]\n"
- "ldr d24, [x20, x17]\n"
+ "ldr d25, [x20, x15]\n"
+ "ldr d24, [x19, x15]\n"
"ushll v27.8h, v27.8b, #0x0\n"
"ushll v26.8h, v26.8b, #0x0\n"
"ushll v25.8h, v25.8b, #0x0\n"
"ushll v24.8h, v24.8b, #0x0\n"
"beq 2f\n"
"1:" // Loop
- "ldr q18, [x13, #0x0]\n"
"smlal v15.4s, v31.4h, v8.4h\n"
- "smlal2 v13.4s, v31.8h, v8.8h\n"
- "ldr x23, [x15, #0x40]\n"
- "smlal v17.4s, v31.4h, v6.4h\n"
- "smlal2 v20.4s, v31.8h, v6.8h\n"
- "ldr x22, [x15, #0x48]\n"
- "ldr x21, [x15, #0x50]\n"
+ "smlal2 v18.4s, v31.8h, v8.8h\n"
+ "ldr x24, [x13, #0x40]\n"
+ "ldr x23, [x13, #0x48]\n"
+ "smlal v13.4s, v31.4h, v6.4h\n"
+ "smlal2 v17.4s, v31.8h, v6.8h\n"
+ "ldr x21, [x13, #0x50]\n"
+ "ldr x19, [x13, #0x58]\n"
"smlal v15.4s, v30.4h, v0.4h\n"
- "smlal2 v13.4s, v30.8h, v0.8h\n"
- "ldr q21, [x12, #0x0]\n"
- "ldr x20, [x15, #0x58]\n"
- "smlal v17.4s, v28.4h, v1.4h\n"
- "smlal2 v20.4s, v28.8h, v1.8h\n"
- "ldr d28, [x22, x17]\n"
+ "smlal2 v18.4s, v30.8h, v0.8h\n"
+ "ldr x22, [x13, #0x78]\n"
+ "ldr x20, [x13, #0x60]\n"
+ "smlal v13.4s, v28.4h, v1.4h\n"
+ "smlal2 v17.4s, v28.8h, v1.8h\n"
+ "ldr d28, [x23, x15]\n"
"ushll v28.8h, v28.8b, #0x0\n"
"smlal v15.4s, v29.4h, v1.4h\n"
- "smlal2 v13.4s, v29.8h, v1.8h\n"
- "ldr d29, [x23, x17]\n"
+ "smlal2 v18.4s, v29.8h, v1.8h\n"
+ "ldr d29, [x24, x15]\n"
"ushll v29.8h, v29.8b, #0x0\n"
- "smlal v17.4s, v27.4h, v2.4h\n"
- "smlal2 v20.4s, v27.8h, v2.8h\n"
- "ldr d27, [x21, x17]\n"
+ "smlal v13.4s, v27.4h, v2.4h\n"
+ "smlal2 v17.4s, v27.8h, v2.8h\n"
+ "ldr d27, [x21, x15]\n"
"ushll v27.8h, v27.8b, #0x0\n"
"smlal v15.4s, v26.4h, v3.4h\n"
- "smlal2 v13.4s, v26.8h, v3.8h\n"
- "ldr d26, [x20, x17]\n"
- "ldr x23, [x15, #0x78]\n"
- "smlal v17.4s, v24.4h, v0.4h\n"
- "smlal2 v20.4s, v24.8h, v0.8h\n"
- "ldr x20, [x15, #0x60]\n"
+ "smlal2 v18.4s, v26.8h, v3.8h\n"
+ "ldr d26, [x19, x15]\n"
"ushll v26.8h, v26.8b, #0x0\n"
+ "smlal v13.4s, v24.4h, v0.4h\n"
+ "smlal2 v17.4s, v24.8h, v0.8h\n"
+ "ldr x21, [x13, #0x80]\n"
+ "ldr x19, [x13, #0x68]\n"
"smlal v15.4s, v25.4h, v4.4h\n"
- "smlal2 v13.4s, v25.8h, v4.8h\n"
- "ldr d25, [x20, x17]\n"
- "ldr x21, [x15, #0x80]\n"
- "smlal v17.4s, v29.4h, v4.4h\n"
- "smlal2 v20.4s, v29.8h, v4.8h\n"
- "ldr q30, [x13, #0x10]\n"
- "ldr x20, [x15, #0x68]\n"
- "smlal v15.4s, v24.4h, v2.4h\n"
- "smlal2 v13.4s, v24.8h, v2.8h\n"
- "ldr d29, [x20, x17]\n"
+ "smlal2 v18.4s, v25.8h, v4.8h\n"
+ "ldr d25, [x20, x15]\n"
"ushll v25.8h, v25.8b, #0x0\n"
- "smlal v17.4s, v28.4h, v5.4h\n"
- "smlal2 v20.4s, v28.8h, v5.8h\n"
- "ldr d28, [x21, x17]\n"
- "ldr x22, [x15, #0x88]\n"
+ "smlal v13.4s, v29.4h, v4.4h\n"
+ "smlal2 v17.4s, v29.8h, v4.8h\n"
+ "ldr x20, [x13, #0x88]\n"
+ "ldr d29, [x19, x15]\n"
+ "smlal v15.4s, v24.4h, v2.4h\n"
+ "smlal2 v18.4s, v24.8h, v2.8h\n"
+ "ldr x19, [x13, #0x70]\n"
+ "ushll v29.8h, v29.8b, #0x0\n"
+ "smlal v13.4s, v28.4h, v5.4h\n"
+ "smlal2 v17.4s, v28.8h, v5.8h\n"
+ "ldr d28, [x21, x15]\n"
+ "ushll v28.8h, v28.8b, #0x0\n"
"smlal v11.4s, v31.4h, v2.4h\n"
"smlal2 v10.4s, v31.8h, v2.8h\n"
- "ldr x20, [x15, #0x70]\n"
- "ushll v28.8h, v28.8b, #0x0\n"
+ "ldr x24, [x13, #0x98]\n"
+ "ldr d24, [x19, x15]\n"
"smlal v15.4s, v27.4h, v5.4h\n"
- "smlal2 v13.4s, v27.8h, v5.8h\n"
- "ushll v29.8h, v29.8b, #0x0\n"
- "ldr x24, [x15, #0x98]\n"
- "smlal v17.4s, v27.4h, v3.4h\n"
- "smlal2 v20.4s, v27.8h, v3.8h\n"
- "ldr d27, [x23, x17]\n"
+ "smlal2 v18.4s, v27.8h, v5.8h\n"
+ "ushll v24.8h, v24.8b, #0x0\n"
+ "ldr x23, [x13, #0x90]\n"
+ "smlal v13.4s, v27.4h, v3.4h\n"
+ "smlal2 v17.4s, v27.8h, v3.8h\n"
+ "ldr d27, [x22, x15]\n"
"ushll v27.8h, v27.8b, #0x0\n"
- "smlal v9.4s, v31.4h, v0.4h\n"
+ "smlal v23.4s, v31.4h, v0.4h\n"
"smlal v11.4s, v26.4h, v3.4h\n"
- "ldr x21, [x15, #0x90]\n"
- "ldr x23, [x15, #0xa8]\n"
+ "ldr x22, [x13, #0xa8]\n"
+ "ldr x19, [x13, #0xa0]\n"
"smlal2 v10.4s, v26.8h, v3.8h\n"
- "ldr d26, [x22, x17]\n"
- "smlal2 v22.4s, v31.8h, v0.8h\n"
- "ldr d24, [x20, x17]\n"
- "smlal v9.4s, v27.4h, v4.4h\n"
- "smlal v11.4s, v25.4h, v0.4h\n"
+ "smlal2 v9.4s, v31.8h, v0.8h\n"
+ "ldr d26, [x20, x15]\n"
"ushll v26.8h, v26.8b, #0x0\n"
- "ldr x20, [x15, #0xa0]\n"
+ "smlal v23.4s, v27.4h, v4.4h\n"
+ "smlal v11.4s, v25.4h, v0.4h\n"
+ "ldr x21, [x13, #0xb0]\n"
+ "ldr x20, [x13, #0xb8]\n"
"smlal2 v10.4s, v25.8h, v0.8h\n"
- "ldr q31, [x12, #0x10]\n"
- "smlal2 v22.4s, v27.8h, v4.8h\n"
- "ldr d27, [x20, x17]\n"
- "smlal v9.4s, v28.4h, v1.4h\n"
+ "smlal2 v9.4s, v27.8h, v4.8h\n"
+ "ldr d27, [x19, x15]\n"
+ "ushll v27.8h, v27.8b, #0x0\n"
+ "smlal v23.4s, v28.4h, v1.4h\n"
"smlal v15.4s, v25.4h, v6.4h\n"
- "ushll v24.8h, v24.8b, #0x0\n"
- "ldr x22, [x15, #0xb0]\n"
- "smlal2 v13.4s, v25.8h, v6.8h\n"
- "ldr d25, [x21, x17]\n"
+ "ldr x19, [x13, #0xc0]\n"
+ "ldr q22, [x12, #0x0]\n"
+ "smlal2 v18.4s, v25.8h, v6.8h\n"
"smlal v11.4s, v29.4h, v4.4h\n"
+ "ldr d25, [x23, x15]\n"
"ushll v25.8h, v25.8b, #0x0\n"
"smlal2 v10.4s, v29.8h, v4.8h\n"
- "ldr d29, [x24, x17]\n"
- "smlal2 v22.4s, v28.8h, v1.8h\n"
+ "ldr d29, [x24, x15]\n"
+ "smlal2 v9.4s, v28.8h, v1.8h\n"
"ushll v29.8h, v29.8b, #0x0\n"
- "smlal v9.4s, v26.4h, v5.4h\n"
+ "smlal v23.4s, v26.4h, v5.4h\n"
"smlal v15.4s, v24.4h, v7.4h\n"
- "ldr x21, [x15, #0xb8]\n"
- "ushll v27.8h, v27.8b, #0x0\n"
- "smlal2 v13.4s, v24.8h, v7.8h\n"
+ "ldr q31, [x11, #0x0]\n"
+ "ldr q19, [x12, #0x10]\n"
+ "smlal2 v18.4s, v24.8h, v7.8h\n"
"smlal v11.4s, v24.4h, v1.4h\n"
- "ldr x20, [x15, #0xc0]\n"
- "sqrdmulh v15.4s, v15.4s, v18.4s\n"
+ "sqrdmulh v15.4s, v15.4s, v22.4s\n"
+ "ldr q30, [x11, #0x10]\n"
"smlal2 v10.4s, v24.8h, v1.8h\n"
- "ldr d24, [x23, x17]\n"
- "smlal2 v22.4s, v26.8h, v5.8h\n"
- "ldr d26, [x22, x17]\n"
- "smlal v9.4s, v29.4h, v2.4h\n"
+ "ldr d24, [x22, x15]\n"
+ "smlal2 v9.4s, v26.8h, v5.8h\n"
"ushll v24.8h, v24.8b, #0x0\n"
- "smlal2 v22.4s, v29.8h, v2.8h\n"
- "ldr x22, [%x[params], %[offsetof_Params_bias]]\n"
- "smlal v11.4s, v25.4h, v6.4h\n"
- "smlal v9.4s, v24.4h, v3.4h\n"
+ "smlal v23.4s, v29.4h, v2.4h\n"
+ "ldr d26, [x21, x15]\n"
+ "smlal2 v9.4s, v29.8h, v2.8h\n"
"ushll v26.8h, v26.8b, #0x0\n"
- "add x14, x14, #0x48\n"
- "smlal v17.4s, v28.4h, v7.4h\n"
- "smlal2 v20.4s, v28.8h, v7.8h\n"
- "and v2.16b, v15.16b, v21.16b\n"
- "subs x8, x8, #0x1\n"
+ "smlal v11.4s, v25.4h, v6.4h\n"
+ "smlal v23.4s, v24.4h, v3.4h\n"
+ "and v4.16b, v15.16b, v31.16b\n"
+ "add x17, x17, #0x48\n"
+ "smlal v13.4s, v28.4h, v7.4h\n"
+ "smlal2 v17.4s, v28.8h, v7.8h\n"
+ "sqrdmulh v18.4s, v18.4s, v19.4s\n"
+ "subs x16, x16, #0x1\n"
"smlal2 v10.4s, v25.8h, v6.8h\n"
- "ldr d25, [x21, x17]\n"
- "smlal2 v22.4s, v24.8h, v3.8h\n"
+ "ldr d25, [x20, x15]\n"
+ "smlal2 v9.4s, v24.8h, v3.8h\n"
"ushll v25.8h, v25.8b, #0x0\n"
"smlal v11.4s, v27.4h, v7.4h\n"
- "smlal v9.4s, v26.4h, v7.4h\n"
- "sqrdmulh v13.4s, v13.4s, v30.4s\n"
- "add x13, x13, #0x20\n"
- "smlal v17.4s, v29.4h, v8.4h\n"
- "smlal2 v20.4s, v29.8h, v8.8h\n"
- "ldr d29, [x20, x17]\n"
+ "smlal v23.4s, v26.4h, v7.4h\n"
+ "sshr v4.4s, v4.4s, #0x1f\n"
+ "add x12, x12, #0x20\n"
+ "smlal v13.4s, v29.4h, v8.4h\n"
+ "smlal2 v17.4s, v29.8h, v8.8h\n"
+ "ldr d29, [x19, x15]\n"
"ushll v29.8h, v29.8b, #0x0\n"
"smlal2 v10.4s, v27.8h, v7.8h\n"
- "smlal2 v22.4s, v26.8h, v7.8h\n"
- "sshr v2.4s, v2.4s, #0x1f\n"
- "add x17, x17, #0x8\n"
+ "smlal2 v9.4s, v26.8h, v7.8h\n"
+ "sqrdmulh v13.4s, v13.4s, v22.4s\n"
+ "add x15, x15, #0x8\n"
"smlal v11.4s, v24.4h, v5.4h\n"
- "smlal v9.4s, v25.4h, v6.4h\n"
- "and v16.16b, v13.16b, v31.16b\n"
- "add x12, x12, #0x20\n"
+ "smlal v23.4s, v25.4h, v6.4h\n"
+ "and v1.16b, v13.16b, v31.16b\n"
+ "add x11, x11, #0x20\n"
"smlal2 v10.4s, v24.8h, v5.8h\n"
- "smlal2 v22.4s, v25.8h, v6.8h\n"
- "sqrdmulh v17.4s, v17.4s, v18.4s\n"
+ "smlal2 v9.4s, v25.8h, v6.8h\n"
+ "sqrdmulh v17.4s, v17.4s, v19.4s\n"
"smlal v11.4s, v25.4h, v8.4h\n"
- "smlal v9.4s, v29.4h, v8.4h\n"
- "sqrdmulh v11.4s, v11.4s, v18.4s\n"
+ "smlal v23.4s, v29.4h, v8.4h\n"
+ "sqrdmulh v11.4s, v11.4s, v22.4s\n"
"smlal2 v10.4s, v25.8h, v8.8h\n"
- "smlal2 v22.4s, v29.8h, v8.8h\n"
- "sqrdmulh v9.4s, v9.4s, v18.4s\n"
- "sqadd v15.4s, v15.4s, v2.4s\n"
- "sshr v16.4s, v16.4s, #0x1f\n"
- "and v18.16b, v17.16b, v21.16b\n"
- "sqrdmulh v20.4s, v20.4s, v30.4s\n"
- "and v28.16b, v11.16b, v21.16b\n"
- "sqrdmulh v10.4s, v10.4s, v30.4s\n"
- "and v2.16b, v9.16b, v21.16b\n"
- "sqrdmulh v22.4s, v22.4s, v30.4s\n"
- "sqadd v13.4s, v13.4s, v16.4s\n"
- "sshr v18.4s, v18.4s, #0x1f\n"
- "and v4.16b, v20.16b, v31.16b\n"
- "sshr v28.4s, v28.4s, #0x1f\n"
- "and v3.16b, v10.16b, v31.16b\n"
- "sshr v2.4s, v2.4s, #0x1f\n"
- "and v16.16b, v22.16b, v31.16b\n"
- "sqadd v17.4s, v17.4s, v18.4s\n"
- "sshr v4.4s, v4.4s, #0x1f\n"
- "sqadd v11.4s, v11.4s, v28.4s\n"
- "sshr v3.4s, v3.4s, #0x1f\n"
- "sqadd v9.4s, v9.4s, v2.4s\n"
- "sshr v16.4s, v16.4s, #0x1f\n"
- "srshl v15.4s, v15.4s, v21.4s\n"
- "srshl v17.4s, v17.4s, v21.4s\n"
- "sqadd v20.4s, v20.4s, v4.4s\n"
- "srshl v11.4s, v11.4s, v21.4s\n"
- "sqadd v10.4s, v10.4s, v3.4s\n"
- "srshl v9.4s, v9.4s, v21.4s\n"
- "sqadd v22.4s, v22.4s, v16.4s\n"
+ "smlal2 v9.4s, v29.8h, v8.8h\n"
+ "sqrdmulh v23.4s, v23.4s, v22.4s\n"
+ "and v22.16b, v11.16b, v31.16b\n"
+ "sqrdmulh v10.4s, v10.4s, v19.4s\n"
+ "and v20.16b, v23.16b, v31.16b\n"
+ "sqrdmulh v9.4s, v9.4s, v19.4s\n"
+ "and v19.16b, v18.16b, v30.16b\n"
+ "sshr v1.4s, v1.4s, #0x1f\n"
+ "and v27.16b, v17.16b, v30.16b\n"
+ "sshr v22.4s, v22.4s, #0x1f\n"
+ "and v25.16b, v10.16b, v30.16b\n"
+ "sshr v20.4s, v20.4s, #0x1f\n"
+ "and v0.16b, v9.16b, v30.16b\n"
+ "sqadd v15.4s, v15.4s, v4.4s\n"
+ "sshr v19.4s, v19.4s, #0x1f\n"
+ "sqadd v13.4s, v13.4s, v1.4s\n"
+ "sshr v27.4s, v27.4s, #0x1f\n"
+ "sqadd v11.4s, v11.4s, v22.4s\n"
+ "sshr v25.4s, v25.4s, #0x1f\n"
+ "sqadd v23.4s, v23.4s, v20.4s\n"
+ "sshr v0.4s, v0.4s, #0x1f\n"
+ "srshl v15.4s, v15.4s, v31.4s\n"
+ "sqadd v18.4s, v18.4s, v19.4s\n"
"srshl v13.4s, v13.4s, v31.4s\n"
+ "sqadd v17.4s, v17.4s, v27.4s\n"
+ "srshl v11.4s, v11.4s, v31.4s\n"
+ "sqadd v10.4s, v10.4s, v25.4s\n"
+ "srshl v23.4s, v23.4s, v31.4s\n"
+ "sqadd v9.4s, v9.4s, v0.4s\n"
+ "srshl v18.4s, v18.4s, v30.4s\n"
"sqxtn v15.4h, v15.4s\n"
- "srshl v20.4s, v20.4s, v31.4s\n"
- "sqxtn v17.4h, v17.4s\n"
- "srshl v10.4s, v10.4s, v31.4s\n"
+ "srshl v17.4s, v17.4s, v30.4s\n"
+ "sqxtn v13.4h, v13.4s\n"
+ "srshl v10.4s, v10.4s, v30.4s\n"
"sqxtn v11.4h, v11.4s\n"
- "srshl v22.4s, v22.4s, v31.4s\n"
- "sqxtn v9.4h, v9.4s\n"
- "sqxtn2 v15.8h, v13.4s\n"
- "sqxtn2 v17.8h, v20.4s\n"
+ "srshl v9.4s, v9.4s, v30.4s\n"
+ "sqxtn v23.4h, v23.4s\n"
+ "sqxtn2 v15.8h, v18.4s\n"
+ "sqxtn2 v13.8h, v17.4s\n"
"sqxtn2 v11.8h, v10.4s\n"
- "sqxtn2 v9.8h, v22.4s\n"
+ "sqxtn2 v23.8h, v9.4s\n"
"sqadd v15.8h, v15.8h, v12.8h\n"
- "sqadd v17.8h, v17.8h, v12.8h\n"
+ "sqadd v13.8h, v13.8h, v12.8h\n"
"sqadd v11.8h, v11.8h, v12.8h\n"
- "sqadd v9.8h, v9.8h, v12.8h\n"
+ "sqadd v23.8h, v23.8h, v12.8h\n"
"smax v15.8h, v15.8h, v14.8h\n"
- "smax v17.8h, v17.8h, v14.8h\n"
+ "smax v13.8h, v13.8h, v14.8h\n"
"smax v11.8h, v11.8h, v14.8h\n"
- "smax v9.8h, v9.8h, v14.8h\n"
- "smin v15.8h, v15.8h, v23.8h\n"
- "smin v17.8h, v17.8h, v23.8h\n"
- "smin v11.8h, v11.8h, v23.8h\n"
- "smin v9.8h, v9.8h, v23.8h\n"
+ "smax v23.8h, v23.8h, v14.8h\n"
+ "smin v15.8h, v15.8h, v21.8h\n"
+ "smin v13.8h, v13.8h, v21.8h\n"
+ "smin v11.8h, v11.8h, v21.8h\n"
+ "smin v23.8h, v23.8h, v21.8h\n"
"uzp1 v15.16b, v15.16b, v15.16b\n"
- "uzp1 v17.16b, v17.16b, v17.16b\n"
- "str d15, [x11, x16]\n"
+ "str d15, [x10, x14]\n"
+ "uzp1 v13.16b, v13.16b, v13.16b\n"
"uzp1 v11.16b, v11.16b, v11.16b\n"
- "uzp1 v9.16b, v9.16b, v9.16b\n"
- "str d17, [x10, x16]\n"
- "str d11, [x9, x16]\n"
- "str d9, [x28, x16]\n"
- "ldr q15, [x22, #0x0]\n"
- "ldr q13, [x22, #0x10]\n"
- "add x22, x22, #0x20\n"
- "ldr d0, [x14, #0x0]\n"
- "ldr d1, [x14, #0x8]\n"
- "add x16, x16, #0x8\n"
- "str x22, [%x[params], %[offsetof_Params_bias]]\n"
- "ldr d2, [x14, #0x10]\n"
- "ldr d3, [x14, #0x18]\n"
- "mov v17.16b, v15.16b\n"
- "mov v20.16b, v13.16b\n"
- "ldr d4, [x14, #0x20]\n"
- "ldr d5, [x14, #0x28]\n"
+ "str d13, [x9, x14]\n"
+ "uzp1 v23.16b, v23.16b, v23.16b\n"
+ "str d11, [x28, x14]\n"
+ "str d23, [x27, x14]\n"
+ "ldr x19, [%x[params], %[offsetof_Params_bias]]\n"
+ "ldr q15, [x19, #0x0]\n"
+ "add x14, x14, #0x8\n"
+ "ldr q18, [x19, #0x10]\n"
+ "add x19, x19, #0x20\n"
+ "str x19, [%x[params], %[offsetof_Params_bias]]\n"
+ "ldr d0, [x17, #0x0]\n"
+ "ldr d1, [x17, #0x8]\n"
+ "ldr d2, [x17, #0x10]\n"
+ "mov v13.16b, v15.16b\n"
+ "mov v17.16b, v18.16b\n"
+ "ldr d3, [x17, #0x18]\n"
+ "ldr d4, [x17, #0x20]\n"
"mov v11.16b, v15.16b\n"
- "mov v10.16b, v13.16b\n"
- "ldr d6, [x14, #0x30]\n"
- "ldr d7, [x14, #0x38]\n"
- "mov v9.16b, v15.16b\n"
- "mov v22.16b, v13.16b\n"
- "ldr d8, [x14, #0x40]\n"
- "ldp x27, x26, [x15, #0x0]\n"
- "usubl v0.8h, v0.8b, v19.8b\n"
- "usubl v1.8h, v1.8b, v19.8b\n"
- "ldp x25, x24, [x15, #0x10]\n"
- "ldp x23, x22, [x15, #0x20]\n"
- "usubl v2.8h, v2.8b, v19.8b\n"
- "usubl v3.8h, v3.8b, v19.8b\n"
- "ldp x21, x20, [x15, #0x30]\n"
- "ldr d31, [x27, x17]\n"
- "usubl v4.8h, v4.8b, v19.8b\n"
- "usubl v5.8h, v5.8b, v19.8b\n"
- "ldr d30, [x26, x17]\n"
- "ldr d29, [x25, x17]\n"
- "usubl v6.8h, v6.8b, v19.8b\n"
- "usubl v7.8h, v7.8b, v19.8b\n"
- "ldr d28, [x24, x17]\n"
- "ldr d27, [x23, x17]\n"
- "usubl v8.8h, v8.8b, v19.8b\n"
+ "mov v10.16b, v18.16b\n"
+ "ldr d5, [x17, #0x28]\n"
+ "ldr d6, [x17, #0x30]\n"
+ "mov v23.16b, v15.16b\n"
+ "mov v9.16b, v18.16b\n"
+ "ldr d7, [x17, #0x38]\n"
+ "ldr d8, [x17, #0x40]\n"
+ "usubl v0.8h, v0.8b, v16.8b\n"
+ "usubl v1.8h, v1.8b, v16.8b\n"
+ "ldp x26, x25, [x13, #0x0]\n"
+ "ldp x24, x23, [x13, #0x10]\n"
+ "usubl v2.8h, v2.8b, v16.8b\n"
+ "usubl v3.8h, v3.8b, v16.8b\n"
+ "ldp x22, x21, [x13, #0x20]\n"
+ "ldp x20, x19, [x13, #0x30]\n"
+ "usubl v4.8h, v4.8b, v16.8b\n"
+ "usubl v5.8h, v5.8b, v16.8b\n"
+ "ldr d31, [x26, x15]\n"
+ "ldr d30, [x25, x15]\n"
+ "usubl v6.8h, v6.8b, v16.8b\n"
+ "usubl v7.8h, v7.8b, v16.8b\n"
+ "ldr d29, [x24, x15]\n"
+ "ldr d28, [x23, x15]\n"
+ "usubl v8.8h, v8.8b, v16.8b\n"
"ushll v31.8h, v31.8b, #0x0\n"
- "ldr d26, [x22, x17]\n"
- "ldr d25, [x21, x17]\n"
+ "ldr d27, [x22, x15]\n"
+ "ldr d26, [x21, x15]\n"
"ushll v30.8h, v30.8b, #0x0\n"
"ushll v29.8h, v29.8b, #0x0\n"
- "ldr d24, [x20, x17]\n"
+ "ldr d25, [x20, x15]\n"
+ "ldr d24, [x19, x15]\n"
"ushll v28.8h, v28.8b, #0x0\n"
"ushll v27.8h, v27.8b, #0x0\n"
"ushll v26.8h, v26.8b, #0x0\n"
@@ -425,967 +425,967 @@ void a64_u8qa_nhwc_3x3_s2_output2x2_mla_depthfirst_impl(
"ushll v24.8h, v24.8b, #0x0\n"
"bgt 1b\n"
"2:" // Tail
- "ldr q18, [x13, #0x0]\n"
"smlal v15.4s, v31.4h, v8.4h\n"
- "smlal2 v13.4s, v31.8h, v8.8h\n"
- "ldr x23, [x15, #0x40]\n"
- "smlal v17.4s, v31.4h, v6.4h\n"
- "smlal2 v20.4s, v31.8h, v6.8h\n"
- "ldr x22, [x15, #0x48]\n"
- "ldr x21, [x15, #0x50]\n"
+ "smlal2 v18.4s, v31.8h, v8.8h\n"
+ "ldr x24, [x13, #0x40]\n"
+ "ldr x23, [x13, #0x48]\n"
+ "smlal v13.4s, v31.4h, v6.4h\n"
+ "smlal2 v17.4s, v31.8h, v6.8h\n"
+ "ldr x21, [x13, #0x50]\n"
+ "ldr x19, [x13, #0x58]\n"
"smlal v15.4s, v30.4h, v0.4h\n"
- "smlal2 v13.4s, v30.8h, v0.8h\n"
- "ldr q21, [x12, #0x0]\n"
- "ldr x20, [x15, #0x58]\n"
- "smlal v17.4s, v28.4h, v1.4h\n"
- "smlal2 v20.4s, v28.8h, v1.8h\n"
- "ldr d28, [x22, x17]\n"
+ "smlal2 v18.4s, v30.8h, v0.8h\n"
+ "ldr x22, [x13, #0x78]\n"
+ "ldr x20, [x13, #0x60]\n"
+ "smlal v13.4s, v28.4h, v1.4h\n"
+ "smlal2 v17.4s, v28.8h, v1.8h\n"
+ "ldr d28, [x23, x15]\n"
"ushll v28.8h, v28.8b, #0x0\n"
"smlal v15.4s, v29.4h, v1.4h\n"
- "smlal2 v13.4s, v29.8h, v1.8h\n"
- "ldr d29, [x23, x17]\n"
+ "smlal2 v18.4s, v29.8h, v1.8h\n"
+ "ldr d29, [x24, x15]\n"
"ushll v29.8h, v29.8b, #0x0\n"
- "smlal v17.4s, v27.4h, v2.4h\n"
- "smlal2 v20.4s, v27.8h, v2.8h\n"
- "ldr d27, [x21, x17]\n"
+ "smlal v13.4s, v27.4h, v2.4h\n"
+ "smlal2 v17.4s, v27.8h, v2.8h\n"
+ "ldr d27, [x21, x15]\n"
"ushll v27.8h, v27.8b, #0x0\n"
"smlal v15.4s, v26.4h, v3.4h\n"
- "smlal2 v13.4s, v26.8h, v3.8h\n"
- "ldr d26, [x20, x17]\n"
- "ldr x23, [x15, #0x78]\n"
- "smlal v17.4s, v24.4h, v0.4h\n"
- "smlal2 v20.4s, v24.8h, v0.8h\n"
- "ldr x20, [x15, #0x60]\n"
+ "smlal2 v18.4s, v26.8h, v3.8h\n"
+ "ldr d26, [x19, x15]\n"
"ushll v26.8h, v26.8b, #0x0\n"
+ "smlal v13.4s, v24.4h, v0.4h\n"
+ "smlal2 v17.4s, v24.8h, v0.8h\n"
+ "ldr x21, [x13, #0x80]\n"
+ "ldr x19, [x13, #0x68]\n"
"smlal v15.4s, v25.4h, v4.4h\n"
- "smlal2 v13.4s, v25.8h, v4.8h\n"
- "ldr d25, [x20, x17]\n"
- "ldr x21, [x15, #0x80]\n"
- "smlal v17.4s, v29.4h, v4.4h\n"
- "smlal2 v20.4s, v29.8h, v4.8h\n"
- "ldr q30, [x13, #0x10]\n"
- "ldr x20, [x15, #0x68]\n"
- "smlal v15.4s, v24.4h, v2.4h\n"
- "smlal2 v13.4s, v24.8h, v2.8h\n"
- "ldr d29, [x20, x17]\n"
+ "smlal2 v18.4s, v25.8h, v4.8h\n"
+ "ldr d25, [x20, x15]\n"
"ushll v25.8h, v25.8b, #0x0\n"
- "smlal v17.4s, v28.4h, v5.4h\n"
- "smlal2 v20.4s, v28.8h, v5.8h\n"
- "ldr d28, [x21, x17]\n"
- "ldr x22, [x15, #0x88]\n"
+ "smlal v13.4s, v29.4h, v4.4h\n"
+ "smlal2 v17.4s, v29.8h, v4.8h\n"
+ "ldr x20, [x13, #0x88]\n"
+ "ldr d29, [x19, x15]\n"
+ "smlal v15.4s, v24.4h, v2.4h\n"
+ "smlal2 v18.4s, v24.8h, v2.8h\n"
+ "ldr x19, [x13, #0x70]\n"
+ "ushll v29.8h, v29.8b, #0x0\n"
+ "smlal v13.4s, v28.4h, v5.4h\n"
+ "smlal2 v17.4s, v28.8h, v5.8h\n"
+ "ldr d28, [x21, x15]\n"
+ "ushll v28.8h, v28.8b, #0x0\n"
"smlal v11.4s, v31.4h, v2.4h\n"
"smlal2 v10.4s, v31.8h, v2.8h\n"
- "ldr x20, [x15, #0x70]\n"
- "ushll v28.8h, v28.8b, #0x0\n"
+ "ldr x24, [x13, #0x98]\n"
+ "ldr d24, [x19, x15]\n"
"smlal v15.4s, v27.4h, v5.4h\n"
- "smlal2 v13.4s, v27.8h, v5.8h\n"
- "ushll v29.8h, v29.8b, #0x0\n"
- "ldr x24, [x15, #0x98]\n"
- "smlal v17.4s, v27.4h, v3.4h\n"
- "smlal2 v20.4s, v27.8h, v3.8h\n"
- "ldr d27, [x23, x17]\n"
+ "smlal2 v18.4s, v27.8h, v5.8h\n"
+ "ushll v24.8h, v24.8b, #0x0\n"
+ "ldr x23, [x13, #0x90]\n"
+ "smlal v13.4s, v27.4h, v3.4h\n"
+ "smlal2 v17.4s, v27.8h, v3.8h\n"
+ "ldr d27, [x22, x15]\n"
"ushll v27.8h, v27.8b, #0x0\n"
- "smlal v9.4s, v31.4h, v0.4h\n"
+ "smlal v23.4s, v31.4h, v0.4h\n"
"smlal v11.4s, v26.4h, v3.4h\n"
- "ldr x21, [x15, #0x90]\n"
- "ldr x23, [x15, #0xa8]\n"
+ "ldr x22, [x13, #0xa8]\n"
+ "ldr x19, [x13, #0xa0]\n"
"smlal2 v10.4s, v26.8h, v3.8h\n"
- "ldr d26, [x22, x17]\n"
- "smlal2 v22.4s, v31.8h, v0.8h\n"
- "ldr d24, [x20, x17]\n"
- "smlal v9.4s, v27.4h, v4.4h\n"
- "smlal v11.4s, v25.4h, v0.4h\n"
+ "smlal2 v9.4s, v31.8h, v0.8h\n"
+ "ldr d26, [x20, x15]\n"
"ushll v26.8h, v26.8b, #0x0\n"
- "ldr x20, [x15, #0xa0]\n"
+ "smlal v23.4s, v27.4h, v4.4h\n"
+ "smlal v11.4s, v25.4h, v0.4h\n"
+ "ldr x21, [x13, #0xb0]\n"
+ "ldr x20, [x13, #0xb8]\n"
"smlal2 v10.4s, v25.8h, v0.8h\n"
- "ldr q31, [x12, #0x10]\n"
- "smlal2 v22.4s, v27.8h, v4.8h\n"
- "ldr d27, [x20, x17]\n"
- "smlal v9.4s, v28.4h, v1.4h\n"
+ "smlal2 v9.4s, v27.8h, v4.8h\n"
+ "ldr d27, [x19, x15]\n"
+ "ushll v27.8h, v27.8b, #0x0\n"
+ "smlal v23.4s, v28.4h, v1.4h\n"
"smlal v15.4s, v25.4h, v6.4h\n"
- "ushll v24.8h, v24.8b, #0x0\n"
- "ldr x22, [x15, #0xb0]\n"
- "smlal2 v13.4s, v25.8h, v6.8h\n"
- "ldr d25, [x21, x17]\n"
+ "ldr x19, [x13, #0xc0]\n"
+ "ldr q22, [x12, #0x0]\n"
+ "smlal2 v18.4s, v25.8h, v6.8h\n"
"smlal v11.4s, v29.4h, v4.4h\n"
+ "ldr d25, [x23, x15]\n"
"ushll v25.8h, v25.8b, #0x0\n"
"smlal2 v10.4s, v29.8h, v4.8h\n"
- "ldr d29, [x24, x17]\n"
- "smlal2 v22.4s, v28.8h, v1.8h\n"
+ "ldr d29, [x24, x15]\n"
+ "smlal2 v9.4s, v28.8h, v1.8h\n"
"ushll v29.8h, v29.8b, #0x0\n"
- "smlal v9.4s, v26.4h, v5.4h\n"
+ "smlal v23.4s, v26.4h, v5.4h\n"
"smlal v15.4s, v24.4h, v7.4h\n"
- "ldr x21, [x15, #0xb8]\n"
- "ushll v27.8h, v27.8b, #0x0\n"
- "smlal2 v13.4s, v24.8h, v7.8h\n"
+ "ldr q31, [x11, #0x0]\n"
+ "ldr q19, [x12, #0x10]\n"
+ "smlal2 v18.4s, v24.8h, v7.8h\n"
"smlal v11.4s, v24.4h, v1.4h\n"
- "ldr x20, [x15, #0xc0]\n"
- "sqrdmulh v15.4s, v15.4s, v18.4s\n"
+ "sqrdmulh v15.4s, v15.4s, v22.4s\n"
+ "ldr q30, [x11, #0x10]\n"
"smlal2 v10.4s, v24.8h, v1.8h\n"
- "ldr d24, [x23, x17]\n"
- "smlal2 v22.4s, v26.8h, v5.8h\n"
- "ldr d26, [x22, x17]\n"
- "smlal v9.4s, v29.4h, v2.4h\n"
+ "ldr d24, [x22, x15]\n"
+ "smlal2 v9.4s, v26.8h, v5.8h\n"
"ushll v24.8h, v24.8b, #0x0\n"
- "smlal2 v22.4s, v29.8h, v2.8h\n"
- "tst x7, #0x7\n"
- "smlal v11.4s, v25.4h, v6.4h\n"
- "smlal v9.4s, v24.4h, v3.4h\n"
+ "smlal v23.4s, v29.4h, v2.4h\n"
+ "ldr d26, [x21, x15]\n"
+ "smlal2 v9.4s, v29.8h, v2.8h\n"
"ushll v26.8h, v26.8b, #0x0\n"
- "add x13, x13, #0x20\n"
- "smlal v17.4s, v28.4h, v7.4h\n"
- "smlal2 v20.4s, v28.8h, v7.8h\n"
- "and v2.16b, v15.16b, v21.16b\n"
+ "smlal v11.4s, v25.4h, v6.4h\n"
+ "smlal v23.4s, v24.4h, v3.4h\n"
+ "and v4.16b, v15.16b, v31.16b\n"
+ "tst x8, #0x7\n"
+ "smlal v13.4s, v28.4h, v7.4h\n"
+ "smlal2 v17.4s, v28.8h, v7.8h\n"
+ "sqrdmulh v18.4s, v18.4s, v19.4s\n"
"add x12, x12, #0x20\n"
"smlal2 v10.4s, v25.8h, v6.8h\n"
- "ldr d25, [x21, x17]\n"
- "smlal2 v22.4s, v24.8h, v3.8h\n"
+ "ldr d25, [x20, x15]\n"
+ "smlal2 v9.4s, v24.8h, v3.8h\n"
"ushll v25.8h, v25.8b, #0x0\n"
"smlal v11.4s, v27.4h, v7.4h\n"
- "smlal v9.4s, v26.4h, v7.4h\n"
- "sqrdmulh v13.4s, v13.4s, v30.4s\n"
- "smlal v17.4s, v29.4h, v8.4h\n"
- "smlal2 v20.4s, v29.8h, v8.8h\n"
- "ldr d29, [x20, x17]\n"
+ "smlal v23.4s, v26.4h, v7.4h\n"
+ "sshr v4.4s, v4.4s, #0x1f\n"
+ "add x11, x11, #0x20\n"
+ "smlal v13.4s, v29.4h, v8.4h\n"
+ "smlal2 v17.4s, v29.8h, v8.8h\n"
+ "ldr d29, [x19, x15]\n"
"ushll v29.8h, v29.8b, #0x0\n"
"smlal2 v10.4s, v27.8h, v7.8h\n"
- "smlal2 v22.4s, v26.8h, v7.8h\n"
- "sshr v2.4s, v2.4s, #0x1f\n"
- "add x17, x17, #0x8\n"
+ "smlal2 v9.4s, v26.8h, v7.8h\n"
+ "sqrdmulh v13.4s, v13.4s, v22.4s\n"
+ "add x15, x15, #0x8\n"
"smlal v11.4s, v24.4h, v5.4h\n"
- "smlal v9.4s, v25.4h, v6.4h\n"
- "and v16.16b, v13.16b, v31.16b\n"
+ "smlal v23.4s, v25.4h, v6.4h\n"
+ "and v1.16b, v13.16b, v31.16b\n"
"smlal2 v10.4s, v24.8h, v5.8h\n"
- "smlal2 v22.4s, v25.8h, v6.8h\n"
- "sqrdmulh v17.4s, v17.4s, v18.4s\n"
+ "smlal2 v9.4s, v25.8h, v6.8h\n"
+ "sqrdmulh v17.4s, v17.4s, v19.4s\n"
"smlal v11.4s, v25.4h, v8.4h\n"
- "smlal v9.4s, v29.4h, v8.4h\n"
- "sqrdmulh v11.4s, v11.4s, v18.4s\n"
+ "smlal v23.4s, v29.4h, v8.4h\n"
+ "sqrdmulh v11.4s, v11.4s, v22.4s\n"
"smlal2 v10.4s, v25.8h, v8.8h\n"
- "smlal2 v22.4s, v29.8h, v8.8h\n"
- "sqrdmulh v9.4s, v9.4s, v18.4s\n"
- "sqadd v15.4s, v15.4s, v2.4s\n"
- "sshr v16.4s, v16.4s, #0x1f\n"
- "and v18.16b, v17.16b, v21.16b\n"
- "sqrdmulh v20.4s, v20.4s, v30.4s\n"
- "and v28.16b, v11.16b, v21.16b\n"
- "sqrdmulh v10.4s, v10.4s, v30.4s\n"
- "and v2.16b, v9.16b, v21.16b\n"
- "sqrdmulh v22.4s, v22.4s, v30.4s\n"
- "sqadd v13.4s, v13.4s, v16.4s\n"
- "sshr v18.4s, v18.4s, #0x1f\n"
- "and v4.16b, v20.16b, v31.16b\n"
- "sshr v28.4s, v28.4s, #0x1f\n"
- "and v3.16b, v10.16b, v31.16b\n"
- "sshr v2.4s, v2.4s, #0x1f\n"
- "and v16.16b, v22.16b, v31.16b\n"
- "sqadd v17.4s, v17.4s, v18.4s\n"
- "sshr v4.4s, v4.4s, #0x1f\n"
- "sqadd v11.4s, v11.4s, v28.4s\n"
- "sshr v3.4s, v3.4s, #0x1f\n"
- "sqadd v9.4s, v9.4s, v2.4s\n"
- "sshr v16.4s, v16.4s, #0x1f\n"
- "srshl v15.4s, v15.4s, v21.4s\n"
- "srshl v17.4s, v17.4s, v21.4s\n"
- "sqadd v20.4s, v20.4s, v4.4s\n"
- "srshl v11.4s, v11.4s, v21.4s\n"
- "sqadd v10.4s, v10.4s, v3.4s\n"
- "srshl v9.4s, v9.4s, v21.4s\n"
- "sqadd v22.4s, v22.4s, v16.4s\n"
+ "smlal2 v9.4s, v29.8h, v8.8h\n"
+ "sqrdmulh v23.4s, v23.4s, v22.4s\n"
+ "and v22.16b, v11.16b, v31.16b\n"
+ "sqrdmulh v10.4s, v10.4s, v19.4s\n"
+ "and v20.16b, v23.16b, v31.16b\n"
+ "sqrdmulh v9.4s, v9.4s, v19.4s\n"
+ "and v19.16b, v18.16b, v30.16b\n"
+ "sshr v1.4s, v1.4s, #0x1f\n"
+ "and v27.16b, v17.16b, v30.16b\n"
+ "sshr v22.4s, v22.4s, #0x1f\n"
+ "and v25.16b, v10.16b, v30.16b\n"
+ "sshr v20.4s, v20.4s, #0x1f\n"
+ "and v0.16b, v9.16b, v30.16b\n"
+ "sqadd v15.4s, v15.4s, v4.4s\n"
+ "sshr v19.4s, v19.4s, #0x1f\n"
+ "sqadd v13.4s, v13.4s, v1.4s\n"
+ "sshr v27.4s, v27.4s, #0x1f\n"
+ "sqadd v11.4s, v11.4s, v22.4s\n"
+ "sshr v25.4s, v25.4s, #0x1f\n"
+ "sqadd v23.4s, v23.4s, v20.4s\n"
+ "sshr v0.4s, v0.4s, #0x1f\n"
+ "srshl v15.4s, v15.4s, v31.4s\n"
+ "sqadd v18.4s, v18.4s, v19.4s\n"
"srshl v13.4s, v13.4s, v31.4s\n"
+ "sqadd v17.4s, v17.4s, v27.4s\n"
+ "srshl v11.4s, v11.4s, v31.4s\n"
+ "sqadd v10.4s, v10.4s, v25.4s\n"
+ "srshl v23.4s, v23.4s, v31.4s\n"
+ "sqadd v9.4s, v9.4s, v0.4s\n"
+ "srshl v18.4s, v18.4s, v30.4s\n"
"sqxtn v15.4h, v15.4s\n"
- "srshl v20.4s, v20.4s, v31.4s\n"
- "sqxtn v17.4h, v17.4s\n"
- "srshl v10.4s, v10.4s, v31.4s\n"
+ "srshl v17.4s, v17.4s, v30.4s\n"
+ "sqxtn v13.4h, v13.4s\n"
+ "srshl v10.4s, v10.4s, v30.4s\n"
"sqxtn v11.4h, v11.4s\n"
- "srshl v22.4s, v22.4s, v31.4s\n"
- "sqxtn v9.4h, v9.4s\n"
- "sqxtn2 v15.8h, v13.4s\n"
- "sqxtn2 v17.8h, v20.4s\n"
+ "srshl v9.4s, v9.4s, v30.4s\n"
+ "sqxtn v23.4h, v23.4s\n"
+ "sqxtn2 v15.8h, v18.4s\n"
+ "sqxtn2 v13.8h, v17.4s\n"
"sqxtn2 v11.8h, v10.4s\n"
- "sqxtn2 v9.8h, v22.4s\n"
+ "sqxtn2 v23.8h, v9.4s\n"
"sqadd v15.8h, v15.8h, v12.8h\n"
- "sqadd v17.8h, v17.8h, v12.8h\n"
+ "sqadd v13.8h, v13.8h, v12.8h\n"
"sqadd v11.8h, v11.8h, v12.8h\n"
- "sqadd v9.8h, v9.8h, v12.8h\n"
+ "sqadd v23.8h, v23.8h, v12.8h\n"
"smax v15.8h, v15.8h, v14.8h\n"
- "smax v17.8h, v17.8h, v14.8h\n"
+ "smax v13.8h, v13.8h, v14.8h\n"
"smax v11.8h, v11.8h, v14.8h\n"
- "smax v9.8h, v9.8h, v14.8h\n"
- "smin v15.8h, v15.8h, v23.8h\n"
- "smin v17.8h, v17.8h, v23.8h\n"
- "smin v11.8h, v11.8h, v23.8h\n"
- "smin v9.8h, v9.8h, v23.8h\n"
+ "smax v23.8h, v23.8h, v14.8h\n"
+ "smin v15.8h, v15.8h, v21.8h\n"
+ "smin v13.8h, v13.8h, v21.8h\n"
+ "smin v11.8h, v11.8h, v21.8h\n"
+ "smin v23.8h, v23.8h, v21.8h\n"
"uzp1 v15.16b, v15.16b, v15.16b\n"
- "uzp1 v17.16b, v17.16b, v17.16b\n"
- "str d15, [x11, x16]\n"
+ "str d15, [x10, x14]\n"
+ "uzp1 v13.16b, v13.16b, v13.16b\n"
"uzp1 v11.16b, v11.16b, v11.16b\n"
- "uzp1 v9.16b, v9.16b, v9.16b\n"
- "str d17, [x10, x16]\n"
- "str d11, [x9, x16]\n"
- "str d9, [x28, x16]\n"
- "add x16, x16, #0x8\n"
+ "str d13, [x9, x14]\n"
+ "uzp1 v23.16b, v23.16b, v23.16b\n"
+ "str d11, [x28, x14]\n"
+ "str d23, [x27, x14]\n"
+ "add x14, x14, #0x8\n"
"beq 88f\n"
- "add x14, x14, #0x48\n"
+ "add x17, x17, #0x48\n"
"3:" // Oddments
- "ldr x22, [%x[params], %[offsetof_Params_bias]]\n"
- "tbz x7, #2, 5f\n"
- "ld1 { v15.4s }, [x22], #0x10\n"
- "tbz x7, #1, 4f\n"
- "ld1 { v13.d }[0], [x22], #0x8\n"
- "tbz x7, #0, 7f\n"
- "ld1 { v13.s }[2], [x22]\n"
+ "ldr x19, [%x[params], %[offsetof_Params_bias]]\n"
+ "tbz x8, #2, 5f\n"
+ "ld1 { v15.4s }, [x19], #0x10\n"
+ "tbz x8, #1, 4f\n"
+ "ld1 { v18.d }[0], [x19], #0x8\n"
+ "tbz x8, #0, 7f\n"
+ "ld1 { v18.s }[2], [x19]\n"
"b 7f\n"
"4:" // Oddments: Load bias: Bit 2: Bit 1: Unset
- "tbz x7, #0, 7f\n"
- "ld1 { v13.s }[0], [x22]\n"
+ "tbz x8, #0, 7f\n"
+ "ld1 { v18.s }[0], [x19]\n"
"b 7f\n"
"5:" // Oddments: Load bias: Bit 2: Unset
- "tbz x7, #1, 6f\n"
- "ld1 { v15.d }[0], [x22], #0x8\n"
- "tbz x7, #0, 7f\n"
- "ld1 { v15.s }[2], [x22]\n"
+ "tbz x8, #1, 6f\n"
+ "ld1 { v15.d }[0], [x19], #0x8\n"
+ "tbz x8, #0, 7f\n"
+ "ld1 { v15.s }[2], [x19]\n"
"b 7f\n"
"6:" // Oddments: Load bias: Bit 2: Unset: Bit 1: Unset
- "tbz x7, #0, 7f\n"
- "ld1 { v15.s }[0], [x22]\n"
+ "tbz x8, #0, 7f\n"
+ "ld1 { v15.s }[0], [x19]\n"
"7:" // Oddments: Load bias: Bit 2: End
- "ldr d0, [x14, #0x0]\n"
- "ldr d1, [x14, #0x8]\n"
- "mov v17.16b, v15.16b\n"
- "mov v20.16b, v13.16b\n"
- "ldr d2, [x14, #0x10]\n"
- "ldr d3, [x14, #0x18]\n"
+ "ldr d0, [x17, #0x0]\n"
+ "ldr d1, [x17, #0x8]\n"
+ "mov v13.16b, v15.16b\n"
+ "mov v17.16b, v18.16b\n"
+ "ldr d2, [x17, #0x10]\n"
+ "ldr d3, [x17, #0x18]\n"
"mov v11.16b, v15.16b\n"
- "mov v10.16b, v13.16b\n"
- "ldr d4, [x14, #0x20]\n"
- "ldr d5, [x14, #0x28]\n"
- "mov v9.16b, v15.16b\n"
- "mov v22.16b, v13.16b\n"
- "ldr d6, [x14, #0x30]\n"
- "ldr d7, [x14, #0x38]\n"
- "usubl v0.8h, v0.8b, v19.8b\n"
- "usubl v1.8h, v1.8b, v19.8b\n"
- "ldr d8, [x14, #0x40]\n"
- "ldp x27, x26, [x15, #0x0]\n"
- "usubl v2.8h, v2.8b, v19.8b\n"
- "usubl v3.8h, v3.8b, v19.8b\n"
- "ldp x25, x24, [x15, #0x10]\n"
- "ldp x23, x22, [x15, #0x20]\n"
- "usubl v4.8h, v4.8b, v19.8b\n"
- "usubl v5.8h, v5.8b, v19.8b\n"
- "ldp x21, x20, [x15, #0x30]\n"
- "usubl v6.8h, v6.8b, v19.8b\n"
- "usubl v7.8h, v7.8b, v19.8b\n"
- "usubl v8.8h, v8.8b, v19.8b\n"
- "add x27, x27, x17\n"
- "add x26, x26, x17\n"
- "add x25, x25, x17\n"
- "add x24, x24, x17\n"
- "add x23, x23, x17\n"
- "add x22, x22, x17\n"
- "add x21, x21, x17\n"
- "add x20, x20, x17\n"
- "tbz x7, #2, 9f\n"
- "ld1 { v31.s }[0], [x27], #0x4\n"
- "ld1 { v30.s }[0], [x26], #0x4\n"
- "ld1 { v29.s }[0], [x25], #0x4\n"
- "ld1 { v28.s }[0], [x24], #0x4\n"
- "ld1 { v27.s }[0], [x23], #0x4\n"
- "ld1 { v26.s }[0], [x22], #0x4\n"
- "ld1 { v25.s }[0], [x21], #0x4\n"
- "ld1 { v24.s }[0], [x20], #0x4\n"
- "tbz x7, #1, 8f\n"
- "ld1 { v31.h }[2], [x27], #0x2\n"
- "ld1 { v30.h }[2], [x26], #0x2\n"
- "ld1 { v29.h }[2], [x25], #0x2\n"
- "ld1 { v28.h }[2], [x24], #0x2\n"
- "ld1 { v27.h }[2], [x23], #0x2\n"
- "ld1 { v26.h }[2], [x22], #0x2\n"
- "ld1 { v25.h }[2], [x21], #0x2\n"
- "ld1 { v24.h }[2], [x20], #0x2\n"
- "tbz x7, #0, 11f\n"
- "ld1 { v31.b }[6], [x27]\n"
- "ld1 { v30.b }[6], [x26]\n"
- "ld1 { v29.b }[6], [x25]\n"
- "ld1 { v28.b }[6], [x24]\n"
- "ld1 { v27.b }[6], [x23]\n"
- "ld1 { v26.b }[6], [x22]\n"
- "ld1 { v25.b }[6], [x21]\n"
- "ld1 { v24.b }[6], [x20]\n"
+ "mov v10.16b, v18.16b\n"
+ "ldr d4, [x17, #0x20]\n"
+ "ldr d5, [x17, #0x28]\n"
+ "mov v23.16b, v15.16b\n"
+ "mov v9.16b, v18.16b\n"
+ "ldr d6, [x17, #0x30]\n"
+ "ldr d7, [x17, #0x38]\n"
+ "usubl v0.8h, v0.8b, v16.8b\n"
+ "usubl v1.8h, v1.8b, v16.8b\n"
+ "ldr d8, [x17, #0x40]\n"
+ "ldp x26, x25, [x13, #0x0]\n"
+ "usubl v2.8h, v2.8b, v16.8b\n"
+ "usubl v3.8h, v3.8b, v16.8b\n"
+ "ldp x24, x23, [x13, #0x10]\n"
+ "ldp x22, x21, [x13, #0x20]\n"
+ "usubl v4.8h, v4.8b, v16.8b\n"
+ "usubl v5.8h, v5.8b, v16.8b\n"
+ "ldp x20, x19, [x13, #0x30]\n"
+ "usubl v6.8h, v6.8b, v16.8b\n"
+ "usubl v7.8h, v7.8b, v16.8b\n"
+ "usubl v8.8h, v8.8b, v16.8b\n"
+ "add x26, x26, x15\n"
+ "add x25, x25, x15\n"
+ "add x24, x24, x15\n"
+ "add x23, x23, x15\n"
+ "add x22, x22, x15\n"
+ "add x21, x21, x15\n"
+ "add x20, x20, x15\n"
+ "add x19, x19, x15\n"
+ "tbz x8, #2, 9f\n"
+ "ld1 { v31.s }[0], [x26], #0x4\n"
+ "ld1 { v30.s }[0], [x25], #0x4\n"
+ "ld1 { v29.s }[0], [x24], #0x4\n"
+ "ld1 { v28.s }[0], [x23], #0x4\n"
+ "ld1 { v27.s }[0], [x22], #0x4\n"
+ "ld1 { v26.s }[0], [x21], #0x4\n"
+ "ld1 { v25.s }[0], [x20], #0x4\n"
+ "ld1 { v24.s }[0], [x19], #0x4\n"
+ "tbz x8, #1, 8f\n"
+ "ld1 { v31.h }[2], [x26], #0x2\n"
+ "ld1 { v30.h }[2], [x25], #0x2\n"
+ "ld1 { v29.h }[2], [x24], #0x2\n"
+ "ld1 { v28.h }[2], [x23], #0x2\n"
+ "ld1 { v27.h }[2], [x22], #0x2\n"
+ "ld1 { v26.h }[2], [x21], #0x2\n"
+ "ld1 { v25.h }[2], [x20], #0x2\n"
+ "ld1 { v24.h }[2], [x19], #0x2\n"
+ "tbz x8, #0, 11f\n"
+ "ld1 { v31.b }[6], [x26]\n"
+ "ld1 { v30.b }[6], [x25]\n"
+ "ld1 { v29.b }[6], [x24]\n"
+ "ld1 { v28.b }[6], [x23]\n"
+ "ld1 { v27.b }[6], [x22]\n"
+ "ld1 { v26.b }[6], [x21]\n"
+ "ld1 { v25.b }[6], [x20]\n"
+ "ld1 { v24.b }[6], [x19]\n"
"b 11f\n"
"8:" // Oddments: Initial loads: Bit 2: Bit 1: Unset
- "tbz x7, #0, 11f\n"
- "ld1 { v31.b }[4], [x27]\n"
- "ld1 { v30.b }[4], [x26]\n"
- "ld1 { v29.b }[4], [x25]\n"
- "ld1 { v28.b }[4], [x24]\n"
- "ld1 { v27.b }[4], [x23]\n"
- "ld1 { v26.b }[4], [x22]\n"
- "ld1 { v25.b }[4], [x21]\n"
- "ld1 { v24.b }[4], [x20]\n"
+ "tbz x8, #0, 11f\n"
+ "ld1 { v31.b }[4], [x26]\n"
+ "ld1 { v30.b }[4], [x25]\n"
+ "ld1 { v29.b }[4], [x24]\n"
+ "ld1 { v28.b }[4], [x23]\n"
+ "ld1 { v27.b }[4], [x22]\n"
+ "ld1 { v26.b }[4], [x21]\n"
+ "ld1 { v25.b }[4], [x20]\n"
+ "ld1 { v24.b }[4], [x19]\n"
"b 11f\n"
"9:" // Oddments: Initial loads: Bit 2: Unset
- "tbz x7, #1, 10f\n"
- "ld1 { v31.h }[0], [x27], #0x2\n"
- "ld1 { v30.h }[0], [x26], #0x2\n"
- "ld1 { v29.h }[0], [x25], #0x2\n"
- "ld1 { v28.h }[0], [x24], #0x2\n"
- "ld1 { v27.h }[0], [x23], #0x2\n"
- "ld1 { v26.h }[0], [x22], #0x2\n"
- "ld1 { v25.h }[0], [x21], #0x2\n"
- "ld1 { v24.h }[0], [x20], #0x2\n"
- "tbz x7, #0, 11f\n"
- "ld1 { v31.b }[2], [x27]\n"
- "ld1 { v30.b }[2], [x26]\n"
- "ld1 { v29.b }[2], [x25]\n"
- "ld1 { v28.b }[2], [x24]\n"
- "ld1 { v27.b }[2], [x23]\n"
- "ld1 { v26.b }[2], [x22]\n"
- "ld1 { v25.b }[2], [x21]\n"
- "ld1 { v24.b }[2], [x20]\n"
+ "tbz x8, #1, 10f\n"
+ "ld1 { v31.h }[0], [x26], #0x2\n"
+ "ld1 { v30.h }[0], [x25], #0x2\n"
+ "ld1 { v29.h }[0], [x24], #0x2\n"
+ "ld1 { v28.h }[0], [x23], #0x2\n"
+ "ld1 { v27.h }[0], [x22], #0x2\n"
+ "ld1 { v26.h }[0], [x21], #0x2\n"
+ "ld1 { v25.h }[0], [x20], #0x2\n"
+ "ld1 { v24.h }[0], [x19], #0x2\n"
+ "tbz x8, #0, 11f\n"
+ "ld1 { v31.b }[2], [x26]\n"
+ "ld1 { v30.b }[2], [x25]\n"
+ "ld1 { v29.b }[2], [x24]\n"
+ "ld1 { v28.b }[2], [x23]\n"
+ "ld1 { v27.b }[2], [x22]\n"
+ "ld1 { v26.b }[2], [x21]\n"
+ "ld1 { v25.b }[2], [x20]\n"
+ "ld1 { v24.b }[2], [x19]\n"
"b 11f\n"
"10:" // Oddments: Initial loads: Bit 2: Unset: Bit 1: Unset
- "tbz x7, #0, 11f\n"
- "ld1 { v31.b }[0], [x27]\n"
- "ld1 { v30.b }[0], [x26]\n"
- "ld1 { v29.b }[0], [x25]\n"
- "ld1 { v28.b }[0], [x24]\n"
- "ld1 { v27.b }[0], [x23]\n"
- "ld1 { v26.b }[0], [x22]\n"
- "ld1 { v25.b }[0], [x21]\n"
- "ld1 { v24.b }[0], [x20]\n"
+ "tbz x8, #0, 11f\n"
+ "ld1 { v31.b }[0], [x26]\n"
+ "ld1 { v30.b }[0], [x25]\n"
+ "ld1 { v29.b }[0], [x24]\n"
+ "ld1 { v28.b }[0], [x23]\n"
+ "ld1 { v27.b }[0], [x22]\n"
+ "ld1 { v26.b }[0], [x21]\n"
+ "ld1 { v25.b }[0], [x20]\n"
+ "ld1 { v24.b }[0], [x19]\n"
"11:" // Oddments: Initial loads: Bit 2: End
"ushll v31.8h, v31.8b, #0x0\n"
"smlal v15.4s, v31.4h, v8.4h\n"
- "smlal2 v13.4s, v31.8h, v8.8h\n"
- "ldr x23, [x15, #0x40]\n"
+ "smlal2 v18.4s, v31.8h, v8.8h\n"
+ "ldr x24, [x13, #0x40]\n"
"ushll v30.8h, v30.8b, #0x0\n"
"smlal v15.4s, v30.4h, v0.4h\n"
- "smlal2 v13.4s, v30.8h, v0.8h\n"
- "add x23, x23, x17\n"
+ "smlal2 v18.4s, v30.8h, v0.8h\n"
+ "add x24, x24, x15\n"
"ushll v29.8h, v29.8b, #0x0\n"
- "smlal v17.4s, v31.4h, v6.4h\n"
- "smlal2 v20.4s, v31.8h, v6.8h\n"
+ "smlal v13.4s, v31.4h, v6.4h\n"
+ "smlal2 v17.4s, v31.8h, v6.8h\n"
"smlal v15.4s, v29.4h, v1.4h\n"
- "smlal2 v13.4s, v29.8h, v1.8h\n"
+ "smlal2 v18.4s, v29.8h, v1.8h\n"
"ushll v28.8h, v28.8b, #0x0\n"
"ushll v26.8h, v26.8b, #0x0\n"
- "smlal v17.4s, v28.4h, v1.4h\n"
- "smlal2 v20.4s, v28.8h, v1.8h\n"
+ "smlal v13.4s, v28.4h, v1.4h\n"
+ "smlal2 v17.4s, v28.8h, v1.8h\n"
"smlal v15.4s, v26.4h, v3.4h\n"
- "smlal2 v13.4s, v26.8h, v3.8h\n"
+ "smlal2 v18.4s, v26.8h, v3.8h\n"
"ushll v27.8h, v27.8b, #0x0\n"
"ushll v25.8h, v25.8b, #0x0\n"
- "smlal v17.4s, v27.4h, v2.4h\n"
- "smlal2 v20.4s, v27.8h, v2.8h\n"
+ "smlal v13.4s, v27.4h, v2.4h\n"
+ "smlal2 v17.4s, v27.8h, v2.8h\n"
"smlal v15.4s, v25.4h, v4.4h\n"
- "smlal2 v13.4s, v25.8h, v4.8h\n"
+ "smlal2 v18.4s, v25.8h, v4.8h\n"
"ushll v24.8h, v24.8b, #0x0\n"
"smlal v11.4s, v31.4h, v2.4h\n"
"smlal2 v10.4s, v31.8h, v2.8h\n"
- "smlal v9.4s, v31.4h, v0.4h\n"
- "smlal2 v22.4s, v31.8h, v0.8h\n"
+ "smlal v23.4s, v31.4h, v0.4h\n"
+ "smlal2 v9.4s, v31.8h, v0.8h\n"
"smlal v15.4s, v24.4h, v2.4h\n"
- "smlal2 v13.4s, v24.8h, v2.8h\n"
- "smlal v17.4s, v24.4h, v0.4h\n"
- "smlal2 v20.4s, v24.8h, v0.8h\n"
- "tbz x7, #2, 13f\n"
- "ld1 { v29.s }[0], [x23], #0x4\n"
- "tbz x7, #1, 12f\n"
- "ld1 { v29.h }[2], [x23], #0x2\n"
- "tbz x7, #0, 15f\n"
- "ld1 { v29.b }[6], [x23]\n"
+ "smlal2 v18.4s, v24.8h, v2.8h\n"
+ "smlal v13.4s, v24.4h, v0.4h\n"
+ "smlal2 v17.4s, v24.8h, v0.8h\n"
+ "tbz x8, #2, 13f\n"
+ "ld1 { v29.s }[0], [x24], #0x4\n"
+ "tbz x8, #1, 12f\n"
+ "ld1 { v29.h }[2], [x24], #0x2\n"
+ "tbz x8, #0, 15f\n"
+ "ld1 { v29.b }[6], [x24]\n"
"b 15f\n"
"12:" // Oddments: Load (1, 3): Bit 2: Bit 1: Unset
- "tbz x7, #0, 15f\n"
- "ld1 { v29.b }[4], [x23]\n"
+ "tbz x8, #0, 15f\n"
+ "ld1 { v29.b }[4], [x24]\n"
"b 15f\n"
"13:" // Oddments: Load (1, 3): Bit 2: Unset
- "tbz x7, #1, 14f\n"
- "ld1 { v29.h }[0], [x23], #0x2\n"
- "tbz x7, #0, 15f\n"
- "ld1 { v29.b }[2], [x23]\n"
+ "tbz x8, #1, 14f\n"
+ "ld1 { v29.h }[0], [x24], #0x2\n"
+ "tbz x8, #0, 15f\n"
+ "ld1 { v29.b }[2], [x24]\n"
"b 15f\n"
"14:" // Oddments: Load (1, 3): Bit 2: Unset: Bit 1: Unset
- "tbz x7, #0, 15f\n"
- "ld1 { v29.b }[0], [x23]\n"
+ "tbz x8, #0, 15f\n"
+ "ld1 { v29.b }[0], [x24]\n"
"15:" // Oddments: Load (1, 3): Bit 2: End
"ushll v29.8h, v29.8b, #0x0\n"
- "ldr x22, [x15, #0x48]\n"
- "smlal v17.4s, v29.4h, v4.4h\n"
- "smlal2 v20.4s, v29.8h, v4.8h\n"
- "add x22, x22, x17\n"
- "tbz x7, #2, 17f\n"
- "ld1 { v28.s }[0], [x22], #0x4\n"
- "tbz x7, #1, 16f\n"
- "ld1 { v28.h }[2], [x22], #0x2\n"
- "tbz x7, #0, 19f\n"
- "ld1 { v28.b }[6], [x22]\n"
+ "ldr x23, [x13, #0x48]\n"
+ "smlal v13.4s, v29.4h, v4.4h\n"
+ "smlal2 v17.4s, v29.8h, v4.8h\n"
+ "add x23, x23, x15\n"
+ "tbz x8, #2, 17f\n"
+ "ld1 { v28.s }[0], [x23], #0x4\n"
+ "tbz x8, #1, 16f\n"
+ "ld1 { v28.h }[2], [x23], #0x2\n"
+ "tbz x8, #0, 19f\n"
+ "ld1 { v28.b }[6], [x23]\n"
"b 19f\n"
"16:" // Oddments: Load (1, 4): Bit 2: Bit 1: Unset
- "tbz x7, #0, 19f\n"
- "ld1 { v28.b }[4], [x22]\n"
+ "tbz x8, #0, 19f\n"
+ "ld1 { v28.b }[4], [x23]\n"
"b 19f\n"
"17:" // Oddments: Load (1, 4): Bit 2: Unset
- "tbz x7, #1, 18f\n"
- "ld1 { v28.h }[0], [x22], #0x2\n"
- "tbz x7, #0, 19f\n"
- "ld1 { v28.b }[2], [x22]\n"
+ "tbz x8, #1, 18f\n"
+ "ld1 { v28.h }[0], [x23], #0x2\n"
+ "tbz x8, #0, 19f\n"
+ "ld1 { v28.b }[2], [x23]\n"
"b 19f\n"
"18:" // Oddments: Load (1, 4): Bit 2: Unset: Bit 1: Unset
- "tbz x7, #0, 19f\n"
- "ld1 { v28.b }[0], [x22]\n"
+ "tbz x8, #0, 19f\n"
+ "ld1 { v28.b }[0], [x23]\n"
"19:" // Oddments: Load (1, 4): Bit 2: End
"ushll v28.8h, v28.8b, #0x0\n"
- "ldr x21, [x15, #0x50]\n"
- "smlal v17.4s, v28.4h, v5.4h\n"
- "smlal2 v20.4s, v28.8h, v5.8h\n"
- "add x21, x21, x17\n"
- "tbz x7, #2, 21f\n"
+ "ldr x21, [x13, #0x50]\n"
+ "smlal v13.4s, v28.4h, v5.4h\n"
+ "smlal2 v17.4s, v28.8h, v5.8h\n"
+ "add x21, x21, x15\n"
+ "tbz x8, #2, 21f\n"
"ld1 { v27.s }[0], [x21], #0x4\n"
- "tbz x7, #1, 20f\n"
+ "tbz x8, #1, 20f\n"
"ld1 { v27.h }[2], [x21], #0x2\n"
- "tbz x7, #0, 23f\n"
+ "tbz x8, #0, 23f\n"
"ld1 { v27.b }[6], [x21]\n"
"b 23f\n"
"20:" // Oddments: Load (1, 2): Bit 2: Bit 1: Unset
- "tbz x7, #0, 23f\n"
+ "tbz x8, #0, 23f\n"
"ld1 { v27.b }[4], [x21]\n"
"b 23f\n"
"21:" // Oddments: Load (1, 2): Bit 2: Unset
- "tbz x7, #1, 22f\n"
+ "tbz x8, #1, 22f\n"
"ld1 { v27.h }[0], [x21], #0x2\n"
- "tbz x7, #0, 23f\n"
+ "tbz x8, #0, 23f\n"
"ld1 { v27.b }[2], [x21]\n"
"b 23f\n"
"22:" // Oddments: Load (1, 2): Bit 2: Unset: Bit 1: Unset
- "tbz x7, #0, 23f\n"
+ "tbz x8, #0, 23f\n"
"ld1 { v27.b }[0], [x21]\n"
"23:" // Oddments: Load (1, 2): Bit 2: End
"ushll v27.8h, v27.8b, #0x0\n"
- "ldr x20, [x15, #0x58]\n"
+ "ldr x19, [x13, #0x58]\n"
"smlal v15.4s, v27.4h, v5.4h\n"
- "smlal2 v13.4s, v27.8h, v5.8h\n"
- "smlal v17.4s, v27.4h, v3.4h\n"
- "smlal2 v20.4s, v27.8h, v3.8h\n"
- "add x20, x20, x17\n"
- "tbz x7, #2, 25f\n"
- "ld1 { v26.s }[0], [x20], #0x4\n"
- "tbz x7, #1, 24f\n"
- "ld1 { v26.h }[2], [x20], #0x2\n"
- "tbz x7, #0, 27f\n"
- "ld1 { v26.b }[6], [x20]\n"
+ "smlal2 v18.4s, v27.8h, v5.8h\n"
+ "smlal v13.4s, v27.4h, v3.4h\n"
+ "smlal2 v17.4s, v27.8h, v3.8h\n"
+ "add x19, x19, x15\n"
+ "tbz x8, #2, 25f\n"
+ "ld1 { v26.s }[0], [x19], #0x4\n"
+ "tbz x8, #1, 24f\n"
+ "ld1 { v26.h }[2], [x19], #0x2\n"
+ "tbz x8, #0, 27f\n"
+ "ld1 { v26.b }[6], [x19]\n"
"b 27f\n"
"24:" // Oddments: Load (3, 0): Bit 2: Bit 1: Unset
- "tbz x7, #0, 27f\n"
- "ld1 { v26.b }[4], [x20]\n"
+ "tbz x8, #0, 27f\n"
+ "ld1 { v26.b }[4], [x19]\n"
"b 27f\n"
"25:" // Oddments: Load (3, 0): Bit 2: Unset
- "tbz x7, #1, 26f\n"
- "ld1 { v26.h }[0], [x20], #0x2\n"
- "tbz x7, #0, 27f\n"
- "ld1 { v26.b }[2], [x20]\n"
+ "tbz x8, #1, 26f\n"
+ "ld1 { v26.h }[0], [x19], #0x2\n"
+ "tbz x8, #0, 27f\n"
+ "ld1 { v26.b }[2], [x19]\n"
"b 27f\n"
"26:" // Oddments: Load (3, 0): Bit 2: Unset: Bit 1: Unset
- "tbz x7, #0, 27f\n"
- "ld1 { v26.b }[0], [x20]\n"
+ "tbz x8, #0, 27f\n"
+ "ld1 { v26.b }[0], [x19]\n"
"27:" // Oddments: Load (3, 0): Bit 2: End
"ushll v26.8h, v26.8b, #0x0\n"
- "ldr x20, [x15, #0x60]\n"
+ "ldr x20, [x13, #0x60]\n"
"smlal v11.4s, v26.4h, v3.4h\n"
"smlal2 v10.4s, v26.8h, v3.8h\n"
- "add x20, x20, x17\n"
- "tbz x7, #2, 29f\n"
+ "add x20, x20, x15\n"
+ "tbz x8, #2, 29f\n"
"ld1 { v25.s }[0], [x20], #0x4\n"
- "tbz x7, #1, 28f\n"
+ "tbz x8, #1, 28f\n"
"ld1 { v25.h }[2], [x20], #0x2\n"
- "tbz x7, #0, 31f\n"
+ "tbz x8, #0, 31f\n"
"ld1 { v25.b }[6], [x20]\n"
"b 31f\n"
"28:" // Oddments: Load (2, 0): Bit 2: Bit 1: Unset
- "tbz x7, #0, 31f\n"
+ "tbz x8, #0, 31f\n"
"ld1 { v25.b }[4], [x20]\n"
"b 31f\n"
"29:" // Oddments: Load (2, 0): Bit 2: Unset
- "tbz x7, #1, 30f\n"
+ "tbz x8, #1, 30f\n"
"ld1 { v25.h }[0], [x20], #0x2\n"
- "tbz x7, #0, 31f\n"
+ "tbz x8, #0, 31f\n"
"ld1 { v25.b }[2], [x20]\n"
"b 31f\n"
"30:" // Oddments: Load (2, 0): Bit 2: Unset: Bit 1: Unset
- "tbz x7, #0, 31f\n"
+ "tbz x8, #0, 31f\n"
"ld1 { v25.b }[0], [x20]\n"
"31:" // Oddments: Load (2, 0): Bit 2: End
"ushll v25.8h, v25.8b, #0x0\n"
- "ldr x20, [x15, #0x68]\n"
+ "ldr x19, [x13, #0x68]\n"
"smlal v15.4s, v25.4h, v6.4h\n"
- "smlal2 v13.4s, v25.8h, v6.8h\n"
+ "smlal2 v18.4s, v25.8h, v6.8h\n"
"smlal v11.4s, v25.4h, v0.4h\n"
"smlal2 v10.4s, v25.8h, v0.8h\n"
- "add x20, x20, x17\n"
- "tbz x7, #2, 33f\n"
- "ld1 { v29.s }[0], [x20], #0x4\n"
- "tbz x7, #1, 32f\n"
- "ld1 { v29.h }[2], [x20], #0x2\n"
- "tbz x7, #0, 35f\n"
- "ld1 { v29.b }[6], [x20]\n"
+ "add x19, x19, x15\n"
+ "tbz x8, #2, 33f\n"
+ "ld1 { v29.s }[0], [x19], #0x4\n"
+ "tbz x8, #1, 32f\n"
+ "ld1 { v29.h }[2], [x19], #0x2\n"
+ "tbz x8, #0, 35f\n"
+ "ld1 { v29.b }[6], [x19]\n"
"b 35f\n"
"32:" // Oddments: Load (3, 1): Bit 2: Bit 1: Unset
- "tbz x7, #0, 35f\n"
- "ld1 { v29.b }[4], [x20]\n"
+ "tbz x8, #0, 35f\n"
+ "ld1 { v29.b }[4], [x19]\n"
"b 35f\n"
"33:" // Oddments: Load (3, 1): Bit 2: Unset
- "tbz x7, #1, 34f\n"
- "ld1 { v29.h }[0], [x20], #0x2\n"
- "tbz x7, #0, 35f\n"
- "ld1 { v29.b }[2], [x20]\n"
+ "tbz x8, #1, 34f\n"
+ "ld1 { v29.h }[0], [x19], #0x2\n"
+ "tbz x8, #0, 35f\n"
+ "ld1 { v29.b }[2], [x19]\n"
"b 35f\n"
"34:" // Oddments: Load (3, 1): Bit 2: Unset: Bit 1: Unset
- "tbz x7, #0, 35f\n"
- "ld1 { v29.b }[0], [x20]\n"
+ "tbz x8, #0, 35f\n"
+ "ld1 { v29.b }[0], [x19]\n"
"35:" // Oddments: Load (3, 1): Bit 2: End
"ushll v29.8h, v29.8b, #0x0\n"
- "ldr x20, [x15, #0x70]\n"
+ "ldr x19, [x13, #0x70]\n"
"smlal v11.4s, v29.4h, v4.4h\n"
"smlal2 v10.4s, v29.8h, v4.8h\n"
- "add x20, x20, x17\n"
- "tbz x7, #2, 37f\n"
- "ld1 { v24.s }[0], [x20], #0x4\n"
- "tbz x7, #1, 36f\n"
- "ld1 { v24.h }[2], [x20], #0x2\n"
- "tbz x7, #0, 39f\n"
- "ld1 { v24.b }[6], [x20]\n"
+ "add x19, x19, x15\n"
+ "tbz x8, #2, 37f\n"
+ "ld1 { v24.s }[0], [x19], #0x4\n"
+ "tbz x8, #1, 36f\n"
+ "ld1 { v24.h }[2], [x19], #0x2\n"
+ "tbz x8, #0, 39f\n"
+ "ld1 { v24.b }[6], [x19]\n"
"b 39f\n"
"36:" // Oddments: Load (2, 1): Bit 2: Bit 1: Unset
- "tbz x7, #0, 39f\n"
- "ld1 { v24.b }[4], [x20]\n"
+ "tbz x8, #0, 39f\n"
+ "ld1 { v24.b }[4], [x19]\n"
"b 39f\n"
"37:" // Oddments: Load (2, 1): Bit 2: Unset
- "tbz x7, #1, 38f\n"
- "ld1 { v24.h }[0], [x20], #0x2\n"
- "tbz x7, #0, 39f\n"
- "ld1 { v24.b }[2], [x20]\n"
+ "tbz x8, #1, 38f\n"
+ "ld1 { v24.h }[0], [x19], #0x2\n"
+ "tbz x8, #0, 39f\n"
+ "ld1 { v24.b }[2], [x19]\n"
"b 39f\n"
"38:" // Oddments: Load (2, 1): Bit 2: Unset: Bit 1: Unset
- "tbz x7, #0, 39f\n"
- "ld1 { v24.b }[0], [x20]\n"
+ "tbz x8, #0, 39f\n"
+ "ld1 { v24.b }[0], [x19]\n"
"39:" // Oddments: Load (2, 1): Bit 2: End
"ushll v24.8h, v24.8b, #0x0\n"
- "ldr x23, [x15, #0x78]\n"
+ "ldr x22, [x13, #0x78]\n"
"smlal v15.4s, v24.4h, v7.4h\n"
- "smlal2 v13.4s, v24.8h, v7.8h\n"
+ "smlal2 v18.4s, v24.8h, v7.8h\n"
"smlal v11.4s, v24.4h, v1.4h\n"
"smlal2 v10.4s, v24.8h, v1.8h\n"
- "add x23, x23, x17\n"
- "tbz x7, #2, 41f\n"
- "ld1 { v27.s }[0], [x23], #0x4\n"
- "tbz x7, #1, 40f\n"
- "ld1 { v27.h }[2], [x23], #0x2\n"
- "tbz x7, #0, 43f\n"
- "ld1 { v27.b }[6], [x23]\n"
+ "add x22, x22, x15\n"
+ "tbz x8, #2, 41f\n"
+ "ld1 { v27.s }[0], [x22], #0x4\n"
+ "tbz x8, #1, 40f\n"
+ "ld1 { v27.h }[2], [x22], #0x2\n"
+ "tbz x8, #0, 43f\n"
+ "ld1 { v27.b }[6], [x22]\n"
"b 43f\n"
"40:" // Oddments: Load (3, 3): Bit 2: Bit 1: Unset
- "tbz x7, #0, 43f\n"
- "ld1 { v27.b }[4], [x23]\n"
+ "tbz x8, #0, 43f\n"
+ "ld1 { v27.b }[4], [x22]\n"
"b 43f\n"
"41:" // Oddments: Load (3, 3): Bit 2: Unset
- "tbz x7, #1, 42f\n"
- "ld1 { v27.h }[0], [x23], #0x2\n"
- "tbz x7, #0, 43f\n"
- "ld1 { v27.b }[2], [x23]\n"
+ "tbz x8, #1, 42f\n"
+ "ld1 { v27.h }[0], [x22], #0x2\n"
+ "tbz x8, #0, 43f\n"
+ "ld1 { v27.b }[2], [x22]\n"
"b 43f\n"
"42:" // Oddments: Load (3, 3): Bit 2: Unset: Bit 1: Unset
- "tbz x7, #0, 43f\n"
- "ld1 { v27.b }[0], [x23]\n"
+ "tbz x8, #0, 43f\n"
+ "ld1 { v27.b }[0], [x22]\n"
"43:" // Oddments: Load (3, 3): Bit 2: End
"ushll v27.8h, v27.8b, #0x0\n"
- "ldr x21, [x15, #0x80]\n"
- "smlal v9.4s, v27.4h, v4.4h\n"
- "smlal2 v22.4s, v27.8h, v4.8h\n"
- "add x21, x21, x17\n"
- "tbz x7, #2, 45f\n"
+ "ldr x21, [x13, #0x80]\n"
+ "smlal v23.4s, v27.4h, v4.4h\n"
+ "smlal2 v9.4s, v27.8h, v4.8h\n"
+ "add x21, x21, x15\n"
+ "tbz x8, #2, 45f\n"
"ld1 { v28.s }[0], [x21], #0x4\n"
- "tbz x7, #1, 44f\n"
+ "tbz x8, #1, 44f\n"
"ld1 { v28.h }[2], [x21], #0x2\n"
- "tbz x7, #0, 47f\n"
+ "tbz x8, #0, 47f\n"
"ld1 { v28.b }[6], [x21]\n"
"b 47f\n"
"44:" // Oddments: Load (2, 3): Bit 2: Bit 1: Unset
- "tbz x7, #0, 47f\n"
+ "tbz x8, #0, 47f\n"
"ld1 { v28.b }[4], [x21]\n"
"b 47f\n"
"45:" // Oddments: Load (2, 3): Bit 2: Unset
- "tbz x7, #1, 46f\n"
+ "tbz x8, #1, 46f\n"
"ld1 { v28.h }[0], [x21], #0x2\n"
- "tbz x7, #0, 47f\n"
+ "tbz x8, #0, 47f\n"
"ld1 { v28.b }[2], [x21]\n"
"b 47f\n"
"46:" // Oddments: Load (2, 3): Bit 2: Unset: Bit 1: Unset
- "tbz x7, #0, 47f\n"
+ "tbz x8, #0, 47f\n"
"ld1 { v28.b }[0], [x21]\n"
"47:" // Oddments: Load (2, 3): Bit 2: End
"ushll v28.8h, v28.8b, #0x0\n"
- "ldr x22, [x15, #0x88]\n"
- "smlal v17.4s, v28.4h, v7.4h\n"
- "smlal2 v20.4s, v28.8h, v7.8h\n"
- "smlal v9.4s, v28.4h, v1.4h\n"
- "smlal2 v22.4s, v28.8h, v1.8h\n"
- "add x22, x22, x17\n"
- "tbz x7, #2, 49f\n"
- "ld1 { v26.s }[0], [x22], #0x4\n"
- "tbz x7, #1, 48f\n"
- "ld1 { v26.h }[2], [x22], #0x2\n"
- "tbz x7, #0, 51f\n"
- "ld1 { v26.b }[6], [x22]\n"
+ "ldr x20, [x13, #0x88]\n"
+ "smlal v13.4s, v28.4h, v7.4h\n"
+ "smlal2 v17.4s, v28.8h, v7.8h\n"
+ "smlal v23.4s, v28.4h, v1.4h\n"
+ "smlal2 v9.4s, v28.8h, v1.8h\n"
+ "add x20, x20, x15\n"
+ "tbz x8, #2, 49f\n"
+ "ld1 { v26.s }[0], [x20], #0x4\n"
+ "tbz x8, #1, 48f\n"
+ "ld1 { v26.h }[2], [x20], #0x2\n"
+ "tbz x8, #0, 51f\n"
+ "ld1 { v26.b }[6], [x20]\n"
"b 51f\n"
"48:" // Oddments: Load (3, 4): Bit 2: Bit 1: Unset
- "tbz x7, #0, 51f\n"
- "ld1 { v26.b }[4], [x22]\n"
+ "tbz x8, #0, 51f\n"
+ "ld1 { v26.b }[4], [x20]\n"
"b 51f\n"
"49:" // Oddments: Load (3, 4): Bit 2: Unset
- "tbz x7, #1, 50f\n"
- "ld1 { v26.h }[0], [x22], #0x2\n"
- "tbz x7, #0, 51f\n"
- "ld1 { v26.b }[2], [x22]\n"
+ "tbz x8, #1, 50f\n"
+ "ld1 { v26.h }[0], [x20], #0x2\n"
+ "tbz x8, #0, 51f\n"
+ "ld1 { v26.b }[2], [x20]\n"
"b 51f\n"
"50:" // Oddments: Load (3, 4): Bit 2: Unset: Bit 1: Unset
- "tbz x7, #0, 51f\n"
- "ld1 { v26.b }[0], [x22]\n"
+ "tbz x8, #0, 51f\n"
+ "ld1 { v26.b }[0], [x20]\n"
"51:" // Oddments: Load (3, 4): Bit 2: End
"ushll v26.8h, v26.8b, #0x0\n"
- "ldr x21, [x15, #0x90]\n"
- "smlal v9.4s, v26.4h, v5.4h\n"
- "smlal2 v22.4s, v26.8h, v5.8h\n"
- "add x21, x21, x17\n"
- "tbz x7, #2, 53f\n"
- "ld1 { v25.s }[0], [x21], #0x4\n"
- "tbz x7, #1, 52f\n"
- "ld1 { v25.h }[2], [x21], #0x2\n"
- "tbz x7, #0, 55f\n"
- "ld1 { v25.b }[6], [x21]\n"
+ "ldr x23, [x13, #0x90]\n"
+ "smlal v23.4s, v26.4h, v5.4h\n"
+ "smlal2 v9.4s, v26.8h, v5.8h\n"
+ "add x23, x23, x15\n"
+ "tbz x8, #2, 53f\n"
+ "ld1 { v25.s }[0], [x23], #0x4\n"
+ "tbz x8, #1, 52f\n"
+ "ld1 { v25.h }[2], [x23], #0x2\n"
+ "tbz x8, #0, 55f\n"
+ "ld1 { v25.b }[6], [x23]\n"
"b 55f\n"
"52:" // Oddments: Load (4, 0): Bit 2: Bit 1: Unset
- "tbz x7, #0, 55f\n"
- "ld1 { v25.b }[4], [x21]\n"
+ "tbz x8, #0, 55f\n"
+ "ld1 { v25.b }[4], [x23]\n"
"b 55f\n"
"53:" // Oddments: Load (4, 0): Bit 2: Unset
- "tbz x7, #1, 54f\n"
- "ld1 { v25.h }[0], [x21], #0x2\n"
- "tbz x7, #0, 55f\n"
- "ld1 { v25.b }[2], [x21]\n"
+ "tbz x8, #1, 54f\n"
+ "ld1 { v25.h }[0], [x23], #0x2\n"
+ "tbz x8, #0, 55f\n"
+ "ld1 { v25.b }[2], [x23]\n"
"b 55f\n"
"54:" // Oddments: Load (4, 0): Bit 2: Unset: Bit 1: Unset
- "tbz x7, #0, 55f\n"
- "ld1 { v25.b }[0], [x21]\n"
+ "tbz x8, #0, 55f\n"
+ "ld1 { v25.b }[0], [x23]\n"
"55:" // Oddments: Load (4, 0): Bit 2: End
"ushll v25.8h, v25.8b, #0x0\n"
- "ldr x24, [x15, #0x98]\n"
+ "ldr x24, [x13, #0x98]\n"
"smlal v11.4s, v25.4h, v6.4h\n"
"smlal2 v10.4s, v25.8h, v6.8h\n"
- "add x24, x24, x17\n"
- "tbz x7, #2, 57f\n"
+ "add x24, x24, x15\n"
+ "tbz x8, #2, 57f\n"
"ld1 { v29.s }[0], [x24], #0x4\n"
- "tbz x7, #1, 56f\n"
+ "tbz x8, #1, 56f\n"
"ld1 { v29.h }[2], [x24], #0x2\n"
- "tbz x7, #0, 59f\n"
+ "tbz x8, #0, 59f\n"
"ld1 { v29.b }[6], [x24]\n"
"b 59f\n"
"56:" // Oddments: Load (2, 4): Bit 2: Bit 1: Unset
- "tbz x7, #0, 59f\n"
+ "tbz x8, #0, 59f\n"
"ld1 { v29.b }[4], [x24]\n"
"b 59f\n"
"57:" // Oddments: Load (2, 4): Bit 2: Unset
- "tbz x7, #1, 58f\n"
+ "tbz x8, #1, 58f\n"
"ld1 { v29.h }[0], [x24], #0x2\n"
- "tbz x7, #0, 59f\n"
+ "tbz x8, #0, 59f\n"
"ld1 { v29.b }[2], [x24]\n"
"b 59f\n"
"58:" // Oddments: Load (2, 4): Bit 2: Unset: Bit 1: Unset
- "tbz x7, #0, 59f\n"
+ "tbz x8, #0, 59f\n"
"ld1 { v29.b }[0], [x24]\n"
"59:" // Oddments: Load (2, 4): Bit 2: End
"ushll v29.8h, v29.8b, #0x0\n"
- "ldr x20, [x15, #0xa0]\n"
- "smlal v17.4s, v29.4h, v8.4h\n"
- "smlal2 v20.4s, v29.8h, v8.8h\n"
- "smlal v9.4s, v29.4h, v2.4h\n"
- "smlal2 v22.4s, v29.8h, v2.8h\n"
- "add x20, x20, x17\n"
- "tbz x7, #2, 61f\n"
- "ld1 { v27.s }[0], [x20], #0x4\n"
- "tbz x7, #1, 60f\n"
- "ld1 { v27.h }[2], [x20], #0x2\n"
- "tbz x7, #0, 63f\n"
- "ld1 { v27.b }[6], [x20]\n"
+ "ldr x19, [x13, #0xa0]\n"
+ "smlal v13.4s, v29.4h, v8.4h\n"
+ "smlal2 v17.4s, v29.8h, v8.8h\n"
+ "smlal v23.4s, v29.4h, v2.4h\n"
+ "smlal2 v9.4s, v29.8h, v2.8h\n"
+ "add x19, x19, x15\n"
+ "tbz x8, #2, 61f\n"
+ "ld1 { v27.s }[0], [x19], #0x4\n"
+ "tbz x8, #1, 60f\n"
+ "ld1 { v27.h }[2], [x19], #0x2\n"
+ "tbz x8, #0, 63f\n"
+ "ld1 { v27.b }[6], [x19]\n"
"b 63f\n"
"60:" // Oddments: Load (4, 1): Bit 2: Bit 1: Unset
- "tbz x7, #0, 63f\n"
- "ld1 { v27.b }[4], [x20]\n"
+ "tbz x8, #0, 63f\n"
+ "ld1 { v27.b }[4], [x19]\n"
"b 63f\n"
"61:" // Oddments: Load (4, 1): Bit 2: Unset
- "tbz x7, #1, 62f\n"
- "ld1 { v27.h }[0], [x20], #0x2\n"
- "tbz x7, #0, 63f\n"
- "ld1 { v27.b }[2], [x20]\n"
+ "tbz x8, #1, 62f\n"
+ "ld1 { v27.h }[0], [x19], #0x2\n"
+ "tbz x8, #0, 63f\n"
+ "ld1 { v27.b }[2], [x19]\n"
"b 63f\n"
"62:" // Oddments: Load (4, 1): Bit 2: Unset: Bit 1: Unset
- "tbz x7, #0, 63f\n"
- "ld1 { v27.b }[0], [x20]\n"
+ "tbz x8, #0, 63f\n"
+ "ld1 { v27.b }[0], [x19]\n"
"63:" // Oddments: Load (4, 1): Bit 2: End
"ushll v27.8h, v27.8b, #0x0\n"
- "ldr x23, [x15, #0xa8]\n"
+ "ldr x22, [x13, #0xa8]\n"
"smlal v11.4s, v27.4h, v7.4h\n"
"smlal2 v10.4s, v27.8h, v7.8h\n"
- "add x23, x23, x17\n"
- "tbz x7, #2, 65f\n"
- "ld1 { v24.s }[0], [x23], #0x4\n"
- "tbz x7, #1, 64f\n"
- "ld1 { v24.h }[2], [x23], #0x2\n"
- "tbz x7, #0, 67f\n"
- "ld1 { v24.b }[6], [x23]\n"
+ "add x22, x22, x15\n"
+ "tbz x8, #2, 65f\n"
+ "ld1 { v24.s }[0], [x22], #0x4\n"
+ "tbz x8, #1, 64f\n"
+ "ld1 { v24.h }[2], [x22], #0x2\n"
+ "tbz x8, #0, 67f\n"
+ "ld1 { v24.b }[6], [x22]\n"
"b 67f\n"
"64:" // Oddments: Load (3, 2): Bit 2: Bit 1: Unset
- "tbz x7, #0, 67f\n"
- "ld1 { v24.b }[4], [x23]\n"
+ "tbz x8, #0, 67f\n"
+ "ld1 { v24.b }[4], [x22]\n"
"b 67f\n"
"65:" // Oddments: Load (3, 2): Bit 2: Unset
- "tbz x7, #1, 66f\n"
- "ld1 { v24.h }[0], [x23], #0x2\n"
- "tbz x7, #0, 67f\n"
- "ld1 { v24.b }[2], [x23]\n"
+ "tbz x8, #1, 66f\n"
+ "ld1 { v24.h }[0], [x22], #0x2\n"
+ "tbz x8, #0, 67f\n"
+ "ld1 { v24.b }[2], [x22]\n"
"b 67f\n"
"66:" // Oddments: Load (3, 2): Bit 2: Unset: Bit 1: Unset
- "tbz x7, #0, 67f\n"
- "ld1 { v24.b }[0], [x23]\n"
+ "tbz x8, #0, 67f\n"
+ "ld1 { v24.b }[0], [x22]\n"
"67:" // Oddments: Load (3, 2): Bit 2: End
"ushll v24.8h, v24.8b, #0x0\n"
- "ldr x22, [x15, #0xb0]\n"
+ "ldr x21, [x13, #0xb0]\n"
"smlal v11.4s, v24.4h, v5.4h\n"
"smlal2 v10.4s, v24.8h, v5.8h\n"
- "smlal v9.4s, v24.4h, v3.4h\n"
- "smlal2 v22.4s, v24.8h, v3.8h\n"
- "add x22, x22, x17\n"
- "tbz x7, #2, 69f\n"
- "ld1 { v26.s }[0], [x22], #0x4\n"
- "tbz x7, #1, 68f\n"
- "ld1 { v26.h }[2], [x22], #0x2\n"
- "tbz x7, #0, 71f\n"
- "ld1 { v26.b }[6], [x22]\n"
+ "smlal v23.4s, v24.4h, v3.4h\n"
+ "smlal2 v9.4s, v24.8h, v3.8h\n"
+ "add x21, x21, x15\n"
+ "tbz x8, #2, 69f\n"
+ "ld1 { v26.s }[0], [x21], #0x4\n"
+ "tbz x8, #1, 68f\n"
+ "ld1 { v26.h }[2], [x21], #0x2\n"
+ "tbz x8, #0, 71f\n"
+ "ld1 { v26.b }[6], [x21]\n"
"b 71f\n"
"68:" // Oddments: Load (4, 3): Bit 2: Bit 1: Unset
- "tbz x7, #0, 71f\n"
- "ld1 { v26.b }[4], [x22]\n"
+ "tbz x8, #0, 71f\n"
+ "ld1 { v26.b }[4], [x21]\n"
"b 71f\n"
"69:" // Oddments: Load (4, 3): Bit 2: Unset
- "tbz x7, #1, 70f\n"
- "ld1 { v26.h }[0], [x22], #0x2\n"
- "tbz x7, #0, 71f\n"
- "ld1 { v26.b }[2], [x22]\n"
+ "tbz x8, #1, 70f\n"
+ "ld1 { v26.h }[0], [x21], #0x2\n"
+ "tbz x8, #0, 71f\n"
+ "ld1 { v26.b }[2], [x21]\n"
"b 71f\n"
"70:" // Oddments: Load (4, 3): Bit 2: Unset: Bit 1: Unset
- "tbz x7, #0, 71f\n"
- "ld1 { v26.b }[0], [x22]\n"
+ "tbz x8, #0, 71f\n"
+ "ld1 { v26.b }[0], [x21]\n"
"71:" // Oddments: Load (4, 3): Bit 2: End
"ushll v26.8h, v26.8b, #0x0\n"
- "ldr x21, [x15, #0xb8]\n"
- "smlal v9.4s, v26.4h, v7.4h\n"
- "smlal2 v22.4s, v26.8h, v7.8h\n"
- "add x21, x21, x17\n"
- "tbz x7, #2, 73f\n"
- "ld1 { v25.s }[0], [x21], #0x4\n"
- "tbz x7, #1, 72f\n"
- "ld1 { v25.h }[2], [x21], #0x2\n"
- "tbz x7, #0, 75f\n"
- "ld1 { v25.b }[6], [x21]\n"
+ "ldr x20, [x13, #0xb8]\n"
+ "smlal v23.4s, v26.4h, v7.4h\n"
+ "smlal2 v9.4s, v26.8h, v7.8h\n"
+ "add x20, x20, x15\n"
+ "tbz x8, #2, 73f\n"
+ "ld1 { v25.s }[0], [x20], #0x4\n"
+ "tbz x8, #1, 72f\n"
+ "ld1 { v25.h }[2], [x20], #0x2\n"
+ "tbz x8, #0, 75f\n"
+ "ld1 { v25.b }[6], [x20]\n"
"b 75f\n"
"72:" // Oddments: Load (4, 2): Bit 2: Bit 1: Unset
- "tbz x7, #0, 75f\n"
- "ld1 { v25.b }[4], [x21]\n"
+ "tbz x8, #0, 75f\n"
+ "ld1 { v25.b }[4], [x20]\n"
"b 75f\n"
"73:" // Oddments: Load (4, 2): Bit 2: Unset
- "tbz x7, #1, 74f\n"
- "ld1 { v25.h }[0], [x21], #0x2\n"
- "tbz x7, #0, 75f\n"
- "ld1 { v25.b }[2], [x21]\n"
+ "tbz x8, #1, 74f\n"
+ "ld1 { v25.h }[0], [x20], #0x2\n"
+ "tbz x8, #0, 75f\n"
+ "ld1 { v25.b }[2], [x20]\n"
"b 75f\n"
"74:" // Oddments: Load (4, 2): Bit 2: Unset: Bit 1: Unset
- "tbz x7, #0, 75f\n"
- "ld1 { v25.b }[0], [x21]\n"
+ "tbz x8, #0, 75f\n"
+ "ld1 { v25.b }[0], [x20]\n"
"75:" // Oddments: Load (4, 2): Bit 2: End
"ushll v25.8h, v25.8b, #0x0\n"
- "ldr x20, [x15, #0xc0]\n"
+ "ldr x19, [x13, #0xc0]\n"
"smlal v11.4s, v25.4h, v8.4h\n"
"smlal2 v10.4s, v25.8h, v8.8h\n"
- "smlal v9.4s, v25.4h, v6.4h\n"
- "smlal2 v22.4s, v25.8h, v6.8h\n"
- "add x20, x20, x17\n"
- "tbz x7, #2, 77f\n"
- "ld1 { v29.s }[0], [x20], #0x4\n"
- "tbz x7, #1, 76f\n"
- "ld1 { v29.h }[2], [x20], #0x2\n"
- "tbz x7, #0, 79f\n"
- "ld1 { v29.b }[6], [x20]\n"
+ "smlal v23.4s, v25.4h, v6.4h\n"
+ "smlal2 v9.4s, v25.8h, v6.8h\n"
+ "add x19, x19, x15\n"
+ "tbz x8, #2, 77f\n"
+ "ld1 { v29.s }[0], [x19], #0x4\n"
+ "tbz x8, #1, 76f\n"
+ "ld1 { v29.h }[2], [x19], #0x2\n"
+ "tbz x8, #0, 79f\n"
+ "ld1 { v29.b }[6], [x19]\n"
"b 79f\n"
"76:" // Oddments: Load (4, 4): Bit 2: Bit 1: Unset
- "tbz x7, #0, 79f\n"
- "ld1 { v29.b }[4], [x20]\n"
+ "tbz x8, #0, 79f\n"
+ "ld1 { v29.b }[4], [x19]\n"
"b 79f\n"
"77:" // Oddments: Load (4, 4): Bit 2: Unset
- "tbz x7, #1, 78f\n"
- "ld1 { v29.h }[0], [x20], #0x2\n"
- "tbz x7, #0, 79f\n"
- "ld1 { v29.b }[2], [x20]\n"
+ "tbz x8, #1, 78f\n"
+ "ld1 { v29.h }[0], [x19], #0x2\n"
+ "tbz x8, #0, 79f\n"
+ "ld1 { v29.b }[2], [x19]\n"
"b 79f\n"
"78:" // Oddments: Load (4, 4): Bit 2: Unset: Bit 1: Unset
- "tbz x7, #0, 79f\n"
- "ld1 { v29.b }[0], [x20]\n"
+ "tbz x8, #0, 79f\n"
+ "ld1 { v29.b }[0], [x19]\n"
"79:" // Oddments: Load (4, 4): Bit 2: End
"ushll v29.8h, v29.8b, #0x0\n"
- "smlal v9.4s, v29.4h, v8.4h\n"
- "smlal2 v22.4s, v29.8h, v8.8h\n"
- "tbz x7, #2, 81f\n"
- "ld1 { v18.4s }, [x13], #0x10\n"
- "ld1 { v21.4s }, [x12], #0x10\n"
- "tbz x7, #1, 80f\n"
- "ld1 { v30.d }[0], [x13], #0x8\n"
- "ld1 { v31.d }[0], [x12], #0x8\n"
- "tbz x7, #0, 83f\n"
- "ld1 { v30.s }[2], [x13]\n"
- "ld1 { v31.s }[2], [x12]\n"
+ "smlal v23.4s, v29.4h, v8.4h\n"
+ "smlal2 v9.4s, v29.8h, v8.8h\n"
+ "tbz x8, #2, 81f\n"
+ "ld1 { v22.4s }, [x12], #0x10\n"
+ "ld1 { v31.4s }, [x11], #0x10\n"
+ "tbz x8, #1, 80f\n"
+ "ld1 { v19.d }[0], [x12], #0x8\n"
+ "ld1 { v30.d }[0], [x11], #0x8\n"
+ "tbz x8, #0, 83f\n"
+ "ld1 { v19.s }[2], [x12]\n"
+ "ld1 { v30.s }[2], [x11]\n"
"b 83f\n"
"80:" // Oddments: Load requant params: Bit 2: Bit 1: Unset
- "tbz x7, #0, 83f\n"
- "ld1 { v30.s }[0], [x13]\n"
- "ld1 { v31.s }[0], [x12]\n"
+ "tbz x8, #0, 83f\n"
+ "ld1 { v19.s }[0], [x12]\n"
+ "ld1 { v30.s }[0], [x11]\n"
"b 83f\n"
"81:" // Oddments: Load requant params: Bit 2: Unset
- "tbz x7, #1, 82f\n"
- "ld1 { v18.d }[0], [x13], #0x8\n"
- "ld1 { v21.d }[0], [x12], #0x8\n"
- "tbz x7, #0, 83f\n"
- "ld1 { v18.s }[2], [x13]\n"
- "ld1 { v21.s }[2], [x12]\n"
+ "tbz x8, #1, 82f\n"
+ "ld1 { v22.d }[0], [x12], #0x8\n"
+ "ld1 { v31.d }[0], [x11], #0x8\n"
+ "tbz x8, #0, 83f\n"
+ "ld1 { v22.s }[2], [x12]\n"
+ "ld1 { v31.s }[2], [x11]\n"
"b 83f\n"
"82:" // Oddments: Load requant params: Bit 2: Unset: Bit 1: Unset
- "tbz x7, #0, 83f\n"
- "ld1 { v18.s }[0], [x13]\n"
- "ld1 { v21.s }[0], [x12]\n"
+ "tbz x8, #0, 83f\n"
+ "ld1 { v22.s }[0], [x12]\n"
+ "ld1 { v31.s }[0], [x11]\n"
"83:" // Oddments: Load requant params: Bit 2: End
- "sqrdmulh v15.4s, v15.4s, v18.4s\n"
- "and v2.16b, v15.16b, v21.16b\n"
- "add x11, x11, x16\n"
- "add x10, x10, x16\n"
- "sqrdmulh v13.4s, v13.4s, v30.4s\n"
- "sshr v2.4s, v2.4s, #0x1f\n"
- "add x9, x9, x16\n"
- "add x28, x28, x16\n"
- "and v16.16b, v13.16b, v31.16b\n"
- "sqrdmulh v17.4s, v17.4s, v18.4s\n"
- "sqrdmulh v11.4s, v11.4s, v18.4s\n"
- "sqrdmulh v9.4s, v9.4s, v18.4s\n"
- "sqadd v15.4s, v15.4s, v2.4s\n"
- "sshr v16.4s, v16.4s, #0x1f\n"
- "and v18.16b, v17.16b, v21.16b\n"
- "sqrdmulh v20.4s, v20.4s, v30.4s\n"
- "and v28.16b, v11.16b, v21.16b\n"
- "sqrdmulh v10.4s, v10.4s, v30.4s\n"
- "and v2.16b, v9.16b, v21.16b\n"
- "sqrdmulh v22.4s, v22.4s, v30.4s\n"
- "sqadd v13.4s, v13.4s, v16.4s\n"
- "sshr v18.4s, v18.4s, #0x1f\n"
- "and v4.16b, v20.16b, v31.16b\n"
- "sshr v28.4s, v28.4s, #0x1f\n"
- "and v3.16b, v10.16b, v31.16b\n"
- "sshr v2.4s, v2.4s, #0x1f\n"
- "and v16.16b, v22.16b, v31.16b\n"
- "sqadd v17.4s, v17.4s, v18.4s\n"
+ "sqrdmulh v15.4s, v15.4s, v22.4s\n"
+ "sqrdmulh v13.4s, v13.4s, v22.4s\n"
+ "add x10, x10, x14\n"
+ "add x9, x9, x14\n"
+ "sqrdmulh v11.4s, v11.4s, v22.4s\n"
+ "sqrdmulh v23.4s, v23.4s, v22.4s\n"
+ "add x28, x28, x14\n"
+ "add x27, x27, x14\n"
+ "and v4.16b, v15.16b, v31.16b\n"
+ "sqrdmulh v18.4s, v18.4s, v19.4s\n"
+ "and v1.16b, v13.16b, v31.16b\n"
+ "sqrdmulh v17.4s, v17.4s, v19.4s\n"
+ "and v22.16b, v11.16b, v31.16b\n"
+ "sqrdmulh v10.4s, v10.4s, v19.4s\n"
+ "and v20.16b, v23.16b, v31.16b\n"
+ "sqrdmulh v9.4s, v9.4s, v19.4s\n"
"sshr v4.4s, v4.4s, #0x1f\n"
- "sqadd v11.4s, v11.4s, v28.4s\n"
- "sshr v3.4s, v3.4s, #0x1f\n"
- "sqadd v9.4s, v9.4s, v2.4s\n"
- "sshr v16.4s, v16.4s, #0x1f\n"
- "srshl v15.4s, v15.4s, v21.4s\n"
- "srshl v17.4s, v17.4s, v21.4s\n"
- "sqadd v20.4s, v20.4s, v4.4s\n"
- "srshl v11.4s, v11.4s, v21.4s\n"
- "sqadd v10.4s, v10.4s, v3.4s\n"
- "srshl v9.4s, v9.4s, v21.4s\n"
- "sqadd v22.4s, v22.4s, v16.4s\n"
+ "and v19.16b, v18.16b, v30.16b\n"
+ "sshr v1.4s, v1.4s, #0x1f\n"
+ "and v27.16b, v17.16b, v30.16b\n"
+ "sshr v22.4s, v22.4s, #0x1f\n"
+ "and v25.16b, v10.16b, v30.16b\n"
+ "sshr v20.4s, v20.4s, #0x1f\n"
+ "and v0.16b, v9.16b, v30.16b\n"
+ "sqadd v15.4s, v15.4s, v4.4s\n"
+ "sshr v19.4s, v19.4s, #0x1f\n"
+ "sqadd v13.4s, v13.4s, v1.4s\n"
+ "sshr v27.4s, v27.4s, #0x1f\n"
+ "sqadd v11.4s, v11.4s, v22.4s\n"
+ "sshr v25.4s, v25.4s, #0x1f\n"
+ "sqadd v23.4s, v23.4s, v20.4s\n"
+ "sshr v0.4s, v0.4s, #0x1f\n"
+ "srshl v15.4s, v15.4s, v31.4s\n"
+ "sqadd v18.4s, v18.4s, v19.4s\n"
"srshl v13.4s, v13.4s, v31.4s\n"
+ "sqadd v17.4s, v17.4s, v27.4s\n"
+ "srshl v11.4s, v11.4s, v31.4s\n"
+ "sqadd v10.4s, v10.4s, v25.4s\n"
+ "srshl v23.4s, v23.4s, v31.4s\n"
+ "sqadd v9.4s, v9.4s, v0.4s\n"
+ "srshl v18.4s, v18.4s, v30.4s\n"
"sqxtn v15.4h, v15.4s\n"
- "srshl v20.4s, v20.4s, v31.4s\n"
- "sqxtn v17.4h, v17.4s\n"
- "srshl v10.4s, v10.4s, v31.4s\n"
+ "srshl v17.4s, v17.4s, v30.4s\n"
+ "sqxtn v13.4h, v13.4s\n"
+ "srshl v10.4s, v10.4s, v30.4s\n"
"sqxtn v11.4h, v11.4s\n"
- "srshl v22.4s, v22.4s, v31.4s\n"
- "sqxtn v9.4h, v9.4s\n"
- "sqxtn2 v15.8h, v13.4s\n"
- "sqxtn2 v17.8h, v20.4s\n"
+ "srshl v9.4s, v9.4s, v30.4s\n"
+ "sqxtn v23.4h, v23.4s\n"
+ "sqxtn2 v15.8h, v18.4s\n"
+ "sqxtn2 v13.8h, v17.4s\n"
"sqxtn2 v11.8h, v10.4s\n"
- "sqxtn2 v9.8h, v22.4s\n"
+ "sqxtn2 v23.8h, v9.4s\n"
"sqadd v15.8h, v15.8h, v12.8h\n"
- "sqadd v17.8h, v17.8h, v12.8h\n"
+ "sqadd v13.8h, v13.8h, v12.8h\n"
"sqadd v11.8h, v11.8h, v12.8h\n"
- "sqadd v9.8h, v9.8h, v12.8h\n"
+ "sqadd v23.8h, v23.8h, v12.8h\n"
"smax v15.8h, v15.8h, v14.8h\n"
- "smax v17.8h, v17.8h, v14.8h\n"
+ "smax v13.8h, v13.8h, v14.8h\n"
"smax v11.8h, v11.8h, v14.8h\n"
- "smax v9.8h, v9.8h, v14.8h\n"
- "smin v15.8h, v15.8h, v23.8h\n"
- "smin v17.8h, v17.8h, v23.8h\n"
- "smin v11.8h, v11.8h, v23.8h\n"
- "smin v9.8h, v9.8h, v23.8h\n"
+ "smax v23.8h, v23.8h, v14.8h\n"
+ "smin v15.8h, v15.8h, v21.8h\n"
+ "smin v13.8h, v13.8h, v21.8h\n"
+ "smin v11.8h, v11.8h, v21.8h\n"
+ "smin v23.8h, v23.8h, v21.8h\n"
"uzp1 v15.16b, v15.16b, v15.16b\n"
- "uzp1 v17.16b, v17.16b, v17.16b\n"
+ "uzp1 v13.16b, v13.16b, v13.16b\n"
"uzp1 v11.16b, v11.16b, v11.16b\n"
- "uzp1 v9.16b, v9.16b, v9.16b\n"
- "tbz x7, #2, 85f\n"
- "st1 { v15.s }[0], [x11], #0x4\n"
- "st1 { v17.s }[0], [x10], #0x4\n"
- "st1 { v11.s }[0], [x9], #0x4\n"
- "st1 { v9.s }[0], [x28], #0x4\n"
- "tbz x7, #1, 84f\n"
- "st1 { v15.h }[2], [x11], #0x2\n"
- "st1 { v17.h }[2], [x10], #0x2\n"
- "st1 { v11.h }[2], [x9], #0x2\n"
- "st1 { v9.h }[2], [x28], #0x2\n"
- "tbz x7, #0, 87f\n"
- "st1 { v15.b }[6], [x11], #0x1\n"
- "st1 { v17.b }[6], [x10], #0x1\n"
- "st1 { v11.b }[6], [x9], #0x1\n"
- "st1 { v9.b }[6], [x28], #0x1\n"
+ "uzp1 v23.16b, v23.16b, v23.16b\n"
+ "tbz x8, #2, 85f\n"
+ "st1 { v15.s }[0], [x10], #0x4\n"
+ "st1 { v13.s }[0], [x9], #0x4\n"
+ "st1 { v11.s }[0], [x28], #0x4\n"
+ "st1 { v23.s }[0], [x27], #0x4\n"
+ "tbz x8, #1, 84f\n"
+ "st1 { v15.h }[2], [x10], #0x2\n"
+ "st1 { v13.h }[2], [x9], #0x2\n"
+ "st1 { v11.h }[2], [x28], #0x2\n"
+ "st1 { v23.h }[2], [x27], #0x2\n"
+ "tbz x8, #0, 87f\n"
+ "st1 { v15.b }[6], [x10], #0x1\n"
+ "st1 { v13.b }[6], [x9], #0x1\n"
+ "st1 { v11.b }[6], [x28], #0x1\n"
+ "st1 { v23.b }[6], [x27], #0x1\n"
"b 87f\n"
"84:" // Oddments: Bit 2: Bit 1: Unset
- "tbz x7, #0, 87f\n"
- "st1 { v15.b }[4], [x11], #0x1\n"
- "st1 { v17.b }[4], [x10], #0x1\n"
- "st1 { v11.b }[4], [x9], #0x1\n"
- "st1 { v9.b }[4], [x28], #0x1\n"
+ "tbz x8, #0, 87f\n"
+ "st1 { v15.b }[4], [x10], #0x1\n"
+ "st1 { v13.b }[4], [x9], #0x1\n"
+ "st1 { v11.b }[4], [x28], #0x1\n"
+ "st1 { v23.b }[4], [x27], #0x1\n"
"b 87f\n"
"85:" // Oddments: Bit 2: Unset
- "tbz x7, #1, 86f\n"
- "st1 { v15.h }[0], [x11], #0x2\n"
- "st1 { v17.h }[0], [x10], #0x2\n"
- "st1 { v11.h }[0], [x9], #0x2\n"
- "st1 { v9.h }[0], [x28], #0x2\n"
- "tbz x7, #0, 87f\n"
- "st1 { v15.b }[2], [x11], #0x1\n"
- "st1 { v17.b }[2], [x10], #0x1\n"
- "st1 { v11.b }[2], [x9], #0x1\n"
- "st1 { v9.b }[2], [x28], #0x1\n"
+ "tbz x8, #1, 86f\n"
+ "st1 { v15.h }[0], [x10], #0x2\n"
+ "st1 { v13.h }[0], [x9], #0x2\n"
+ "st1 { v11.h }[0], [x28], #0x2\n"
+ "st1 { v23.h }[0], [x27], #0x2\n"
+ "tbz x8, #0, 87f\n"
+ "st1 { v15.b }[2], [x10], #0x1\n"
+ "st1 { v13.b }[2], [x9], #0x1\n"
+ "st1 { v11.b }[2], [x28], #0x1\n"
+ "st1 { v23.b }[2], [x27], #0x1\n"
"b 87f\n"
"86:" // Oddments: Bit 2: Unset: Bit 1: Unset
- "tbz x7, #0, 87f\n"
- "st1 { v15.b }[0], [x11], #0x1\n"
- "st1 { v17.b }[0], [x10], #0x1\n"
- "st1 { v11.b }[0], [x9], #0x1\n"
- "st1 { v9.b }[0], [x28], #0x1\n"
+ "tbz x8, #0, 87f\n"
+ "st1 { v15.b }[0], [x10], #0x1\n"
+ "st1 { v13.b }[0], [x9], #0x1\n"
+ "st1 { v11.b }[0], [x28], #0x1\n"
+ "st1 { v23.b }[0], [x27], #0x1\n"
"87:" // Oddments: Bit 2: End
"88:" // End
:
: [offsetof_Params_bias] "I" (offsetof(Params, bias)), [offsetof_Params_inptrs] "I" (offsetof(Params, inptrs)), [offsetof_Params_n_channels] "I" (offsetof(Params, n_channels)), [offsetof_Params_outptrs] "I" (offsetof(Params, outptrs)), [offsetof_Params_requant] "I" (offsetof(Params, requant)), [offsetof_Params_requant_muls] "I" (offsetof(Params, requant_muls)), [offsetof_Params_requant_shifts] "I" (offsetof(Params, requant_shifts)), [offsetof_Params_weights] "I" (offsetof(Params, weights)), [offsetof_Requantize32_b_offset] "I" (offsetof(arm_gemm::Requantize32, b_offset)), [offsetof_Requantize32_c_offset] "I" (offsetof(arm_gemm::Requantize32, c_offset)), [offsetof_Requantize32_maxval] "I" (offsetof(arm_gemm::Requantize32, maxval)), [offsetof_Requantize32_minval] "I" (offsetof(arm_gemm::Requantize32, minval)), [params] "r" (&params)
- : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28"
+ : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28"
);
}
generated by cgit v1.2.1 (git 2.23.0) at 2024-05-20 10:58:13 +0000