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authorSang-Hoon Park <sang-hoon.park@arm.com>2020-10-01 10:13:07 +0100
committerSang-Hoon Park <sang-hoon.park@arm.com>2020-10-19 08:08:24 +0000
commite4558b501bc4a8e4e731517916a29fb1594d2a78 (patch)
tree1de4af663025100a09a2f39c801eb233003a4942 /tests
parent671d4f01d96b62a24cf0688059118a1e7908650e (diff)
downloadComputeLibrary-e4558b501bc4a8e4e731517916a29fb1594d2a78.tar.gz
COMPMID-3163: Remove padding from NEDepthwiseConvolutionLayerNativeKernel
Change-Id: Ibbd6bee5c6a4ce4f212b207d17a65b9c33bcfa78 Signed-off-by: Sang-Hoon Park <sang-hoon.park@arm.com> Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/4106 Comments-Addressed: Arm Jenkins <bsgcomp@arm.com> Reviewed-by: Michele Di Giorgio <michele.digiorgio@arm.com> Tested-by: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'tests')
-rw-r--r--tests/validation/NEON/DepthwiseConvolutionLayer.cpp16
-rw-r--r--tests/validation/NEON/DepthwiseConvolutionLayerNative.cpp31
2 files changed, 32 insertions, 15 deletions
diff --git a/tests/validation/NEON/DepthwiseConvolutionLayer.cpp b/tests/validation/NEON/DepthwiseConvolutionLayer.cpp
index 407ebe362a..e255fc7b4d 100644
--- a/tests/validation/NEON/DepthwiseConvolutionLayer.cpp
+++ b/tests/validation/NEON/DepthwiseConvolutionLayer.cpp
@@ -177,8 +177,6 @@ DATA_TEST_CASE(ValidateGeneric, framework::DatasetMode::ALL, zip(zip(zip(zip(zip
TensorInfo(TensorShape(27U, 13U, 2U), 1, DataType::F32), // Invalid output size
TensorInfo(TensorShape(27U, 13U, 8U), 1, DataType::F32), // Patch size bigger than input width
TensorInfo(TensorShape(27U, 13U, 8U), 1, DataType::F32), // Dilation < 1
- TensorInfo(TensorShape(27U, 13U, 8U), 1, DataType::F32), // Window shrinking
- TensorInfo(TensorShape(32U, 13U, 8U), 1, DataType::QASYMM8), // Window shrinking
}),
framework::dataset::make("WeightsInfo", { TensorInfo(TensorShape(3U, 3U, 2U), 1, DataType::F16),
TensorInfo(TensorShape(3U, 3U, 2U), 1, DataType::F32),
@@ -188,8 +186,6 @@ DATA_TEST_CASE(ValidateGeneric, framework::DatasetMode::ALL, zip(zip(zip(zip(zip
TensorInfo(TensorShape(3U, 3U, 2U), 1, DataType::F32),
TensorInfo(TensorShape(3U, 3U, 16U), 1, DataType::F32),
TensorInfo(TensorShape(3U, 3U, 16U), 1, DataType::F32),
- TensorInfo(TensorShape(3U, 3U, 16U), 1, DataType::F32),
- TensorInfo(TensorShape(3U, 3U, 24U), 1, DataType::QASYMM8),
})),
framework::dataset::make("BiasesInfo", { TensorInfo(TensorShape(2U), 1, DataType::F32),
TensorInfo(TensorShape(2U), 1, DataType::F32),
@@ -199,8 +195,6 @@ DATA_TEST_CASE(ValidateGeneric, framework::DatasetMode::ALL, zip(zip(zip(zip(zip
TensorInfo(TensorShape(2U), 1, DataType::F32),
TensorInfo(TensorShape(16U), 1, DataType::F32),
TensorInfo(TensorShape(16U), 1, DataType::F32),
- TensorInfo(TensorShape(16U), 1, DataType::F32),
- TensorInfo(TensorShape(24U), 1, DataType::S32),
})),
framework::dataset::make("OutputInfo", { TensorInfo(TensorShape(25U, 11U, 2U), 1, DataType::F32),
TensorInfo(TensorShape(25U, 11U, 2U), 1, DataType::F32),
@@ -210,8 +204,6 @@ DATA_TEST_CASE(ValidateGeneric, framework::DatasetMode::ALL, zip(zip(zip(zip(zip
TensorInfo(TensorShape(27U, 13U, 2U), 1, DataType::F32),
TensorInfo(TensorShape(25U, 11U, 16U), 1, DataType::F32),
TensorInfo(TensorShape(25U, 11U, 16U), 1, DataType::F32),
- TensorInfo(TensorShape(25U, 11U, 16U), 1, DataType::F32),
- TensorInfo(TensorShape(32U, 11U, 24U), 1, DataType::QASYMM8),
})),
framework::dataset::make("ConvInfo", { PadStrideInfo(1, 1, 0, 0),
PadStrideInfo(1, 1, 0, 0),
@@ -221,8 +213,6 @@ DATA_TEST_CASE(ValidateGeneric, framework::DatasetMode::ALL, zip(zip(zip(zip(zip
PadStrideInfo(1, 1, 0, 0),
PadStrideInfo(1, 1, 0, 0),
PadStrideInfo(1, 1, 0, 0),
- PadStrideInfo(1, 1, 0, 0),
- PadStrideInfo(1, 1, 1, 0),
})),
framework::dataset::make("DepthMultiplier", { 1,
1,
@@ -232,8 +222,6 @@ DATA_TEST_CASE(ValidateGeneric, framework::DatasetMode::ALL, zip(zip(zip(zip(zip
1,
2,
2,
- 2,
- 3,
})),
framework::dataset::make("Dilation", { Size2D(1U, 1U),
Size2D(1U, 1U),
@@ -243,10 +231,8 @@ DATA_TEST_CASE(ValidateGeneric, framework::DatasetMode::ALL, zip(zip(zip(zip(zip
Size2D(1U, 1U),
Size2D(25U, 1U),
Size2D(0U, 1U),
- Size2D(1U, 1U),
- Size2D(1U, 1U),
})),
- framework::dataset::make("Expected", { false, false, false, false, false, false,false, false, false, false })),
+ framework::dataset::make("Expected", { false, false, false, false, false, false, false, false})),
input_info, weights_info, biases_info, output_info, conv_info, depth_multiplier,dilation, expected)
{
bool is_valid = bool(NEDepthwiseConvolutionLayer::validate(&input_info.clone()->set_is_resizable(false), &weights_info.clone()->set_is_resizable(false), &biases_info.clone()->set_is_resizable(false), &output_info.clone()->set_is_resizable(false), conv_info, depth_multiplier, ActivationLayerInfo(), dilation));
diff --git a/tests/validation/NEON/DepthwiseConvolutionLayerNative.cpp b/tests/validation/NEON/DepthwiseConvolutionLayerNative.cpp
index be0eee32e0..47551355bb 100644
--- a/tests/validation/NEON/DepthwiseConvolutionLayerNative.cpp
+++ b/tests/validation/NEON/DepthwiseConvolutionLayerNative.cpp
@@ -102,6 +102,37 @@ const auto data_layout_values = framework::dataset::make("data_layout", { DataLa
TEST_SUITE(NEON)
TEST_SUITE(DepthwiseConvolutionLayerNative)
+
+TEST_CASE(ValidateNoPadding, framework::DatasetMode::ALL)
+{
+ // this test case will ensure that the kernel is not adding implicit padding
+ constexpr uint32_t vector_size = 8; // Asummed vector size of the current native kernel
+ constexpr auto depth = vector_size * 2 + 1; // mis-aligned depth to force padding if exists.
+ constexpr auto data_layout = DataLayout::NHWC;
+ constexpr auto data_type = DataType::F32;
+
+ const auto input_size = Size2D{ 100, 100 }; // random plane size of the input
+ const auto kernel_size = Size2D{ 4, 4 }; // random plane size of the kernel
+ const auto pad_stride_info = PadStrideInfo(3, 3); // random convolution information to
+
+ TensorShape src_shape{ depth, input_size.x(), input_size.y() };
+ TensorShape weights_shape{ depth, kernel_size.x(), kernel_size.y() };
+ TensorShape bias_shape{ depth };
+
+ auto src = create_tensor<Tensor>(src_shape, data_type, 1, QuantizationInfo(), data_layout);
+ auto weights = create_tensor<Tensor>(weights_shape, data_type, 1, QuantizationInfo(), data_layout);
+ auto biases = create_tensor<Tensor>(bias_shape, data_type, 1, QuantizationInfo(), data_layout);
+ auto dst = create_tensor<Tensor>(TensorShape(), data_type, 1, QuantizationInfo(), data_layout);
+
+ NEDepthwiseConvolutionLayerNativeKernel dwc;
+ dwc.configure(&src, &weights, &biases, &dst, pad_stride_info);
+
+ ARM_COMPUTE_EXPECT(src.info()->padding().empty(), framework::LogLevel::ERRORS);
+ ARM_COMPUTE_EXPECT(weights.info()->padding().empty(), framework::LogLevel::ERRORS);
+ ARM_COMPUTE_EXPECT(biases.info()->padding().empty(), framework::LogLevel::ERRORS);
+ ARM_COMPUTE_EXPECT(dst.info()->padding().empty(), framework::LogLevel::ERRORS);
+}
+
TEST_SUITE(Float)
TEST_SUITE(FP32)
FIXTURE_DATA_TEST_CASE(RunSmall, NEDepthwiseConvolutionLayerNativeFixture<float>, framework::DatasetMode::ALL,