COMPMID-666: Adds the ability to import backing memory in a Tensor(CPU).

Change-Id: I62b843b544fe9048837fd64c22e970fc6a0aaf23
Reviewed-on: http://mpd-gerrit.cambridge.arm.com/94881
Reviewed-by: Anthony Barbier <anthony.barbier@arm.com>
Tested-by: Kaizen <jeremy.johnson+kaizengerrit@arm.com>

1 files changed, 92 insertions, 0 deletions

diff --git a/tests/validation/NEON/UNIT/TensorAllocator.cpp b/tests/validation/NEON/UNIT/TensorAllocator.cpp
new file mode 100644
index 0000000000..069831880a
--- /dev/null
+++ b/tests/validation/NEON/UNIT/TensorAllocator.cpp
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2017 ARM Limited.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include "arm_compute/runtime/TensorAllocator.h"
+
+#include "arm_compute/runtime/MemoryGroup.h"
+#include "support/ToolchainSupport.h"
+#include "tests/Utils.h"
+#include "tests/framework/Asserts.h"
+#include "tests/framework/Macros.h"
+
+namespace arm_compute
+{
+namespace test
+{
+namespace validation
+{
+TEST_SUITE(NEON)
+TEST_SUITE(UNIT)
+TEST_SUITE(TensorAllocator)
+
+TEST_CASE(ImportMemory, framework::DatasetMode::ALL)
+{
+    // Init tensor info
+    TensorInfo info(TensorShape(24U, 16U, 3U), 1, DataType::F32);
+
+    // Allocate memory buffer
+    std::shared_ptr<uint8_t> buf(new uint8_t[info.total_size()](), [](uint8_t *ptr)
+    {
+        delete[] ptr;
+    });
+
+    // Negative case : Import empty memory
+    Tensor t1;
+    t1.allocator()->init(info);
+    ARM_COMPUTE_EXPECT(bool(t1.allocator()->import_memory(Memory())), framework::LogLevel::ERRORS);
+    ARM_COMPUTE_EXPECT(t1.info()->is_resizable(), framework::LogLevel::ERRORS);
+
+    // Negative case : Import memory to a tensor that is memory managed
+    Tensor      t2;
+    MemoryGroup mg;
+    t2.allocator()->set_associated_memory_group(&mg);
+    ARM_COMPUTE_EXPECT(bool(t2.allocator()->import_memory(Memory(buf.get()))), framework::LogLevel::ERRORS);
+    ARM_COMPUTE_EXPECT(t2.info()->is_resizable(), framework::LogLevel::ERRORS);
+
+    // Positive case : Set raw pointer
+    Tensor t3;
+    t3.allocator()->init(info);
+    ARM_COMPUTE_EXPECT(!bool(t3.allocator()->import_memory(Memory(buf.get()))), framework::LogLevel::ERRORS);
+    ARM_COMPUTE_EXPECT(!t3.info()->is_resizable(), framework::LogLevel::ERRORS);
+    ARM_COMPUTE_EXPECT(t3.buffer() == buf.get(), framework::LogLevel::ERRORS);
+    t3.allocator()->free();
+    ARM_COMPUTE_EXPECT(t3.info()->is_resizable(), framework::LogLevel::ERRORS);
+    ARM_COMPUTE_EXPECT(t3.buffer() == nullptr, framework::LogLevel::ERRORS);
+
+    // Positive case : Set managed pointer
+    Tensor t4;
+    t4.allocator()->init(info);
+    ARM_COMPUTE_EXPECT(!bool(t4.allocator()->import_memory(Memory(buf))), framework::LogLevel::ERRORS);
+    ARM_COMPUTE_EXPECT(!t4.info()->is_resizable(), framework::LogLevel::ERRORS);
+    ARM_COMPUTE_EXPECT(t4.buffer() == buf.get(), framework::LogLevel::ERRORS);
+    t4.allocator()->free();
+    ARM_COMPUTE_EXPECT(t4.info()->is_resizable(), framework::LogLevel::ERRORS);
+    ARM_COMPUTE_EXPECT(t4.buffer() == nullptr, framework::LogLevel::ERRORS);
+}
+
+TEST_SUITE_END()
+TEST_SUITE_END()
+TEST_SUITE_END()
+} // namespace validation
+} // namespace test
+} // namespace arm_compute