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| author | Gian Marco Iodice <gianmarco.iodice@arm.com> | 2019-08-20 11:27:20 +0100 |
|---|---|---|
| committer | Michele Di Giorgio <michele.digiorgio@arm.com> | 2019-08-20 13:00:57 +0000 |
| commit | 1e6c9150612ae44b9c7693c01e082134270c826b (patch) | |
| tree | 2ea2f51102df8a5e08ab73747a1c7e291e3494ee /src | |
| parent | 9f0d5ecb52d5145a1fff51d1824ecfb8fe417023 (diff) | |
| download | ComputeLibrary-1e6c9150612ae44b9c7693c01e082134270c826b.tar.gz | |
COMPMID-2604: (Nightly) Failing 'GC/ConvolutionLayer/Configuration
Change-Id: I336d736f27c7113d09b6b94a92d929613a6b06e4
Signed-off-by: Gian Marco Iodice <gianmarco.iodice@arm.com>
Reviewed-on: https://review.mlplatform.org/c/1767
Reviewed-by: Michele Di Giorgio <michele.digiorgio@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'src')
3 files changed, 6 insertions, 6 deletions
diff --git a/src/core/GLES_COMPUTE/kernels/GCActivationLayerKernel.cpp b/src/core/GLES_COMPUTE/kernels/GCActivationLayerKernel.cpp index 874c3368a5..174e04811a 100644 --- a/src/core/GLES_COMPUTE/kernels/GCActivationLayerKernel.cpp +++ b/src/core/GLES_COMPUTE/kernels/GCActivationLayerKernel.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018 ARM Limited. + * Copyright (c) 2017-2019 ARM Limited. * * SPDX-License-Identifier: MIT * @@ -90,7 +90,7 @@ void GCActivationLayerKernel::configure(IGCTensor *input, IGCTensor *output, Act AccessWindowHorizontal(input->info(), 0, num_elems_processed_per_iteration), output_access); - output_access.set_valid_region(win, input->info()->valid_region()); + output->info()->set_valid_region(ValidRegion(Coordinates(), output->info()->tensor_shape())); } else { diff --git a/src/core/GLES_COMPUTE/kernels/GCGEMMInterleave4x4Kernel.cpp b/src/core/GLES_COMPUTE/kernels/GCGEMMInterleave4x4Kernel.cpp index efd5747985..ff8422d85d 100644 --- a/src/core/GLES_COMPUTE/kernels/GCGEMMInterleave4x4Kernel.cpp +++ b/src/core/GLES_COMPUTE/kernels/GCGEMMInterleave4x4Kernel.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018 ARM Limited. + * Copyright (c) 2017-2019 ARM Limited. * * SPDX-License-Identifier: MIT * @@ -82,7 +82,7 @@ void GCGEMMInterleave4x4Kernel::configure(const IGCTensor *input, IGCTensor *out update_window_and_padding(win, input_access, output_access); - output_access.set_valid_region(win, input->info()->valid_region()); + output->info()->set_valid_region(ValidRegion(Coordinates(), output->info()->tensor_shape())); IGCKernel::configure(win); } diff --git a/src/core/GLES_COMPUTE/kernels/GCGEMMTranspose1xWKernel.cpp b/src/core/GLES_COMPUTE/kernels/GCGEMMTranspose1xWKernel.cpp index dfbd0216b4..89dc887d28 100644 --- a/src/core/GLES_COMPUTE/kernels/GCGEMMTranspose1xWKernel.cpp +++ b/src/core/GLES_COMPUTE/kernels/GCGEMMTranspose1xWKernel.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018 ARM Limited. + * Copyright (c) 2017-2019 ARM Limited. * * SPDX-License-Identifier: MIT * @@ -90,7 +90,7 @@ void GCGEMMTranspose1xWKernel::configure(const IGCTensor *input, IGCTensor *outp update_window_and_padding(win, input_access, output_access); - output_access.set_valid_region(win, ValidRegion(Coordinates(), input->info()->tensor_shape())); + output->info()->set_valid_region(ValidRegion(Coordinates(), output->info()->tensor_shape())); IGCKernel::configure(win); } |