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| author | Gian Marco Iodice <gianmarco.iodice@arm.com> | 2023-01-10 12:46:29 +0000 |
|---|---|---|
| committer | Gian Marco Iodice <gianmarco.iodice@arm.com> | 2023-01-12 15:09:56 +0000 |
| commit | bc672082ae31778164ed3ec23b7a4a8f1a8dc454 (patch) | |
| tree | ed776c6190e57a95d27577ba4da2570a25242a40 /src/runtime | |
| parent | 6bcdc578a388782f5ec80ec348c5dd3f5c1f8363 (diff) | |
| download | ComputeLibrary-bc672082ae31778164ed3ec23b7a4a8f1a8dc454.tar.gz | |
Update the heuristic for CLDepthwiseConvolutionNative kernel
- Use T_LOAD2D_INDIRECT macro instead of T_LOAD_NHWC_WITH_DILATION in
the depthwise convolution opencl kernels
- Update the heuristic for Arm® Mali™-G77
Resolves COMPMID-5716
Signed-off-by: Gian Marco Iodice <gianmarco.iodice@arm.com>
Change-Id: I32d375b220e04bf05f5d8f0af2231bde600f0665
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/8930
Benchmark: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Jakub Sujak <jakub.sujak@arm.com>
Reviewed-by: Viet-Hoa Do <viet-hoa.do@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'src/runtime')
| -rw-r--r-- | src/runtime/heuristics/dwc_native/ClDWCNativeDefaultConfigValhall.cpp | 19 |
1 files changed, 17 insertions, 2 deletions
diff --git a/src/runtime/heuristics/dwc_native/ClDWCNativeDefaultConfigValhall.cpp b/src/runtime/heuristics/dwc_native/ClDWCNativeDefaultConfigValhall.cpp index 49485c83a9..d0ade1bdd7 100644 --- a/src/runtime/heuristics/dwc_native/ClDWCNativeDefaultConfigValhall.cpp +++ b/src/runtime/heuristics/dwc_native/ClDWCNativeDefaultConfigValhall.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Arm Limited. + * Copyright (c) 2022-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -283,15 +283,30 @@ DWCComputeKernelInfo ClDWCNativeDefaultConfigValhall::configure_G77_f16(const IT desc.n0 = adjust_vec_size(desc.n0, kernel_c); // Set m0 only if stride_x == 1 and dilation_x == 1 + // m0 affects the number of rows to load from the input tensor. In fact, when depth_multiplier = 1, the number of rows + // loaded from the input tensors are -> kernel_width - (M0 - 1) + // The bigger the kernel_width, the smaller the M0 to avoid register spilling. if(conv_info.stride().first == 1 && dilation.x() == 1) { + // When the kernel width and kernel height are unit, it means that we have a pointwise multiplication. Therefore, M0 can be 1 if((kernel_w >= 9) || (kernel_w == 1)) { desc.m0 = 1; } else { - desc.m0 = 2; + switch(kernel_w) + { + case 3: + desc.m0 = 4; + break; + case 5: + desc.m0 = 3; + break; + default: + desc.m0 = 2; + break; + } } } else |