aboutsummaryrefslogtreecommitdiff
path: root/src/runtime/heuristics/indirect_conv/ClIndirectConvDefaultConfigValhall.h
diff options
context:
space:
mode:
authorGian Marco Iodice <gianmarco.iodice@arm.com>2022-12-30 09:45:00 +0000
committerGian Marco Iodice <gianmarco.iodice@arm.com>2022-12-30 13:33:34 +0000
commit9d3bd41030366326e9c8afe5db3a5812a76b135b (patch)
treee2ee02632bca1a8f671043b2b6ee1f35f8f9c9d5 /src/runtime/heuristics/indirect_conv/ClIndirectConvDefaultConfigValhall.h
parentb7e8626717b2ef81b0d03284c8f6ffdbe9cd2245 (diff)
downloadComputeLibrary-9d3bd41030366326e9c8afe5db3a5812a76b135b.tar.gz
Move DWC native heuristic into the heuristic folder
- Move the DWC native heuristic from CLDepthwiseConvolutionLayer to heuristic/ - Update the heuristic for Arm® Mali™-G77. Use a smaller block size (4x2) for Fp16 - Call the new heuristic in GpuDepthwiseConv2d Resolves COMPMID-5798 Signed-off-by: Gian Marco Iodice <gianmarco.iodice@arm.com> Change-Id: I6bfd30cea76bea2e98202a7a5c1d51709f3382a4 Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/8889 Comments-Addressed: Arm Jenkins <bsgcomp@arm.com> Reviewed-by: Gunes Bayir <gunes.bayir@arm.com> Tested-by: Arm Jenkins <bsgcomp@arm.com> Benchmark: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'src/runtime/heuristics/indirect_conv/ClIndirectConvDefaultConfigValhall.h')
-rw-r--r--src/runtime/heuristics/indirect_conv/ClIndirectConvDefaultConfigValhall.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/runtime/heuristics/indirect_conv/ClIndirectConvDefaultConfigValhall.h b/src/runtime/heuristics/indirect_conv/ClIndirectConvDefaultConfigValhall.h
index cd9a6a5c37..68dca91885 100644
--- a/src/runtime/heuristics/indirect_conv/ClIndirectConvDefaultConfigValhall.h
+++ b/src/runtime/heuristics/indirect_conv/ClIndirectConvDefaultConfigValhall.h
@@ -47,6 +47,6 @@ private:
DirectConvComputeKernelInfo configure_G77_f32(const ITensorInfo *src, const ITensorInfo *wei, const PadStrideInfo &conv_info);
DirectConvComputeKernelInfo configure_G77_f16(const ITensorInfo *src, const ITensorInfo *wei, const PadStrideInfo &conv_info);
};
-} // namespace opencl
+} // namespace cl_indirect_conv
} // namespace arm_compute
#endif /* SRC_RUNTIME_HEURISTICS_INDIRECT_CONV_CLINDIRECTCONVDEFAULTCONFIGVALHALL */