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| author | Michele Di Giorgio <michele.digiorgio@arm.com> | 2021-01-22 09:47:04 +0000 |
|---|---|---|
| committer | Michele Di Giorgio <michele.digiorgio@arm.com> | 2021-06-18 10:33:48 +0000 |
| commit | d02d5edfa15ba6c04a9986a8a362a945cb38ac31 (patch) | |
| tree | ced4f49691d6c7038e347a8709b315bff59c64cf /src/runtime/cpu/operators/CpuDepthwiseConv2d.cpp | |
| parent | b014c27ba6db9840e4a72519760d51a87a2af7e7 (diff) | |
| download | ComputeLibrary-d02d5edfa15ba6c04a9986a8a362a945cb38ac31.tar.gz | |
Integrate improved CPU depthwise convolution kernels
* Replace assembly kernels for depthwise convolution with more optimized
ones.
* Add int8 assembly kernels.
* Fix implicit padding on optimized kernels
Resolves: COMPMID-3867, COMPMID-4361
Change-Id: I0b0867e05f61be4f368f62190d55e14d0ab3ebf2
Signed-off-by: Michele Di Giorgio <michele.digiorgio@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/5622
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
Diffstat (limited to 'src/runtime/cpu/operators/CpuDepthwiseConv2d.cpp')
| -rw-r--r-- | src/runtime/cpu/operators/CpuDepthwiseConv2d.cpp | 16 |
1 files changed, 4 insertions, 12 deletions
diff --git a/src/runtime/cpu/operators/CpuDepthwiseConv2d.cpp b/src/runtime/cpu/operators/CpuDepthwiseConv2d.cpp index 160a9fd70b..f577e94def 100644 --- a/src/runtime/cpu/operators/CpuDepthwiseConv2d.cpp +++ b/src/runtime/cpu/operators/CpuDepthwiseConv2d.cpp @@ -62,8 +62,8 @@ Status validate_arguments_optimized(const ITensorInfo *src, const ITensorInfo *w ARM_COMPUTE_RETURN_ON_ERROR(CpuDepthwiseConv2dAssemblyDispatch::validate(src, weights, biases, dst, info)); - //Validate Activation Layer - if(info.act_info.enabled()) + // Validate Activation Layer + if(info.act_info.enabled() && !CpuDepthwiseConv2dAssemblyDispatch::is_activation_supported(info.act_info)) { ARM_COMPUTE_RETURN_ON_ERROR(CpuActivation::validate(dst, nullptr, info.act_info)); } @@ -95,15 +95,7 @@ void CpuDepthwiseConv2d::CpuDepthwiseConv2dOptimizedInternal::configure(ITensorI _is_prepared = false; // Configure pipeline - ActivationLayerInfo act_info_to_use = ActivationLayerInfo(); - const bool is_relu = arm_compute::utils::info_helpers::is_relu(info.act_info); - const bool is_relu6 = arm_compute::utils::info_helpers::is_relu6(info.act_info); - _is_activationlayer_enabled = info.act_info.enabled() && !(is_relu || is_relu6); - - if(!_is_activationlayer_enabled) - { - act_info_to_use = info.act_info; - } + _is_activationlayer_enabled = info.act_info.enabled() && !CpuDepthwiseConv2dAssemblyDispatch::is_activation_supported(info.act_info); _dwc_optimized_func = std::make_unique<CpuDepthwiseConv2dAssemblyDispatch>(); if(_is_nchw) @@ -359,7 +351,7 @@ Status CpuDepthwiseConv2d::CpuDepthwiseConv2dGeneric::validate(const ITensorInfo } // Validate Activation Layer - if(info.act_info.enabled()) + if(info.act_info.enabled() && !CpuDepthwiseConv2dAssemblyDispatch::is_activation_supported(info.act_info)) { ARM_COMPUTE_RETURN_ON_ERROR(CpuActivation::validate(dst, nullptr, info.act_info)); } |