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| author | Georgios Pinitas <georgios.pinitas@arm.com> | 2018-06-04 19:27:13 +0100 |
|---|---|---|
| committer | Anthony Barbier <anthony.barbier@arm.com> | 2018-11-02 16:52:54 +0000 |
| commit | 17812ba9f7cf2c8f5121c11760ac45fbbdb7aeaf (patch) | |
| tree | 28c7bb65a8306e82de91a644fdcc1c0947c6f6d7 /src/runtime/CL/functions/CLPoolingLayer.cpp | |
| parent | f8d8f3aff04faf731f20411ecb91027eab4365c5 (diff) | |
| download | ComputeLibrary-17812ba9f7cf2c8f5121c11760ac45fbbdb7aeaf.tar.gz | |
COMPMID-817: Tuner: Port kernels to new design.
Change-Id: Iaabb1153c2abe0400ec79d51a21347debe92d642
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/134062
Tested-by: Jenkins <bsgcomp@arm.com>
Reviewed-by: Anthony Barbier <anthony.barbier@arm.com>
Diffstat (limited to 'src/runtime/CL/functions/CLPoolingLayer.cpp')
| -rw-r--r-- | src/runtime/CL/functions/CLPoolingLayer.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/runtime/CL/functions/CLPoolingLayer.cpp b/src/runtime/CL/functions/CLPoolingLayer.cpp index 17875a38ad..cbe1ce3b47 100644 --- a/src/runtime/CL/functions/CLPoolingLayer.cpp +++ b/src/runtime/CL/functions/CLPoolingLayer.cpp @@ -63,6 +63,9 @@ void CLPoolingLayer::configure(ICLTensor *input, ICLTensor *output, const Poolin ARM_COMPUTE_ERROR("Data layout not supported"); } _border_handler.configure(input, _kernel->border_size(), border_mode, pixel_value); + + // Tune kernels + CLScheduler::get().tune_kernel_static(*_kernel); } Status CLPoolingLayer::validate(const ITensorInfo *input, const ITensorInfo *output, const PoolingLayerInfo &pool_info) |