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| author | Anitha Raj <anitha.raj@arm.com> | 2023-07-14 11:19:34 +0100 |
|---|---|---|
| committer | Anitha Raj <Anitha.Raj@arm.com> | 2023-08-22 09:42:32 +0000 |
| commit | eb5696d99d85e1d402188151e021bc4b14f93969 (patch) | |
| tree | f78337a676d6cfbb8421ff27315b0d7ad4dffc34 /src/cpu/operators | |
| parent | e1c3b466960d5e3fd5a54871287f5eb6102bfb8c (diff) | |
| download | ComputeLibrary-eb5696d99d85e1d402188151e021bc4b14f93969.tar.gz | |
Optimize CpuReshapeKernel
Resolves COMPMID-5279
Change-Id: Id9b007eed62c200702bbfcc83b94dab7b5de1714
Signed-off-by: Anitha Raj <anitha.raj@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/9962
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: SiCong Li <sicong.li@arm.com>
Reviewed-by: Viet-Hoa Do <viet-hoa.do@arm.com>
Benchmark: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'src/cpu/operators')
| -rw-r--r-- | src/cpu/operators/CpuReshape.cpp | 16 | ||||
| -rw-r--r-- | src/cpu/operators/CpuReshape.h | 9 |
2 files changed, 23 insertions, 2 deletions
diff --git a/src/cpu/operators/CpuReshape.cpp b/src/cpu/operators/CpuReshape.cpp index 79e7b8fe6e..e6892a2e7e 100644 --- a/src/cpu/operators/CpuReshape.cpp +++ b/src/cpu/operators/CpuReshape.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021, 2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -27,6 +27,8 @@ #include "src/common/utils/Log.h" +#include "arm_compute/runtime/NEON/NEScheduler.h" + namespace arm_compute { namespace cpu @@ -43,5 +45,17 @@ Status CpuReshape::validate(const ITensorInfo *src, const ITensorInfo *dst) { return kernels::CpuReshapeKernel::validate(src, dst); } + +void CpuReshape::run(ITensorPack &tensors) +{ + ARM_COMPUTE_ERROR_ON_MSG(tensors.empty(), "No inputs provided"); + if(!_is_prepared) + { + static_cast<kernels::CpuReshapeKernel *>(_kernel.get())->prepare(tensors); + _is_prepared = true; + } + const auto split_dimension = static_cast<kernels::CpuReshapeKernel *>(_kernel.get())->get_split_dimension(); + NEScheduler::get().schedule_op(_kernel.get(), split_dimension, _kernel->window(), tensors); +} } // namespace cpu } // namespace arm_compute diff --git a/src/cpu/operators/CpuReshape.h b/src/cpu/operators/CpuReshape.h index 92dcb09aa9..9bc43e7db4 100644 --- a/src/cpu/operators/CpuReshape.h +++ b/src/cpu/operators/CpuReshape.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021, 2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -25,6 +25,7 @@ #define ARM_COMPUTE_CPU_RESHAPE_H #include "src/cpu/ICpuOperator.h" +#include "arm_compute/core/Window.h" namespace arm_compute { @@ -47,6 +48,12 @@ public: * @return a status */ static Status validate(const ITensorInfo *src, const ITensorInfo *dst); + + // Inherited methods overridden: + void run(ITensorPack &tensors) override; + +private: + bool _is_prepared{ false } ; }; } // namespace cpu } // namespace arm_compute |